1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ARMv8 PMUv3 Performance Events handling code. 4 * 5 * Copyright (C) 2012 ARM Limited 6 * Author: Will Deacon <will.deacon@arm.com> 7 * 8 * This code is based heavily on the ARMv7 perf event code. 9 */ 10 11 #include <asm/irq_regs.h> 12 #include <asm/perf_event.h> 13 #include <asm/virt.h> 14 15 #include <clocksource/arm_arch_timer.h> 16 17 #include <linux/acpi.h> 18 #include <linux/bitfield.h> 19 #include <linux/clocksource.h> 20 #include <linux/of.h> 21 #include <linux/perf/arm_pmu.h> 22 #include <linux/perf/arm_pmuv3.h> 23 #include <linux/platform_device.h> 24 #include <linux/sched_clock.h> 25 #include <linux/smp.h> 26 #include <linux/nmi.h> 27 28 /* ARMv8 Cortex-A53 specific event types. */ 29 #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 30 31 /* ARMv8 Cavium ThunderX specific event types. */ 32 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9 33 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA 34 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB 35 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC 36 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED 37 38 /* 39 * ARMv8 Architectural defined events, not all of these may 40 * be supported on any given implementation. Unsupported events will 41 * be disabled at run-time based on the PMCEID registers. 42 */ 43 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = { 44 PERF_MAP_ALL_UNSUPPORTED, 45 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, 46 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED, 47 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, 48 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, 49 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, 50 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES, 51 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND, 52 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND, 53 }; 54 55 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 56 [PERF_COUNT_HW_CACHE_OP_MAX] 57 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 58 PERF_CACHE_MAP_ALL_UNSUPPORTED, 59 60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, 61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, 62 63 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, 64 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, 65 66 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL, 67 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB, 68 69 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, 70 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB, 71 72 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD, 73 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD, 74 75 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, 76 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, 77 }; 78 79 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 80 [PERF_COUNT_HW_CACHE_OP_MAX] 81 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 82 PERF_CACHE_MAP_ALL_UNSUPPORTED, 83 84 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL, 85 86 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 87 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 88 }; 89 90 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 91 [PERF_COUNT_HW_CACHE_OP_MAX] 92 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 93 PERF_CACHE_MAP_ALL_UNSUPPORTED, 94 95 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 96 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 97 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 98 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, 99 100 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 101 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 102 103 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 104 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 105 }; 106 107 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 108 [PERF_COUNT_HW_CACHE_OP_MAX] 109 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 110 PERF_CACHE_MAP_ALL_UNSUPPORTED, 111 112 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 113 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 114 }; 115 116 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 117 [PERF_COUNT_HW_CACHE_OP_MAX] 118 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 119 PERF_CACHE_MAP_ALL_UNSUPPORTED, 120 121 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 122 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 123 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 124 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST, 125 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS, 126 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS, 127 128 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS, 129 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS, 130 131 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, 132 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 133 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, 134 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 135 }; 136 137 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 138 [PERF_COUNT_HW_CACHE_OP_MAX] 139 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 140 PERF_CACHE_MAP_ALL_UNSUPPORTED, 141 142 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 143 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 144 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 145 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, 146 147 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, 148 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, 149 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 150 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 151 152 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 153 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 154 }; 155 156 static ssize_t 157 armv8pmu_events_sysfs_show(struct device *dev, 158 struct device_attribute *attr, char *page) 159 { 160 struct perf_pmu_events_attr *pmu_attr; 161 162 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 163 164 return sprintf(page, "event=0x%04llx\n", pmu_attr->id); 165 } 166 167 #define ARMV8_EVENT_ATTR(name, config) \ 168 PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config) 169 170 static struct attribute *armv8_pmuv3_event_attrs[] = { 171 /* 172 * Don't expose the sw_incr event in /sys. It's not usable as writes to 173 * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation 174 * means we don't have a fixed event<->counter relationship regardless. 175 */ 176 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL), 177 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL), 178 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL), 179 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE), 180 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL), 181 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED), 182 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED), 183 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED), 184 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN), 185 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN), 186 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED), 187 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED), 188 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED), 189 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED), 190 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED), 191 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED), 192 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES), 193 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED), 194 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS), 195 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE), 196 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB), 197 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE), 198 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL), 199 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB), 200 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS), 201 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR), 202 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC), 203 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED), 204 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES), 205 /* Don't expose the chain event in /sys, since it's useless in isolation */ 206 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE), 207 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE), 208 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED), 209 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED), 210 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND), 211 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND), 212 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB), 213 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB), 214 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE), 215 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL), 216 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE), 217 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL), 218 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE), 219 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB), 220 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL), 221 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL), 222 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB), 223 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB), 224 ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS), 225 ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE), 226 ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS), 227 ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK), 228 ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK), 229 ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD), 230 ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD), 231 ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD), 232 ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD), 233 ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED), 234 ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC), 235 ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL), 236 ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND), 237 ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND), 238 ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT), 239 ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP), 240 ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED), 241 ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE), 242 ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION), 243 ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES), 244 ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM), 245 ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS), 246 ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD), 247 ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS), 248 ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD), 249 ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP), 250 ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG), 251 ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0), 252 ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1), 253 ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2), 254 ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3), 255 ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4), 256 ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5), 257 ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6), 258 ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7), 259 ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT), 260 ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT), 261 ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT), 262 ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED), 263 ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD), 264 ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR), 265 NULL, 266 }; 267 268 static umode_t 269 armv8pmu_event_attr_is_visible(struct kobject *kobj, 270 struct attribute *attr, int unused) 271 { 272 struct device *dev = kobj_to_dev(kobj); 273 struct pmu *pmu = dev_get_drvdata(dev); 274 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 275 struct perf_pmu_events_attr *pmu_attr; 276 277 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); 278 279 if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS && 280 test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap)) 281 return attr->mode; 282 283 if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) { 284 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE; 285 286 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS && 287 test_bit(id, cpu_pmu->pmceid_ext_bitmap)) 288 return attr->mode; 289 } 290 291 return 0; 292 } 293 294 static const struct attribute_group armv8_pmuv3_events_attr_group = { 295 .name = "events", 296 .attrs = armv8_pmuv3_event_attrs, 297 .is_visible = armv8pmu_event_attr_is_visible, 298 }; 299 300 /* User ABI */ 301 #define ATTR_CFG_FLD_event_CFG config 302 #define ATTR_CFG_FLD_event_LO 0 303 #define ATTR_CFG_FLD_event_HI 15 304 #define ATTR_CFG_FLD_long_CFG config1 305 #define ATTR_CFG_FLD_long_LO 0 306 #define ATTR_CFG_FLD_long_HI 0 307 #define ATTR_CFG_FLD_rdpmc_CFG config1 308 #define ATTR_CFG_FLD_rdpmc_LO 1 309 #define ATTR_CFG_FLD_rdpmc_HI 1 310 #define ATTR_CFG_FLD_threshold_count_CFG config1 /* PMEVTYPER.TC[0] */ 311 #define ATTR_CFG_FLD_threshold_count_LO 2 312 #define ATTR_CFG_FLD_threshold_count_HI 2 313 #define ATTR_CFG_FLD_threshold_compare_CFG config1 /* PMEVTYPER.TC[2:1] */ 314 #define ATTR_CFG_FLD_threshold_compare_LO 3 315 #define ATTR_CFG_FLD_threshold_compare_HI 4 316 #define ATTR_CFG_FLD_threshold_CFG config1 /* PMEVTYPER.TH */ 317 #define ATTR_CFG_FLD_threshold_LO 5 318 #define ATTR_CFG_FLD_threshold_HI 16 319 320 GEN_PMU_FORMAT_ATTR(event); 321 GEN_PMU_FORMAT_ATTR(long); 322 GEN_PMU_FORMAT_ATTR(rdpmc); 323 GEN_PMU_FORMAT_ATTR(threshold_count); 324 GEN_PMU_FORMAT_ATTR(threshold_compare); 325 GEN_PMU_FORMAT_ATTR(threshold); 326 327 static int sysctl_perf_user_access __read_mostly; 328 329 static bool armv8pmu_event_is_64bit(struct perf_event *event) 330 { 331 return ATTR_CFG_GET_FLD(&event->attr, long); 332 } 333 334 static bool armv8pmu_event_want_user_access(struct perf_event *event) 335 { 336 return ATTR_CFG_GET_FLD(&event->attr, rdpmc); 337 } 338 339 static u32 armv8pmu_event_get_threshold(struct perf_event_attr *attr) 340 { 341 return ATTR_CFG_GET_FLD(attr, threshold); 342 } 343 344 static u8 armv8pmu_event_threshold_control(struct perf_event_attr *attr) 345 { 346 u8 th_compare = ATTR_CFG_GET_FLD(attr, threshold_compare); 347 u8 th_count = ATTR_CFG_GET_FLD(attr, threshold_count); 348 349 /* 350 * The count bit is always the bottom bit of the full control field, and 351 * the comparison is the upper two bits, but it's not explicitly 352 * labelled in the Arm ARM. For the Perf interface we split it into two 353 * fields, so reconstruct it here. 354 */ 355 return (th_compare << 1) | th_count; 356 } 357 358 static struct attribute *armv8_pmuv3_format_attrs[] = { 359 &format_attr_event.attr, 360 &format_attr_long.attr, 361 &format_attr_rdpmc.attr, 362 &format_attr_threshold.attr, 363 &format_attr_threshold_compare.attr, 364 &format_attr_threshold_count.attr, 365 NULL, 366 }; 367 368 static const struct attribute_group armv8_pmuv3_format_attr_group = { 369 .name = "format", 370 .attrs = armv8_pmuv3_format_attrs, 371 }; 372 373 static ssize_t slots_show(struct device *dev, struct device_attribute *attr, 374 char *page) 375 { 376 struct pmu *pmu = dev_get_drvdata(dev); 377 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 378 u32 slots = FIELD_GET(ARMV8_PMU_SLOTS, cpu_pmu->reg_pmmir); 379 380 return sysfs_emit(page, "0x%08x\n", slots); 381 } 382 383 static DEVICE_ATTR_RO(slots); 384 385 static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr, 386 char *page) 387 { 388 struct pmu *pmu = dev_get_drvdata(dev); 389 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 390 u32 bus_slots = FIELD_GET(ARMV8_PMU_BUS_SLOTS, cpu_pmu->reg_pmmir); 391 392 return sysfs_emit(page, "0x%08x\n", bus_slots); 393 } 394 395 static DEVICE_ATTR_RO(bus_slots); 396 397 static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr, 398 char *page) 399 { 400 struct pmu *pmu = dev_get_drvdata(dev); 401 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 402 u32 bus_width = FIELD_GET(ARMV8_PMU_BUS_WIDTH, cpu_pmu->reg_pmmir); 403 u32 val = 0; 404 405 /* Encoded as Log2(number of bytes), plus one */ 406 if (bus_width > 2 && bus_width < 13) 407 val = 1 << (bus_width - 1); 408 409 return sysfs_emit(page, "0x%08x\n", val); 410 } 411 412 static DEVICE_ATTR_RO(bus_width); 413 414 static u32 threshold_max(struct arm_pmu *cpu_pmu) 415 { 416 /* 417 * PMMIR.THWIDTH is readable and non-zero on aarch32, but it would be 418 * impossible to write the threshold in the upper 32 bits of PMEVTYPER. 419 */ 420 if (IS_ENABLED(CONFIG_ARM)) 421 return 0; 422 423 /* 424 * The largest value that can be written to PMEVTYPER<n>_EL0.TH is 425 * (2 ^ PMMIR.THWIDTH) - 1. 426 */ 427 return (1 << FIELD_GET(ARMV8_PMU_THWIDTH, cpu_pmu->reg_pmmir)) - 1; 428 } 429 430 static ssize_t threshold_max_show(struct device *dev, 431 struct device_attribute *attr, char *page) 432 { 433 struct pmu *pmu = dev_get_drvdata(dev); 434 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 435 436 return sysfs_emit(page, "0x%08x\n", threshold_max(cpu_pmu)); 437 } 438 439 static DEVICE_ATTR_RO(threshold_max); 440 441 static struct attribute *armv8_pmuv3_caps_attrs[] = { 442 &dev_attr_slots.attr, 443 &dev_attr_bus_slots.attr, 444 &dev_attr_bus_width.attr, 445 &dev_attr_threshold_max.attr, 446 NULL, 447 }; 448 449 static const struct attribute_group armv8_pmuv3_caps_attr_group = { 450 .name = "caps", 451 .attrs = armv8_pmuv3_caps_attrs, 452 }; 453 454 /* 455 * Perf Events' indices 456 */ 457 #define ARMV8_IDX_CYCLE_COUNTER 0 458 #define ARMV8_IDX_COUNTER0 1 459 #define ARMV8_IDX_CYCLE_COUNTER_USER 32 460 461 /* 462 * We unconditionally enable ARMv8.5-PMU long event counter support 463 * (64-bit events) where supported. Indicate if this arm_pmu has long 464 * event counter support. 465 * 466 * On AArch32, long counters make no sense (you can't access the top 467 * bits), so we only enable this on AArch64. 468 */ 469 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu) 470 { 471 return (IS_ENABLED(CONFIG_ARM64) && is_pmuv3p5(cpu_pmu->pmuver)); 472 } 473 474 static bool armv8pmu_event_has_user_read(struct perf_event *event) 475 { 476 return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT; 477 } 478 479 /* 480 * We must chain two programmable counters for 64 bit events, 481 * except when we have allocated the 64bit cycle counter (for CPU 482 * cycles event) or when user space counter access is enabled. 483 */ 484 static bool armv8pmu_event_is_chained(struct perf_event *event) 485 { 486 int idx = event->hw.idx; 487 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 488 489 return !armv8pmu_event_has_user_read(event) && 490 armv8pmu_event_is_64bit(event) && 491 !armv8pmu_has_long_event(cpu_pmu) && 492 (idx != ARMV8_IDX_CYCLE_COUNTER); 493 } 494 495 /* 496 * ARMv8 low level PMU access 497 */ 498 499 /* 500 * Perf Event to low level counters mapping 501 */ 502 #define ARMV8_IDX_TO_COUNTER(x) \ 503 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK) 504 505 static u64 armv8pmu_pmcr_read(void) 506 { 507 return read_pmcr(); 508 } 509 510 static void armv8pmu_pmcr_write(u64 val) 511 { 512 val &= ARMV8_PMU_PMCR_MASK; 513 isb(); 514 write_pmcr(val); 515 } 516 517 static int armv8pmu_has_overflowed(u32 pmovsr) 518 { 519 return pmovsr & ARMV8_PMU_OVERFLOWED_MASK; 520 } 521 522 static int armv8pmu_counter_has_overflowed(u32 pmnc, int idx) 523 { 524 return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx)); 525 } 526 527 static u64 armv8pmu_read_evcntr(int idx) 528 { 529 u32 counter = ARMV8_IDX_TO_COUNTER(idx); 530 531 return read_pmevcntrn(counter); 532 } 533 534 static u64 armv8pmu_read_hw_counter(struct perf_event *event) 535 { 536 int idx = event->hw.idx; 537 u64 val = armv8pmu_read_evcntr(idx); 538 539 if (armv8pmu_event_is_chained(event)) 540 val = (val << 32) | armv8pmu_read_evcntr(idx - 1); 541 return val; 542 } 543 544 /* 545 * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP 546 * is set the event counters also become 64-bit counters. Unless the 547 * user has requested a long counter (attr.config1) then we want to 548 * interrupt upon 32-bit overflow - we achieve this by applying a bias. 549 */ 550 static bool armv8pmu_event_needs_bias(struct perf_event *event) 551 { 552 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 553 struct hw_perf_event *hwc = &event->hw; 554 int idx = hwc->idx; 555 556 if (armv8pmu_event_is_64bit(event)) 557 return false; 558 559 if (armv8pmu_has_long_event(cpu_pmu) || 560 idx == ARMV8_IDX_CYCLE_COUNTER) 561 return true; 562 563 return false; 564 } 565 566 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value) 567 { 568 if (armv8pmu_event_needs_bias(event)) 569 value |= GENMASK_ULL(63, 32); 570 571 return value; 572 } 573 574 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value) 575 { 576 if (armv8pmu_event_needs_bias(event)) 577 value &= ~GENMASK_ULL(63, 32); 578 579 return value; 580 } 581 582 static u64 armv8pmu_read_counter(struct perf_event *event) 583 { 584 struct hw_perf_event *hwc = &event->hw; 585 int idx = hwc->idx; 586 u64 value; 587 588 if (idx == ARMV8_IDX_CYCLE_COUNTER) 589 value = read_pmccntr(); 590 else 591 value = armv8pmu_read_hw_counter(event); 592 593 return armv8pmu_unbias_long_counter(event, value); 594 } 595 596 static void armv8pmu_write_evcntr(int idx, u64 value) 597 { 598 u32 counter = ARMV8_IDX_TO_COUNTER(idx); 599 600 write_pmevcntrn(counter, value); 601 } 602 603 static void armv8pmu_write_hw_counter(struct perf_event *event, 604 u64 value) 605 { 606 int idx = event->hw.idx; 607 608 if (armv8pmu_event_is_chained(event)) { 609 armv8pmu_write_evcntr(idx, upper_32_bits(value)); 610 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value)); 611 } else { 612 armv8pmu_write_evcntr(idx, value); 613 } 614 } 615 616 static void armv8pmu_write_counter(struct perf_event *event, u64 value) 617 { 618 struct hw_perf_event *hwc = &event->hw; 619 int idx = hwc->idx; 620 621 value = armv8pmu_bias_long_counter(event, value); 622 623 if (idx == ARMV8_IDX_CYCLE_COUNTER) 624 write_pmccntr(value); 625 else 626 armv8pmu_write_hw_counter(event, value); 627 } 628 629 static void armv8pmu_write_evtype(int idx, unsigned long val) 630 { 631 u32 counter = ARMV8_IDX_TO_COUNTER(idx); 632 unsigned long mask = ARMV8_PMU_EVTYPE_EVENT | 633 ARMV8_PMU_INCLUDE_EL2 | 634 ARMV8_PMU_EXCLUDE_EL0 | 635 ARMV8_PMU_EXCLUDE_EL1; 636 637 if (IS_ENABLED(CONFIG_ARM64)) 638 mask |= ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH; 639 640 val &= mask; 641 write_pmevtypern(counter, val); 642 } 643 644 static void armv8pmu_write_event_type(struct perf_event *event) 645 { 646 struct hw_perf_event *hwc = &event->hw; 647 int idx = hwc->idx; 648 649 /* 650 * For chained events, the low counter is programmed to count 651 * the event of interest and the high counter is programmed 652 * with CHAIN event code with filters set to count at all ELs. 653 */ 654 if (armv8pmu_event_is_chained(event)) { 655 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN | 656 ARMV8_PMU_INCLUDE_EL2; 657 658 armv8pmu_write_evtype(idx - 1, hwc->config_base); 659 armv8pmu_write_evtype(idx, chain_evt); 660 } else { 661 if (idx == ARMV8_IDX_CYCLE_COUNTER) 662 write_pmccfiltr(hwc->config_base); 663 else 664 armv8pmu_write_evtype(idx, hwc->config_base); 665 } 666 } 667 668 static u32 armv8pmu_event_cnten_mask(struct perf_event *event) 669 { 670 int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx); 671 u32 mask = BIT(counter); 672 673 if (armv8pmu_event_is_chained(event)) 674 mask |= BIT(counter - 1); 675 return mask; 676 } 677 678 static void armv8pmu_enable_counter(u32 mask) 679 { 680 /* 681 * Make sure event configuration register writes are visible before we 682 * enable the counter. 683 * */ 684 isb(); 685 write_pmcntenset(mask); 686 } 687 688 static void armv8pmu_enable_event_counter(struct perf_event *event) 689 { 690 struct perf_event_attr *attr = &event->attr; 691 u32 mask = armv8pmu_event_cnten_mask(event); 692 693 kvm_set_pmu_events(mask, attr); 694 695 /* We rely on the hypervisor switch code to enable guest counters */ 696 if (!kvm_pmu_counter_deferred(attr)) 697 armv8pmu_enable_counter(mask); 698 } 699 700 static void armv8pmu_disable_counter(u32 mask) 701 { 702 write_pmcntenclr(mask); 703 /* 704 * Make sure the effects of disabling the counter are visible before we 705 * start configuring the event. 706 */ 707 isb(); 708 } 709 710 static void armv8pmu_disable_event_counter(struct perf_event *event) 711 { 712 struct perf_event_attr *attr = &event->attr; 713 u32 mask = armv8pmu_event_cnten_mask(event); 714 715 kvm_clr_pmu_events(mask); 716 717 /* We rely on the hypervisor switch code to disable guest counters */ 718 if (!kvm_pmu_counter_deferred(attr)) 719 armv8pmu_disable_counter(mask); 720 } 721 722 static void armv8pmu_enable_intens(u32 mask) 723 { 724 write_pmintenset(mask); 725 } 726 727 static void armv8pmu_enable_event_irq(struct perf_event *event) 728 { 729 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx); 730 armv8pmu_enable_intens(BIT(counter)); 731 } 732 733 static void armv8pmu_disable_intens(u32 mask) 734 { 735 write_pmintenclr(mask); 736 isb(); 737 /* Clear the overflow flag in case an interrupt is pending. */ 738 write_pmovsclr(mask); 739 isb(); 740 } 741 742 static void armv8pmu_disable_event_irq(struct perf_event *event) 743 { 744 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx); 745 armv8pmu_disable_intens(BIT(counter)); 746 } 747 748 static u32 armv8pmu_getreset_flags(void) 749 { 750 u32 value; 751 752 /* Read */ 753 value = read_pmovsclr(); 754 755 /* Write to clear flags */ 756 value &= ARMV8_PMU_OVERFLOWED_MASK; 757 write_pmovsclr(value); 758 759 return value; 760 } 761 762 static void update_pmuserenr(u64 val) 763 { 764 lockdep_assert_irqs_disabled(); 765 766 /* 767 * The current PMUSERENR_EL0 value might be the value for the guest. 768 * If that's the case, have KVM keep tracking of the register value 769 * for the host EL0 so that KVM can restore it before returning to 770 * the host EL0. Otherwise, update the register now. 771 */ 772 if (kvm_set_pmuserenr(val)) 773 return; 774 775 write_pmuserenr(val); 776 } 777 778 static void armv8pmu_disable_user_access(void) 779 { 780 update_pmuserenr(0); 781 } 782 783 static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) 784 { 785 int i; 786 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 787 788 /* Clear any unused counters to avoid leaking their contents */ 789 for_each_clear_bit(i, cpuc->used_mask, cpu_pmu->num_events) { 790 if (i == ARMV8_IDX_CYCLE_COUNTER) 791 write_pmccntr(0); 792 else 793 armv8pmu_write_evcntr(i, 0); 794 } 795 796 update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR); 797 } 798 799 static void armv8pmu_enable_event(struct perf_event *event) 800 { 801 /* 802 * Enable counter and interrupt, and set the counter to count 803 * the event that we're interested in. 804 */ 805 armv8pmu_disable_event_counter(event); 806 armv8pmu_write_event_type(event); 807 armv8pmu_enable_event_irq(event); 808 armv8pmu_enable_event_counter(event); 809 } 810 811 static void armv8pmu_disable_event(struct perf_event *event) 812 { 813 armv8pmu_disable_event_counter(event); 814 armv8pmu_disable_event_irq(event); 815 } 816 817 static void armv8pmu_start(struct arm_pmu *cpu_pmu) 818 { 819 struct perf_event_context *ctx; 820 int nr_user = 0; 821 822 ctx = perf_cpu_task_ctx(); 823 if (ctx) 824 nr_user = ctx->nr_user; 825 826 if (sysctl_perf_user_access && nr_user) 827 armv8pmu_enable_user_access(cpu_pmu); 828 else 829 armv8pmu_disable_user_access(); 830 831 /* Enable all counters */ 832 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E); 833 834 kvm_vcpu_pmu_resync_el0(); 835 } 836 837 static void armv8pmu_stop(struct arm_pmu *cpu_pmu) 838 { 839 /* Disable all counters */ 840 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E); 841 } 842 843 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) 844 { 845 u32 pmovsr; 846 struct perf_sample_data data; 847 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 848 struct pt_regs *regs; 849 int idx; 850 851 /* 852 * Get and reset the IRQ flags 853 */ 854 pmovsr = armv8pmu_getreset_flags(); 855 856 /* 857 * Did an overflow occur? 858 */ 859 if (!armv8pmu_has_overflowed(pmovsr)) 860 return IRQ_NONE; 861 862 /* 863 * Handle the counter(s) overflow(s) 864 */ 865 regs = get_irq_regs(); 866 867 /* 868 * Stop the PMU while processing the counter overflows 869 * to prevent skews in group events. 870 */ 871 armv8pmu_stop(cpu_pmu); 872 for (idx = 0; idx < cpu_pmu->num_events; ++idx) { 873 struct perf_event *event = cpuc->events[idx]; 874 struct hw_perf_event *hwc; 875 876 /* Ignore if we don't have an event. */ 877 if (!event) 878 continue; 879 880 /* 881 * We have a single interrupt for all counters. Check that 882 * each counter has overflowed before we process it. 883 */ 884 if (!armv8pmu_counter_has_overflowed(pmovsr, idx)) 885 continue; 886 887 hwc = &event->hw; 888 armpmu_event_update(event); 889 perf_sample_data_init(&data, 0, hwc->last_period); 890 if (!armpmu_event_set_period(event)) 891 continue; 892 893 /* 894 * Perf event overflow will queue the processing of the event as 895 * an irq_work which will be taken care of in the handling of 896 * IPI_IRQ_WORK. 897 */ 898 if (perf_event_overflow(event, &data, regs)) 899 cpu_pmu->disable(event); 900 } 901 armv8pmu_start(cpu_pmu); 902 903 return IRQ_HANDLED; 904 } 905 906 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc, 907 struct arm_pmu *cpu_pmu) 908 { 909 int idx; 910 911 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx++) { 912 if (!test_and_set_bit(idx, cpuc->used_mask)) 913 return idx; 914 } 915 return -EAGAIN; 916 } 917 918 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc, 919 struct arm_pmu *cpu_pmu) 920 { 921 int idx; 922 923 /* 924 * Chaining requires two consecutive event counters, where 925 * the lower idx must be even. 926 */ 927 for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) { 928 if (!test_and_set_bit(idx, cpuc->used_mask)) { 929 /* Check if the preceding even counter is available */ 930 if (!test_and_set_bit(idx - 1, cpuc->used_mask)) 931 return idx; 932 /* Release the Odd counter */ 933 clear_bit(idx, cpuc->used_mask); 934 } 935 } 936 return -EAGAIN; 937 } 938 939 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, 940 struct perf_event *event) 941 { 942 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 943 struct hw_perf_event *hwc = &event->hw; 944 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; 945 946 /* Always prefer to place a cycle counter into the cycle counter. */ 947 if ((evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && 948 !armv8pmu_event_get_threshold(&event->attr)) { 949 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) 950 return ARMV8_IDX_CYCLE_COUNTER; 951 else if (armv8pmu_event_is_64bit(event) && 952 armv8pmu_event_want_user_access(event) && 953 !armv8pmu_has_long_event(cpu_pmu)) 954 return -EAGAIN; 955 } 956 957 /* 958 * Otherwise use events counters 959 */ 960 if (armv8pmu_event_is_chained(event)) 961 return armv8pmu_get_chain_idx(cpuc, cpu_pmu); 962 else 963 return armv8pmu_get_single_idx(cpuc, cpu_pmu); 964 } 965 966 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc, 967 struct perf_event *event) 968 { 969 int idx = event->hw.idx; 970 971 clear_bit(idx, cpuc->used_mask); 972 if (armv8pmu_event_is_chained(event)) 973 clear_bit(idx - 1, cpuc->used_mask); 974 } 975 976 static int armv8pmu_user_event_idx(struct perf_event *event) 977 { 978 if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event)) 979 return 0; 980 981 /* 982 * We remap the cycle counter index to 32 to 983 * match the offset applied to the rest of 984 * the counter indices. 985 */ 986 if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER) 987 return ARMV8_IDX_CYCLE_COUNTER_USER; 988 989 return event->hw.idx; 990 } 991 992 /* 993 * Add an event filter to a given event. 994 */ 995 static int armv8pmu_set_event_filter(struct hw_perf_event *event, 996 struct perf_event_attr *attr) 997 { 998 unsigned long config_base = 0; 999 struct perf_event *perf_event = container_of(attr, struct perf_event, 1000 attr); 1001 struct arm_pmu *cpu_pmu = to_arm_pmu(perf_event->pmu); 1002 u32 th; 1003 1004 if (attr->exclude_idle) { 1005 pr_debug("ARM performance counters do not support mode exclusion\n"); 1006 return -EOPNOTSUPP; 1007 } 1008 1009 /* 1010 * If we're running in hyp mode, then we *are* the hypervisor. 1011 * Therefore we ignore exclude_hv in this configuration, since 1012 * there's no hypervisor to sample anyway. This is consistent 1013 * with other architectures (x86 and Power). 1014 */ 1015 if (is_kernel_in_hyp_mode()) { 1016 if (!attr->exclude_kernel && !attr->exclude_host) 1017 config_base |= ARMV8_PMU_INCLUDE_EL2; 1018 if (attr->exclude_guest) 1019 config_base |= ARMV8_PMU_EXCLUDE_EL1; 1020 if (attr->exclude_host) 1021 config_base |= ARMV8_PMU_EXCLUDE_EL0; 1022 } else { 1023 if (!attr->exclude_hv && !attr->exclude_host) 1024 config_base |= ARMV8_PMU_INCLUDE_EL2; 1025 } 1026 1027 /* 1028 * Filter out !VHE kernels and guest kernels 1029 */ 1030 if (attr->exclude_kernel) 1031 config_base |= ARMV8_PMU_EXCLUDE_EL1; 1032 1033 if (attr->exclude_user) 1034 config_base |= ARMV8_PMU_EXCLUDE_EL0; 1035 1036 /* 1037 * If FEAT_PMUv3_TH isn't implemented, then THWIDTH (threshold_max) will 1038 * be 0 and will also trigger this check, preventing it from being used. 1039 */ 1040 th = armv8pmu_event_get_threshold(attr); 1041 if (th > threshold_max(cpu_pmu)) { 1042 pr_debug("PMU event threshold exceeds max value\n"); 1043 return -EINVAL; 1044 } 1045 1046 if (th) { 1047 config_base |= FIELD_PREP(ARMV8_PMU_EVTYPE_TH, th); 1048 config_base |= FIELD_PREP(ARMV8_PMU_EVTYPE_TC, 1049 armv8pmu_event_threshold_control(attr)); 1050 } 1051 1052 /* 1053 * Install the filter into config_base as this is used to 1054 * construct the event type. 1055 */ 1056 event->config_base = config_base; 1057 1058 return 0; 1059 } 1060 1061 static void armv8pmu_reset(void *info) 1062 { 1063 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; 1064 u64 pmcr; 1065 1066 /* The counter and interrupt enable registers are unknown at reset. */ 1067 armv8pmu_disable_counter(U32_MAX); 1068 armv8pmu_disable_intens(U32_MAX); 1069 1070 /* Clear the counters we flip at guest entry/exit */ 1071 kvm_clr_pmu_events(U32_MAX); 1072 1073 /* 1074 * Initialize & Reset PMNC. Request overflow interrupt for 1075 * 64 bit cycle counter but cheat in armv8pmu_write_counter(). 1076 */ 1077 pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC; 1078 1079 /* Enable long event counter support where available */ 1080 if (armv8pmu_has_long_event(cpu_pmu)) 1081 pmcr |= ARMV8_PMU_PMCR_LP; 1082 1083 armv8pmu_pmcr_write(pmcr); 1084 } 1085 1086 static int __armv8_pmuv3_map_event_id(struct arm_pmu *armpmu, 1087 struct perf_event *event) 1088 { 1089 if (event->attr.type == PERF_TYPE_HARDWARE && 1090 event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) { 1091 1092 if (test_bit(ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED, 1093 armpmu->pmceid_bitmap)) 1094 return ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED; 1095 1096 if (test_bit(ARMV8_PMUV3_PERFCTR_BR_RETIRED, 1097 armpmu->pmceid_bitmap)) 1098 return ARMV8_PMUV3_PERFCTR_BR_RETIRED; 1099 1100 return HW_OP_UNSUPPORTED; 1101 } 1102 1103 return armpmu_map_event(event, &armv8_pmuv3_perf_map, 1104 &armv8_pmuv3_perf_cache_map, 1105 ARMV8_PMU_EVTYPE_EVENT); 1106 } 1107 1108 static int __armv8_pmuv3_map_event(struct perf_event *event, 1109 const unsigned (*extra_event_map) 1110 [PERF_COUNT_HW_MAX], 1111 const unsigned (*extra_cache_map) 1112 [PERF_COUNT_HW_CACHE_MAX] 1113 [PERF_COUNT_HW_CACHE_OP_MAX] 1114 [PERF_COUNT_HW_CACHE_RESULT_MAX]) 1115 { 1116 int hw_event_id; 1117 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); 1118 1119 hw_event_id = __armv8_pmuv3_map_event_id(armpmu, event); 1120 1121 /* 1122 * CHAIN events only work when paired with an adjacent counter, and it 1123 * never makes sense for a user to open one in isolation, as they'll be 1124 * rotated arbitrarily. 1125 */ 1126 if (hw_event_id == ARMV8_PMUV3_PERFCTR_CHAIN) 1127 return -EINVAL; 1128 1129 if (armv8pmu_event_is_64bit(event)) 1130 event->hw.flags |= ARMPMU_EVT_64BIT; 1131 1132 /* 1133 * User events must be allocated into a single counter, and so 1134 * must not be chained. 1135 * 1136 * Most 64-bit events require long counter support, but 64-bit 1137 * CPU_CYCLES events can be placed into the dedicated cycle 1138 * counter when this is free. 1139 */ 1140 if (armv8pmu_event_want_user_access(event)) { 1141 if (!(event->attach_state & PERF_ATTACH_TASK)) 1142 return -EINVAL; 1143 if (armv8pmu_event_is_64bit(event) && 1144 (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && 1145 !armv8pmu_has_long_event(armpmu)) 1146 return -EOPNOTSUPP; 1147 1148 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; 1149 } 1150 1151 /* Only expose micro/arch events supported by this PMU */ 1152 if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) 1153 && test_bit(hw_event_id, armpmu->pmceid_bitmap)) { 1154 return hw_event_id; 1155 } 1156 1157 return armpmu_map_event(event, extra_event_map, extra_cache_map, 1158 ARMV8_PMU_EVTYPE_EVENT); 1159 } 1160 1161 static int armv8_pmuv3_map_event(struct perf_event *event) 1162 { 1163 return __armv8_pmuv3_map_event(event, NULL, NULL); 1164 } 1165 1166 static int armv8_a53_map_event(struct perf_event *event) 1167 { 1168 return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map); 1169 } 1170 1171 static int armv8_a57_map_event(struct perf_event *event) 1172 { 1173 return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map); 1174 } 1175 1176 static int armv8_a73_map_event(struct perf_event *event) 1177 { 1178 return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map); 1179 } 1180 1181 static int armv8_thunder_map_event(struct perf_event *event) 1182 { 1183 return __armv8_pmuv3_map_event(event, NULL, 1184 &armv8_thunder_perf_cache_map); 1185 } 1186 1187 static int armv8_vulcan_map_event(struct perf_event *event) 1188 { 1189 return __armv8_pmuv3_map_event(event, NULL, 1190 &armv8_vulcan_perf_cache_map); 1191 } 1192 1193 struct armv8pmu_probe_info { 1194 struct arm_pmu *pmu; 1195 bool present; 1196 }; 1197 1198 static void __armv8pmu_probe_pmu(void *info) 1199 { 1200 struct armv8pmu_probe_info *probe = info; 1201 struct arm_pmu *cpu_pmu = probe->pmu; 1202 u64 pmceid_raw[2]; 1203 u32 pmceid[2]; 1204 int pmuver; 1205 1206 pmuver = read_pmuver(); 1207 if (!pmuv3_implemented(pmuver)) 1208 return; 1209 1210 cpu_pmu->pmuver = pmuver; 1211 probe->present = true; 1212 1213 /* Read the nb of CNTx counters supported from PMNC */ 1214 cpu_pmu->num_events = FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read()); 1215 1216 /* Add the CPU cycles counter */ 1217 cpu_pmu->num_events += 1; 1218 1219 pmceid[0] = pmceid_raw[0] = read_pmceid0(); 1220 pmceid[1] = pmceid_raw[1] = read_pmceid1(); 1221 1222 bitmap_from_arr32(cpu_pmu->pmceid_bitmap, 1223 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); 1224 1225 pmceid[0] = pmceid_raw[0] >> 32; 1226 pmceid[1] = pmceid_raw[1] >> 32; 1227 1228 bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap, 1229 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); 1230 1231 /* store PMMIR register for sysfs */ 1232 if (is_pmuv3p4(pmuver)) 1233 cpu_pmu->reg_pmmir = read_pmmir(); 1234 else 1235 cpu_pmu->reg_pmmir = 0; 1236 } 1237 1238 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) 1239 { 1240 struct armv8pmu_probe_info probe = { 1241 .pmu = cpu_pmu, 1242 .present = false, 1243 }; 1244 int ret; 1245 1246 ret = smp_call_function_any(&cpu_pmu->supported_cpus, 1247 __armv8pmu_probe_pmu, 1248 &probe, 1); 1249 if (ret) 1250 return ret; 1251 1252 return probe.present ? 0 : -ENODEV; 1253 } 1254 1255 static void armv8pmu_disable_user_access_ipi(void *unused) 1256 { 1257 armv8pmu_disable_user_access(); 1258 } 1259 1260 static int armv8pmu_proc_user_access_handler(const struct ctl_table *table, int write, 1261 void *buffer, size_t *lenp, loff_t *ppos) 1262 { 1263 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); 1264 if (ret || !write || sysctl_perf_user_access) 1265 return ret; 1266 1267 on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1); 1268 return 0; 1269 } 1270 1271 static struct ctl_table armv8_pmu_sysctl_table[] = { 1272 { 1273 .procname = "perf_user_access", 1274 .data = &sysctl_perf_user_access, 1275 .maxlen = sizeof(unsigned int), 1276 .mode = 0644, 1277 .proc_handler = armv8pmu_proc_user_access_handler, 1278 .extra1 = SYSCTL_ZERO, 1279 .extra2 = SYSCTL_ONE, 1280 }, 1281 }; 1282 1283 static void armv8_pmu_register_sysctl_table(void) 1284 { 1285 static u32 tbl_registered = 0; 1286 1287 if (!cmpxchg_relaxed(&tbl_registered, 0, 1)) 1288 register_sysctl("kernel", armv8_pmu_sysctl_table); 1289 } 1290 1291 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, 1292 int (*map_event)(struct perf_event *event)) 1293 { 1294 int ret = armv8pmu_probe_pmu(cpu_pmu); 1295 if (ret) 1296 return ret; 1297 1298 cpu_pmu->handle_irq = armv8pmu_handle_irq; 1299 cpu_pmu->enable = armv8pmu_enable_event; 1300 cpu_pmu->disable = armv8pmu_disable_event; 1301 cpu_pmu->read_counter = armv8pmu_read_counter; 1302 cpu_pmu->write_counter = armv8pmu_write_counter; 1303 cpu_pmu->get_event_idx = armv8pmu_get_event_idx; 1304 cpu_pmu->clear_event_idx = armv8pmu_clear_event_idx; 1305 cpu_pmu->start = armv8pmu_start; 1306 cpu_pmu->stop = armv8pmu_stop; 1307 cpu_pmu->reset = armv8pmu_reset; 1308 cpu_pmu->set_event_filter = armv8pmu_set_event_filter; 1309 1310 cpu_pmu->pmu.event_idx = armv8pmu_user_event_idx; 1311 1312 cpu_pmu->name = name; 1313 cpu_pmu->map_event = map_event; 1314 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &armv8_pmuv3_events_attr_group; 1315 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv8_pmuv3_format_attr_group; 1316 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = &armv8_pmuv3_caps_attr_group; 1317 armv8_pmu_register_sysctl_table(); 1318 return 0; 1319 } 1320 1321 #define PMUV3_INIT_SIMPLE(name) \ 1322 static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ 1323 { \ 1324 return armv8_pmu_init(cpu_pmu, #name, armv8_pmuv3_map_event); \ 1325 } 1326 1327 #define PMUV3_INIT_MAP_EVENT(name, map_event) \ 1328 static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ 1329 { \ 1330 return armv8_pmu_init(cpu_pmu, #name, map_event); \ 1331 } 1332 1333 PMUV3_INIT_SIMPLE(armv8_pmuv3) 1334 1335 PMUV3_INIT_SIMPLE(armv8_cortex_a34) 1336 PMUV3_INIT_SIMPLE(armv8_cortex_a55) 1337 PMUV3_INIT_SIMPLE(armv8_cortex_a65) 1338 PMUV3_INIT_SIMPLE(armv8_cortex_a75) 1339 PMUV3_INIT_SIMPLE(armv8_cortex_a76) 1340 PMUV3_INIT_SIMPLE(armv8_cortex_a77) 1341 PMUV3_INIT_SIMPLE(armv8_cortex_a78) 1342 PMUV3_INIT_SIMPLE(armv9_cortex_a510) 1343 PMUV3_INIT_SIMPLE(armv9_cortex_a520) 1344 PMUV3_INIT_SIMPLE(armv9_cortex_a710) 1345 PMUV3_INIT_SIMPLE(armv9_cortex_a715) 1346 PMUV3_INIT_SIMPLE(armv9_cortex_a720) 1347 PMUV3_INIT_SIMPLE(armv9_cortex_a725) 1348 PMUV3_INIT_SIMPLE(armv8_cortex_x1) 1349 PMUV3_INIT_SIMPLE(armv9_cortex_x2) 1350 PMUV3_INIT_SIMPLE(armv9_cortex_x3) 1351 PMUV3_INIT_SIMPLE(armv9_cortex_x4) 1352 PMUV3_INIT_SIMPLE(armv9_cortex_x925) 1353 PMUV3_INIT_SIMPLE(armv8_neoverse_e1) 1354 PMUV3_INIT_SIMPLE(armv8_neoverse_n1) 1355 PMUV3_INIT_SIMPLE(armv9_neoverse_n2) 1356 PMUV3_INIT_SIMPLE(armv9_neoverse_n3) 1357 PMUV3_INIT_SIMPLE(armv8_neoverse_v1) 1358 PMUV3_INIT_SIMPLE(armv8_neoverse_v2) 1359 PMUV3_INIT_SIMPLE(armv8_neoverse_v3) 1360 PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae) 1361 1362 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) 1363 PMUV3_INIT_SIMPLE(armv8_nvidia_denver) 1364 1365 PMUV3_INIT_MAP_EVENT(armv8_cortex_a35, armv8_a53_map_event) 1366 PMUV3_INIT_MAP_EVENT(armv8_cortex_a53, armv8_a53_map_event) 1367 PMUV3_INIT_MAP_EVENT(armv8_cortex_a57, armv8_a57_map_event) 1368 PMUV3_INIT_MAP_EVENT(armv8_cortex_a72, armv8_a57_map_event) 1369 PMUV3_INIT_MAP_EVENT(armv8_cortex_a73, armv8_a73_map_event) 1370 PMUV3_INIT_MAP_EVENT(armv8_cavium_thunder, armv8_thunder_map_event) 1371 PMUV3_INIT_MAP_EVENT(armv8_brcm_vulcan, armv8_vulcan_map_event) 1372 1373 static const struct of_device_id armv8_pmu_of_device_ids[] = { 1374 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init}, 1375 {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init}, 1376 {.compatible = "arm,cortex-a35-pmu", .data = armv8_cortex_a35_pmu_init}, 1377 {.compatible = "arm,cortex-a53-pmu", .data = armv8_cortex_a53_pmu_init}, 1378 {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init}, 1379 {.compatible = "arm,cortex-a57-pmu", .data = armv8_cortex_a57_pmu_init}, 1380 {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init}, 1381 {.compatible = "arm,cortex-a72-pmu", .data = armv8_cortex_a72_pmu_init}, 1382 {.compatible = "arm,cortex-a73-pmu", .data = armv8_cortex_a73_pmu_init}, 1383 {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init}, 1384 {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init}, 1385 {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init}, 1386 {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init}, 1387 {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init}, 1388 {.compatible = "arm,cortex-a520-pmu", .data = armv9_cortex_a520_pmu_init}, 1389 {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init}, 1390 {.compatible = "arm,cortex-a715-pmu", .data = armv9_cortex_a715_pmu_init}, 1391 {.compatible = "arm,cortex-a720-pmu", .data = armv9_cortex_a720_pmu_init}, 1392 {.compatible = "arm,cortex-a725-pmu", .data = armv9_cortex_a725_pmu_init}, 1393 {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init}, 1394 {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init}, 1395 {.compatible = "arm,cortex-x3-pmu", .data = armv9_cortex_x3_pmu_init}, 1396 {.compatible = "arm,cortex-x4-pmu", .data = armv9_cortex_x4_pmu_init}, 1397 {.compatible = "arm,cortex-x925-pmu", .data = armv9_cortex_x925_pmu_init}, 1398 {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init}, 1399 {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init}, 1400 {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init}, 1401 {.compatible = "arm,neoverse-n3-pmu", .data = armv9_neoverse_n3_pmu_init}, 1402 {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init}, 1403 {.compatible = "arm,neoverse-v2-pmu", .data = armv8_neoverse_v2_pmu_init}, 1404 {.compatible = "arm,neoverse-v3-pmu", .data = armv8_neoverse_v3_pmu_init}, 1405 {.compatible = "arm,neoverse-v3ae-pmu", .data = armv8_neoverse_v3ae_pmu_init}, 1406 {.compatible = "cavium,thunder-pmu", .data = armv8_cavium_thunder_pmu_init}, 1407 {.compatible = "brcm,vulcan-pmu", .data = armv8_brcm_vulcan_pmu_init}, 1408 {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init}, 1409 {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init}, 1410 {}, 1411 }; 1412 1413 static int armv8_pmu_device_probe(struct platform_device *pdev) 1414 { 1415 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL); 1416 } 1417 1418 static struct platform_driver armv8_pmu_driver = { 1419 .driver = { 1420 .name = ARMV8_PMU_PDEV_NAME, 1421 .of_match_table = armv8_pmu_of_device_ids, 1422 .suppress_bind_attrs = true, 1423 }, 1424 .probe = armv8_pmu_device_probe, 1425 }; 1426 1427 static int __init armv8_pmu_driver_init(void) 1428 { 1429 int ret; 1430 1431 if (acpi_disabled) 1432 ret = platform_driver_register(&armv8_pmu_driver); 1433 else 1434 ret = arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); 1435 1436 if (!ret) 1437 lockup_detector_retry_init(); 1438 1439 return ret; 1440 } 1441 device_initcall(armv8_pmu_driver_init) 1442 1443 void arch_perf_update_userpage(struct perf_event *event, 1444 struct perf_event_mmap_page *userpg, u64 now) 1445 { 1446 struct clock_read_data *rd; 1447 unsigned int seq; 1448 u64 ns; 1449 1450 userpg->cap_user_time = 0; 1451 userpg->cap_user_time_zero = 0; 1452 userpg->cap_user_time_short = 0; 1453 userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event); 1454 1455 if (userpg->cap_user_rdpmc) { 1456 if (event->hw.flags & ARMPMU_EVT_64BIT) 1457 userpg->pmc_width = 64; 1458 else 1459 userpg->pmc_width = 32; 1460 } 1461 1462 do { 1463 rd = sched_clock_read_begin(&seq); 1464 1465 if (rd->read_sched_clock != arch_timer_read_counter) 1466 return; 1467 1468 userpg->time_mult = rd->mult; 1469 userpg->time_shift = rd->shift; 1470 userpg->time_zero = rd->epoch_ns; 1471 userpg->time_cycles = rd->epoch_cyc; 1472 userpg->time_mask = rd->sched_clock_mask; 1473 1474 /* 1475 * Subtract the cycle base, such that software that 1476 * doesn't know about cap_user_time_short still 'works' 1477 * assuming no wraps. 1478 */ 1479 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift); 1480 userpg->time_zero -= ns; 1481 1482 } while (sched_clock_read_retry(seq)); 1483 1484 userpg->time_offset = userpg->time_zero - now; 1485 1486 /* 1487 * time_shift is not expected to be greater than 31 due to 1488 * the original published conversion algorithm shifting a 1489 * 32-bit value (now specifies a 64-bit value) - refer 1490 * perf_event_mmap_page documentation in perf_event.h. 1491 */ 1492 if (userpg->time_shift == 32) { 1493 userpg->time_shift = 31; 1494 userpg->time_mult >>= 1; 1495 } 1496 1497 /* 1498 * Internal timekeeping for enabled/running/stopped times 1499 * is always computed with the sched_clock. 1500 */ 1501 userpg->cap_user_time = 1; 1502 userpg->cap_user_time_zero = 1; 1503 userpg->cap_user_time_short = 1; 1504 } 1505