1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ACPI probing code for ARM performance counters. 4 * 5 * Copyright (C) 2017 ARM Ltd. 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/cpumask.h> 10 #include <linux/init.h> 11 #include <linux/irq.h> 12 #include <linux/irqdesc.h> 13 #include <linux/percpu.h> 14 #include <linux/perf/arm_pmu.h> 15 16 #include <asm/cpu.h> 17 #include <asm/cputype.h> 18 19 static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus); 20 static DEFINE_PER_CPU(int, pmu_irqs); 21 22 static int arm_pmu_acpi_register_irq(int cpu) 23 { 24 struct acpi_madt_generic_interrupt *gicc; 25 int gsi, trigger; 26 27 gicc = acpi_cpu_get_madt_gicc(cpu); 28 29 gsi = gicc->performance_interrupt; 30 31 /* 32 * Per the ACPI spec, the MADT cannot describe a PMU that doesn't 33 * have an interrupt. QEMU advertises this by using a GSI of zero, 34 * which is not known to be valid on any hardware despite being 35 * valid per the spec. Take the pragmatic approach and reject a 36 * GSI of zero for now. 37 */ 38 if (!gsi) 39 return 0; 40 41 if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE) 42 trigger = ACPI_EDGE_SENSITIVE; 43 else 44 trigger = ACPI_LEVEL_SENSITIVE; 45 46 /* 47 * Helpfully, the MADT GICC doesn't have a polarity flag for the 48 * "performance interrupt". Luckily, on compliant GICs the polarity is 49 * a fixed value in HW (for both SPIs and PPIs) that we cannot change 50 * from SW. 51 * 52 * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This 53 * may not match the real polarity, but that should not matter. 54 * 55 * Other interrupt controllers are not supported with ACPI. 56 */ 57 return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH); 58 } 59 60 static void arm_pmu_acpi_unregister_irq(int cpu) 61 { 62 struct acpi_madt_generic_interrupt *gicc; 63 int gsi; 64 65 gicc = acpi_cpu_get_madt_gicc(cpu); 66 67 gsi = gicc->performance_interrupt; 68 if (gsi) 69 acpi_unregister_gsi(gsi); 70 } 71 72 #if IS_ENABLED(CONFIG_ARM_SPE_PMU) 73 static struct resource spe_resources[] = { 74 { 75 /* irq */ 76 .flags = IORESOURCE_IRQ, 77 } 78 }; 79 80 static struct platform_device spe_dev = { 81 .name = ARMV8_SPE_PDEV_NAME, 82 .id = -1, 83 .resource = spe_resources, 84 .num_resources = ARRAY_SIZE(spe_resources) 85 }; 86 87 /* 88 * For lack of a better place, hook the normal PMU MADT walk 89 * and create a SPE device if we detect a recent MADT with 90 * a homogeneous PPI mapping. 91 */ 92 static void arm_spe_acpi_register_device(void) 93 { 94 int cpu, hetid, irq, ret; 95 bool first = true; 96 u16 gsi = 0; 97 98 /* 99 * Sanity check all the GICC tables for the same interrupt number. 100 * For now, we only support homogeneous ACPI/SPE machines. 101 */ 102 for_each_possible_cpu(cpu) { 103 struct acpi_madt_generic_interrupt *gicc; 104 105 gicc = acpi_cpu_get_madt_gicc(cpu); 106 if (gicc->header.length < ACPI_MADT_GICC_SPE) 107 return; 108 109 if (first) { 110 gsi = gicc->spe_interrupt; 111 if (!gsi) 112 return; 113 hetid = find_acpi_cpu_topology_hetero_id(cpu); 114 first = false; 115 } else if ((gsi != gicc->spe_interrupt) || 116 (hetid != find_acpi_cpu_topology_hetero_id(cpu))) { 117 pr_warn("ACPI: SPE must be homogeneous\n"); 118 return; 119 } 120 } 121 122 irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, 123 ACPI_ACTIVE_HIGH); 124 if (irq < 0) { 125 pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi); 126 return; 127 } 128 129 spe_resources[0].start = irq; 130 ret = platform_device_register(&spe_dev); 131 if (ret < 0) { 132 pr_warn("ACPI: SPE: Unable to register device\n"); 133 acpi_unregister_gsi(gsi); 134 } 135 } 136 #else 137 static inline void arm_spe_acpi_register_device(void) 138 { 139 } 140 #endif /* CONFIG_ARM_SPE_PMU */ 141 142 static int arm_pmu_acpi_parse_irqs(void) 143 { 144 int irq, cpu, irq_cpu, err; 145 146 for_each_possible_cpu(cpu) { 147 irq = arm_pmu_acpi_register_irq(cpu); 148 if (irq < 0) { 149 err = irq; 150 pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n", 151 cpu, err); 152 goto out_err; 153 } else if (irq == 0) { 154 pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu); 155 } 156 157 /* 158 * Log and request the IRQ so the core arm_pmu code can manage 159 * it. We'll have to sanity-check IRQs later when we associate 160 * them with their PMUs. 161 */ 162 per_cpu(pmu_irqs, cpu) = irq; 163 err = armpmu_request_irq(irq, cpu); 164 if (err) 165 goto out_err; 166 } 167 168 return 0; 169 170 out_err: 171 for_each_possible_cpu(cpu) { 172 irq = per_cpu(pmu_irqs, cpu); 173 if (!irq) 174 continue; 175 176 arm_pmu_acpi_unregister_irq(cpu); 177 178 /* 179 * Blat all copies of the IRQ so that we only unregister the 180 * corresponding GSI once (e.g. when we have PPIs). 181 */ 182 for_each_possible_cpu(irq_cpu) { 183 if (per_cpu(pmu_irqs, irq_cpu) == irq) 184 per_cpu(pmu_irqs, irq_cpu) = 0; 185 } 186 } 187 188 return err; 189 } 190 191 static struct arm_pmu *arm_pmu_acpi_find_pmu(void) 192 { 193 unsigned long cpuid = read_cpuid_id(); 194 struct arm_pmu *pmu; 195 int cpu; 196 197 for_each_possible_cpu(cpu) { 198 pmu = per_cpu(probed_pmus, cpu); 199 if (!pmu || pmu->acpi_cpuid != cpuid) 200 continue; 201 202 return pmu; 203 } 204 205 return NULL; 206 } 207 208 /* 209 * Check whether the new IRQ is compatible with those already associated with 210 * the PMU (e.g. we don't have mismatched PPIs). 211 */ 212 static bool pmu_irq_matches(struct arm_pmu *pmu, int irq) 213 { 214 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; 215 int cpu; 216 217 if (!irq) 218 return true; 219 220 for_each_cpu(cpu, &pmu->supported_cpus) { 221 int other_irq = per_cpu(hw_events->irq, cpu); 222 if (!other_irq) 223 continue; 224 225 if (irq == other_irq) 226 continue; 227 if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq)) 228 continue; 229 230 pr_warn("mismatched PPIs detected\n"); 231 return false; 232 } 233 234 return true; 235 } 236 237 static void arm_pmu_acpi_associate_pmu_cpu(struct arm_pmu *pmu, 238 unsigned int cpu) 239 { 240 int irq = per_cpu(pmu_irqs, cpu); 241 242 per_cpu(probed_pmus, cpu) = pmu; 243 244 if (pmu_irq_matches(pmu, irq)) { 245 struct pmu_hw_events __percpu *hw_events; 246 hw_events = pmu->hw_events; 247 per_cpu(hw_events->irq, cpu) = irq; 248 } 249 250 cpumask_set_cpu(cpu, &pmu->supported_cpus); 251 } 252 253 /* 254 * This must run before the common arm_pmu hotplug logic, so that we can 255 * associate a CPU and its interrupt before the common code tries to manage the 256 * affinity and so on. 257 * 258 * Note that hotplug events are serialized, so we cannot race with another CPU 259 * coming up. The perf core won't open events while a hotplug event is in 260 * progress. 261 */ 262 static int arm_pmu_acpi_cpu_starting(unsigned int cpu) 263 { 264 struct arm_pmu *pmu; 265 266 /* If we've already probed this CPU, we have nothing to do */ 267 if (per_cpu(probed_pmus, cpu)) 268 return 0; 269 270 pmu = arm_pmu_acpi_find_pmu(); 271 if (!pmu) { 272 pr_warn_ratelimited("Unable to associate CPU%d with a PMU\n", 273 cpu); 274 return 0; 275 } 276 277 arm_pmu_acpi_associate_pmu_cpu(pmu, cpu); 278 return 0; 279 } 280 281 static void arm_pmu_acpi_probe_matching_cpus(struct arm_pmu *pmu, 282 unsigned long cpuid) 283 { 284 int cpu; 285 286 for_each_online_cpu(cpu) { 287 unsigned long cpu_cpuid = per_cpu(cpu_data, cpu).reg_midr; 288 289 if (cpu_cpuid == cpuid) 290 arm_pmu_acpi_associate_pmu_cpu(pmu, cpu); 291 } 292 } 293 294 int arm_pmu_acpi_probe(armpmu_init_fn init_fn) 295 { 296 int pmu_idx = 0; 297 unsigned int cpu; 298 int ret; 299 300 ret = arm_pmu_acpi_parse_irqs(); 301 if (ret) 302 return ret; 303 304 ret = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_ACPI_STARTING, 305 "perf/arm/pmu_acpi:starting", 306 arm_pmu_acpi_cpu_starting, NULL); 307 if (ret) 308 return ret; 309 310 /* 311 * Initialise and register the set of PMUs which we know about right 312 * now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we 313 * could handle late hotplug, but this may lead to deadlock since we 314 * might try to register a hotplug notifier instance from within a 315 * hotplug notifier. 316 * 317 * There's also the problem of having access to the right init_fn, 318 * without tying this too deeply into the "real" PMU driver. 319 * 320 * For the moment, as with the platform/DT case, we need at least one 321 * of a PMU's CPUs to be online at probe time. 322 */ 323 for_each_online_cpu(cpu) { 324 struct arm_pmu *pmu = per_cpu(probed_pmus, cpu); 325 unsigned long cpuid; 326 char *base_name; 327 328 /* If we've already probed this CPU, we have nothing to do */ 329 if (pmu) 330 continue; 331 332 pmu = armpmu_alloc(); 333 if (!pmu) { 334 pr_warn("Unable to allocate PMU for CPU%d\n", 335 cpu); 336 return -ENOMEM; 337 } 338 339 cpuid = per_cpu(cpu_data, cpu).reg_midr; 340 pmu->acpi_cpuid = cpuid; 341 342 arm_pmu_acpi_probe_matching_cpus(pmu, cpuid); 343 344 ret = init_fn(pmu); 345 if (ret == -ENODEV) { 346 /* PMU not handled by this driver, or not present */ 347 continue; 348 } else if (ret) { 349 pr_warn("Unable to initialise PMU for CPU%d\n", cpu); 350 return ret; 351 } 352 353 base_name = pmu->name; 354 pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++); 355 if (!pmu->name) { 356 pr_warn("Unable to allocate PMU name for CPU%d\n", cpu); 357 return -ENOMEM; 358 } 359 360 ret = armpmu_register(pmu); 361 if (ret) { 362 pr_warn("Failed to register PMU for CPU%d\n", cpu); 363 kfree(pmu->name); 364 return ret; 365 } 366 } 367 368 return ret; 369 } 370 371 static int arm_pmu_acpi_init(void) 372 { 373 if (acpi_disabled) 374 return 0; 375 376 arm_spe_acpi_register_device(); 377 378 return 0; 379 } 380 subsys_initcall(arm_pmu_acpi_init) 381