xref: /linux/drivers/perf/arm_pmu.c (revision 680e6ffa15103ab610c0fc1241d2f98c801b13e2)
1 #undef DEBUG
2 
3 /*
4  * ARM performance counter support.
5  *
6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
8  *
9  * This code is based on the sparc64 perf event code, which is in turn based
10  * on the x86 code.
11  */
12 #define pr_fmt(fmt) "hw perfevents: " fmt
13 
14 #include <linux/bitmap.h>
15 #include <linux/cpumask.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/export.h>
18 #include <linux/kernel.h>
19 #include <linux/perf/arm_pmu.h>
20 #include <linux/slab.h>
21 #include <linux/sched/clock.h>
22 #include <linux/spinlock.h>
23 #include <linux/irq.h>
24 #include <linux/irqdesc.h>
25 
26 #include <asm/irq_regs.h>
27 
28 static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
29 static DEFINE_PER_CPU(int, cpu_irq);
30 
31 static inline u64 arm_pmu_event_max_period(struct perf_event *event)
32 {
33 	if (event->hw.flags & ARMPMU_EVT_64BIT)
34 		return GENMASK_ULL(63, 0);
35 	else
36 		return GENMASK_ULL(31, 0);
37 }
38 
39 static int
40 armpmu_map_cache_event(const unsigned (*cache_map)
41 				      [PERF_COUNT_HW_CACHE_MAX]
42 				      [PERF_COUNT_HW_CACHE_OP_MAX]
43 				      [PERF_COUNT_HW_CACHE_RESULT_MAX],
44 		       u64 config)
45 {
46 	unsigned int cache_type, cache_op, cache_result, ret;
47 
48 	cache_type = (config >>  0) & 0xff;
49 	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
50 		return -EINVAL;
51 
52 	cache_op = (config >>  8) & 0xff;
53 	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
54 		return -EINVAL;
55 
56 	cache_result = (config >> 16) & 0xff;
57 	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
58 		return -EINVAL;
59 
60 	if (!cache_map)
61 		return -ENOENT;
62 
63 	ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
64 
65 	if (ret == CACHE_OP_UNSUPPORTED)
66 		return -ENOENT;
67 
68 	return ret;
69 }
70 
71 static int
72 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
73 {
74 	int mapping;
75 
76 	if (config >= PERF_COUNT_HW_MAX)
77 		return -EINVAL;
78 
79 	if (!event_map)
80 		return -ENOENT;
81 
82 	mapping = (*event_map)[config];
83 	return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
84 }
85 
86 static int
87 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
88 {
89 	return (int)(config & raw_event_mask);
90 }
91 
92 int
93 armpmu_map_event(struct perf_event *event,
94 		 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
95 		 const unsigned (*cache_map)
96 				[PERF_COUNT_HW_CACHE_MAX]
97 				[PERF_COUNT_HW_CACHE_OP_MAX]
98 				[PERF_COUNT_HW_CACHE_RESULT_MAX],
99 		 u32 raw_event_mask)
100 {
101 	u64 config = event->attr.config;
102 	int type = event->attr.type;
103 
104 	if (type == event->pmu->type)
105 		return armpmu_map_raw_event(raw_event_mask, config);
106 
107 	switch (type) {
108 	case PERF_TYPE_HARDWARE:
109 		return armpmu_map_hw_event(event_map, config);
110 	case PERF_TYPE_HW_CACHE:
111 		return armpmu_map_cache_event(cache_map, config);
112 	case PERF_TYPE_RAW:
113 		return armpmu_map_raw_event(raw_event_mask, config);
114 	}
115 
116 	return -ENOENT;
117 }
118 
119 int armpmu_event_set_period(struct perf_event *event)
120 {
121 	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
122 	struct hw_perf_event *hwc = &event->hw;
123 	s64 left = local64_read(&hwc->period_left);
124 	s64 period = hwc->sample_period;
125 	u64 max_period;
126 	int ret = 0;
127 
128 	max_period = arm_pmu_event_max_period(event);
129 	if (unlikely(left <= -period)) {
130 		left = period;
131 		local64_set(&hwc->period_left, left);
132 		hwc->last_period = period;
133 		ret = 1;
134 	}
135 
136 	if (unlikely(left <= 0)) {
137 		left += period;
138 		local64_set(&hwc->period_left, left);
139 		hwc->last_period = period;
140 		ret = 1;
141 	}
142 
143 	/*
144 	 * Limit the maximum period to prevent the counter value
145 	 * from overtaking the one we are about to program. In
146 	 * effect we are reducing max_period to account for
147 	 * interrupt latency (and we are being very conservative).
148 	 */
149 	if (left > (max_period >> 1))
150 		left = (max_period >> 1);
151 
152 	local64_set(&hwc->prev_count, (u64)-left);
153 
154 	armpmu->write_counter(event, (u64)(-left) & max_period);
155 
156 	perf_event_update_userpage(event);
157 
158 	return ret;
159 }
160 
161 u64 armpmu_event_update(struct perf_event *event)
162 {
163 	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
164 	struct hw_perf_event *hwc = &event->hw;
165 	u64 delta, prev_raw_count, new_raw_count;
166 	u64 max_period = arm_pmu_event_max_period(event);
167 
168 again:
169 	prev_raw_count = local64_read(&hwc->prev_count);
170 	new_raw_count = armpmu->read_counter(event);
171 
172 	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
173 			     new_raw_count) != prev_raw_count)
174 		goto again;
175 
176 	delta = (new_raw_count - prev_raw_count) & max_period;
177 
178 	local64_add(delta, &event->count);
179 	local64_sub(delta, &hwc->period_left);
180 
181 	return new_raw_count;
182 }
183 
184 static void
185 armpmu_read(struct perf_event *event)
186 {
187 	armpmu_event_update(event);
188 }
189 
190 static void
191 armpmu_stop(struct perf_event *event, int flags)
192 {
193 	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
194 	struct hw_perf_event *hwc = &event->hw;
195 
196 	/*
197 	 * ARM pmu always has to update the counter, so ignore
198 	 * PERF_EF_UPDATE, see comments in armpmu_start().
199 	 */
200 	if (!(hwc->state & PERF_HES_STOPPED)) {
201 		armpmu->disable(event);
202 		armpmu_event_update(event);
203 		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
204 	}
205 }
206 
207 static void armpmu_start(struct perf_event *event, int flags)
208 {
209 	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
210 	struct hw_perf_event *hwc = &event->hw;
211 
212 	/*
213 	 * ARM pmu always has to reprogram the period, so ignore
214 	 * PERF_EF_RELOAD, see the comment below.
215 	 */
216 	if (flags & PERF_EF_RELOAD)
217 		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
218 
219 	hwc->state = 0;
220 	/*
221 	 * Set the period again. Some counters can't be stopped, so when we
222 	 * were stopped we simply disabled the IRQ source and the counter
223 	 * may have been left counting. If we don't do this step then we may
224 	 * get an interrupt too soon or *way* too late if the overflow has
225 	 * happened since disabling.
226 	 */
227 	armpmu_event_set_period(event);
228 	armpmu->enable(event);
229 }
230 
231 static void
232 armpmu_del(struct perf_event *event, int flags)
233 {
234 	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
235 	struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
236 	struct hw_perf_event *hwc = &event->hw;
237 	int idx = hwc->idx;
238 
239 	armpmu_stop(event, PERF_EF_UPDATE);
240 	hw_events->events[idx] = NULL;
241 	armpmu->clear_event_idx(hw_events, event);
242 	perf_event_update_userpage(event);
243 	/* Clear the allocated counter */
244 	hwc->idx = -1;
245 }
246 
247 static int
248 armpmu_add(struct perf_event *event, int flags)
249 {
250 	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
251 	struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
252 	struct hw_perf_event *hwc = &event->hw;
253 	int idx;
254 
255 	/* An event following a process won't be stopped earlier */
256 	if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
257 		return -ENOENT;
258 
259 	/* If we don't have a space for the counter then finish early. */
260 	idx = armpmu->get_event_idx(hw_events, event);
261 	if (idx < 0)
262 		return idx;
263 
264 	/*
265 	 * If there is an event in the counter we are going to use then make
266 	 * sure it is disabled.
267 	 */
268 	event->hw.idx = idx;
269 	armpmu->disable(event);
270 	hw_events->events[idx] = event;
271 
272 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
273 	if (flags & PERF_EF_START)
274 		armpmu_start(event, PERF_EF_RELOAD);
275 
276 	/* Propagate our changes to the userspace mapping. */
277 	perf_event_update_userpage(event);
278 
279 	return 0;
280 }
281 
282 static int
283 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
284 			       struct perf_event *event)
285 {
286 	struct arm_pmu *armpmu;
287 
288 	if (is_software_event(event))
289 		return 1;
290 
291 	/*
292 	 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
293 	 * core perf code won't check that the pmu->ctx == leader->ctx
294 	 * until after pmu->event_init(event).
295 	 */
296 	if (event->pmu != pmu)
297 		return 0;
298 
299 	if (event->state < PERF_EVENT_STATE_OFF)
300 		return 1;
301 
302 	if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
303 		return 1;
304 
305 	armpmu = to_arm_pmu(event->pmu);
306 	return armpmu->get_event_idx(hw_events, event) >= 0;
307 }
308 
309 static int
310 validate_group(struct perf_event *event)
311 {
312 	struct perf_event *sibling, *leader = event->group_leader;
313 	struct pmu_hw_events fake_pmu;
314 
315 	/*
316 	 * Initialise the fake PMU. We only need to populate the
317 	 * used_mask for the purposes of validation.
318 	 */
319 	memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
320 
321 	if (!validate_event(event->pmu, &fake_pmu, leader))
322 		return -EINVAL;
323 
324 	for_each_sibling_event(sibling, leader) {
325 		if (!validate_event(event->pmu, &fake_pmu, sibling))
326 			return -EINVAL;
327 	}
328 
329 	if (!validate_event(event->pmu, &fake_pmu, event))
330 		return -EINVAL;
331 
332 	return 0;
333 }
334 
335 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
336 {
337 	struct arm_pmu *armpmu;
338 	int ret;
339 	u64 start_clock, finish_clock;
340 
341 	/*
342 	 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
343 	 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
344 	 * do any necessary shifting, we just need to perform the first
345 	 * dereference.
346 	 */
347 	armpmu = *(void **)dev;
348 	if (WARN_ON_ONCE(!armpmu))
349 		return IRQ_NONE;
350 
351 	start_clock = sched_clock();
352 	ret = armpmu->handle_irq(armpmu);
353 	finish_clock = sched_clock();
354 
355 	perf_sample_event_took(finish_clock - start_clock);
356 	return ret;
357 }
358 
359 static int
360 __hw_perf_event_init(struct perf_event *event)
361 {
362 	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
363 	struct hw_perf_event *hwc = &event->hw;
364 	int mapping;
365 
366 	hwc->flags = 0;
367 	mapping = armpmu->map_event(event);
368 
369 	if (mapping < 0) {
370 		pr_debug("event %x:%llx not supported\n", event->attr.type,
371 			 event->attr.config);
372 		return mapping;
373 	}
374 
375 	/*
376 	 * We don't assign an index until we actually place the event onto
377 	 * hardware. Use -1 to signify that we haven't decided where to put it
378 	 * yet. For SMP systems, each core has it's own PMU so we can't do any
379 	 * clever allocation or constraints checking at this point.
380 	 */
381 	hwc->idx		= -1;
382 	hwc->config_base	= 0;
383 	hwc->config		= 0;
384 	hwc->event_base		= 0;
385 
386 	/*
387 	 * Check whether we need to exclude the counter from certain modes.
388 	 */
389 	if (armpmu->set_event_filter &&
390 	    armpmu->set_event_filter(hwc, &event->attr)) {
391 		pr_debug("ARM performance counters do not support "
392 			 "mode exclusion\n");
393 		return -EOPNOTSUPP;
394 	}
395 
396 	/*
397 	 * Store the event encoding into the config_base field.
398 	 */
399 	hwc->config_base	    |= (unsigned long)mapping;
400 
401 	if (!is_sampling_event(event)) {
402 		/*
403 		 * For non-sampling runs, limit the sample_period to half
404 		 * of the counter width. That way, the new counter value
405 		 * is far less likely to overtake the previous one unless
406 		 * you have some serious IRQ latency issues.
407 		 */
408 		hwc->sample_period  = arm_pmu_event_max_period(event) >> 1;
409 		hwc->last_period    = hwc->sample_period;
410 		local64_set(&hwc->period_left, hwc->sample_period);
411 	}
412 
413 	if (event->group_leader != event) {
414 		if (validate_group(event) != 0)
415 			return -EINVAL;
416 	}
417 
418 	return 0;
419 }
420 
421 static int armpmu_event_init(struct perf_event *event)
422 {
423 	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
424 
425 	/*
426 	 * Reject CPU-affine events for CPUs that are of a different class to
427 	 * that which this PMU handles. Process-following events (where
428 	 * event->cpu == -1) can be migrated between CPUs, and thus we have to
429 	 * reject them later (in armpmu_add) if they're scheduled on a
430 	 * different class of CPU.
431 	 */
432 	if (event->cpu != -1 &&
433 		!cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
434 		return -ENOENT;
435 
436 	/* does not support taken branch sampling */
437 	if (has_branch_stack(event))
438 		return -EOPNOTSUPP;
439 
440 	if (armpmu->map_event(event) == -ENOENT)
441 		return -ENOENT;
442 
443 	return __hw_perf_event_init(event);
444 }
445 
446 static void armpmu_enable(struct pmu *pmu)
447 {
448 	struct arm_pmu *armpmu = to_arm_pmu(pmu);
449 	struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
450 	int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
451 
452 	/* For task-bound events we may be called on other CPUs */
453 	if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
454 		return;
455 
456 	if (enabled)
457 		armpmu->start(armpmu);
458 }
459 
460 static void armpmu_disable(struct pmu *pmu)
461 {
462 	struct arm_pmu *armpmu = to_arm_pmu(pmu);
463 
464 	/* For task-bound events we may be called on other CPUs */
465 	if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
466 		return;
467 
468 	armpmu->stop(armpmu);
469 }
470 
471 /*
472  * In heterogeneous systems, events are specific to a particular
473  * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
474  * the same microarchitecture.
475  */
476 static int armpmu_filter_match(struct perf_event *event)
477 {
478 	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
479 	unsigned int cpu = smp_processor_id();
480 	int ret;
481 
482 	ret = cpumask_test_cpu(cpu, &armpmu->supported_cpus);
483 	if (ret && armpmu->filter_match)
484 		return armpmu->filter_match(event);
485 
486 	return ret;
487 }
488 
489 static ssize_t armpmu_cpumask_show(struct device *dev,
490 				   struct device_attribute *attr, char *buf)
491 {
492 	struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
493 	return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
494 }
495 
496 static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
497 
498 static struct attribute *armpmu_common_attrs[] = {
499 	&dev_attr_cpus.attr,
500 	NULL,
501 };
502 
503 static struct attribute_group armpmu_common_attr_group = {
504 	.attrs = armpmu_common_attrs,
505 };
506 
507 /* Set at runtime when we know what CPU type we are. */
508 static struct arm_pmu *__oprofile_cpu_pmu;
509 
510 /*
511  * Despite the names, these two functions are CPU-specific and are used
512  * by the OProfile/perf code.
513  */
514 const char *perf_pmu_name(void)
515 {
516 	if (!__oprofile_cpu_pmu)
517 		return NULL;
518 
519 	return __oprofile_cpu_pmu->name;
520 }
521 EXPORT_SYMBOL_GPL(perf_pmu_name);
522 
523 int perf_num_counters(void)
524 {
525 	int max_events = 0;
526 
527 	if (__oprofile_cpu_pmu != NULL)
528 		max_events = __oprofile_cpu_pmu->num_events;
529 
530 	return max_events;
531 }
532 EXPORT_SYMBOL_GPL(perf_num_counters);
533 
534 static int armpmu_count_irq_users(const int irq)
535 {
536 	int cpu, count = 0;
537 
538 	for_each_possible_cpu(cpu) {
539 		if (per_cpu(cpu_irq, cpu) == irq)
540 			count++;
541 	}
542 
543 	return count;
544 }
545 
546 void armpmu_free_irq(int irq, int cpu)
547 {
548 	if (per_cpu(cpu_irq, cpu) == 0)
549 		return;
550 	if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
551 		return;
552 
553 	if (!irq_is_percpu_devid(irq))
554 		free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu));
555 	else if (armpmu_count_irq_users(irq) == 1)
556 		free_percpu_irq(irq, &cpu_armpmu);
557 
558 	per_cpu(cpu_irq, cpu) = 0;
559 }
560 
561 int armpmu_request_irq(int irq, int cpu)
562 {
563 	int err = 0;
564 	const irq_handler_t handler = armpmu_dispatch_irq;
565 	if (!irq)
566 		return 0;
567 
568 	if (!irq_is_percpu_devid(irq)) {
569 		unsigned long irq_flags;
570 
571 		err = irq_force_affinity(irq, cpumask_of(cpu));
572 
573 		if (err && num_possible_cpus() > 1) {
574 			pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
575 				irq, cpu);
576 			goto err_out;
577 		}
578 
579 		irq_flags = IRQF_PERCPU |
580 			    IRQF_NOBALANCING |
581 			    IRQF_NO_THREAD;
582 
583 		irq_set_status_flags(irq, IRQ_NOAUTOEN);
584 		err = request_irq(irq, handler, irq_flags, "arm-pmu",
585 				  per_cpu_ptr(&cpu_armpmu, cpu));
586 	} else if (armpmu_count_irq_users(irq) == 0) {
587 		err = request_percpu_irq(irq, handler, "arm-pmu",
588 					 &cpu_armpmu);
589 	}
590 
591 	if (err)
592 		goto err_out;
593 
594 	per_cpu(cpu_irq, cpu) = irq;
595 	return 0;
596 
597 err_out:
598 	pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
599 	return err;
600 }
601 
602 static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
603 {
604 	struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
605 	return per_cpu(hw_events->irq, cpu);
606 }
607 
608 /*
609  * PMU hardware loses all context when a CPU goes offline.
610  * When a CPU is hotplugged back in, since some hardware registers are
611  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
612  * junk values out of them.
613  */
614 static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
615 {
616 	struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
617 	int irq;
618 
619 	if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
620 		return 0;
621 	if (pmu->reset)
622 		pmu->reset(pmu);
623 
624 	per_cpu(cpu_armpmu, cpu) = pmu;
625 
626 	irq = armpmu_get_cpu_irq(pmu, cpu);
627 	if (irq) {
628 		if (irq_is_percpu_devid(irq))
629 			enable_percpu_irq(irq, IRQ_TYPE_NONE);
630 		else
631 			enable_irq(irq);
632 	}
633 
634 	return 0;
635 }
636 
637 static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
638 {
639 	struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
640 	int irq;
641 
642 	if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
643 		return 0;
644 
645 	irq = armpmu_get_cpu_irq(pmu, cpu);
646 	if (irq) {
647 		if (irq_is_percpu_devid(irq))
648 			disable_percpu_irq(irq);
649 		else
650 			disable_irq_nosync(irq);
651 	}
652 
653 	per_cpu(cpu_armpmu, cpu) = NULL;
654 
655 	return 0;
656 }
657 
658 #ifdef CONFIG_CPU_PM
659 static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
660 {
661 	struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
662 	struct perf_event *event;
663 	int idx;
664 
665 	for (idx = 0; idx < armpmu->num_events; idx++) {
666 		event = hw_events->events[idx];
667 		if (!event)
668 			continue;
669 
670 		switch (cmd) {
671 		case CPU_PM_ENTER:
672 			/*
673 			 * Stop and update the counter
674 			 */
675 			armpmu_stop(event, PERF_EF_UPDATE);
676 			break;
677 		case CPU_PM_EXIT:
678 		case CPU_PM_ENTER_FAILED:
679 			 /*
680 			  * Restore and enable the counter.
681 			  * armpmu_start() indirectly calls
682 			  *
683 			  * perf_event_update_userpage()
684 			  *
685 			  * that requires RCU read locking to be functional,
686 			  * wrap the call within RCU_NONIDLE to make the
687 			  * RCU subsystem aware this cpu is not idle from
688 			  * an RCU perspective for the armpmu_start() call
689 			  * duration.
690 			  */
691 			RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
692 			break;
693 		default:
694 			break;
695 		}
696 	}
697 }
698 
699 static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
700 			     void *v)
701 {
702 	struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
703 	struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
704 	int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
705 
706 	if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
707 		return NOTIFY_DONE;
708 
709 	/*
710 	 * Always reset the PMU registers on power-up even if
711 	 * there are no events running.
712 	 */
713 	if (cmd == CPU_PM_EXIT && armpmu->reset)
714 		armpmu->reset(armpmu);
715 
716 	if (!enabled)
717 		return NOTIFY_OK;
718 
719 	switch (cmd) {
720 	case CPU_PM_ENTER:
721 		armpmu->stop(armpmu);
722 		cpu_pm_pmu_setup(armpmu, cmd);
723 		break;
724 	case CPU_PM_EXIT:
725 		cpu_pm_pmu_setup(armpmu, cmd);
726 	case CPU_PM_ENTER_FAILED:
727 		armpmu->start(armpmu);
728 		break;
729 	default:
730 		return NOTIFY_DONE;
731 	}
732 
733 	return NOTIFY_OK;
734 }
735 
736 static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
737 {
738 	cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
739 	return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
740 }
741 
742 static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
743 {
744 	cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
745 }
746 #else
747 static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
748 static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
749 #endif
750 
751 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
752 {
753 	int err;
754 
755 	err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
756 				       &cpu_pmu->node);
757 	if (err)
758 		goto out;
759 
760 	err = cpu_pm_pmu_register(cpu_pmu);
761 	if (err)
762 		goto out_unregister;
763 
764 	return 0;
765 
766 out_unregister:
767 	cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
768 					    &cpu_pmu->node);
769 out:
770 	return err;
771 }
772 
773 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
774 {
775 	cpu_pm_pmu_unregister(cpu_pmu);
776 	cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
777 					    &cpu_pmu->node);
778 }
779 
780 static struct arm_pmu *__armpmu_alloc(gfp_t flags)
781 {
782 	struct arm_pmu *pmu;
783 	int cpu;
784 
785 	pmu = kzalloc(sizeof(*pmu), flags);
786 	if (!pmu) {
787 		pr_info("failed to allocate PMU device!\n");
788 		goto out;
789 	}
790 
791 	pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
792 	if (!pmu->hw_events) {
793 		pr_info("failed to allocate per-cpu PMU data.\n");
794 		goto out_free_pmu;
795 	}
796 
797 	pmu->pmu = (struct pmu) {
798 		.pmu_enable	= armpmu_enable,
799 		.pmu_disable	= armpmu_disable,
800 		.event_init	= armpmu_event_init,
801 		.add		= armpmu_add,
802 		.del		= armpmu_del,
803 		.start		= armpmu_start,
804 		.stop		= armpmu_stop,
805 		.read		= armpmu_read,
806 		.filter_match	= armpmu_filter_match,
807 		.attr_groups	= pmu->attr_groups,
808 		/*
809 		 * This is a CPU PMU potentially in a heterogeneous
810 		 * configuration (e.g. big.LITTLE). This is not an uncore PMU,
811 		 * and we have taken ctx sharing into account (e.g. with our
812 		 * pmu::filter_match callback and pmu::event_init group
813 		 * validation).
814 		 */
815 		.capabilities	= PERF_PMU_CAP_HETEROGENEOUS_CPUS,
816 	};
817 
818 	pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
819 		&armpmu_common_attr_group;
820 
821 	for_each_possible_cpu(cpu) {
822 		struct pmu_hw_events *events;
823 
824 		events = per_cpu_ptr(pmu->hw_events, cpu);
825 		raw_spin_lock_init(&events->pmu_lock);
826 		events->percpu_pmu = pmu;
827 	}
828 
829 	return pmu;
830 
831 out_free_pmu:
832 	kfree(pmu);
833 out:
834 	return NULL;
835 }
836 
837 struct arm_pmu *armpmu_alloc(void)
838 {
839 	return __armpmu_alloc(GFP_KERNEL);
840 }
841 
842 struct arm_pmu *armpmu_alloc_atomic(void)
843 {
844 	return __armpmu_alloc(GFP_ATOMIC);
845 }
846 
847 
848 void armpmu_free(struct arm_pmu *pmu)
849 {
850 	free_percpu(pmu->hw_events);
851 	kfree(pmu);
852 }
853 
854 int armpmu_register(struct arm_pmu *pmu)
855 {
856 	int ret;
857 
858 	ret = cpu_pmu_init(pmu);
859 	if (ret)
860 		return ret;
861 
862 	if (!pmu->set_event_filter)
863 		pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
864 
865 	ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
866 	if (ret)
867 		goto out_destroy;
868 
869 	if (!__oprofile_cpu_pmu)
870 		__oprofile_cpu_pmu = pmu;
871 
872 	pr_info("enabled with %s PMU driver, %d counters available\n",
873 		pmu->name, pmu->num_events);
874 
875 	return 0;
876 
877 out_destroy:
878 	cpu_pmu_destroy(pmu);
879 	return ret;
880 }
881 
882 static int arm_pmu_hp_init(void)
883 {
884 	int ret;
885 
886 	ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
887 				      "perf/arm/pmu:starting",
888 				      arm_perf_starting_cpu,
889 				      arm_perf_teardown_cpu);
890 	if (ret)
891 		pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
892 		       ret);
893 	return ret;
894 }
895 subsys_initcall(arm_pmu_hp_init);
896