1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * ARM CoreSight Architecture PMU driver. 4 * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. 5 * 6 */ 7 8 #ifndef __ARM_CSPMU_H__ 9 #define __ARM_CSPMU_H__ 10 11 #include <linux/bitfield.h> 12 #include <linux/cpumask.h> 13 #include <linux/device.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/perf_event.h> 17 #include <linux/platform_device.h> 18 #include <linux/types.h> 19 20 #define to_arm_cspmu(p) (container_of(p, struct arm_cspmu, pmu)) 21 22 #define ARM_CSPMU_EXT_ATTR(_name, _func, _config) \ 23 (&((struct dev_ext_attribute[]){ \ 24 { \ 25 .attr = __ATTR(_name, 0444, _func, NULL), \ 26 .var = (void *)_config \ 27 } \ 28 })[0].attr.attr) 29 30 #define ARM_CSPMU_FORMAT_ATTR(_name, _config) \ 31 ARM_CSPMU_EXT_ATTR(_name, device_show_string, _config) 32 33 #define ARM_CSPMU_EVENT_ATTR(_name, _config) \ 34 PMU_EVENT_ATTR_ID(_name, arm_cspmu_sysfs_event_show, _config) 35 36 37 /* Default event id mask */ 38 #define ARM_CSPMU_EVENT_MASK GENMASK_ULL(63, 0) 39 40 /* Default filter value mask */ 41 #define ARM_CSPMU_FILTER_MASK GENMASK_ULL(63, 0) 42 43 /* Default event format */ 44 #define ARM_CSPMU_FORMAT_EVENT_ATTR \ 45 ARM_CSPMU_FORMAT_ATTR(event, "config:0-32") 46 47 /* Default filter format */ 48 #define ARM_CSPMU_FORMAT_FILTER_ATTR \ 49 ARM_CSPMU_FORMAT_ATTR(filter, "config1:0-31") 50 #define ARM_CSPMU_FORMAT_FILTER2_ATTR \ 51 ARM_CSPMU_FORMAT_ATTR(filter2, "config2:0-31") 52 53 /* 54 * This is the default event number for cycle count, if supported, since the 55 * ARM Coresight PMU specification does not define a standard event code 56 * for cycle count. 57 */ 58 #define ARM_CSPMU_EVT_CYCLES_DEFAULT (0x1ULL << 32) 59 60 /* 61 * The ARM Coresight PMU supports up to 256 event counters. 62 * If the counters are larger-than 32-bits, then the PMU includes at 63 * most 128 counters. 64 */ 65 #define ARM_CSPMU_MAX_HW_CNTRS 256 66 67 /* The cycle counter, if implemented, is located at counter[31]. */ 68 #define ARM_CSPMU_CYCLE_CNTR_IDX 31 69 70 /* 71 * CoreSight PMU Arch register offsets. 72 */ 73 #define PMEVCNTR_LO 0x0 74 #define PMEVCNTR_HI 0x4 75 #define PMEVTYPER 0x400 76 #define PMCCFILTR 0x47C 77 #define PMEVFILT2R 0x800 78 #define PMEVFILTR 0xA00 79 #define PMCNTENSET 0xC00 80 #define PMCNTENCLR 0xC20 81 #define PMINTENSET 0xC40 82 #define PMINTENCLR 0xC60 83 #define PMOVSCLR 0xC80 84 #define PMOVSSET 0xCC0 85 #define PMIMPDEF 0xD80 86 #define PMCFGR 0xE00 87 #define PMCR 0xE04 88 #define PMIIDR 0xE08 89 #define PMPIDR0 0xFE0 90 #define PMPIDR1 0xFE4 91 #define PMPIDR2 0xFE8 92 #define PMPIDR3 0xFEC 93 #define PMPIDR4 0xFD0 94 95 /* PMCFGR register field */ 96 #define PMCFGR_NCG GENMASK(31, 28) 97 #define PMCFGR_HDBG BIT(24) 98 #define PMCFGR_TRO BIT(23) 99 #define PMCFGR_SS BIT(22) 100 #define PMCFGR_FZO BIT(21) 101 #define PMCFGR_MSI BIT(20) 102 #define PMCFGR_UEN BIT(19) 103 #define PMCFGR_NA BIT(17) 104 #define PMCFGR_EX BIT(16) 105 #define PMCFGR_CCD BIT(15) 106 #define PMCFGR_CC BIT(14) 107 #define PMCFGR_SIZE GENMASK(13, 8) 108 #define PMCFGR_N GENMASK(7, 0) 109 110 /* PMCR register field */ 111 #define PMCR_TRO BIT(11) 112 #define PMCR_HDBG BIT(10) 113 #define PMCR_FZO BIT(9) 114 #define PMCR_NA BIT(8) 115 #define PMCR_DP BIT(5) 116 #define PMCR_X BIT(4) 117 #define PMCR_D BIT(3) 118 #define PMCR_C BIT(2) 119 #define PMCR_P BIT(1) 120 #define PMCR_E BIT(0) 121 122 /* PMIIDR register field */ 123 #define PMIIDR_IMPLEMENTER GENMASK(11, 0) 124 #define PMIIDR_IMPLEMENTER_DES_0 GENMASK(3, 0) 125 #define PMIIDR_IMPLEMENTER_DES_1 GENMASK(6, 4) 126 #define PMIIDR_IMPLEMENTER_DES_2 GENMASK(11, 8) 127 #define PMIIDR_REVISION GENMASK(15, 12) 128 #define PMIIDR_VARIANT GENMASK(19, 16) 129 #define PMIIDR_PRODUCTID GENMASK(31, 20) 130 #define PMIIDR_PRODUCTID_PART_0 GENMASK(27, 20) 131 #define PMIIDR_PRODUCTID_PART_1 GENMASK(31, 28) 132 133 /* PMPIDR0 register field */ 134 #define PMPIDR0_PART_0 GENMASK(7, 0) 135 136 /* PMPIDR1 register field */ 137 #define PMPIDR1_DES_0 GENMASK(7, 4) 138 #define PMPIDR1_PART_1 GENMASK(3, 0) 139 140 /* PMPIDR2 register field */ 141 #define PMPIDR2_REVISION GENMASK(7, 4) 142 #define PMPIDR2_DES_1 GENMASK(2, 0) 143 144 /* PMPIDR3 register field */ 145 #define PMPIDR3_REVAND GENMASK(7, 4) 146 #define PMPIDR3_CMOD GENMASK(3, 0) 147 148 /* PMPIDR4 register field */ 149 #define PMPIDR4_SIZE GENMASK(7, 4) 150 #define PMPIDR4_DES_2 GENMASK(3, 0) 151 152 /* JEDEC-assigned JEP106 identification code */ 153 #define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B 154 #define ARM_CSPMU_IMPL_ID_AMPERE 0xA16 155 156 struct arm_cspmu; 157 158 /* This tracks the events assigned to each counter in the PMU. */ 159 struct arm_cspmu_hw_events { 160 /* The events that are active on the PMU for a given logical index. */ 161 struct perf_event **events; 162 163 /* 164 * Each bit indicates a logical counter is being used (or not) for an 165 * event. If cycle counter is supported and there is a gap between 166 * regular and cycle counter, the last logical counter is mapped to 167 * cycle counter. Otherwise, logical and physical have 1-to-1 mapping. 168 */ 169 DECLARE_BITMAP(used_ctrs, ARM_CSPMU_MAX_HW_CNTRS); 170 }; 171 172 /* Contains ops to query vendor/implementer specific attribute. */ 173 struct arm_cspmu_impl_ops { 174 /* Get event attributes */ 175 struct attribute **(*get_event_attrs)(const struct arm_cspmu *cspmu); 176 /* Get format attributes */ 177 struct attribute **(*get_format_attrs)(const struct arm_cspmu *cspmu); 178 /* Get string identifier */ 179 const char *(*get_identifier)(const struct arm_cspmu *cspmu); 180 /* Get PMU name to register to core perf */ 181 const char *(*get_name)(const struct arm_cspmu *cspmu); 182 /* Check if the event corresponds to cycle count event */ 183 bool (*is_cycle_counter_event)(const struct perf_event *event); 184 /* Decode event type/id from configs */ 185 u32 (*event_type)(const struct perf_event *event); 186 /* Set/reset event filters */ 187 void (*set_cc_filter)(struct arm_cspmu *cspmu, 188 const struct perf_event *event); 189 void (*set_ev_filter)(struct arm_cspmu *cspmu, 190 const struct perf_event *event); 191 void (*reset_ev_filter)(struct arm_cspmu *cspmu, 192 const struct perf_event *event); 193 /* Implementation specific event validation */ 194 int (*validate_event)(struct arm_cspmu *cspmu, 195 struct perf_event *event); 196 /* Hide/show unsupported events */ 197 umode_t (*event_attr_is_visible)(struct kobject *kobj, 198 struct attribute *attr, int unused); 199 }; 200 201 /* Vendor/implementer registration parameter. */ 202 struct arm_cspmu_impl_match { 203 /* Backend module. */ 204 struct module *module; 205 const char *module_name; 206 /* PMIIDR value/mask. */ 207 u32 pmiidr_val; 208 u32 pmiidr_mask; 209 /* Callback to vendor backend to init arm_cspmu_impl::ops. */ 210 int (*impl_init_ops)(struct arm_cspmu *cspmu); 211 }; 212 213 /* Vendor/implementer descriptor. */ 214 struct arm_cspmu_impl { 215 u32 pmiidr; 216 struct module *module; 217 struct arm_cspmu_impl_match *match; 218 struct arm_cspmu_impl_ops ops; 219 void *ctx; 220 }; 221 222 /* Coresight PMU descriptor. */ 223 struct arm_cspmu { 224 struct pmu pmu; 225 struct device *dev; 226 const char *name; 227 const char *identifier; 228 void __iomem *base0; 229 void __iomem *base1; 230 cpumask_t associated_cpus; 231 cpumask_t active_cpu; 232 struct hlist_node cpuhp_node; 233 int irq; 234 235 bool has_atomic_dword; 236 u32 pmcfgr; 237 u32 num_logical_ctrs; 238 u32 num_set_clr_reg; 239 int cycle_counter_logical_idx; 240 241 struct arm_cspmu_hw_events hw_events; 242 const struct attribute_group *attr_groups[5]; 243 244 struct arm_cspmu_impl impl; 245 }; 246 247 /* Default function to show event attribute in sysfs. */ 248 ssize_t arm_cspmu_sysfs_event_show(struct device *dev, 249 struct device_attribute *attr, 250 char *buf); 251 252 /* Register vendor backend. */ 253 int arm_cspmu_impl_register(const struct arm_cspmu_impl_match *impl_match); 254 255 /* Unregister vendor backend. */ 256 void arm_cspmu_impl_unregister(const struct arm_cspmu_impl_match *impl_match); 257 258 #endif /* __ARM_CSPMU_H__ */ 259