1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2016-2020 Arm Limited 3 // ARM CMN/CI interconnect PMU driver 4 5 #include <linux/acpi.h> 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/debugfs.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/perf_event.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/sort.h> 20 21 /* Common register stuff */ 22 #define CMN_NODE_INFO 0x0000 23 #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0) 24 #define CMN_NI_NODE_ID GENMASK_ULL(31, 16) 25 #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) 26 27 #define CMN_CHILD_INFO 0x0080 28 #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0) 29 #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16) 30 31 #define CMN_CHILD_NODE_ADDR GENMASK(29, 0) 32 #define CMN_CHILD_NODE_ISOLATED BIT(30) 33 #define CMN_CHILD_NODE_EXTERNAL BIT(31) 34 35 /* Some implementations use a mesh larger than the architectural max of 12 */ 36 #define CMN_MAX_DIMENSION 14 37 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION) 38 #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4) 39 40 /* Currently XPs are the node type we can have most of; others top out at 128 */ 41 #define CMN_MAX_NODES_PER_EVENT CMN_MAX_XPS 42 43 /* The CFG node has various info besides the discovery tree */ 44 #define CMN_CFGM_PERIPH_ID_01 0x0008 45 #define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7, 0) 46 #define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35, 32) 47 #define CMN_CFGM_PERIPH_ID_23 0x0010 48 #define CMN_CFGM_PID2_REVISION GENMASK_ULL(7, 4) 49 50 #define CMN_CFGM_INFO_GLOBAL 0x0900 51 #define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63) 52 #define CMN_S3_R2_MULTIPLE_DTM_EN BIT_ULL(59) 53 #define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52) 54 #define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50) 55 #define CMN_INFO_DEVICE_ISO_ENABLE BIT_ULL(44) 56 57 #define CMN_CFGM_INFO_GLOBAL_1 0x0908 58 #define CMN_S3_R2_RSP_VC_NUM GENMASK_ULL(11, 9) 59 #define CMN_S3_R2_DAT_VC_NUM GENMASK_ULL(8, 6) 60 #define CMN_S3_R2_SNP_VC_NUM GENMASK_ULL(5, 3) 61 #define CMN_S3_R2_REQ_VC_NUM GENMASK_ULL(2, 0) 62 #define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2) 63 #define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0) 64 65 /* XPs also have some local topology info which has uses too */ 66 #define CMN_MXP__CONNECT_INFO(p) (0x0008 + 8 * (p)) 67 #define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(5, 0) 68 69 #define CMN_MAX_PORTS 6 70 #define CI700_CONNECT_INFO_P2_5_OFFSET 0x10 71 72 /* PMU registers occupy the 3rd 4KB page of each node's region */ 73 #define CMN_PMU_OFFSET 0x2000 74 /* ...except when they don't :( */ 75 #define CMN_S3_R1_DTM_OFFSET 0xa000 76 #define CMN_S3_PMU_OFFSET 0xd900 77 78 /* For most nodes, this is all there is */ 79 #define CMN_PMU_EVENT_SEL 0x000 80 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42) 81 #define CMN__PMU_SN_HOME_SEL GENMASK_ULL(40, 39) 82 #define CMN__PMU_HBT_LBT_SEL GENMASK_ULL(38, 37) 83 #define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35) 84 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */ 85 #define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32) 86 87 /* But then... */ 88 #define CMN__PMU_EVICT_STATE_SEL GENMASK_ULL(54, 52) 89 #define CMN__PMU_ENHANCED_HBT_LBT_SEL GENMASK_ULL(51, 48) 90 #define CMN__PMU_SNP_VC_SEL GENMASK_ULL(47, 46) 91 #define CMN__S3_R2_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(45, 42) 92 #define CMN__S3_R2_SN_HOME_SEL GENMASK_ULL(41, 40) 93 #define CMN__S3_R2_HBT_LBT_SEL GENMASK_ULL(39, 38) 94 #define CMN__S3_R2_CLASS_OCCUP_ID GENMASK_ULL(37, 36) 95 #define CMN__S3_R2_OCCUP1_ID GENMASK_ULL(35, 32) 96 97 /* Some types are designed to coexist with another device in the same node */ 98 #define CMN_CCLA_PMU_EVENT_SEL 0x008 99 #define CMN_HNP_PMU_EVENT_SEL 0x008 100 101 /* DTMs live in the PMU space of XP registers */ 102 #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18) 103 #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00) 104 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19) 105 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17) 106 #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9) 107 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8) 108 #define CMN600_WPn_CONFIG_WP_COMBINE BIT(6) 109 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5) 110 #define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4) 111 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1) 112 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0) 113 #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08) 114 #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10) 115 116 #define CMN_DTM_PMU_CONFIG 0x210 117 #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32) 118 #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00 119 #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04 120 #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10 121 #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16) 122 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4) 123 #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n)) 124 #define CMN__PMEVCNT23_COMBINED BIT(2) 125 #define CMN__PMEVCNT01_COMBINED BIT(1) 126 #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0) 127 128 #define CMN_DTM_PMEVCNT 0x220 129 130 #define CMN_DTM_PMEVCNTSR 0x240 131 132 #define CMN650_DTM_UNIT_INFO 0x0910 133 #define CMN_DTM_UNIT_INFO 0x0960 134 #define CMN_DTM_UNIT_INFO_DTC_DOMAIN GENMASK_ULL(1, 0) 135 136 #define CMN_DTM_NUM_COUNTERS 4 137 /* Want more local counters? Why not replicate the whole DTM! Ugh... */ 138 #define CMN_DTM_OFFSET(n) ((n) * 0x200) 139 140 /* The DTC node is where the magic happens */ 141 #define CMN_DT_DTC_CTL 0x0a00 142 #define CMN_DT_DTC_CTL_DT_EN BIT(0) 143 #define CMN_DT_DTC_CTL_CG_DISABLE BIT(10) 144 145 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */ 146 #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4) 147 #define CMN_DT_PMEVCNT(dtc, n) ((dtc)->pmu_base + _CMN_DT_CNT_REG(n)) 148 #define CMN_DT_PMCCNTR(dtc) ((dtc)->pmu_base + 0x40) 149 150 #define CMN_DT_PMEVCNTSR(dtc, n) ((dtc)->pmu_base + 0x50 + _CMN_DT_CNT_REG(n)) 151 #define CMN_DT_PMCCNTRSR(dtc) ((dtc)->pmu_base + 0x90) 152 153 #define CMN_DT_PMCR(dtc) ((dtc)->pmu_base + 0x100) 154 #define CMN_DT_PMCR_PMU_EN BIT(0) 155 #define CMN_DT_PMCR_CNTR_RST BIT(5) 156 #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6) 157 158 #define CMN_DT_PMOVSR(dtc) ((dtc)->pmu_base + 0x118) 159 #define CMN_DT_PMOVSR_CLR(dtc) ((dtc)->pmu_base + 0x120) 160 161 #define CMN_DT_PMSSR(dtc) ((dtc)->pmu_base + 0x128) 162 #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n) 163 164 #define CMN_DT_PMSRR(dtc) ((dtc)->pmu_base + 0x130) 165 #define CMN_DT_PMSRR_SS_REQ BIT(0) 166 167 #define CMN_DT_NUM_COUNTERS 8 168 #define CMN_MAX_DTCS 4 169 170 /* 171 * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles, 172 * so throwing away one bit to make overflow handling easy is no big deal. 173 */ 174 #define CMN_COUNTER_INIT 0x80000000 175 /* Similarly for the 40-bit cycle counter */ 176 #define CMN_CC_INIT 0x8000000000ULL 177 178 179 /* Event attributes */ 180 #define CMN_CONFIG_TYPE GENMASK_ULL(15, 0) 181 #define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16) 182 #define CMN_CONFIG_FILTER GENMASK_ULL(30, 27) 183 #define CMN_CONFIG_BYNODEID BIT_ULL(31) 184 #define CMN_CONFIG_NODEID GENMASK_ULL(47, 32) 185 #define CMN_CONFIG_FILTER2 GENMASK_ULL(51, 48) 186 187 #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config) 188 #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config) 189 #define CMN_EVENT_FILTER(event) FIELD_GET(CMN_CONFIG_FILTER, (event)->attr.config) 190 #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config) 191 #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config) 192 #define CMN_EVENT_FILTER2(event) FIELD_GET(CMN_CONFIG_FILTER2, (event)->attr.config) 193 194 #define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27) 195 #define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48) 196 #define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51) 197 #define CMN_CONFIG_WP_GRP GENMASK_ULL(57, 56) 198 #define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(58) 199 #define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0) 200 #define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0) 201 202 #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config) 203 #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config) 204 #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config) 205 #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config) 206 #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config) 207 #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1) 208 #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2) 209 210 /* Made-up event IDs for watchpoint direction */ 211 #define CMN_WP_UP 0 212 #define CMN_WP_DOWN 2 213 214 215 /* Internal values for encoding event support */ 216 enum cmn_model { 217 CMN600 = 1, 218 CMN650 = 2, 219 CI700 = 4, 220 CMN700 = 8, 221 CMNS3R01 = 16, 222 CMNS3R2 = 32, 223 /* ...and then we can use bitmap tricks for commonality */ 224 CMN_ANY = -1, 225 NOT_CMN600 = -2, 226 CMN_700ON = ~(CMN700 - 1), 227 CMN_650ON = CMN_700ON | CMN650, 228 CMNS3 = CMNS3R01 | CMNS3R2, 229 }; 230 231 /* Actual part numbers and revision IDs defined by the hardware */ 232 enum cmn_part { 233 PART_CMN600 = 0x434, 234 PART_CMN650 = 0x436, 235 PART_CMN600AE = 0x438, 236 PART_CMN700 = 0x43c, 237 PART_CI700 = 0x43a, 238 PART_CMN_S3 = 0x43e, 239 /* Synthetic part number, overridden to PART_CMN_S3 during discovery */ 240 PART_GRAVITON5 = 0xa5, 241 }; 242 243 /* CMN-600 r0px shouldn't exist in silicon, thankfully */ 244 enum cmn_revision { 245 REV_CMN600_R1P0, 246 REV_CMN600_R1P1, 247 REV_CMN600_R1P2, 248 REV_CMN600_R1P3, 249 REV_CMN600_R2P0, 250 REV_CMN600_R3P0, 251 REV_CMN600_R3P1, 252 REV_CMN650_R0P0 = 0, 253 REV_CMN650_R1P0, 254 REV_CMN650_R1P1, 255 REV_CMN650_R2P0, 256 REV_CMN650_R1P2, 257 REV_CMN700_R0P0 = 0, 258 REV_CMN700_R1P0, 259 REV_CMN700_R2P0, 260 REV_CMN700_R3P0, 261 REV_CMNS3_R0P0 = 0, 262 REV_CMNS3_R0P1, 263 REV_CMNS3_R1P0, 264 REV_CMNS3_R2P0, 265 REV_CMNS3_R2P1, 266 REV_CMNS3_R2P2, 267 REV_CMNS3_R2P5, 268 REV_CI700_R0P0 = 0, 269 REV_CI700_R1P0, 270 REV_CI700_R2P0, 271 }; 272 273 enum cmn_node_type { 274 CMN_TYPE_INVALID, 275 CMN_TYPE_DVM, 276 CMN_TYPE_CFG, 277 CMN_TYPE_DTC, 278 CMN_TYPE_HNI, 279 CMN_TYPE_HNF, 280 CMN_TYPE_XP, 281 CMN_TYPE_SBSX, 282 CMN_TYPE_MPAM_S, 283 CMN_TYPE_MPAM_NS, 284 CMN_TYPE_RNI, 285 CMN_TYPE_RND = 0xd, 286 CMN_TYPE_RNSAM = 0xf, 287 CMN_TYPE_MTSX, 288 CMN_TYPE_HNP, 289 CMN_TYPE_CXRA = 0x100, 290 CMN_TYPE_CXHA, 291 CMN_TYPE_CXLA, 292 CMN_TYPE_CCRA, 293 CMN_TYPE_CCHA, 294 CMN_TYPE_CCLA, 295 CMN_TYPE_CCLA_RNI, 296 CMN_TYPE_HNS = 0x200, 297 CMN_TYPE_HNS_MPAM_S, 298 CMN_TYPE_HNS_MPAM_NS, 299 CMN_TYPE_APB = 0x1000, 300 /* Not a real node type */ 301 CMN_TYPE_WP = 0x7770 302 }; 303 304 enum cmn_filter_select { 305 SEL_NONE, 306 SEL_OCCUP1_ID, 307 SEL_CLASS_OCCUP_ID, 308 SEL_CBUSY_SNTHROTTLE_SEL, 309 SEL_HBT_LBT_SEL, 310 SEL_SN_HOME_SEL, 311 SEL_SNP_VC_SEL, 312 SEL_ENHANCED_HBT_LBT_SEL, 313 SEL_EVICT_STATE_SEL, 314 SEL_MAX 315 }; 316 317 struct arm_cmn_node { 318 void __iomem *pmu_base; 319 u16 id, logid; 320 enum cmn_node_type type; 321 322 /* XP properties really, but replicated to children for convenience */ 323 u8 dtm; 324 s8 dtc; 325 u8 portid_bits:4; 326 u8 deviceid_bits:4; 327 /* DN/HN-F/CXHA */ 328 struct { 329 u8 val : 4; 330 u8 count : 4; 331 } filter[SEL_MAX]; 332 union { 333 u8 event[4]; 334 __le32 event_sel; 335 u16 event_w[4]; 336 __le64 event_sel_w; 337 }; 338 }; 339 340 struct arm_cmn_dtm { 341 void __iomem *base; 342 u32 pmu_config_low; 343 union { 344 u8 input_sel[4]; 345 __le32 pmu_config_high; 346 }; 347 s8 wp_event[4]; 348 }; 349 350 struct arm_cmn_dtc { 351 void __iomem *base; 352 void __iomem *pmu_base; 353 int irq; 354 s8 irq_friend; 355 bool cc_active; 356 357 struct perf_event *counters[CMN_DT_NUM_COUNTERS]; 358 struct perf_event *cycles; 359 }; 360 361 #define CMN_STATE_DISABLED BIT(0) 362 #define CMN_STATE_TXN BIT(1) 363 364 struct arm_cmn { 365 struct device *dev; 366 void __iomem *base; 367 unsigned int state; 368 369 enum cmn_revision rev; 370 enum cmn_part part; 371 u8 mesh_x; 372 u8 mesh_y; 373 u16 num_xps; 374 u16 num_dns; 375 bool multi_dtm; 376 u8 ports_used; 377 struct { 378 unsigned int rsp_vc_num : 2; 379 unsigned int dat_vc_num : 2; 380 unsigned int snp_vc_num : 2; 381 unsigned int req_vc_num : 2; 382 }; 383 384 struct arm_cmn_node *xps; 385 struct arm_cmn_node *dns; 386 387 struct arm_cmn_dtm *dtms; 388 struct arm_cmn_dtc *dtc; 389 unsigned int num_dtcs; 390 391 int cpu; 392 struct hlist_node cpuhp_node; 393 394 struct pmu pmu; 395 struct dentry *debug; 396 }; 397 398 #define to_cmn(p) container_of(p, struct arm_cmn, pmu) 399 400 static int arm_cmn_hp_state; 401 402 struct arm_cmn_nodeid { 403 u8 port; 404 u8 dev; 405 }; 406 407 static int arm_cmn_xyidbits(const struct arm_cmn *cmn) 408 { 409 return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1)); 410 } 411 412 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn_node *dn) 413 { 414 struct arm_cmn_nodeid nid; 415 416 nid.dev = dn->id & ((1U << dn->deviceid_bits) - 1); 417 nid.port = (dn->id >> dn->deviceid_bits) & ((1U << dn->portid_bits) - 1); 418 return nid; 419 } 420 421 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn, 422 const struct arm_cmn_node *dn) 423 { 424 int id = dn->id >> (dn->portid_bits + dn->deviceid_bits); 425 int bits = arm_cmn_xyidbits(cmn); 426 int x = id >> bits; 427 int y = id & ((1U << bits) - 1); 428 429 return cmn->xps + cmn->mesh_x * y + x; 430 } 431 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, 432 enum cmn_node_type type) 433 { 434 struct arm_cmn_node *dn; 435 436 for (dn = cmn->dns; dn->type; dn++) 437 if (dn->type == type) 438 return dn; 439 return NULL; 440 } 441 442 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn) 443 { 444 switch (cmn->part) { 445 case PART_CMN600: 446 return CMN600; 447 case PART_CMN650: 448 return CMN650; 449 case PART_CMN700: 450 return CMN700; 451 case PART_CI700: 452 return CI700; 453 case PART_CMN_S3: 454 if (cmn->rev >= REV_CMNS3_R2P0) 455 return CMNS3R2; 456 return CMNS3R01; 457 default: 458 return 0; 459 }; 460 } 461 462 static int arm_cmn_pmu_offset(const struct arm_cmn *cmn, const struct arm_cmn_node *dn) 463 { 464 if (cmn->part == PART_CMN_S3) { 465 if (cmn->rev >= REV_CMNS3_R1P0 && dn->type == CMN_TYPE_XP) 466 return CMN_S3_R1_DTM_OFFSET; 467 return CMN_S3_PMU_OFFSET; 468 } 469 return CMN_PMU_OFFSET; 470 } 471 472 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn, 473 const struct arm_cmn_node *xp, int port) 474 { 475 int offset = CMN_MXP__CONNECT_INFO(port) - arm_cmn_pmu_offset(cmn, xp); 476 477 if (port >= 2) { 478 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650) 479 return 0; 480 /* 481 * CI-700 may have extra ports, but still has the 482 * mesh_port_connect_info registers in the way. 483 */ 484 if (cmn->part == PART_CI700) 485 offset += CI700_CONNECT_INFO_P2_5_OFFSET; 486 } 487 488 return readl_relaxed(xp->pmu_base + offset); 489 } 490 491 static struct dentry *arm_cmn_debugfs; 492 493 #ifdef CONFIG_DEBUG_FS 494 static const char *arm_cmn_device_type(u8 type) 495 { 496 switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) { 497 case 0x00: return " |"; 498 case 0x01: return " RN-I |"; 499 case 0x02: return " RN-D |"; 500 case 0x04: return " RN-F_B |"; 501 case 0x05: return "RN-F_B_E|"; 502 case 0x06: return " RN-F_A |"; 503 case 0x07: return "RN-F_A_E|"; 504 case 0x08: return " HN-T |"; 505 case 0x09: return " HN-I |"; 506 case 0x0a: return " HN-D |"; 507 case 0x0b: return " HN-P |"; 508 case 0x0c: return " SN-F |"; 509 case 0x0d: return " SBSX |"; 510 case 0x0e: return " HN-F |"; 511 case 0x0f: return " SN-F_E |"; 512 case 0x10: return " SN-F_D |"; 513 case 0x11: return " CXHA |"; 514 case 0x12: return " CXRA |"; 515 case 0x13: return " CXRH |"; 516 case 0x14: return " RN-F_D |"; 517 case 0x15: return "RN-F_D_E|"; 518 case 0x16: return " RN-F_C |"; 519 case 0x17: return "RN-F_C_E|"; 520 case 0x18: return " RN-F_E |"; 521 case 0x19: return "RN-F_E_E|"; 522 case 0x1a: return " HN-S |"; 523 case 0x1b: return " LCN |"; 524 case 0x1c: return " MTSX |"; 525 case 0x1d: return " HN-V |"; 526 case 0x1e: return " CCG |"; 527 case 0x20: return " RN-F_F |"; 528 case 0x21: return "RN-F_F_E|"; 529 case 0x22: return " SN-F_F |"; 530 default: return " ???? |"; 531 } 532 } 533 534 static void arm_cmn_show_logid(struct seq_file *s, const struct arm_cmn_node *xp, int p, int d) 535 { 536 struct arm_cmn *cmn = s->private; 537 struct arm_cmn_node *dn; 538 u16 id = xp->id | d | (p << xp->deviceid_bits); 539 540 for (dn = cmn->dns; dn->type; dn++) { 541 int pad = dn->logid < 10; 542 543 if (dn->type == CMN_TYPE_XP) 544 continue; 545 /* Ignore the extra components that will overlap on some ports */ 546 if (dn->type < CMN_TYPE_HNI) 547 continue; 548 549 if (dn->id != id) 550 continue; 551 552 seq_printf(s, " %*c#%-*d |", pad + 1, ' ', 3 - pad, dn->logid); 553 return; 554 } 555 seq_puts(s, " |"); 556 } 557 558 static int arm_cmn_map_show(struct seq_file *s, void *data) 559 { 560 struct arm_cmn *cmn = s->private; 561 int x, y, p, pmax = fls(cmn->ports_used); 562 563 seq_puts(s, " X"); 564 for (x = 0; x < cmn->mesh_x; x++) 565 seq_printf(s, " %-2d ", x); 566 seq_puts(s, "\nY P D+"); 567 y = cmn->mesh_y; 568 while (y--) { 569 int xp_base = cmn->mesh_x * y; 570 struct arm_cmn_node *xp = cmn->xps + xp_base; 571 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION]; 572 573 for (x = 0; x < cmn->mesh_x; x++) 574 seq_puts(s, "--------+"); 575 576 seq_printf(s, "\n%-2d |", y); 577 for (x = 0; x < cmn->mesh_x; x++) { 578 for (p = 0; p < CMN_MAX_PORTS; p++) 579 port[p][x] = arm_cmn_device_connect_info(cmn, xp + x, p); 580 seq_printf(s, " XP #%-3d|", xp_base + x); 581 } 582 583 seq_puts(s, "\n |"); 584 for (x = 0; x < cmn->mesh_x; x++) { 585 s8 dtc = xp[x].dtc; 586 587 if (dtc < 0) 588 seq_puts(s, " DTC ?? |"); 589 else 590 seq_printf(s, " DTC %d |", dtc); 591 } 592 seq_puts(s, "\n |"); 593 for (x = 0; x < cmn->mesh_x; x++) 594 seq_puts(s, "........|"); 595 596 for (p = 0; p < pmax; p++) { 597 seq_printf(s, "\n %d |", p); 598 for (x = 0; x < cmn->mesh_x; x++) 599 seq_puts(s, arm_cmn_device_type(port[p][x])); 600 seq_puts(s, "\n 0|"); 601 for (x = 0; x < cmn->mesh_x; x++) 602 arm_cmn_show_logid(s, xp + x, p, 0); 603 seq_puts(s, "\n 1|"); 604 for (x = 0; x < cmn->mesh_x; x++) 605 arm_cmn_show_logid(s, xp + x, p, 1); 606 } 607 seq_puts(s, "\n-----+"); 608 } 609 for (x = 0; x < cmn->mesh_x; x++) 610 seq_puts(s, "--------+"); 611 seq_puts(s, "\n"); 612 return 0; 613 } 614 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map); 615 616 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) 617 { 618 const char *name = "map"; 619 620 if (id > 0) 621 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id); 622 if (!name) 623 return; 624 625 cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops); 626 } 627 #else 628 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {} 629 #endif 630 631 enum cmn_filter_type { 632 FILT_NONE, 633 FILT_OCCUP1_ID, 634 FILT_HNF_700, 635 FILT_HNS, 636 FILT_HNS_S3R2, 637 }; 638 #define CMN_FILTER(_sel) [SEL_##_sel] = CMN__PMU_##_sel 639 #define CMN_FILTER_V2(_sel) [SEL_##_sel] = CMN__S3_R2_##_sel 640 641 static const u64 arm_cmn_filters[][SEL_MAX] = { 642 [FILT_NONE] = {}, 643 /* DVM etc. */ 644 [FILT_OCCUP1_ID] = { 645 CMN_FILTER(OCCUP1_ID) 646 }, 647 /* Newer HN-F */ 648 [FILT_HNF_700] = { 649 CMN_FILTER(OCCUP1_ID), 650 CMN_FILTER(CLASS_OCCUP_ID), 651 CMN_FILTER(CBUSY_SNTHROTTLE_SEL) 652 }, 653 /* HN-S */ 654 [FILT_HNS] = { 655 CMN_FILTER(OCCUP1_ID), 656 CMN_FILTER(CLASS_OCCUP_ID), 657 CMN_FILTER(CBUSY_SNTHROTTLE_SEL), 658 CMN_FILTER(HBT_LBT_SEL), 659 CMN_FILTER(SN_HOME_SEL) 660 }, 661 /* Newer HN-S */ 662 [FILT_HNS_S3R2] = { 663 CMN_FILTER_V2(OCCUP1_ID), 664 CMN_FILTER_V2(CLASS_OCCUP_ID), 665 CMN_FILTER_V2(CBUSY_SNTHROTTLE_SEL), 666 CMN_FILTER_V2(HBT_LBT_SEL), 667 CMN_FILTER_V2(SN_HOME_SEL), 668 CMN_FILTER(SNP_VC_SEL), 669 CMN_FILTER(ENHANCED_HBT_LBT_SEL), 670 CMN_FILTER(EVICT_STATE_SEL) 671 } 672 }; 673 674 static enum cmn_filter_type arm_cmn_filter(enum cmn_node_type node, 675 enum cmn_model model) 676 { 677 switch (node) { 678 default: 679 return FILT_NONE; 680 case CMN_TYPE_DVM: 681 case CMN_TYPE_CXRA: 682 case CMN_TYPE_CXHA: 683 case CMN_TYPE_CCRA: 684 case CMN_TYPE_CCHA: 685 return FILT_OCCUP1_ID; 686 case CMN_TYPE_HNF: 687 if (model < CMN700) 688 return FILT_OCCUP1_ID; 689 return FILT_HNF_700; 690 case CMN_TYPE_HNS: 691 if (model < CMNS3R2) 692 return FILT_HNS; 693 return FILT_HNS_S3R2; 694 }; 695 } 696 697 struct arm_cmn_hw_event { 698 struct arm_cmn_node *dn; 699 union { 700 unsigned long *dtm_idx; 701 int cc_idx; 702 }; 703 unsigned long *wp_idx; 704 s8 dtc_idx[CMN_MAX_DTCS]; 705 u8 num_dns; 706 u8 dtm_offset; 707 bool wide_sel; 708 enum cmn_filter_select filter_sel; 709 }; 710 static_assert(sizeof(struct arm_cmn_hw_event) <= offsetof(struct hw_perf_event, target)); 711 712 #define for_each_hw_dn(hw, dn, i) \ 713 for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++) 714 715 /* @i is the DTC number, @idx is the counter index on that DTC */ 716 #define for_each_hw_dtc_idx(hw, i, idx) \ 717 for (int i = 0, idx; i < CMN_MAX_DTCS; i++) if ((idx = hw->dtc_idx[i]) >= 0) 718 719 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event) 720 { 721 return (struct arm_cmn_hw_event *)&event->hw; 722 } 723 724 #define BPL2 (BITS_PER_LONG / 2) 725 726 static void arm_cmn_set_dtm_idx(struct arm_cmn_hw_event *hw, unsigned int pos, unsigned int val) 727 { 728 hw->dtm_idx[pos / BPL2] |= (unsigned long)val << ((pos % BPL2) * 2); 729 } 730 731 static unsigned int arm_cmn_get_dtm_idx(struct arm_cmn_hw_event *hw, unsigned int pos) 732 { 733 return (hw->dtm_idx[pos / BPL2] >> ((pos % BPL2) * 2)) & 3; 734 } 735 736 static unsigned long *arm_cmn_alloc_dtm_idx(void) 737 { 738 return bitmap_zalloc(CMN_MAX_NODES_PER_EVENT * 2, GFP_KERNEL); 739 } 740 741 static void arm_cmn_set_wp_idx(struct arm_cmn_hw_event *hw, unsigned int pos, bool val) 742 { 743 if (val) 744 set_bit(pos, hw->wp_idx); 745 } 746 747 static unsigned int arm_cmn_get_wp_idx(struct arm_cmn_hw_event *hw, unsigned int pos) 748 { 749 return test_bit(pos, hw->wp_idx); 750 } 751 752 static unsigned long *arm_cmn_alloc_wp_idx(void) 753 { 754 return bitmap_zalloc(CMN_MAX_XPS, GFP_KERNEL); 755 } 756 757 static void arm_cmn_clear_idx(struct arm_cmn_hw_event *hw) 758 { 759 bitmap_zero(hw->dtm_idx, CMN_MAX_NODES_PER_EVENT * 2); 760 if (hw->wp_idx) 761 bitmap_zero(hw->wp_idx, CMN_MAX_XPS); 762 } 763 764 struct arm_cmn_filter_attr { 765 enum cmn_filter_select sel; 766 u8 val; 767 }; 768 769 struct arm_cmn_event_attr { 770 struct device_attribute attr; 771 enum cmn_model model; 772 enum cmn_node_type type; 773 u16 eventid; 774 struct arm_cmn_filter_attr filter[2]; 775 }; 776 777 struct arm_cmn_format_attr { 778 struct device_attribute attr; 779 u64 field; 780 int config; 781 }; 782 783 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _fa, _fb, _fc, _fd, ...) \ 784 (&((struct arm_cmn_event_attr[]) {{ \ 785 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \ 786 .model = _model, \ 787 .type = _type, \ 788 .eventid = _eventid, \ 789 .filter = {{_fa, _fb}, {_fc, _fd}}, \ 790 }})[0].attr.attr) 791 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid, _filter...) \ 792 _CMN_EVENT_ATTR(_model, _name, _type, _eventid, ##_filter, 0, 0, 0, 0) 793 794 static ssize_t arm_cmn_event_show(struct device *dev, 795 struct device_attribute *attr, char *buf) 796 { 797 struct arm_cmn_event_attr *eattr; 798 struct arm_cmn_filter_attr *filter; 799 800 eattr = container_of(attr, typeof(*eattr), attr); 801 filter = eattr->filter; 802 803 if (eattr->type == CMN_TYPE_DTC) 804 return sysfs_emit(buf, "type=0x%x\n", eattr->type); 805 806 if (eattr->type == CMN_TYPE_WP) 807 return sysfs_emit(buf, 808 "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n", 809 eattr->type, eattr->eventid); 810 811 if (filter[1].sel) 812 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,filter=0x%x,filter2=0x%x\n", 813 eattr->type, eattr->eventid, filter[0].val, filter[1].val); 814 815 if (filter[0].sel) 816 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,filter=0x%x\n", 817 eattr->type, eattr->eventid, filter[0].val); 818 819 return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type, 820 eattr->eventid); 821 } 822 823 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, 824 struct attribute *attr, 825 int unused) 826 { 827 struct device *dev = kobj_to_dev(kobj); 828 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 829 struct arm_cmn_event_attr *eattr; 830 enum cmn_node_type type; 831 u16 eventid; 832 833 eattr = container_of(attr, typeof(*eattr), attr.attr); 834 835 if (!(eattr->model & arm_cmn_model(cmn))) 836 return 0; 837 838 type = eattr->type; 839 eventid = eattr->eventid; 840 841 /* Watchpoints aren't nodes, so avoid confusion */ 842 if (type == CMN_TYPE_WP) 843 return attr->mode; 844 845 /* Hide XP events for unused interfaces/channels */ 846 if (type == CMN_TYPE_XP) { 847 unsigned int intf = (eventid >> 2) & 7; 848 unsigned int chan = eventid >> 5; 849 850 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3))) 851 return 0; 852 853 if (chan == 4 && cmn->part == PART_CMN600) 854 return 0; 855 856 if ((chan == 5 && cmn->rsp_vc_num < 2) || 857 (chan == 6 && cmn->dat_vc_num < 2) || 858 (chan == 7 && cmn->req_vc_num < 2) || 859 (chan == 8 && cmn->snp_vc_num < 2)) 860 return 0; 861 } 862 863 /* Revision-specific differences */ 864 if (cmn->part == PART_CMN600) { 865 if (cmn->rev < REV_CMN600_R1P3) { 866 if (type == CMN_TYPE_CXRA && eventid > 0x10) 867 return 0; 868 } 869 if (cmn->rev < REV_CMN600_R1P2) { 870 if (type == CMN_TYPE_HNF && eventid == 0x1b) 871 return 0; 872 if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA) 873 return 0; 874 } 875 } else if (cmn->part == PART_CMN650) { 876 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) { 877 if (type == CMN_TYPE_HNF && eventid > 0x22) 878 return 0; 879 if (type == CMN_TYPE_SBSX && eventid == 0x17) 880 return 0; 881 if (type == CMN_TYPE_RNI && eventid > 0x10) 882 return 0; 883 } 884 } else if (cmn->part == PART_CMN700) { 885 if (cmn->rev < REV_CMN700_R2P0) { 886 if (type == CMN_TYPE_HNF && eventid > 0x2c) 887 return 0; 888 if (type == CMN_TYPE_CCHA && eventid > 0x74) 889 return 0; 890 if (type == CMN_TYPE_CCLA && eventid > 0x27) 891 return 0; 892 } 893 if (cmn->rev < REV_CMN700_R1P0) { 894 if (type == CMN_TYPE_HNF && eventid > 0x2b) 895 return 0; 896 } 897 } 898 899 if (!arm_cmn_node(cmn, type)) 900 return 0; 901 902 return attr->mode; 903 } 904 905 #define CMN_EVENT_DVM(_model, _name, _event, _filter...) \ 906 CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, ##_filter) 907 #define CMN_EVENT_DTC(_name) \ 908 CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0) 909 #define CMN_EVENT_HNF(_model, _name, _event) \ 910 CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event) 911 #define CMN_EVENT_HNI(_name, _event) \ 912 CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event) 913 #define CMN_EVENT_HNP(_name, _event) \ 914 CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event) 915 #define __CMN_EVENT_XP(_name, _event) \ 916 CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event) 917 #define CMN_EVENT_SBSX(_model, _name, _event) \ 918 CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event) 919 #define CMN_EVENT_RNID(_model, _name, _event) \ 920 CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event) 921 #define CMN_EVENT_MTSX(_name, _event) \ 922 CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event) 923 #define CMN_EVENT_CXRA(_model, _name, _event) \ 924 CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event) 925 #define CMN_EVENT_CXHA(_name, _event) \ 926 CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event) 927 #define CMN_EVENT_CCRA(_name, _event) \ 928 CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event) 929 #define CMN_EVENT_CCHA(_model, _name, _event) \ 930 CMN_EVENT_ATTR(_model, ccha_##_name, CMN_TYPE_CCHA, _event) 931 #define CMN_EVENT_CCLA(_name, _event) \ 932 CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event) 933 #define _CMN_EVENT_HNS(_model, _name, _event, _filter...) \ 934 CMN_EVENT_ATTR(_model, hns_##_name, CMN_TYPE_HNS, _event, ##_filter) 935 936 #define CMN_EVENT_DVM_OCC(_model, _name, _event) \ 937 CMN_EVENT_DVM(_model, _name##_all, _event, SEL_OCCUP1_ID, 0), \ 938 CMN_EVENT_DVM(_model, _name##_dvmop, _event, SEL_OCCUP1_ID, 1), \ 939 CMN_EVENT_DVM(_model, _name##_dvmsync, _event, SEL_OCCUP1_ID, 2) 940 941 #define CMN_EVENT_HN_OCC(_model, _name, _type, _event) \ 942 CMN_EVENT_ATTR(_model, _name##_all, _type, _event, SEL_OCCUP1_ID, 0), \ 943 CMN_EVENT_ATTR(_model, _name##_read, _type, _event, SEL_OCCUP1_ID, 1), \ 944 CMN_EVENT_ATTR(_model, _name##_write, _type, _event, SEL_OCCUP1_ID, 2), \ 945 CMN_EVENT_ATTR(_model, _name##_atomic, _type, _event, SEL_OCCUP1_ID, 3), \ 946 CMN_EVENT_ATTR(_model, _name##_stash, _type, _event, SEL_OCCUP1_ID, 4) 947 #define CMN_EVENT_HN_CLS(_model, _name, _type, _event) \ 948 CMN_EVENT_ATTR(_model, _name##_class0, _type, _event, SEL_CLASS_OCCUP_ID, 0), \ 949 CMN_EVENT_ATTR(_model, _name##_class1, _type, _event, SEL_CLASS_OCCUP_ID, 1), \ 950 CMN_EVENT_ATTR(_model, _name##_class2, _type, _event, SEL_CLASS_OCCUP_ID, 2), \ 951 CMN_EVENT_ATTR(_model, _name##_class3, _type, _event, SEL_CLASS_OCCUP_ID, 3) 952 #define CMN_EVENT_HN_SNT(_model, _name, _type, _event) \ 953 CMN_EVENT_ATTR(_model, _name##_all, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 0), \ 954 CMN_EVENT_ATTR(_model, _name##_group0_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 1), \ 955 CMN_EVENT_ATTR(_model, _name##_group0_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 2), \ 956 CMN_EVENT_ATTR(_model, _name##_group1_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 3), \ 957 CMN_EVENT_ATTR(_model, _name##_group1_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 4), \ 958 CMN_EVENT_ATTR(_model, _name##_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 5), \ 959 CMN_EVENT_ATTR(_model, _name##_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 6), \ 960 CMN_EVENT_ATTR(CMNS3R2, _name##_ccg_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 9), \ 961 CMN_EVENT_ATTR(CMNS3R2, _name##_ccg_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 10), \ 962 CMN_EVENT_ATTR(CMNS3R2, _name##_lbt_read, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 11), \ 963 CMN_EVENT_ATTR(CMNS3R2, _name##_lbt_write, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 12), \ 964 CMN_EVENT_ATTR(CMNS3R2, _name##_lbt, _type, _event, SEL_CBUSY_SNTHROTTLE_SEL, 13) 965 966 #define CMN_EVENT_HNF_OCC(_model, _name, _event) \ 967 CMN_EVENT_HN_OCC(_model, hnf_##_name, CMN_TYPE_HNF, _event) 968 #define CMN_EVENT_HNF_CLS(_model, _name, _event) \ 969 CMN_EVENT_HN_CLS(_model, hnf_##_name, CMN_TYPE_HNF, _event) 970 #define CMN_EVENT_HNF_SNT(_model, _name, _event) \ 971 CMN_EVENT_HN_SNT(_model, hnf_##_name, CMN_TYPE_HNF, _event) 972 973 #define CMN_EVENT_HNS(_name, _event) \ 974 _CMN_EVENT_HNS(CMN_ANY, _name, _event) 975 #define CMN_EVENT_HNSR0(_name, _event) \ 976 _CMN_EVENT_HNS(CMN700 | CMNS3R01, _name, _event) 977 #define _CMN_EVENT_HNS_HBT(_model, _name, _event, _sel) \ 978 _CMN_EVENT_HNS(_model, _name##_all, _event, _sel, 0), \ 979 _CMN_EVENT_HNS(_model, _name##_hbt, _event, _sel, 1), \ 980 _CMN_EVENT_HNS(_model, _name##_lbt, _event, _sel, 2) 981 #define _CMN_EVENT_HNS_HBT2(_model, _name, _event, _fsel1, f1) \ 982 _CMN_EVENT_HNS(_model, _name##_all, _event, _fsel1, f1, SEL_HBT_LBT_SEL, 0), \ 983 _CMN_EVENT_HNS(_model, _name##_hbt, _event, _fsel1, f1, SEL_HBT_LBT_SEL, 1), \ 984 _CMN_EVENT_HNS(_model, _name##_lbt, _event, _fsel1, f1, SEL_HBT_LBT_SEL, 2) 985 986 #define CMN_EVENT_HNS_OCC(_model, _name, _event) \ 987 CMN_EVENT_HN_OCC(_model, hns_##_name, CMN_TYPE_HNS, _event), \ 988 _CMN_EVENT_HNS(_model, _name##_rxsnp, _event, SEL_OCCUP1_ID, 5), \ 989 _CMN_EVENT_HNS(_model, _name##_lbt, _event, SEL_OCCUP1_ID, 6), \ 990 _CMN_EVENT_HNS(_model, _name##_hbt, _event, SEL_OCCUP1_ID, 7), \ 991 _CMN_EVENT_HNS(CMNS3R2, _name##_rnf, _event, SEL_OCCUP1_ID, 8), \ 992 _CMN_EVENT_HNS(CMNS3R2, _name##_rni, _event, SEL_OCCUP1_ID, 9), \ 993 _CMN_EVENT_HNS(CMNS3R2, _name##_ccglcn, _event, SEL_OCCUP1_ID, 10), \ 994 _CMN_EVENT_HNS(CMNS3R2, _name##_ccgrn, _event, SEL_OCCUP1_ID, 11) 995 #define CMN_EVENT_HNS_CLS( _name, _event) \ 996 CMN_EVENT_HN_CLS(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event) 997 #define CMN_EVENT_HNSR0_CLS( _name, _event) \ 998 CMN_EVENT_HN_CLS(CMN700 | CMNS3R01, hns_##_name, CMN_TYPE_HNS, _event) 999 #define CMN_EVENT_HNS_SNT(_model, _name, _event) \ 1000 CMN_EVENT_HN_SNT(_model, hns_##_name, CMN_TYPE_HNS, _event) 1001 #define CMN_EVENT_HNS_SNH(_model, _name, _event) \ 1002 _CMN_EVENT_HNS(_model, _name##_all, _event, SEL_SN_HOME_SEL, 0), \ 1003 _CMN_EVENT_HNS(_model, _name##_sn, _event, SEL_SN_HOME_SEL, 1), \ 1004 _CMN_EVENT_HNS(_model, _name##_home, _event, SEL_SN_HOME_SEL, 2) 1005 #define CMN_EVENT_HNS_VC(_name, _event) \ 1006 CMN_EVENT_HNSR0(_name, _event), \ 1007 _CMN_EVENT_HNS(CMNS3R2, _name##_vc0, _event, SEL_SNP_VC_SEL, 0), \ 1008 _CMN_EVENT_HNS(CMNS3R2, _name##_vc1, _event, SEL_SNP_VC_SEL, 1), \ 1009 _CMN_EVENT_HNS(CMNS3R2, _name##_vc2, _event, SEL_SNP_VC_SEL, 2) 1010 #define CMN_EVENT_HNS_ENHBT(_name, _event) \ 1011 _CMN_EVENT_HNS_HBT(CMNS3R2, _name, _event, SEL_ENHANCED_HBT_LBT_SEL), \ 1012 _CMN_EVENT_HNS(CMNS3R2, _name##_rnf, _event, SEL_ENHANCED_HBT_LBT_SEL, 3), \ 1013 _CMN_EVENT_HNS(CMNS3R2, _name##_rni, _event, SEL_ENHANCED_HBT_LBT_SEL, 4), \ 1014 _CMN_EVENT_HNS(CMNS3R2, _name##_ccglcn, _event, SEL_ENHANCED_HBT_LBT_SEL, 5), \ 1015 _CMN_EVENT_HNS(CMNS3R2, _name##_ccgrn, _event, SEL_ENHANCED_HBT_LBT_SEL, 6) 1016 #define CMN_EVENT_HNS_EVICT(_model, _name, _event) \ 1017 _CMN_EVENT_HNS_HBT2(_model, _name##_all, _event, SEL_EVICT_STATE_SEL, 0), \ 1018 _CMN_EVENT_HNS_HBT2(_model, _name##_eu, _event, SEL_EVICT_STATE_SEL, 1), \ 1019 _CMN_EVENT_HNS_HBT2(_model, _name##_en, _event, SEL_EVICT_STATE_SEL, 2), \ 1020 _CMN_EVENT_HNS_HBT2(_model, _name##_su, _event, SEL_EVICT_STATE_SEL, 3), \ 1021 _CMN_EVENT_HNS_HBT2(_model, _name##_sn, _event, SEL_EVICT_STATE_SEL, 4), \ 1022 _CMN_EVENT_HNS_HBT2(_model, _name##_mu, _event, SEL_EVICT_STATE_SEL, 5), \ 1023 _CMN_EVENT_HNS_HBT2(_model, _name##_mn, _event, SEL_EVICT_STATE_SEL, 6) 1024 1025 #define CMN_EVENT_HNSR0_HBT(_name, _event) \ 1026 _CMN_EVENT_HNS_HBT(CMN700 | CMNS3R01, _name, _event, SEL_HBT_LBT_SEL) 1027 #define CMN_EVENT_HNS_R2SNH(_name, _event) \ 1028 CMN_EVENT_HNSR0(_name, _event), \ 1029 CMN_EVENT_HNS_SNH(CMNS3R2, _name, _event) 1030 #define CMN_EVENT_HNS_R2HBT(_name, _event) \ 1031 CMN_EVENT_HNSR0(_name, _event), \ 1032 _CMN_EVENT_HNS_HBT(CMNS3R2, _name, _event, SEL_HBT_LBT_SEL) 1033 #define CMN_EVENT_HNS_HBT_ENHBT(_name, _event) \ 1034 CMN_EVENT_HNSR0_HBT(_name, _event), \ 1035 CMN_EVENT_HNS_ENHBT(_name, _event) 1036 #define CMN_EVENT_HNS_HBT_OCC(_name, _event) \ 1037 CMN_EVENT_HNSR0_HBT(_name, _event), \ 1038 CMN_EVENT_HNS_OCC(CMNS3R2, _name, _event) 1039 #define CMN_EVENT_HNS_HBT_EVICT(_name, _event) \ 1040 CMN_EVENT_HNSR0_HBT(_name, _event), \ 1041 CMN_EVENT_HNS_EVICT(CMNS3R2, _name, _event) 1042 1043 #define _CMN_EVENT_XP_MESH(_name, _event) \ 1044 __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \ 1045 __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \ 1046 __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \ 1047 __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)) 1048 1049 #define _CMN_EVENT_XP_PORT(_name, _event) \ 1050 __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \ 1051 __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \ 1052 __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \ 1053 __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2)) 1054 1055 #define _CMN_EVENT_XP(_name, _event) \ 1056 _CMN_EVENT_XP_MESH(_name, _event), \ 1057 _CMN_EVENT_XP_PORT(_name, _event) 1058 1059 /* Good thing there are only 3 fundamental XP events... */ 1060 #define CMN_EVENT_XP(_name, _event) \ 1061 _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \ 1062 _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \ 1063 _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \ 1064 _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \ 1065 _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \ 1066 _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \ 1067 _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)), \ 1068 _CMN_EVENT_XP(req2_##_name, (_event) | (7 << 5)), \ 1069 _CMN_EVENT_XP(snp2_##_name, (_event) | (8 << 5)) 1070 1071 #define CMN_EVENT_XP_DAT(_name, _event) \ 1072 _CMN_EVENT_XP_PORT(dat_##_name, (_event) | (3 << 5)), \ 1073 _CMN_EVENT_XP_PORT(dat2_##_name, (_event) | (6 << 5)) 1074 1075 1076 static struct attribute *arm_cmn_event_attrs[] = { 1077 CMN_EVENT_DTC(cycles), 1078 1079 /* 1080 * DVM node events conflict with HN-I events in the equivalent PMU 1081 * slot, but our lazy short-cut of using the DTM counter index for 1082 * the PMU index as well happens to avoid that by construction. 1083 */ 1084 CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01), 1085 CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02), 1086 CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03), 1087 CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04), 1088 CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy, 0x05), 1089 CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi, 0x01), 1090 CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi, 0x02), 1091 CMN_EVENT_DVM(NOT_CMN600, dvmop_pici, 0x03), 1092 CMN_EVENT_DVM(NOT_CMN600, dvmop_vici, 0x04), 1093 CMN_EVENT_DVM(NOT_CMN600, dvmsync, 0x05), 1094 CMN_EVENT_DVM(NOT_CMN600, vmid_filtered, 0x06), 1095 CMN_EVENT_DVM(NOT_CMN600, rndop_filtered, 0x07), 1096 CMN_EVENT_DVM(NOT_CMN600, retry, 0x08), 1097 CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv, 0x09), 1098 CMN_EVENT_DVM(NOT_CMN600, txsnp_stall, 0x0a), 1099 CMN_EVENT_DVM(NOT_CMN600, trkfull, 0x0b), 1100 CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy, 0x0c), 1101 CMN_EVENT_DVM_OCC(CMN_700ON, trk_occupancy_cxha, 0x0d), 1102 CMN_EVENT_DVM_OCC(CMN_700ON, trk_occupancy_pdn, 0x0e), 1103 CMN_EVENT_DVM(CMN_700ON, trk_alloc, 0x0f), 1104 CMN_EVENT_DVM(CMN_700ON, trk_cxha_alloc, 0x10), 1105 CMN_EVENT_DVM(CMN_700ON, trk_pdn_alloc, 0x11), 1106 CMN_EVENT_DVM(CMN_700ON, txsnp_stall_limit, 0x12), 1107 CMN_EVENT_DVM(CMN_700ON, rxsnp_stall_starv, 0x13), 1108 CMN_EVENT_DVM(CMN_700ON, txsnp_sync_stall_op, 0x14), 1109 1110 CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01), 1111 CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02), 1112 CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03), 1113 CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04), 1114 CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05), 1115 CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06), 1116 CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07), 1117 CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08), 1118 CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09), 1119 CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a), 1120 CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b), 1121 CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c), 1122 CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d), 1123 CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e), 1124 CMN_EVENT_HNF_OCC(CMN_ANY, qos_pocq_occupancy, 0x0f), 1125 CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10), 1126 CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11), 1127 CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12), 1128 CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13), 1129 CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14), 1130 CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15), 1131 CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16), 1132 CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17), 1133 CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18), 1134 CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19), 1135 CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a), 1136 CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b), 1137 CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c), 1138 CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d), 1139 CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e), 1140 CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f), 1141 CMN_EVENT_HNF(NOT_CMN600, atomic_fwd, 0x20), 1142 CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim, 0x21), 1143 CMN_EVENT_HNF(NOT_CMN600, mpam_softlim, 0x22), 1144 CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster, 0x23), 1145 CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict, 0x24), 1146 CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line, 0x25), 1147 CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup, 0x26), 1148 CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry, 0x27), 1149 CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs, 0x28), 1150 CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin, 0x29), 1151 CMN_EVENT_HNF_SNT(CMN700, sn_throttle, 0x2a), 1152 CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min, 0x2b), 1153 CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise, 0x2c), 1154 CMN_EVENT_HNF(CMN700, snp_intv_cln, 0x2d), 1155 CMN_EVENT_HNF(CMN700, nc_excl, 0x2e), 1156 CMN_EVENT_HNF(CMN700, excl_mon_ovfl, 0x2f), 1157 1158 CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), 1159 CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), 1160 CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22), 1161 CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23), 1162 CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24), 1163 CMN_EVENT_HNI(rrt_rd_alloc, 0x25), 1164 CMN_EVENT_HNI(rrt_wr_alloc, 0x26), 1165 CMN_EVENT_HNI(rdt_rd_alloc, 0x27), 1166 CMN_EVENT_HNI(rdt_wr_alloc, 0x28), 1167 CMN_EVENT_HNI(wdb_alloc, 0x29), 1168 CMN_EVENT_HNI(txrsp_retryack, 0x2a), 1169 CMN_EVENT_HNI(arvalid_no_arready, 0x2b), 1170 CMN_EVENT_HNI(arready_no_arvalid, 0x2c), 1171 CMN_EVENT_HNI(awvalid_no_awready, 0x2d), 1172 CMN_EVENT_HNI(awready_no_awvalid, 0x2e), 1173 CMN_EVENT_HNI(wvalid_no_wready, 0x2f), 1174 CMN_EVENT_HNI(txdat_stall, 0x30), 1175 CMN_EVENT_HNI(nonpcie_serialization, 0x31), 1176 CMN_EVENT_HNI(pcie_serialization, 0x32), 1177 1178 /* 1179 * HN-P events squat on top of the HN-I similarly to DVM events, except 1180 * for being crammed into the same physical node as well. And of course 1181 * where would the fun be if the same events were in the same order... 1182 */ 1183 CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl, 0x01), 1184 CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl, 0x02), 1185 CMN_EVENT_HNP(wdb_occ_cnt_ovfl, 0x03), 1186 CMN_EVENT_HNP(rrt_wr_alloc, 0x04), 1187 CMN_EVENT_HNP(rdt_wr_alloc, 0x05), 1188 CMN_EVENT_HNP(wdb_alloc, 0x06), 1189 CMN_EVENT_HNP(awvalid_no_awready, 0x07), 1190 CMN_EVENT_HNP(awready_no_awvalid, 0x08), 1191 CMN_EVENT_HNP(wvalid_no_wready, 0x09), 1192 CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl, 0x11), 1193 CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl, 0x12), 1194 CMN_EVENT_HNP(rrt_rd_alloc, 0x13), 1195 CMN_EVENT_HNP(rdt_rd_alloc, 0x14), 1196 CMN_EVENT_HNP(arvalid_no_arready, 0x15), 1197 CMN_EVENT_HNP(arready_no_arvalid, 0x16), 1198 1199 CMN_EVENT_XP(txflit_valid, 0x01), 1200 CMN_EVENT_XP(txflit_stall, 0x02), 1201 CMN_EVENT_XP_DAT(partial_dat_flit, 0x03), 1202 /* We treat watchpoints as a special made-up class of XP events */ 1203 CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP), 1204 CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN), 1205 1206 CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01), 1207 CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02), 1208 CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03), 1209 CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04), 1210 CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05), 1211 CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06), 1212 CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11), 1213 CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12), 1214 CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13), 1215 CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14), 1216 CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15), 1217 CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16), 1218 CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl, 0x17), 1219 CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21), 1220 CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22), 1221 CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23), 1222 CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24), 1223 CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25), 1224 1225 CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01), 1226 CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02), 1227 CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03), 1228 CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04), 1229 CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05), 1230 CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06), 1231 CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07), 1232 CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08), 1233 CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09), 1234 CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a), 1235 CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b), 1236 CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c), 1237 CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d), 1238 CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e), 1239 CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f), 1240 CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10), 1241 CMN_EVENT_RNID(CMN600, rdb_unord, 0x11), 1242 CMN_EVENT_RNID(CMN600, rdb_replay, 0x12), 1243 CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13), 1244 CMN_EVENT_RNID(CMN600, rdb_ord, 0x14), 1245 CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl, 0x11), 1246 CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl, 0x12), 1247 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13), 1248 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14), 1249 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15), 1250 CMN_EVENT_RNID(NOT_CMN600, wrt_throttled, 0x16), 1251 CMN_EVENT_RNID(CMN700, ldb_full, 0x17), 1252 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18), 1253 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19), 1254 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a), 1255 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b), 1256 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c), 1257 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d), 1258 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e), 1259 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f), 1260 CMN_EVENT_RNID(CMN700, rrt_burst_alloc, 0x20), 1261 CMN_EVENT_RNID(CMN700, awid_hash, 0x21), 1262 CMN_EVENT_RNID(CMN700, atomic_alloc, 0x22), 1263 CMN_EVENT_RNID(CMN700, atomic_occ_ovfl, 0x23), 1264 1265 CMN_EVENT_MTSX(tc_lookup, 0x01), 1266 CMN_EVENT_MTSX(tc_fill, 0x02), 1267 CMN_EVENT_MTSX(tc_miss, 0x03), 1268 CMN_EVENT_MTSX(tdb_forward, 0x04), 1269 CMN_EVENT_MTSX(tcq_hazard, 0x05), 1270 CMN_EVENT_MTSX(tcq_rd_alloc, 0x06), 1271 CMN_EVENT_MTSX(tcq_wr_alloc, 0x07), 1272 CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08), 1273 CMN_EVENT_MTSX(axi_rd_req, 0x09), 1274 CMN_EVENT_MTSX(axi_wr_req, 0x0a), 1275 CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b), 1276 CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c), 1277 1278 CMN_EVENT_CXRA(CMN_ANY, rht_occ, 0x01), 1279 CMN_EVENT_CXRA(CMN_ANY, sht_occ, 0x02), 1280 CMN_EVENT_CXRA(CMN_ANY, rdb_occ, 0x03), 1281 CMN_EVENT_CXRA(CMN_ANY, wdb_occ, 0x04), 1282 CMN_EVENT_CXRA(CMN_ANY, ssb_occ, 0x05), 1283 CMN_EVENT_CXRA(CMN_ANY, snp_bcasts, 0x06), 1284 CMN_EVENT_CXRA(CMN_ANY, req_chains, 0x07), 1285 CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen, 0x08), 1286 CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls, 0x09), 1287 CMN_EVENT_CXRA(CMN_ANY, chidat_stalls, 0x0a), 1288 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b), 1289 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c), 1290 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d), 1291 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e), 1292 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f), 1293 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10), 1294 CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11), 1295 CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12), 1296 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13), 1297 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14), 1298 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15), 1299 1300 CMN_EVENT_CXHA(rddatbyp, 0x21), 1301 CMN_EVENT_CXHA(chirsp_up_stall, 0x22), 1302 CMN_EVENT_CXHA(chidat_up_stall, 0x23), 1303 CMN_EVENT_CXHA(snppcrd_link0_stall, 0x24), 1304 CMN_EVENT_CXHA(snppcrd_link1_stall, 0x25), 1305 CMN_EVENT_CXHA(snppcrd_link2_stall, 0x26), 1306 CMN_EVENT_CXHA(reqtrk_occ, 0x27), 1307 CMN_EVENT_CXHA(rdb_occ, 0x28), 1308 CMN_EVENT_CXHA(rdbyp_occ, 0x29), 1309 CMN_EVENT_CXHA(wdb_occ, 0x2a), 1310 CMN_EVENT_CXHA(snptrk_occ, 0x2b), 1311 CMN_EVENT_CXHA(sdb_occ, 0x2c), 1312 CMN_EVENT_CXHA(snphaz_occ, 0x2d), 1313 1314 CMN_EVENT_CCRA(rht_occ, 0x41), 1315 CMN_EVENT_CCRA(sht_occ, 0x42), 1316 CMN_EVENT_CCRA(rdb_occ, 0x43), 1317 CMN_EVENT_CCRA(wdb_occ, 0x44), 1318 CMN_EVENT_CCRA(ssb_occ, 0x45), 1319 CMN_EVENT_CCRA(snp_bcasts, 0x46), 1320 CMN_EVENT_CCRA(req_chains, 0x47), 1321 CMN_EVENT_CCRA(req_chain_avglen, 0x48), 1322 CMN_EVENT_CCRA(chirsp_stalls, 0x49), 1323 CMN_EVENT_CCRA(chidat_stalls, 0x4a), 1324 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0, 0x4b), 1325 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1, 0x4c), 1326 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2, 0x4d), 1327 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0, 0x4e), 1328 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1, 0x4f), 1329 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2, 0x50), 1330 CMN_EVENT_CCRA(external_chirsp_stalls, 0x51), 1331 CMN_EVENT_CCRA(external_chidat_stalls, 0x52), 1332 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0, 0x53), 1333 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1, 0x54), 1334 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2, 0x55), 1335 CMN_EVENT_CCRA(rht_alloc, 0x56), 1336 CMN_EVENT_CCRA(sht_alloc, 0x57), 1337 CMN_EVENT_CCRA(rdb_alloc, 0x58), 1338 CMN_EVENT_CCRA(wdb_alloc, 0x59), 1339 CMN_EVENT_CCRA(ssb_alloc, 0x5a), 1340 1341 CMN_EVENT_CCHA(CMN_ANY, rddatbyp, 0x61), 1342 CMN_EVENT_CCHA(CMN_ANY, chirsp_up_stall, 0x62), 1343 CMN_EVENT_CCHA(CMN_ANY, chidat_up_stall, 0x63), 1344 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link0_stall, 0x64), 1345 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link1_stall, 0x65), 1346 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link2_stall, 0x66), 1347 CMN_EVENT_CCHA(CMN_ANY, reqtrk_occ, 0x67), 1348 CMN_EVENT_CCHA(CMN_ANY, rdb_occ, 0x68), 1349 CMN_EVENT_CCHA(CMN_ANY, rdbyp_occ, 0x69), 1350 CMN_EVENT_CCHA(CMN_ANY, wdb_occ, 0x6a), 1351 CMN_EVENT_CCHA(CMN_ANY, snptrk_occ, 0x6b), 1352 CMN_EVENT_CCHA(CMN_ANY, sdb_occ, 0x6c), 1353 CMN_EVENT_CCHA(CMN_ANY, snphaz_occ, 0x6d), 1354 CMN_EVENT_CCHA(CMN_ANY, reqtrk_alloc, 0x6e), 1355 CMN_EVENT_CCHA(CMN_ANY, rdb_alloc, 0x6f), 1356 CMN_EVENT_CCHA(CMN_ANY, rdbyp_alloc, 0x70), 1357 CMN_EVENT_CCHA(CMN_ANY, wdb_alloc, 0x71), 1358 CMN_EVENT_CCHA(CMN_ANY, snptrk_alloc, 0x72), 1359 CMN_EVENT_CCHA(CMN_ANY, db_alloc, 0x73), 1360 CMN_EVENT_CCHA(CMN_ANY, snphaz_alloc, 0x74), 1361 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_req_occ, 0x75), 1362 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_req_alloc, 0x76), 1363 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_req_occ, 0x77), 1364 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_req_alloc, 0x78), 1365 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_req_occ, 0x79), 1366 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_req_alloc, 0x7a), 1367 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_reg_req_occ, 0x7b), 1368 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_reg_req_alloc, 0x7c), 1369 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_rsvd_req_occ, 0x7d), 1370 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_rsvd_req_alloc, 0x7e), 1371 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_dat_occ, 0x7f), 1372 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_dat_alloc, 0x80), 1373 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_dat_occ, 0x81), 1374 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_dat_alloc, 0x82), 1375 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_dat_occ, 0x83), 1376 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_dat_alloc, 0x84), 1377 CMN_EVENT_CCHA(CMNS3, chirsp1_up_stall, 0x85), 1378 1379 CMN_EVENT_CCLA(rx_cxs, 0x21), 1380 CMN_EVENT_CCLA(tx_cxs, 0x22), 1381 CMN_EVENT_CCLA(rx_cxs_avg_size, 0x23), 1382 CMN_EVENT_CCLA(tx_cxs_avg_size, 0x24), 1383 CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure, 0x25), 1384 CMN_EVENT_CCLA(link_crdbuf_occ, 0x26), 1385 CMN_EVENT_CCLA(link_crdbuf_alloc, 0x27), 1386 CMN_EVENT_CCLA(pfwd_rcvr_cxs, 0x28), 1387 CMN_EVENT_CCLA(pfwd_sndr_num_flits, 0x29), 1388 CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd, 0x2a), 1389 CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd, 0x2b), 1390 1391 CMN_EVENT_HNS_HBT_ENHBT(cache_miss, 0x01), 1392 CMN_EVENT_HNS_HBT_ENHBT(slc_sf_cache_access, 0x02), 1393 CMN_EVENT_HNS_HBT_ENHBT(cache_fill, 0x03), 1394 CMN_EVENT_HNS_HBT_OCC(pocq_retry, 0x04), 1395 CMN_EVENT_HNS_HBT_OCC(pocq_reqs_recvd, 0x05), 1396 CMN_EVENT_HNS_HBT_ENHBT(sf_hit, 0x06), 1397 CMN_EVENT_HNS_HBT_EVICT(sf_evictions, 0x07), 1398 CMN_EVENT_HNS_VC(dir_snoops_sent, 0x08), 1399 CMN_EVENT_HNS_VC(brd_snoops_sent, 0x09), 1400 CMN_EVENT_HNS_HBT_EVICT(slc_eviction, 0x0a), 1401 CMN_EVENT_HNS_HBT_ENHBT(slc_fill_invalid_way, 0x0b), 1402 CMN_EVENT_HNS_R2SNH(mc_retries_local, 0x0c), 1403 CMN_EVENT_HNS_SNH(CMN_ANY, mc_reqs_local, 0x0d), 1404 CMN_EVENT_HNS(qos_hh_retry, 0x0e), 1405 CMN_EVENT_HNS_OCC(CMN_ANY, qos_pocq_occupancy, 0x0f), 1406 CMN_EVENT_HNS_HBT_ENHBT(pocq_addrhaz, 0x10), 1407 CMN_EVENT_HNS_HBT_ENHBT(pocq_atomic_addrhaz, 0x11), 1408 CMN_EVENT_HNSR0(ld_st_swp_adq_full, 0x12), 1409 CMN_EVENT_HNSR0(cmp_adq_full, 0x13), 1410 CMN_EVENT_HNS(txdat_stall, 0x14), 1411 CMN_EVENT_HNS(txrsp_stall, 0x15), 1412 CMN_EVENT_HNSR0(seq_full, 0x16), 1413 CMN_EVENT_HNS(seq_hit, 0x17), 1414 CMN_EVENT_HNS_VC(snp_sent, 0x18), 1415 CMN_EVENT_HNS_VC(sfbi_dir_snp_sent, 0x19), 1416 CMN_EVENT_HNS_VC(sfbi_brd_snp_sent, 0x1a), 1417 CMN_EVENT_HNS(intv_dirty, 0x1c), 1418 CMN_EVENT_HNSR0(stash_snp_sent, 0x1d), 1419 CMN_EVENT_HNSR0(stash_data_pull, 0x1e), 1420 CMN_EVENT_HNS_VC(snp_fwded, 0x1f), 1421 CMN_EVENT_HNSR0(atomic_fwd, 0x20), 1422 CMN_EVENT_HNS(mpam_hardlim, 0x21), 1423 CMN_EVENT_HNS(mpam_softlim, 0x22), 1424 CMN_EVENT_HNS_VC(snp_sent_cluster, 0x23), 1425 CMN_EVENT_HNS_R2HBT(sf_imprecise_evict, 0x24), 1426 CMN_EVENT_HNS(sf_evict_shared_line, 0x25), 1427 CMN_EVENT_HNS_CLS(pocq_class_occup, 0x26), 1428 CMN_EVENT_HNS_CLS(pocq_class_retry, 0x27), 1429 CMN_EVENT_HNS_CLS(class_mc_reqs_local, 0x28), 1430 CMN_EVENT_HNSR0_CLS(class_cgnt_cmin, 0x29), 1431 CMN_EVENT_HNS_SNT(CMN_ANY, sn_throttle, 0x2a), 1432 CMN_EVENT_HNS_SNT(CMN_ANY, sn_throttle_min, 0x2b), 1433 CMN_EVENT_HNS(sf_precise_to_imprecise, 0x2c), 1434 CMN_EVENT_HNS(snp_intv_cln, 0x2d), 1435 CMN_EVENT_HNS(nc_excl, 0x2e), 1436 CMN_EVENT_HNSR0(excl_mon_ovfl, 0x2f), 1437 CMN_EVENT_HNS(snp_req_recvd, 0x30), 1438 CMN_EVENT_HNS(snp_req_byp_pocq, 0x31), 1439 CMN_EVENT_HNS(dir_ccgha_snp_sent, 0x32), 1440 CMN_EVENT_HNS(brd_ccgha_snp_sent, 0x33), 1441 CMN_EVENT_HNSR0(ccgha_snp_stall, 0x34), 1442 CMN_EVENT_HNS(lbt_req_hardlim, 0x35), 1443 CMN_EVENT_HNS(hbt_req_hardlim, 0x36), 1444 CMN_EVENT_HNS(sf_reupdate, 0x37), 1445 CMN_EVENT_HNS_R2HBT(excl_sf_imprecise, 0x38), 1446 CMN_EVENT_HNS(snp_pocq_addrhaz, 0x39), 1447 CMN_EVENT_HNS_R2SNH(mc_retries_remote, 0x3a), 1448 CMN_EVENT_HNS_SNH(CMN_ANY, mc_reqs_remote, 0x3b), 1449 CMN_EVENT_HNS_CLS(class_mc_reqs_remote, 0x3c), 1450 CMN_EVENT_HNS_ENHBT(readonce_hazard_detected, 0x3d), 1451 CMN_EVENT_HNS_ENHBT(readonce_fwd_data_completed, 0x3e), 1452 CMN_EVENT_HNS_SNT(CMNS3R2, cbusy00, 0x40), 1453 CMN_EVENT_HNS_SNT(CMNS3R2, cbusy01, 0x41), 1454 CMN_EVENT_HNS_SNT(CMNS3R2, cbusy10, 0x42), 1455 CMN_EVENT_HNS_SNT(CMNS3R2, cbusy11, 0x43), 1456 CMN_EVENT_HNS_ENHBT(ro_rnsd_new_alloc_hint, 0x44), 1457 1458 NULL 1459 }; 1460 1461 static const struct attribute_group arm_cmn_event_attrs_group = { 1462 .name = "events", 1463 .attrs = arm_cmn_event_attrs, 1464 .is_visible = arm_cmn_event_attr_is_visible, 1465 }; 1466 1467 static ssize_t arm_cmn_format_show(struct device *dev, 1468 struct device_attribute *attr, char *buf) 1469 { 1470 struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr); 1471 1472 if (!fmt->config) 1473 return sysfs_emit(buf, "config:%*pbl\n", 64, &fmt->field); 1474 1475 return sysfs_emit(buf, "config%d:%*pbl\n", fmt->config, 64, &fmt->field); 1476 } 1477 1478 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \ 1479 (&((struct arm_cmn_format_attr[]) {{ \ 1480 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \ 1481 .config = _cfg, \ 1482 .field = _fld, \ 1483 }})[0].attr.attr) 1484 #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld) 1485 1486 static struct attribute *arm_cmn_format_attrs[] = { 1487 CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE), 1488 CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID), 1489 CMN_FORMAT_ATTR(filter, CMN_CONFIG_FILTER), 1490 CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID), 1491 CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID), 1492 CMN_FORMAT_ATTR(filter2, CMN_CONFIG_FILTER2), 1493 1494 CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL), 1495 CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL), 1496 CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP), 1497 CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE), 1498 CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE), 1499 1500 _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL), 1501 _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK), 1502 1503 /* Old name for UAPI compatibility */ 1504 CMN_FORMAT_ATTR(occupid, CMN_CONFIG_FILTER), 1505 1506 NULL 1507 }; 1508 1509 static const struct attribute_group arm_cmn_format_attrs_group = { 1510 .name = "format", 1511 .attrs = arm_cmn_format_attrs, 1512 }; 1513 1514 static ssize_t arm_cmn_cpumask_show(struct device *dev, 1515 struct device_attribute *attr, char *buf) 1516 { 1517 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1518 1519 return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu)); 1520 } 1521 1522 static struct device_attribute arm_cmn_cpumask_attr = 1523 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL); 1524 1525 static ssize_t arm_cmn_identifier_show(struct device *dev, 1526 struct device_attribute *attr, char *buf) 1527 { 1528 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1529 1530 return sysfs_emit(buf, "%03x%02x\n", cmn->part, cmn->rev); 1531 } 1532 1533 static struct device_attribute arm_cmn_identifier_attr = 1534 __ATTR(identifier, 0444, arm_cmn_identifier_show, NULL); 1535 1536 static struct attribute *arm_cmn_other_attrs[] = { 1537 &arm_cmn_cpumask_attr.attr, 1538 &arm_cmn_identifier_attr.attr, 1539 NULL, 1540 }; 1541 1542 static const struct attribute_group arm_cmn_other_attrs_group = { 1543 .attrs = arm_cmn_other_attrs, 1544 }; 1545 1546 static const struct attribute_group *arm_cmn_attr_groups[] = { 1547 &arm_cmn_event_attrs_group, 1548 &arm_cmn_format_attrs_group, 1549 &arm_cmn_other_attrs_group, 1550 NULL 1551 }; 1552 1553 static int arm_cmn_find_free_wp_idx(struct arm_cmn_dtm *dtm, 1554 struct perf_event *event) 1555 { 1556 int wp_idx = CMN_EVENT_EVENTID(event); 1557 1558 if (dtm->wp_event[wp_idx] >= 0) 1559 if (dtm->wp_event[++wp_idx] >= 0) 1560 return -ENOSPC; 1561 1562 return wp_idx; 1563 } 1564 1565 static int arm_cmn_get_assigned_wp_idx(struct perf_event *event, 1566 struct arm_cmn_hw_event *hw, 1567 unsigned int pos) 1568 { 1569 return CMN_EVENT_EVENTID(event) + arm_cmn_get_wp_idx(hw, pos); 1570 } 1571 1572 static void arm_cmn_claim_wp_idx(struct arm_cmn_dtm *dtm, 1573 struct perf_event *event, 1574 unsigned int dtc, int wp_idx, 1575 unsigned int pos) 1576 { 1577 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1578 1579 dtm->wp_event[wp_idx] = hw->dtc_idx[dtc]; 1580 arm_cmn_set_wp_idx(hw, pos, wp_idx - CMN_EVENT_EVENTID(event)); 1581 } 1582 1583 static u32 arm_cmn_wp_config(struct perf_event *event, int wp_idx) 1584 { 1585 u32 config; 1586 u32 dev = CMN_EVENT_WP_DEV_SEL(event); 1587 u32 chn = CMN_EVENT_WP_CHN_SEL(event); 1588 u32 grp = CMN_EVENT_WP_GRP(event); 1589 u32 exc = CMN_EVENT_WP_EXCLUSIVE(event); 1590 u32 combine = CMN_EVENT_WP_COMBINE(event); 1591 bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600; 1592 1593 /* CMN-600 supports only primary and secondary matching groups */ 1594 if (is_cmn600) 1595 grp &= 1; 1596 1597 config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) | 1598 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) | 1599 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) | 1600 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1); 1601 if (exc) 1602 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE : 1603 CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE; 1604 1605 /* wp_combine is available only on WP0 and WP2 */ 1606 if (combine && !(wp_idx & 0x1)) 1607 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE : 1608 CMN_DTM_WPn_CONFIG_WP_COMBINE; 1609 return config; 1610 } 1611 1612 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state) 1613 { 1614 if (!cmn->state) 1615 writel_relaxed(0, CMN_DT_PMCR(&cmn->dtc[0])); 1616 cmn->state |= state; 1617 } 1618 1619 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state) 1620 { 1621 cmn->state &= ~state; 1622 if (!cmn->state) 1623 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, 1624 CMN_DT_PMCR(&cmn->dtc[0])); 1625 } 1626 1627 static void arm_cmn_pmu_enable(struct pmu *pmu) 1628 { 1629 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED); 1630 } 1631 1632 static void arm_cmn_pmu_disable(struct pmu *pmu) 1633 { 1634 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED); 1635 } 1636 1637 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, 1638 bool snapshot) 1639 { 1640 struct arm_cmn_dtm *dtm = NULL; 1641 struct arm_cmn_node *dn; 1642 unsigned int i, offset, dtm_idx; 1643 u64 reg, count = 0; 1644 1645 offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; 1646 for_each_hw_dn(hw, dn, i) { 1647 if (dtm != &cmn->dtms[dn->dtm]) { 1648 dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1649 reg = readq_relaxed(dtm->base + offset); 1650 } 1651 dtm_idx = arm_cmn_get_dtm_idx(hw, i); 1652 count += (u16)(reg >> (dtm_idx * 16)); 1653 } 1654 return count; 1655 } 1656 1657 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc) 1658 { 1659 void __iomem *pmccntr = CMN_DT_PMCCNTR(dtc); 1660 u64 val = readq_relaxed(pmccntr); 1661 1662 writeq_relaxed(CMN_CC_INIT, pmccntr); 1663 return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1); 1664 } 1665 1666 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx) 1667 { 1668 void __iomem *pmevcnt = CMN_DT_PMEVCNT(dtc, idx); 1669 u32 val = readl_relaxed(pmevcnt); 1670 1671 writel_relaxed(CMN_COUNTER_INIT, pmevcnt); 1672 return val - CMN_COUNTER_INIT; 1673 } 1674 1675 static void arm_cmn_init_counter(struct perf_event *event) 1676 { 1677 struct arm_cmn *cmn = to_cmn(event->pmu); 1678 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1679 u64 count; 1680 1681 for_each_hw_dtc_idx(hw, i, idx) { 1682 writel_relaxed(CMN_COUNTER_INIT, CMN_DT_PMEVCNT(&cmn->dtc[i], idx)); 1683 cmn->dtc[i].counters[idx] = event; 1684 } 1685 1686 count = arm_cmn_read_dtm(cmn, hw, false); 1687 local64_set(&event->hw.prev_count, count); 1688 } 1689 1690 static void arm_cmn_event_read(struct perf_event *event) 1691 { 1692 struct arm_cmn *cmn = to_cmn(event->pmu); 1693 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1694 u64 delta, new, prev; 1695 unsigned long flags; 1696 1697 if (CMN_EVENT_TYPE(event) == CMN_TYPE_DTC) { 1698 delta = arm_cmn_read_cc(cmn->dtc + hw->cc_idx); 1699 local64_add(delta, &event->count); 1700 return; 1701 } 1702 new = arm_cmn_read_dtm(cmn, hw, false); 1703 prev = local64_xchg(&event->hw.prev_count, new); 1704 1705 delta = new - prev; 1706 1707 local_irq_save(flags); 1708 for_each_hw_dtc_idx(hw, i, idx) { 1709 new = arm_cmn_read_counter(cmn->dtc + i, idx); 1710 delta += new << 16; 1711 } 1712 local_irq_restore(flags); 1713 local64_add(delta, &event->count); 1714 } 1715 1716 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn, 1717 enum cmn_filter_select fsel, u8 val) 1718 { 1719 if (!dn->filter[fsel].count) { 1720 const u64 *filter = arm_cmn_filters[dn->filter[SEL_NONE].val]; 1721 u64 reg = 0; 1722 1723 dn->filter[fsel].val = val; 1724 for (int i = SEL_OCCUP1_ID; i < SEL_MAX; i++) { 1725 if (filter[i]) 1726 reg |= field_prep(filter[i], dn->filter[i].val); 1727 } 1728 1729 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4); 1730 } else if (dn->filter[fsel].val != val) { 1731 return -EBUSY; 1732 } 1733 dn->filter[fsel].count++; 1734 return 0; 1735 } 1736 1737 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx, 1738 int eventid, bool wide_sel) 1739 { 1740 if (wide_sel) { 1741 dn->event_w[dtm_idx] = eventid; 1742 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); 1743 } else { 1744 dn->event[dtm_idx] = eventid; 1745 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); 1746 } 1747 } 1748 1749 static void arm_cmn_event_start(struct perf_event *event, int flags) 1750 { 1751 struct arm_cmn *cmn = to_cmn(event->pmu); 1752 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1753 struct arm_cmn_node *dn; 1754 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1755 int i; 1756 1757 if (type == CMN_TYPE_DTC) { 1758 struct arm_cmn_dtc *dtc = cmn->dtc + hw->cc_idx; 1759 1760 writel_relaxed(CMN_DT_DTC_CTL_DT_EN | CMN_DT_DTC_CTL_CG_DISABLE, 1761 dtc->base + CMN_DT_DTC_CTL); 1762 writeq_relaxed(CMN_CC_INIT, CMN_DT_PMCCNTR(dtc)); 1763 dtc->cc_active = true; 1764 } else if (type == CMN_TYPE_WP) { 1765 u64 val = CMN_EVENT_WP_VAL(event); 1766 u64 mask = CMN_EVENT_WP_MASK(event); 1767 1768 for_each_hw_dn(hw, dn, i) { 1769 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1770 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i); 1771 1772 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); 1773 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); 1774 } 1775 } else for_each_hw_dn(hw, dn, i) { 1776 int dtm_idx = arm_cmn_get_dtm_idx(hw, i); 1777 1778 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event), 1779 hw->wide_sel); 1780 } 1781 } 1782 1783 static void arm_cmn_event_stop(struct perf_event *event, int flags) 1784 { 1785 struct arm_cmn *cmn = to_cmn(event->pmu); 1786 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1787 struct arm_cmn_node *dn; 1788 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1789 int i; 1790 1791 if (type == CMN_TYPE_DTC) { 1792 struct arm_cmn_dtc *dtc = cmn->dtc + hw->cc_idx; 1793 1794 dtc->cc_active = false; 1795 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); 1796 } else if (type == CMN_TYPE_WP) { 1797 for_each_hw_dn(hw, dn, i) { 1798 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1799 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i); 1800 1801 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); 1802 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); 1803 } 1804 } else for_each_hw_dn(hw, dn, i) { 1805 int dtm_idx = arm_cmn_get_dtm_idx(hw, i); 1806 1807 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel); 1808 } 1809 1810 arm_cmn_event_read(event); 1811 } 1812 1813 struct arm_cmn_val { 1814 u8 dtm_count[CMN_MAX_DTMS]; 1815 u8 filter[CMN_MAX_DTMS][SEL_MAX]; 1816 u8 wp[CMN_MAX_DTMS][4]; 1817 u8 wp_combine[CMN_MAX_DTMS][2]; 1818 int dtc_count[CMN_MAX_DTCS]; 1819 bool cycles; 1820 }; 1821 1822 static int arm_cmn_val_find_free_wp_config(struct perf_event *event, 1823 struct arm_cmn_val *val, int dtm) 1824 { 1825 int wp_idx = CMN_EVENT_EVENTID(event); 1826 1827 if (val->wp[dtm][wp_idx]) 1828 if (val->wp[dtm][++wp_idx]) 1829 return -ENOSPC; 1830 1831 return wp_idx; 1832 } 1833 1834 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val, 1835 struct perf_event *event) 1836 { 1837 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1838 struct arm_cmn_node *dn; 1839 enum cmn_node_type type; 1840 int i; 1841 1842 if (is_software_event(event)) 1843 return; 1844 1845 type = CMN_EVENT_TYPE(event); 1846 if (type == CMN_TYPE_DTC) { 1847 val->cycles = true; 1848 return; 1849 } 1850 1851 for_each_hw_dtc_idx(hw, dtc, idx) 1852 val->dtc_count[dtc]++; 1853 1854 for_each_hw_dn(hw, dn, i) { 1855 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel; 1856 1857 val->dtm_count[dtm]++; 1858 1859 if (sel) 1860 val->filter[dtm][sel] = CMN_EVENT_FILTER(event) + 1; 1861 if (sel == SEL_EVICT_STATE_SEL) 1862 val->filter[dtm][SEL_HBT_LBT_SEL] = CMN_EVENT_FILTER2(event) + 1; 1863 1864 if (type != CMN_TYPE_WP) 1865 continue; 1866 1867 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm); 1868 val->wp[dtm][wp_idx] = 1; 1869 val->wp_combine[dtm][wp_idx >> 1] += !!CMN_EVENT_WP_COMBINE(event); 1870 } 1871 } 1872 1873 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event) 1874 { 1875 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1876 struct arm_cmn_node *dn; 1877 struct perf_event *sibling, *leader = event->group_leader; 1878 enum cmn_node_type type; 1879 struct arm_cmn_val *val; 1880 int i, ret = -EINVAL; 1881 1882 if (leader == event) 1883 return 0; 1884 1885 if (event->pmu != leader->pmu && !is_software_event(leader)) 1886 return -EINVAL; 1887 1888 val = kzalloc_obj(*val); 1889 if (!val) 1890 return -ENOMEM; 1891 1892 arm_cmn_val_add_event(cmn, val, leader); 1893 1894 for_each_sibling_event(sibling, leader) 1895 arm_cmn_val_add_event(cmn, val, sibling); 1896 1897 type = CMN_EVENT_TYPE(event); 1898 if (type == CMN_TYPE_DTC) { 1899 ret = val->cycles ? -EINVAL : 0; 1900 goto done; 1901 } 1902 1903 for_each_hw_dtc_idx(hw, dtc, idx) 1904 if (val->dtc_count[dtc] == CMN_DT_NUM_COUNTERS) 1905 goto done; 1906 1907 for_each_hw_dn(hw, dn, i) { 1908 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel; 1909 1910 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS) 1911 goto done; 1912 1913 if (sel && val->filter[dtm][sel] && 1914 val->filter[dtm][sel] != CMN_EVENT_FILTER(event) + 1) 1915 goto done; 1916 1917 if (sel == SEL_EVICT_STATE_SEL && val->filter[dtm][SEL_HBT_LBT_SEL] && 1918 val->filter[dtm][SEL_HBT_LBT_SEL] != CMN_EVENT_FILTER2(event) + 1) 1919 goto done; 1920 1921 if (type != CMN_TYPE_WP) 1922 continue; 1923 1924 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm); 1925 if (wp_idx < 0) 1926 goto done; 1927 1928 if (wp_idx & 1 && 1929 val->wp_combine[dtm][wp_idx >> 1] != !!CMN_EVENT_WP_COMBINE(event)) 1930 goto done; 1931 } 1932 1933 ret = 0; 1934 done: 1935 kfree(val); 1936 return ret; 1937 } 1938 1939 static enum cmn_filter_select arm_cmn_event_filter(const struct arm_cmn *cmn, 1940 enum cmn_node_type type, 1941 unsigned int eventid) 1942 { 1943 struct arm_cmn_event_attr *e; 1944 enum cmn_model model = arm_cmn_model(cmn); 1945 1946 for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) { 1947 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr); 1948 if (e->model & model && e->type == type && e->eventid == eventid) 1949 return e->filter[0].sel; 1950 } 1951 return SEL_NONE; 1952 } 1953 1954 1955 static void arm_cmn_event_destroy(struct perf_event *event) 1956 { 1957 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1958 1959 bitmap_free(hw->dtm_idx); 1960 bitmap_free(hw->wp_idx); 1961 } 1962 1963 static int arm_cmn_event_init(struct perf_event *event) 1964 { 1965 struct arm_cmn *cmn = to_cmn(event->pmu); 1966 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1967 struct arm_cmn_node *dn; 1968 enum cmn_node_type type; 1969 bool bynodeid; 1970 u16 nodeid, eventid; 1971 1972 if (event->attr.type != event->pmu->type) 1973 return -ENOENT; 1974 1975 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 1976 return -EINVAL; 1977 1978 event->cpu = cmn->cpu; 1979 if (event->cpu < 0) 1980 return -EINVAL; 1981 1982 type = CMN_EVENT_TYPE(event); 1983 /* DTC events (i.e. cycles) already have everything they need */ 1984 if (type == CMN_TYPE_DTC) 1985 return arm_cmn_validate_group(cmn, event); 1986 1987 event->destroy = arm_cmn_event_destroy; 1988 hw->dtm_idx = arm_cmn_alloc_dtm_idx(); 1989 if (!hw->dtm_idx) 1990 return -ENOMEM; 1991 1992 eventid = CMN_EVENT_EVENTID(event); 1993 /* For watchpoints we need the actual XP node here */ 1994 if (type == CMN_TYPE_WP) { 1995 type = CMN_TYPE_XP; 1996 /* ...and we need a "real" direction */ 1997 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN) 1998 return -EINVAL; 1999 /* ...but the DTM may depend on which port we're watching */ 2000 if (cmn->multi_dtm) 2001 hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2; 2002 hw->wp_idx = arm_cmn_alloc_wp_idx(); 2003 if (!hw->wp_idx) 2004 return -ENOMEM; 2005 } else if (type == CMN_TYPE_XP && 2006 (cmn->part == PART_CMN700 || cmn->part == PART_CMN_S3)) { 2007 hw->wide_sel = true; 2008 } else if (type == CMN_TYPE_RND) { 2009 /* Secretly permit this as an alias for "rnid" events */ 2010 type = CMN_TYPE_RNI; 2011 } 2012 2013 /* This is sufficiently annoying to recalculate, so cache it */ 2014 hw->filter_sel = arm_cmn_event_filter(cmn, type, eventid); 2015 2016 bynodeid = CMN_EVENT_BYNODEID(event); 2017 nodeid = CMN_EVENT_NODEID(event); 2018 2019 hw->dn = arm_cmn_node(cmn, type); 2020 if (!hw->dn) 2021 return -EINVAL; 2022 2023 memset(hw->dtc_idx, -1, sizeof(hw->dtc_idx)); 2024 for (dn = hw->dn; dn->type == type; dn++) { 2025 if (bynodeid && dn->id != nodeid) { 2026 hw->dn++; 2027 continue; 2028 } 2029 hw->num_dns++; 2030 if (dn->dtc < 0) 2031 memset(hw->dtc_idx, 0, cmn->num_dtcs); 2032 else 2033 hw->dtc_idx[dn->dtc] = 0; 2034 2035 if (bynodeid) 2036 break; 2037 } 2038 2039 if (!hw->num_dns) { 2040 dev_dbg(cmn->dev, "invalid node 0x%x type 0x%x\n", nodeid, type); 2041 return -EINVAL; 2042 } 2043 2044 return arm_cmn_validate_group(cmn, event); 2045 } 2046 2047 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, 2048 int i) 2049 { 2050 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 2051 enum cmn_node_type type = CMN_EVENT_TYPE(event); 2052 2053 while (i--) { 2054 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset; 2055 unsigned int dtm_idx = arm_cmn_get_dtm_idx(hw, i); 2056 2057 if (type == CMN_TYPE_WP) { 2058 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i); 2059 2060 dtm->wp_event[wp_idx] = -1; 2061 } 2062 2063 if (hw->filter_sel) 2064 hw->dn[i].filter[hw->filter_sel].count--; 2065 if (hw->filter_sel == SEL_EVICT_STATE_SEL) 2066 hw->dn[i].filter[SEL_HBT_LBT_SEL].count--; 2067 2068 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); 2069 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 2070 } 2071 arm_cmn_clear_idx(hw); 2072 2073 for_each_hw_dtc_idx(hw, j, idx) 2074 cmn->dtc[j].counters[idx] = NULL; 2075 } 2076 2077 static int arm_cmn_set_event_filter(struct arm_cmn_node *dn, struct perf_event *event) 2078 { 2079 enum cmn_filter_select fsel = to_cmn_hw(event)->filter_sel; 2080 int ret = 0; 2081 2082 if (fsel) 2083 ret = arm_cmn_set_event_sel_hi(dn, fsel, CMN_EVENT_FILTER(event)); 2084 2085 if (fsel == SEL_EVICT_STATE_SEL && !ret) { 2086 ret = arm_cmn_set_event_sel_hi(dn, SEL_HBT_LBT_SEL, CMN_EVENT_FILTER2(event)); 2087 if (ret) 2088 dn->filter[fsel].count--; 2089 } 2090 return ret; 2091 } 2092 2093 static int arm_cmn_event_add(struct perf_event *event, int flags) 2094 { 2095 struct arm_cmn *cmn = to_cmn(event->pmu); 2096 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 2097 struct arm_cmn_node *dn; 2098 enum cmn_node_type type = CMN_EVENT_TYPE(event); 2099 unsigned int input_sel, i = 0; 2100 2101 if (type == CMN_TYPE_DTC) { 2102 while (cmn->dtc[i].cycles) 2103 if (++i == cmn->num_dtcs) 2104 return -ENOSPC; 2105 2106 cmn->dtc[i].cycles = event; 2107 hw->cc_idx = i; 2108 2109 if (flags & PERF_EF_START) 2110 arm_cmn_event_start(event, 0); 2111 return 0; 2112 } 2113 2114 /* Grab the global counters first... */ 2115 for_each_hw_dtc_idx(hw, j, idx) { 2116 if (cmn->part == PART_CMN600 && j > 0) { 2117 idx = hw->dtc_idx[0]; 2118 } else { 2119 idx = 0; 2120 while (cmn->dtc[j].counters[idx]) 2121 if (++idx == CMN_DT_NUM_COUNTERS) 2122 return -ENOSPC; 2123 } 2124 hw->dtc_idx[j] = idx; 2125 } 2126 2127 /* ...then the local counters to feed them */ 2128 for_each_hw_dn(hw, dn, i) { 2129 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 2130 unsigned int dtm_idx, shift, d = max_t(int, dn->dtc, 0); 2131 u64 reg; 2132 2133 dtm_idx = 0; 2134 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx)) 2135 if (++dtm_idx == CMN_DTM_NUM_COUNTERS) 2136 goto free_dtms; 2137 2138 if (type == CMN_TYPE_XP) { 2139 input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx; 2140 } else if (type == CMN_TYPE_WP) { 2141 int tmp, wp_idx; 2142 u32 cfg; 2143 2144 wp_idx = arm_cmn_find_free_wp_idx(dtm, event); 2145 if (wp_idx < 0) 2146 goto free_dtms; 2147 2148 cfg = arm_cmn_wp_config(event, wp_idx); 2149 2150 tmp = dtm->wp_event[wp_idx ^ 1]; 2151 if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) != 2152 CMN_EVENT_WP_COMBINE(cmn->dtc[d].counters[tmp])) 2153 goto free_dtms; 2154 2155 input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx; 2156 2157 arm_cmn_claim_wp_idx(dtm, event, d, wp_idx, i); 2158 writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx)); 2159 } else { 2160 struct arm_cmn_nodeid nid = arm_cmn_nid(dn); 2161 2162 if (cmn->multi_dtm) 2163 nid.port %= 2; 2164 2165 input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx + 2166 (nid.port << 4) + (nid.dev << 2); 2167 2168 if (arm_cmn_set_event_filter(dn, event)) 2169 goto free_dtms; 2170 } 2171 2172 arm_cmn_set_dtm_idx(hw, i, dtm_idx); 2173 2174 dtm->input_sel[dtm_idx] = input_sel; 2175 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx); 2176 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift); 2177 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, hw->dtc_idx[d]) << shift; 2178 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx); 2179 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low; 2180 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); 2181 } 2182 2183 /* Go go go! */ 2184 arm_cmn_init_counter(event); 2185 2186 if (flags & PERF_EF_START) 2187 arm_cmn_event_start(event, 0); 2188 2189 return 0; 2190 2191 free_dtms: 2192 arm_cmn_event_clear(cmn, event, i); 2193 return -ENOSPC; 2194 } 2195 2196 static void arm_cmn_event_del(struct perf_event *event, int flags) 2197 { 2198 struct arm_cmn *cmn = to_cmn(event->pmu); 2199 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 2200 enum cmn_node_type type = CMN_EVENT_TYPE(event); 2201 2202 arm_cmn_event_stop(event, PERF_EF_UPDATE); 2203 2204 if (type == CMN_TYPE_DTC) 2205 cmn->dtc[hw->cc_idx].cycles = NULL; 2206 else 2207 arm_cmn_event_clear(cmn, event, hw->num_dns); 2208 } 2209 2210 /* 2211 * We stop the PMU for both add and read, to avoid skew across DTM counters. 2212 * In theory we could use snapshots to read without stopping, but then it 2213 * becomes a lot trickier to deal with overlow and racing against interrupts, 2214 * plus it seems they don't work properly on some hardware anyway :( 2215 */ 2216 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags) 2217 { 2218 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN); 2219 } 2220 2221 static void arm_cmn_end_txn(struct pmu *pmu) 2222 { 2223 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN); 2224 } 2225 2226 static int arm_cmn_commit_txn(struct pmu *pmu) 2227 { 2228 arm_cmn_end_txn(pmu); 2229 return 0; 2230 } 2231 2232 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu) 2233 { 2234 unsigned int i; 2235 2236 perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu); 2237 for (i = 0; i < cmn->num_dtcs; i++) 2238 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu)); 2239 cmn->cpu = cpu; 2240 } 2241 2242 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 2243 { 2244 struct arm_cmn *cmn; 2245 int node; 2246 2247 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 2248 node = dev_to_node(cmn->dev); 2249 if (cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node) 2250 arm_cmn_migrate(cmn, cpu); 2251 return 0; 2252 } 2253 2254 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 2255 { 2256 struct arm_cmn *cmn; 2257 unsigned int target; 2258 int node; 2259 2260 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 2261 if (cpu != cmn->cpu) 2262 return 0; 2263 2264 node = dev_to_node(cmn->dev); 2265 2266 target = cpumask_any_and_but(cpumask_of_node(node), cpu_online_mask, cpu); 2267 if (target >= nr_cpu_ids) 2268 target = cpumask_any_but(cpu_online_mask, cpu); 2269 2270 if (target < nr_cpu_ids) 2271 arm_cmn_migrate(cmn, target); 2272 2273 return 0; 2274 } 2275 2276 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id) 2277 { 2278 struct arm_cmn_dtc *dtc = dev_id; 2279 irqreturn_t ret = IRQ_NONE; 2280 2281 for (;;) { 2282 u32 status = readl_relaxed(CMN_DT_PMOVSR(dtc)); 2283 u64 delta; 2284 int i; 2285 2286 for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) { 2287 if (status & (1U << i)) { 2288 ret = IRQ_HANDLED; 2289 if (WARN_ON(!dtc->counters[i])) 2290 continue; 2291 delta = (u64)arm_cmn_read_counter(dtc, i) << 16; 2292 local64_add(delta, &dtc->counters[i]->count); 2293 } 2294 } 2295 2296 if (status & (1U << CMN_DT_NUM_COUNTERS)) { 2297 ret = IRQ_HANDLED; 2298 if (dtc->cc_active && !WARN_ON(!dtc->cycles)) { 2299 delta = arm_cmn_read_cc(dtc); 2300 local64_add(delta, &dtc->cycles->count); 2301 } 2302 } 2303 2304 writel_relaxed(status, CMN_DT_PMOVSR_CLR(dtc)); 2305 2306 if (!dtc->irq_friend) 2307 return ret; 2308 dtc += dtc->irq_friend; 2309 } 2310 } 2311 2312 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */ 2313 static int arm_cmn_init_irqs(struct arm_cmn *cmn) 2314 { 2315 int i, j, irq, err; 2316 2317 for (i = 0; i < cmn->num_dtcs; i++) { 2318 irq = cmn->dtc[i].irq; 2319 for (j = i; j--; ) { 2320 if (cmn->dtc[j].irq == irq) { 2321 cmn->dtc[j].irq_friend = i - j; 2322 goto next; 2323 } 2324 } 2325 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq, 2326 IRQF_NOBALANCING | IRQF_NO_THREAD, 2327 dev_name(cmn->dev), &cmn->dtc[i]); 2328 if (err) 2329 return err; 2330 2331 err = irq_set_affinity(irq, cpumask_of(cmn->cpu)); 2332 if (err) 2333 return err; 2334 next: 2335 ; /* isn't C great? */ 2336 } 2337 return 0; 2338 } 2339 2340 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx) 2341 { 2342 int i; 2343 2344 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx); 2345 dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; 2346 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 2347 for (i = 0; i < 4; i++) { 2348 dtm->wp_event[i] = -1; 2349 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i)); 2350 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i)); 2351 } 2352 } 2353 2354 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx) 2355 { 2356 struct arm_cmn_dtc *dtc = cmn->dtc + idx; 2357 const struct resource *cfg; 2358 resource_size_t base, size; 2359 2360 dtc->pmu_base = dn->pmu_base; 2361 dtc->base = dtc->pmu_base - arm_cmn_pmu_offset(cmn, dn); 2362 dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx); 2363 if (dtc->irq < 0) 2364 return dtc->irq; 2365 2366 cfg = platform_get_resource(to_platform_device(cmn->dev), IORESOURCE_MEM, 0); 2367 base = dtc->base - cmn->base + cfg->start; 2368 size = cmn->part == PART_CMN600 ? SZ_16K : SZ_64K; 2369 if (!devm_request_mem_region(cmn->dev, base, size, dev_name(cmn->dev))) 2370 return dev_err_probe(cmn->dev, -EBUSY, 2371 "Failed to request DTC region 0x%pa\n", &base); 2372 2373 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); 2374 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, CMN_DT_PMCR(dtc)); 2375 writeq_relaxed(0, CMN_DT_PMCCNTR(dtc)); 2376 writel_relaxed(0x1ff, CMN_DT_PMOVSR_CLR(dtc)); 2377 2378 return 0; 2379 } 2380 2381 static int arm_cmn_node_cmp(const void *a, const void *b) 2382 { 2383 const struct arm_cmn_node *dna = a, *dnb = b; 2384 int cmp; 2385 2386 cmp = dna->type - dnb->type; 2387 if (!cmp) 2388 cmp = dna->logid - dnb->logid; 2389 return cmp; 2390 } 2391 2392 static int arm_cmn_init_dtcs(struct arm_cmn *cmn) 2393 { 2394 struct arm_cmn_node *dn, *xp; 2395 int dtc_idx = 0; 2396 2397 cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL); 2398 if (!cmn->dtc) 2399 return -ENOMEM; 2400 2401 sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL); 2402 2403 cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP); 2404 2405 for (dn = cmn->dns; dn->type; dn++) { 2406 if (dn->type == CMN_TYPE_XP) 2407 continue; 2408 2409 xp = arm_cmn_node_to_xp(cmn, dn); 2410 dn->dtc = xp->dtc; 2411 dn->dtm = xp->dtm; 2412 if (cmn->multi_dtm) 2413 dn->dtm += arm_cmn_nid(dn).port / 2; 2414 2415 if (dn->type == CMN_TYPE_DTC) { 2416 int err = arm_cmn_init_dtc(cmn, dn, dtc_idx++); 2417 2418 if (err) 2419 return err; 2420 } 2421 2422 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */ 2423 if (dn->type == CMN_TYPE_RND) 2424 dn->type = CMN_TYPE_RNI; 2425 2426 /* We split the RN-I off already, so let the CCLA part match CCLA events */ 2427 if (dn->type == CMN_TYPE_CCLA_RNI) 2428 dn->type = CMN_TYPE_CCLA; 2429 } 2430 2431 arm_cmn_set_state(cmn, CMN_STATE_DISABLED); 2432 2433 return 0; 2434 } 2435 2436 static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_region) 2437 { 2438 int offset = CMN_DTM_UNIT_INFO; 2439 2440 if (cmn->part == PART_CMN650 || cmn->part == PART_CI700) 2441 offset = CMN650_DTM_UNIT_INFO; 2442 2443 return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset)); 2444 } 2445 2446 static unsigned int arm_cmn_graviton5_dtc_domain(u16 xp_id) 2447 { 2448 unsigned int x = (xp_id >> 7) & 0xf; 2449 unsigned int y = (xp_id >> 3) & 0xf; 2450 2451 /* 2452 * The unit info register reads as zero; derive the DTC domain from 2453 * the XP's mesh coordinates over the 10x14 mesh. 2454 */ 2455 return (x / 5) + (y / 7) * 2; 2456 } 2457 2458 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node) 2459 { 2460 int level; 2461 u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO); 2462 2463 node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg); 2464 node->id = FIELD_GET(CMN_NI_NODE_ID, reg); 2465 node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg); 2466 2467 node->pmu_base = cmn->base + offset + arm_cmn_pmu_offset(cmn, node); 2468 2469 if (node->type == CMN_TYPE_CFG) 2470 level = 0; 2471 else if (node->type == CMN_TYPE_XP) 2472 level = 1; 2473 else 2474 level = 2; 2475 2476 dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n", 2477 (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ', 2478 node->type, node->logid, offset); 2479 } 2480 2481 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type) 2482 { 2483 switch (type) { 2484 case CMN_TYPE_HNP: 2485 return CMN_TYPE_HNI; 2486 case CMN_TYPE_CCLA_RNI: 2487 return CMN_TYPE_RNI; 2488 default: 2489 return CMN_TYPE_INVALID; 2490 } 2491 } 2492 2493 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) 2494 { 2495 void __iomem *cfg_region, __iomem *xp_region; 2496 struct arm_cmn_node cfg, *dn; 2497 struct arm_cmn_dtm *dtm; 2498 enum cmn_model model; 2499 enum cmn_part part; 2500 u16 child_count, child_poff; 2501 u64 reg; 2502 int i, j; 2503 size_t sz; 2504 bool graviton5_workaround = false; 2505 2506 arm_cmn_init_node_info(cmn, rgn_offset, &cfg); 2507 if (cfg.type != CMN_TYPE_CFG) 2508 return -ENODEV; 2509 2510 cfg_region = cmn->base + rgn_offset; 2511 2512 reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01); 2513 part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg); 2514 part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8; 2515 2516 /* Graviton5 has a customised CMN-S3 which needs some fixups */ 2517 if (cmn->part == PART_GRAVITON5) { 2518 cmn->part = PART_CMN_S3; 2519 graviton5_workaround = true; 2520 } 2521 2522 /* 600AE is close enough that it's not really worth more complexity */ 2523 if (part == PART_CMN600AE) 2524 part = PART_CMN600; 2525 if (cmn->part && cmn->part != part) 2526 dev_warn(cmn->dev, 2527 "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n", 2528 cmn->part, part); 2529 cmn->part = part; 2530 2531 reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23); 2532 cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); 2533 2534 model = arm_cmn_model(cmn); 2535 if (!model) 2536 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part); 2537 2538 /* 2539 * With the device isolation feature, if firmware has neglected to enable 2540 * an XP port then we risk locking up if we try to access anything behind 2541 * it; however prior to CMN S3 r2p0 we also have no way to tell from 2542 * Non-Secure whether any given port is disabled or not, so in that case 2543 * the only way to win is not to play... 2544 */ 2545 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL); 2546 if (reg & CMN_INFO_DEVICE_ISO_ENABLE && model == CMNS3R01) { 2547 dev_err(cmn->dev, "Device isolation enabled, not continuing due to risk of lockup\n"); 2548 return -ENODEV; 2549 } 2550 if (model < CMNS3R2) { 2551 cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN; 2552 cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg); 2553 cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg); 2554 } else { 2555 cmn->multi_dtm = reg & CMN_S3_R2_MULTIPLE_DTM_EN; 2556 } 2557 2558 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1); 2559 if (model < CMNS3R2) { 2560 cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg); 2561 cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg); 2562 } else { 2563 cmn->rsp_vc_num = FIELD_GET(CMN_S3_R2_RSP_VC_NUM, reg); 2564 cmn->dat_vc_num = FIELD_GET(CMN_S3_R2_DAT_VC_NUM, reg); 2565 cmn->snp_vc_num = FIELD_GET(CMN_S3_R2_SNP_VC_NUM, reg); 2566 cmn->req_vc_num = FIELD_GET(CMN_S3_R2_REQ_VC_NUM, reg); 2567 } 2568 2569 reg = readq_relaxed(cfg_region + CMN_CHILD_INFO); 2570 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2571 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2572 2573 cmn->num_xps = child_count; 2574 cmn->num_dns = cmn->num_xps; 2575 2576 /* Pass 1: visit the XPs, enumerate their children */ 2577 cfg_region += child_poff; 2578 for (i = 0; i < cmn->num_xps; i++) { 2579 reg = readq_relaxed(cfg_region + i * 8); 2580 xp_region = cmn->base + (reg & CMN_CHILD_NODE_ADDR); 2581 2582 reg = readq_relaxed(xp_region + CMN_CHILD_INFO); 2583 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2584 } 2585 2586 /* 2587 * Some nodes effectively have two separate types, which we'll handle 2588 * by creating one of each internally. For a (very) safe initial upper 2589 * bound, account for double the number of non-XP nodes. 2590 */ 2591 dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps, 2592 sizeof(*dn), GFP_KERNEL); 2593 if (!dn) 2594 return -ENOMEM; 2595 2596 /* Initial safe upper bound on DTMs for any possible mesh layout */ 2597 i = cmn->num_xps; 2598 if (cmn->multi_dtm) 2599 i += cmn->num_xps + 1; 2600 dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL); 2601 if (!dtm) 2602 return -ENOMEM; 2603 2604 /* Pass 2: now we can actually populate the nodes */ 2605 cmn->dns = dn; 2606 cmn->dtms = dtm; 2607 for (i = 0; i < cmn->num_xps; i++) { 2608 struct arm_cmn_node *xp = dn++; 2609 unsigned int xp_ports = 0; 2610 2611 reg = readq_relaxed(cfg_region + i * 8); 2612 xp_region = cmn->base + (reg & CMN_CHILD_NODE_ADDR); 2613 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, xp); 2614 /* 2615 * Thanks to the order in which XP logical IDs seem to be 2616 * assigned, we can handily infer the mesh X dimension by 2617 * looking out for the XP at (0,1) without needing to know 2618 * the exact node ID format, which we can later derive. 2619 */ 2620 if (xp->id == (1 << 3)) 2621 cmn->mesh_x = xp->logid; 2622 2623 if (cmn->part == PART_CMN600) 2624 xp->dtc = -1; 2625 else if (graviton5_workaround) 2626 xp->dtc = arm_cmn_graviton5_dtc_domain(xp->id); 2627 else 2628 xp->dtc = arm_cmn_dtc_domain(cmn, xp_region); 2629 2630 xp->dtm = dtm - cmn->dtms; 2631 arm_cmn_init_dtm(dtm++, xp, 0); 2632 /* 2633 * Keeping track of connected ports will let us filter out 2634 * unnecessary XP events easily, and also infer the per-XP 2635 * part of the node ID format. 2636 */ 2637 for (int p = 0; p < CMN_MAX_PORTS; p++) 2638 if (arm_cmn_device_connect_info(cmn, xp, p)) 2639 xp_ports |= BIT(p); 2640 2641 if (cmn->num_xps == 1) { 2642 xp->portid_bits = 3; 2643 xp->deviceid_bits = 2; 2644 } else if (xp_ports > 0x3) { 2645 xp->portid_bits = 2; 2646 xp->deviceid_bits = 1; 2647 } else { 2648 xp->portid_bits = 1; 2649 xp->deviceid_bits = 2; 2650 } 2651 2652 if (cmn->multi_dtm && (xp_ports > 0x3)) 2653 arm_cmn_init_dtm(dtm++, xp, 1); 2654 if (cmn->multi_dtm && (xp_ports > 0xf)) 2655 arm_cmn_init_dtm(dtm++, xp, 2); 2656 2657 cmn->ports_used |= xp_ports; 2658 2659 reg = readq_relaxed(xp_region + CMN_CHILD_INFO); 2660 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2661 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2662 2663 for (j = 0; j < child_count; j++) { 2664 reg = readq_relaxed(xp_region + child_poff + j * 8); 2665 /* 2666 * Don't even try to touch anything external, since in general 2667 * we haven't a clue how to power up arbitrary CHI requesters, 2668 * and none of them have standard PMU events anyway. Isolated 2669 * nodes effectively just do not exist at all from our PoV. 2670 */ 2671 if (reg & (CMN_CHILD_NODE_EXTERNAL | CMN_CHILD_NODE_ISOLATED)) { 2672 dev_dbg(cmn->dev, "ignoring external/isolated node %llx\n", reg); 2673 continue; 2674 } 2675 /* 2676 * AmpereOneX erratum AC04_MESH_1 makes some XPs report a bogus 2677 * child count larger than the number of valid child pointers. 2678 * A child offset of 0 can only occur on CMN-600; otherwise it 2679 * would imply the root node being its own grandchild, which 2680 * we can safely dismiss in general. 2681 */ 2682 if (reg == 0 && cmn->part != PART_CMN600) { 2683 dev_dbg(cmn->dev, "bogus child pointer?\n"); 2684 continue; 2685 } 2686 2687 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn); 2688 dn->portid_bits = xp->portid_bits; 2689 dn->deviceid_bits = xp->deviceid_bits; 2690 /* 2691 * Logical IDs are assigned from 0 per node type, so as 2692 * soon as we see one bigger than expected, we can assume 2693 * there are more than we can cope with. 2694 */ 2695 if (dn->logid > CMN_MAX_NODES_PER_EVENT) { 2696 dev_err(cmn->dev, "Node ID invalid for supported CMN versions: %d\n", dn->logid); 2697 return -ENODEV; 2698 } 2699 /* 2700 * We can utilise the "wasted" filter array slot to store 2701 * the index for referencing the filter encodings later. 2702 */ 2703 dn->filter[SEL_NONE].val = arm_cmn_filter(dn->type, model); 2704 2705 switch (dn->type) { 2706 case CMN_TYPE_DTC: 2707 if (graviton5_workaround) { 2708 /* Node info logical ID is zeroed; use the XP's */ 2709 dn->logid = xp->logid; 2710 } 2711 cmn->num_dtcs++; 2712 dn++; 2713 break; 2714 /* These guys have PMU events */ 2715 case CMN_TYPE_DVM: 2716 case CMN_TYPE_HNI: 2717 case CMN_TYPE_HNF: 2718 case CMN_TYPE_SBSX: 2719 case CMN_TYPE_RNI: 2720 case CMN_TYPE_RND: 2721 case CMN_TYPE_MTSX: 2722 case CMN_TYPE_CXRA: 2723 case CMN_TYPE_CXHA: 2724 case CMN_TYPE_CCRA: 2725 case CMN_TYPE_CCHA: 2726 case CMN_TYPE_HNS: 2727 dn++; 2728 break; 2729 case CMN_TYPE_CCLA: 2730 dn->pmu_base += CMN_CCLA_PMU_EVENT_SEL; 2731 dn++; 2732 break; 2733 /* Nothing to see here */ 2734 case CMN_TYPE_MPAM_S: 2735 case CMN_TYPE_MPAM_NS: 2736 case CMN_TYPE_RNSAM: 2737 case CMN_TYPE_CXLA: 2738 case CMN_TYPE_HNS_MPAM_S: 2739 case CMN_TYPE_HNS_MPAM_NS: 2740 case CMN_TYPE_APB: 2741 break; 2742 /* 2743 * Split "optimised" combination nodes into separate 2744 * types for the different event sets. Offsetting the 2745 * base address lets us handle the second pmu_event_sel 2746 * register via the normal mechanism later. 2747 */ 2748 case CMN_TYPE_HNP: 2749 case CMN_TYPE_CCLA_RNI: 2750 dn[1] = dn[0]; 2751 dn[0].pmu_base += CMN_CCLA_PMU_EVENT_SEL; 2752 dn[1].type = arm_cmn_subtype(dn->type); 2753 dn += 2; 2754 break; 2755 /* Something has gone horribly wrong */ 2756 default: 2757 dev_err(cmn->dev, "Device node type invalid for supported CMN versions: 0x%x\n", dn->type); 2758 return -ENODEV; 2759 } 2760 } 2761 } 2762 2763 /* Correct for any nodes we added or skipped */ 2764 cmn->num_dns = dn - cmn->dns; 2765 2766 /* Cheeky +1 to help terminate pointer-based iteration later */ 2767 sz = (void *)(dn + 1) - (void *)cmn->dns; 2768 dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL); 2769 if (dn) 2770 cmn->dns = dn; 2771 2772 sz = (void *)dtm - (void *)cmn->dtms; 2773 dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL); 2774 if (dtm) 2775 cmn->dtms = dtm; 2776 2777 /* 2778 * If mesh_x wasn't set during discovery then we never saw 2779 * an XP at (0,1), thus we must have an Nx1 configuration. 2780 */ 2781 if (!cmn->mesh_x) 2782 cmn->mesh_x = cmn->num_xps; 2783 cmn->mesh_y = cmn->num_xps / cmn->mesh_x; 2784 2785 if (max(cmn->mesh_x, cmn->mesh_y) > CMN_MAX_DIMENSION) { 2786 dev_err(cmn->dev, "Mesh size invalid for supported CMN versions: %dx%d\n", cmn->mesh_x, cmn->mesh_y); 2787 return -ENODEV; 2788 } 2789 /* 1x1 config plays havoc with XP event encodings */ 2790 if (cmn->num_xps == 1) 2791 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n"); 2792 2793 dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev); 2794 reg = cmn->ports_used; 2795 dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n", 2796 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), ®, 2797 cmn->multi_dtm ? ", multi-DTM" : ""); 2798 2799 return 0; 2800 } 2801 2802 static int arm_cmn_get_root(struct arm_cmn *cmn, const struct resource *cfg) 2803 { 2804 const struct device_node *np = cmn->dev->of_node; 2805 const struct resource *root; 2806 u32 rootnode; 2807 2808 if (cmn->part != PART_CMN600) 2809 return 0; 2810 2811 if (np) 2812 return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode; 2813 2814 root = platform_get_resource(to_platform_device(cmn->dev), IORESOURCE_MEM, 1); 2815 return root ? root->start - cfg->start : -EINVAL; 2816 } 2817 2818 static int arm_cmn_probe(struct platform_device *pdev) 2819 { 2820 struct arm_cmn *cmn; 2821 const struct resource *cfg; 2822 const char *name; 2823 static atomic_t id; 2824 int err, rootnode, this_id; 2825 2826 cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); 2827 if (!cmn) 2828 return -ENOMEM; 2829 2830 cmn->dev = &pdev->dev; 2831 cmn->part = (unsigned long)device_get_match_data(cmn->dev); 2832 cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev)); 2833 platform_set_drvdata(pdev, cmn); 2834 2835 cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2836 if (!cfg) 2837 return -EINVAL; 2838 2839 /* Map the whole region now, claim the DTCs once we've found them */ 2840 cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg)); 2841 if (!cmn->base) 2842 return -ENOMEM; 2843 2844 rootnode = arm_cmn_get_root(cmn, cfg); 2845 if (rootnode < 0) 2846 return rootnode; 2847 2848 err = arm_cmn_discover(cmn, rootnode); 2849 if (err) 2850 return err; 2851 2852 err = arm_cmn_init_dtcs(cmn); 2853 if (err) 2854 return err; 2855 2856 err = arm_cmn_init_irqs(cmn); 2857 if (err) 2858 return err; 2859 2860 cmn->pmu = (struct pmu) { 2861 .module = THIS_MODULE, 2862 .parent = cmn->dev, 2863 .attr_groups = arm_cmn_attr_groups, 2864 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 2865 .task_ctx_nr = perf_invalid_context, 2866 .pmu_enable = arm_cmn_pmu_enable, 2867 .pmu_disable = arm_cmn_pmu_disable, 2868 .event_init = arm_cmn_event_init, 2869 .add = arm_cmn_event_add, 2870 .del = arm_cmn_event_del, 2871 .start = arm_cmn_event_start, 2872 .stop = arm_cmn_event_stop, 2873 .read = arm_cmn_event_read, 2874 .start_txn = arm_cmn_start_txn, 2875 .commit_txn = arm_cmn_commit_txn, 2876 .cancel_txn = arm_cmn_end_txn, 2877 }; 2878 2879 this_id = atomic_fetch_inc(&id); 2880 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id); 2881 if (!name) 2882 return -ENOMEM; 2883 2884 err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node); 2885 if (err) 2886 return err; 2887 2888 err = perf_pmu_register(&cmn->pmu, name, -1); 2889 if (err) 2890 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2891 else 2892 arm_cmn_debugfs_init(cmn, this_id); 2893 2894 return err; 2895 } 2896 2897 static void arm_cmn_remove(struct platform_device *pdev) 2898 { 2899 struct arm_cmn *cmn = platform_get_drvdata(pdev); 2900 2901 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL); 2902 2903 perf_pmu_unregister(&cmn->pmu); 2904 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2905 debugfs_remove(cmn->debug); 2906 } 2907 2908 #ifdef CONFIG_OF 2909 static const struct of_device_id arm_cmn_of_match[] = { 2910 { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 }, 2911 { .compatible = "arm,cmn-650" }, 2912 { .compatible = "arm,cmn-700" }, 2913 { .compatible = "arm,cmn-s3" }, 2914 { .compatible = "arm,ci-700" }, 2915 {} 2916 }; 2917 MODULE_DEVICE_TABLE(of, arm_cmn_of_match); 2918 #endif 2919 2920 #ifdef CONFIG_ACPI 2921 static const struct acpi_device_id arm_cmn_acpi_match[] = { 2922 { "ARMHC600", PART_CMN600 }, 2923 { "ARMHC650" }, 2924 { "ARMHC700" }, 2925 { "ARMHC003" }, 2926 { "AMZN0070", PART_GRAVITON5 }, 2927 {} 2928 }; 2929 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match); 2930 #endif 2931 2932 static struct platform_driver arm_cmn_driver = { 2933 .driver = { 2934 .name = "arm-cmn", 2935 .of_match_table = of_match_ptr(arm_cmn_of_match), 2936 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match), 2937 .suppress_bind_attrs = true, 2938 }, 2939 .probe = arm_cmn_probe, 2940 .remove = arm_cmn_remove, 2941 }; 2942 2943 static int __init arm_cmn_init(void) 2944 { 2945 int ret; 2946 2947 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 2948 "perf/arm/cmn:online", 2949 arm_cmn_pmu_online_cpu, 2950 arm_cmn_pmu_offline_cpu); 2951 if (ret < 0) 2952 return ret; 2953 2954 arm_cmn_hp_state = ret; 2955 arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL); 2956 2957 ret = platform_driver_register(&arm_cmn_driver); 2958 if (ret) { 2959 cpuhp_remove_multi_state(arm_cmn_hp_state); 2960 debugfs_remove(arm_cmn_debugfs); 2961 } 2962 return ret; 2963 } 2964 2965 static void __exit arm_cmn_exit(void) 2966 { 2967 platform_driver_unregister(&arm_cmn_driver); 2968 cpuhp_remove_multi_state(arm_cmn_hp_state); 2969 debugfs_remove(arm_cmn_debugfs); 2970 } 2971 2972 module_init(arm_cmn_init); 2973 module_exit(arm_cmn_exit); 2974 2975 MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>"); 2976 MODULE_DESCRIPTION("Arm CMN/CI interconnect PMU driver"); 2977 MODULE_LICENSE("GPL v2"); 2978