1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2016-2020 Arm Limited 3 // CMN-600 Coherent Mesh Network PMU driver 4 5 #include <linux/acpi.h> 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/debugfs.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/perf_event.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/sort.h> 20 21 /* Common register stuff */ 22 #define CMN_NODE_INFO 0x0000 23 #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0) 24 #define CMN_NI_NODE_ID GENMASK_ULL(31, 16) 25 #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) 26 27 #define CMN_NODEID_DEVID(reg) ((reg) & 3) 28 #define CMN_NODEID_EXT_DEVID(reg) ((reg) & 1) 29 #define CMN_NODEID_PID(reg) (((reg) >> 2) & 1) 30 #define CMN_NODEID_EXT_PID(reg) (((reg) >> 1) & 3) 31 #define CMN_NODEID_1x1_PID(reg) (((reg) >> 2) & 7) 32 #define CMN_NODEID_X(reg, bits) ((reg) >> (3 + (bits))) 33 #define CMN_NODEID_Y(reg, bits) (((reg) >> 3) & ((1U << (bits)) - 1)) 34 35 #define CMN_CHILD_INFO 0x0080 36 #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0) 37 #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16) 38 39 #define CMN_CHILD_NODE_ADDR GENMASK(29, 0) 40 #define CMN_CHILD_NODE_EXTERNAL BIT(31) 41 42 #define CMN_MAX_DIMENSION 12 43 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION) 44 #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4) 45 46 /* The CFG node has various info besides the discovery tree */ 47 #define CMN_CFGM_PERIPH_ID_2 0x0010 48 #define CMN_CFGM_PID2_REVISION GENMASK(7, 4) 49 50 #define CMN_CFGM_INFO_GLOBAL 0x900 51 #define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63) 52 #define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52) 53 #define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50) 54 55 #define CMN_CFGM_INFO_GLOBAL_1 0x908 56 #define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2) 57 #define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0) 58 59 /* XPs also have some local topology info which has uses too */ 60 #define CMN_MXP__CONNECT_INFO(p) (0x0008 + 8 * (p)) 61 #define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(4, 0) 62 63 #define CMN_MAX_PORTS 6 64 #define CI700_CONNECT_INFO_P2_5_OFFSET 0x10 65 66 /* PMU registers occupy the 3rd 4KB page of each node's region */ 67 #define CMN_PMU_OFFSET 0x2000 68 69 /* For most nodes, this is all there is */ 70 #define CMN_PMU_EVENT_SEL 0x000 71 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42) 72 #define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35) 73 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */ 74 #define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32) 75 76 /* HN-Ps are weird... */ 77 #define CMN_HNP_PMU_EVENT_SEL 0x008 78 79 /* DTMs live in the PMU space of XP registers */ 80 #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18) 81 #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00) 82 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19) 83 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17) 84 #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9) 85 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8) 86 #define CMN600_WPn_CONFIG_WP_COMBINE BIT(6) 87 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5) 88 #define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4) 89 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1) 90 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0) 91 #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08) 92 #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10) 93 94 #define CMN_DTM_PMU_CONFIG 0x210 95 #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32) 96 #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00 97 #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04 98 #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10 99 #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16) 100 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4) 101 #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n)) 102 #define CMN__PMEVCNT23_COMBINED BIT(2) 103 #define CMN__PMEVCNT01_COMBINED BIT(1) 104 #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0) 105 106 #define CMN_DTM_PMEVCNT 0x220 107 108 #define CMN_DTM_PMEVCNTSR 0x240 109 110 #define CMN_DTM_UNIT_INFO 0x0910 111 112 #define CMN_DTM_NUM_COUNTERS 4 113 /* Want more local counters? Why not replicate the whole DTM! Ugh... */ 114 #define CMN_DTM_OFFSET(n) ((n) * 0x200) 115 116 /* The DTC node is where the magic happens */ 117 #define CMN_DT_DTC_CTL 0x0a00 118 #define CMN_DT_DTC_CTL_DT_EN BIT(0) 119 120 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */ 121 #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4) 122 #define CMN_DT_PMEVCNT(n) (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n)) 123 #define CMN_DT_PMCCNTR (CMN_PMU_OFFSET + 0x40) 124 125 #define CMN_DT_PMEVCNTSR(n) (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n)) 126 #define CMN_DT_PMCCNTRSR (CMN_PMU_OFFSET + 0x90) 127 128 #define CMN_DT_PMCR (CMN_PMU_OFFSET + 0x100) 129 #define CMN_DT_PMCR_PMU_EN BIT(0) 130 #define CMN_DT_PMCR_CNTR_RST BIT(5) 131 #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6) 132 133 #define CMN_DT_PMOVSR (CMN_PMU_OFFSET + 0x118) 134 #define CMN_DT_PMOVSR_CLR (CMN_PMU_OFFSET + 0x120) 135 136 #define CMN_DT_PMSSR (CMN_PMU_OFFSET + 0x128) 137 #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n) 138 139 #define CMN_DT_PMSRR (CMN_PMU_OFFSET + 0x130) 140 #define CMN_DT_PMSRR_SS_REQ BIT(0) 141 142 #define CMN_DT_NUM_COUNTERS 8 143 #define CMN_MAX_DTCS 4 144 145 /* 146 * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles, 147 * so throwing away one bit to make overflow handling easy is no big deal. 148 */ 149 #define CMN_COUNTER_INIT 0x80000000 150 /* Similarly for the 40-bit cycle counter */ 151 #define CMN_CC_INIT 0x8000000000ULL 152 153 154 /* Event attributes */ 155 #define CMN_CONFIG_TYPE GENMASK_ULL(15, 0) 156 #define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16) 157 #define CMN_CONFIG_OCCUPID GENMASK_ULL(30, 27) 158 #define CMN_CONFIG_BYNODEID BIT_ULL(31) 159 #define CMN_CONFIG_NODEID GENMASK_ULL(47, 32) 160 161 #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config) 162 #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config) 163 #define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config) 164 #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config) 165 #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config) 166 167 #define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27) 168 #define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48) 169 #define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51) 170 /* Note that we don't yet support the tertiary match group on newer IPs */ 171 #define CMN_CONFIG_WP_GRP BIT_ULL(56) 172 #define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(57) 173 #define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0) 174 #define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0) 175 176 #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config) 177 #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config) 178 #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config) 179 #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config) 180 #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config) 181 #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1) 182 #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2) 183 184 /* Made-up event IDs for watchpoint direction */ 185 #define CMN_WP_UP 0 186 #define CMN_WP_DOWN 2 187 188 189 enum cmn_model { 190 CMN600 = 1, 191 CMN650 = 2, 192 CMN700 = 4, 193 CI700 = 8, 194 /* ...and then we can use bitmap tricks for commonality */ 195 CMN_ANY = -1, 196 NOT_CMN600 = -2, 197 CMN_650ON = CMN650 | CMN700, 198 }; 199 200 /* CMN-600 r0px shouldn't exist in silicon, thankfully */ 201 enum cmn_revision { 202 CMN600_R1P0, 203 CMN600_R1P1, 204 CMN600_R1P2, 205 CMN600_R1P3, 206 CMN600_R2P0, 207 CMN600_R3P0, 208 CMN600_R3P1, 209 CMN650_R0P0 = 0, 210 CMN650_R1P0, 211 CMN650_R1P1, 212 CMN650_R2P0, 213 CMN650_R1P2, 214 CMN700_R0P0 = 0, 215 CMN700_R1P0, 216 CMN700_R2P0, 217 CI700_R0P0 = 0, 218 CI700_R1P0, 219 CI700_R2P0, 220 }; 221 222 enum cmn_node_type { 223 CMN_TYPE_INVALID, 224 CMN_TYPE_DVM, 225 CMN_TYPE_CFG, 226 CMN_TYPE_DTC, 227 CMN_TYPE_HNI, 228 CMN_TYPE_HNF, 229 CMN_TYPE_XP, 230 CMN_TYPE_SBSX, 231 CMN_TYPE_MPAM_S, 232 CMN_TYPE_MPAM_NS, 233 CMN_TYPE_RNI, 234 CMN_TYPE_RND = 0xd, 235 CMN_TYPE_RNSAM = 0xf, 236 CMN_TYPE_MTSX, 237 CMN_TYPE_HNP, 238 CMN_TYPE_CXRA = 0x100, 239 CMN_TYPE_CXHA, 240 CMN_TYPE_CXLA, 241 CMN_TYPE_CCRA, 242 CMN_TYPE_CCHA, 243 CMN_TYPE_CCLA, 244 CMN_TYPE_CCLA_RNI, 245 /* Not a real node type */ 246 CMN_TYPE_WP = 0x7770 247 }; 248 249 enum cmn_filter_select { 250 SEL_NONE = -1, 251 SEL_OCCUP1ID, 252 SEL_CLASS_OCCUP_ID, 253 SEL_CBUSY_SNTHROTTLE_SEL, 254 SEL_MAX 255 }; 256 257 struct arm_cmn_node { 258 void __iomem *pmu_base; 259 u16 id, logid; 260 enum cmn_node_type type; 261 262 int dtm; 263 union { 264 /* DN/HN-F/CXHA */ 265 struct { 266 u8 val : 4; 267 u8 count : 4; 268 } occupid[SEL_MAX]; 269 /* XP */ 270 u8 dtc; 271 }; 272 union { 273 u8 event[4]; 274 __le32 event_sel; 275 u16 event_w[4]; 276 __le64 event_sel_w; 277 }; 278 }; 279 280 struct arm_cmn_dtm { 281 void __iomem *base; 282 u32 pmu_config_low; 283 union { 284 u8 input_sel[4]; 285 __le32 pmu_config_high; 286 }; 287 s8 wp_event[4]; 288 }; 289 290 struct arm_cmn_dtc { 291 void __iomem *base; 292 int irq; 293 int irq_friend; 294 bool cc_active; 295 296 struct perf_event *counters[CMN_DT_NUM_COUNTERS]; 297 struct perf_event *cycles; 298 }; 299 300 #define CMN_STATE_DISABLED BIT(0) 301 #define CMN_STATE_TXN BIT(1) 302 303 struct arm_cmn { 304 struct device *dev; 305 void __iomem *base; 306 unsigned int state; 307 308 enum cmn_revision rev; 309 enum cmn_model model; 310 u8 mesh_x; 311 u8 mesh_y; 312 u16 num_xps; 313 u16 num_dns; 314 bool multi_dtm; 315 u8 ports_used; 316 struct { 317 unsigned int rsp_vc_num : 2; 318 unsigned int dat_vc_num : 2; 319 unsigned int snp_vc_num : 2; 320 unsigned int req_vc_num : 2; 321 }; 322 323 struct arm_cmn_node *xps; 324 struct arm_cmn_node *dns; 325 326 struct arm_cmn_dtm *dtms; 327 struct arm_cmn_dtc *dtc; 328 unsigned int num_dtcs; 329 330 int cpu; 331 struct hlist_node cpuhp_node; 332 333 struct pmu pmu; 334 struct dentry *debug; 335 }; 336 337 #define to_cmn(p) container_of(p, struct arm_cmn, pmu) 338 339 static int arm_cmn_hp_state; 340 341 struct arm_cmn_nodeid { 342 u8 x; 343 u8 y; 344 u8 port; 345 u8 dev; 346 }; 347 348 static int arm_cmn_xyidbits(const struct arm_cmn *cmn) 349 { 350 return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1) | 2); 351 } 352 353 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id) 354 { 355 struct arm_cmn_nodeid nid; 356 357 if (cmn->num_xps == 1) { 358 nid.x = 0; 359 nid.y = 0; 360 nid.port = CMN_NODEID_1x1_PID(id); 361 nid.dev = CMN_NODEID_DEVID(id); 362 } else { 363 int bits = arm_cmn_xyidbits(cmn); 364 365 nid.x = CMN_NODEID_X(id, bits); 366 nid.y = CMN_NODEID_Y(id, bits); 367 if (cmn->ports_used & 0xc) { 368 nid.port = CMN_NODEID_EXT_PID(id); 369 nid.dev = CMN_NODEID_EXT_DEVID(id); 370 } else { 371 nid.port = CMN_NODEID_PID(id); 372 nid.dev = CMN_NODEID_DEVID(id); 373 } 374 } 375 return nid; 376 } 377 378 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn, 379 const struct arm_cmn_node *dn) 380 { 381 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); 382 int xp_idx = cmn->mesh_x * nid.y + nid.x; 383 384 return cmn->xps + xp_idx; 385 } 386 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, 387 enum cmn_node_type type) 388 { 389 struct arm_cmn_node *dn; 390 391 for (dn = cmn->dns; dn->type; dn++) 392 if (dn->type == type) 393 return dn; 394 return NULL; 395 } 396 397 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn, 398 const struct arm_cmn_node *xp, int port) 399 { 400 int offset = CMN_MXP__CONNECT_INFO(port); 401 402 if (port >= 2) { 403 if (cmn->model & (CMN600 | CMN650)) 404 return 0; 405 /* 406 * CI-700 may have extra ports, but still has the 407 * mesh_port_connect_info registers in the way. 408 */ 409 if (cmn->model == CI700) 410 offset += CI700_CONNECT_INFO_P2_5_OFFSET; 411 } 412 413 return readl_relaxed(xp->pmu_base - CMN_PMU_OFFSET + offset); 414 } 415 416 static struct dentry *arm_cmn_debugfs; 417 418 #ifdef CONFIG_DEBUG_FS 419 static const char *arm_cmn_device_type(u8 type) 420 { 421 switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) { 422 case 0x00: return " |"; 423 case 0x01: return " RN-I |"; 424 case 0x02: return " RN-D |"; 425 case 0x04: return " RN-F_B |"; 426 case 0x05: return "RN-F_B_E|"; 427 case 0x06: return " RN-F_A |"; 428 case 0x07: return "RN-F_A_E|"; 429 case 0x08: return " HN-T |"; 430 case 0x09: return " HN-I |"; 431 case 0x0a: return " HN-D |"; 432 case 0x0b: return " HN-P |"; 433 case 0x0c: return " SN-F |"; 434 case 0x0d: return " SBSX |"; 435 case 0x0e: return " HN-F |"; 436 case 0x0f: return " SN-F_E |"; 437 case 0x10: return " SN-F_D |"; 438 case 0x11: return " CXHA |"; 439 case 0x12: return " CXRA |"; 440 case 0x13: return " CXRH |"; 441 case 0x14: return " RN-F_D |"; 442 case 0x15: return "RN-F_D_E|"; 443 case 0x16: return " RN-F_C |"; 444 case 0x17: return "RN-F_C_E|"; 445 case 0x18: return " RN-F_E |"; 446 case 0x19: return "RN-F_E_E|"; 447 case 0x1c: return " MTSX |"; 448 case 0x1d: return " HN-V |"; 449 case 0x1e: return " CCG |"; 450 default: return " ???? |"; 451 } 452 } 453 454 static void arm_cmn_show_logid(struct seq_file *s, int x, int y, int p, int d) 455 { 456 struct arm_cmn *cmn = s->private; 457 struct arm_cmn_node *dn; 458 459 for (dn = cmn->dns; dn->type; dn++) { 460 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); 461 462 if (dn->type == CMN_TYPE_XP) 463 continue; 464 /* Ignore the extra components that will overlap on some ports */ 465 if (dn->type < CMN_TYPE_HNI) 466 continue; 467 468 if (nid.x != x || nid.y != y || nid.port != p || nid.dev != d) 469 continue; 470 471 seq_printf(s, " #%-2d |", dn->logid); 472 return; 473 } 474 seq_puts(s, " |"); 475 } 476 477 static int arm_cmn_map_show(struct seq_file *s, void *data) 478 { 479 struct arm_cmn *cmn = s->private; 480 int x, y, p, pmax = fls(cmn->ports_used); 481 482 seq_puts(s, " X"); 483 for (x = 0; x < cmn->mesh_x; x++) 484 seq_printf(s, " %d ", x); 485 seq_puts(s, "\nY P D+"); 486 y = cmn->mesh_y; 487 while (y--) { 488 int xp_base = cmn->mesh_x * y; 489 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION]; 490 491 for (x = 0; x < cmn->mesh_x; x++) 492 seq_puts(s, "--------+"); 493 494 seq_printf(s, "\n%d |", y); 495 for (x = 0; x < cmn->mesh_x; x++) { 496 struct arm_cmn_node *xp = cmn->xps + xp_base + x; 497 498 for (p = 0; p < CMN_MAX_PORTS; p++) 499 port[p][x] = arm_cmn_device_connect_info(cmn, xp, p); 500 seq_printf(s, " XP #%-2d |", xp_base + x); 501 } 502 503 seq_puts(s, "\n |"); 504 for (x = 0; x < cmn->mesh_x; x++) { 505 u8 dtc = cmn->xps[xp_base + x].dtc; 506 507 if (dtc & (dtc - 1)) 508 seq_puts(s, " DTC ?? |"); 509 else 510 seq_printf(s, " DTC %ld |", __ffs(dtc)); 511 } 512 seq_puts(s, "\n |"); 513 for (x = 0; x < cmn->mesh_x; x++) 514 seq_puts(s, "........|"); 515 516 for (p = 0; p < pmax; p++) { 517 seq_printf(s, "\n %d |", p); 518 for (x = 0; x < cmn->mesh_x; x++) 519 seq_puts(s, arm_cmn_device_type(port[p][x])); 520 seq_puts(s, "\n 0|"); 521 for (x = 0; x < cmn->mesh_x; x++) 522 arm_cmn_show_logid(s, x, y, p, 0); 523 seq_puts(s, "\n 1|"); 524 for (x = 0; x < cmn->mesh_x; x++) 525 arm_cmn_show_logid(s, x, y, p, 1); 526 } 527 seq_puts(s, "\n-----+"); 528 } 529 for (x = 0; x < cmn->mesh_x; x++) 530 seq_puts(s, "--------+"); 531 seq_puts(s, "\n"); 532 return 0; 533 } 534 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map); 535 536 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) 537 { 538 const char *name = "map"; 539 540 if (id > 0) 541 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id); 542 if (!name) 543 return; 544 545 cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops); 546 } 547 #else 548 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {} 549 #endif 550 551 struct arm_cmn_hw_event { 552 struct arm_cmn_node *dn; 553 u64 dtm_idx[4]; 554 unsigned int dtc_idx; 555 u8 dtcs_used; 556 u8 num_dns; 557 u8 dtm_offset; 558 bool wide_sel; 559 enum cmn_filter_select filter_sel; 560 }; 561 562 #define for_each_hw_dn(hw, dn, i) \ 563 for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++) 564 565 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event) 566 { 567 BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target)); 568 return (struct arm_cmn_hw_event *)&event->hw; 569 } 570 571 static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val) 572 { 573 x[pos / 32] |= (u64)val << ((pos % 32) * 2); 574 } 575 576 static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos) 577 { 578 return (x[pos / 32] >> ((pos % 32) * 2)) & 3; 579 } 580 581 struct arm_cmn_event_attr { 582 struct device_attribute attr; 583 enum cmn_model model; 584 enum cmn_node_type type; 585 enum cmn_filter_select fsel; 586 u16 eventid; 587 u8 occupid; 588 }; 589 590 struct arm_cmn_format_attr { 591 struct device_attribute attr; 592 u64 field; 593 int config; 594 }; 595 596 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\ 597 (&((struct arm_cmn_event_attr[]) {{ \ 598 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \ 599 .model = _model, \ 600 .type = _type, \ 601 .eventid = _eventid, \ 602 .occupid = _occupid, \ 603 .fsel = _fsel, \ 604 }})[0].attr.attr) 605 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid) \ 606 _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE) 607 608 static ssize_t arm_cmn_event_show(struct device *dev, 609 struct device_attribute *attr, char *buf) 610 { 611 struct arm_cmn_event_attr *eattr; 612 613 eattr = container_of(attr, typeof(*eattr), attr); 614 615 if (eattr->type == CMN_TYPE_DTC) 616 return sysfs_emit(buf, "type=0x%x\n", eattr->type); 617 618 if (eattr->type == CMN_TYPE_WP) 619 return sysfs_emit(buf, 620 "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n", 621 eattr->type, eattr->eventid); 622 623 if (eattr->fsel > SEL_NONE) 624 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n", 625 eattr->type, eattr->eventid, eattr->occupid); 626 627 return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type, 628 eattr->eventid); 629 } 630 631 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, 632 struct attribute *attr, 633 int unused) 634 { 635 struct device *dev = kobj_to_dev(kobj); 636 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 637 struct arm_cmn_event_attr *eattr; 638 enum cmn_node_type type; 639 u16 eventid; 640 641 eattr = container_of(attr, typeof(*eattr), attr.attr); 642 643 if (!(eattr->model & cmn->model)) 644 return 0; 645 646 type = eattr->type; 647 eventid = eattr->eventid; 648 649 /* Watchpoints aren't nodes, so avoid confusion */ 650 if (type == CMN_TYPE_WP) 651 return attr->mode; 652 653 /* Hide XP events for unused interfaces/channels */ 654 if (type == CMN_TYPE_XP) { 655 unsigned int intf = (eventid >> 2) & 7; 656 unsigned int chan = eventid >> 5; 657 658 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3))) 659 return 0; 660 661 if (chan == 4 && cmn->model == CMN600) 662 return 0; 663 664 if ((chan == 5 && cmn->rsp_vc_num < 2) || 665 (chan == 6 && cmn->dat_vc_num < 2) || 666 (chan == 7 && cmn->snp_vc_num < 2) || 667 (chan == 8 && cmn->req_vc_num < 2)) 668 return 0; 669 } 670 671 /* Revision-specific differences */ 672 if (cmn->model == CMN600) { 673 if (cmn->rev < CMN600_R1P3) { 674 if (type == CMN_TYPE_CXRA && eventid > 0x10) 675 return 0; 676 } 677 if (cmn->rev < CMN600_R1P2) { 678 if (type == CMN_TYPE_HNF && eventid == 0x1b) 679 return 0; 680 if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA) 681 return 0; 682 } 683 } else if (cmn->model == CMN650) { 684 if (cmn->rev < CMN650_R2P0 || cmn->rev == CMN650_R1P2) { 685 if (type == CMN_TYPE_HNF && eventid > 0x22) 686 return 0; 687 if (type == CMN_TYPE_SBSX && eventid == 0x17) 688 return 0; 689 if (type == CMN_TYPE_RNI && eventid > 0x10) 690 return 0; 691 } 692 } else if (cmn->model == CMN700) { 693 if (cmn->rev < CMN700_R2P0) { 694 if (type == CMN_TYPE_HNF && eventid > 0x2c) 695 return 0; 696 if (type == CMN_TYPE_CCHA && eventid > 0x74) 697 return 0; 698 if (type == CMN_TYPE_CCLA && eventid > 0x27) 699 return 0; 700 } 701 if (cmn->rev < CMN700_R1P0) { 702 if (type == CMN_TYPE_HNF && eventid > 0x2b) 703 return 0; 704 } 705 } 706 707 if (!arm_cmn_node(cmn, type)) 708 return 0; 709 710 return attr->mode; 711 } 712 713 #define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel) \ 714 _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel) 715 #define CMN_EVENT_DTC(_name) \ 716 CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0) 717 #define _CMN_EVENT_HNF(_model, _name, _event, _occup, _fsel) \ 718 _CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event, _occup, _fsel) 719 #define CMN_EVENT_HNI(_name, _event) \ 720 CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event) 721 #define CMN_EVENT_HNP(_name, _event) \ 722 CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event) 723 #define __CMN_EVENT_XP(_name, _event) \ 724 CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event) 725 #define CMN_EVENT_SBSX(_model, _name, _event) \ 726 CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event) 727 #define CMN_EVENT_RNID(_model, _name, _event) \ 728 CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event) 729 #define CMN_EVENT_MTSX(_name, _event) \ 730 CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event) 731 #define CMN_EVENT_CXRA(_model, _name, _event) \ 732 CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event) 733 #define CMN_EVENT_CXHA(_name, _event) \ 734 CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event) 735 #define CMN_EVENT_CCRA(_name, _event) \ 736 CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event) 737 #define CMN_EVENT_CCHA(_name, _event) \ 738 CMN_EVENT_ATTR(CMN_ANY, ccha_##_name, CMN_TYPE_CCHA, _event) 739 #define CMN_EVENT_CCLA(_name, _event) \ 740 CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event) 741 #define CMN_EVENT_CCLA_RNI(_name, _event) \ 742 CMN_EVENT_ATTR(CMN_ANY, ccla_rni_##_name, CMN_TYPE_CCLA_RNI, _event) 743 744 #define CMN_EVENT_DVM(_model, _name, _event) \ 745 _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE) 746 #define CMN_EVENT_DVM_OCC(_model, _name, _event) \ 747 _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID), \ 748 _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \ 749 _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID) 750 #define CMN_EVENT_HNF(_model, _name, _event) \ 751 _CMN_EVENT_HNF(_model, _name, _event, 0, SEL_NONE) 752 #define CMN_EVENT_HNF_CLS(_model, _name, _event) \ 753 _CMN_EVENT_HNF(_model, _name##_class0, _event, 0, SEL_CLASS_OCCUP_ID), \ 754 _CMN_EVENT_HNF(_model, _name##_class1, _event, 1, SEL_CLASS_OCCUP_ID), \ 755 _CMN_EVENT_HNF(_model, _name##_class2, _event, 2, SEL_CLASS_OCCUP_ID), \ 756 _CMN_EVENT_HNF(_model, _name##_class3, _event, 3, SEL_CLASS_OCCUP_ID) 757 #define CMN_EVENT_HNF_SNT(_model, _name, _event) \ 758 _CMN_EVENT_HNF(_model, _name##_all, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \ 759 _CMN_EVENT_HNF(_model, _name##_group0_read, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \ 760 _CMN_EVENT_HNF(_model, _name##_group0_write, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \ 761 _CMN_EVENT_HNF(_model, _name##_group1_read, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \ 762 _CMN_EVENT_HNF(_model, _name##_group1_write, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \ 763 _CMN_EVENT_HNF(_model, _name##_read, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \ 764 _CMN_EVENT_HNF(_model, _name##_write, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL) 765 766 #define _CMN_EVENT_XP(_name, _event) \ 767 __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \ 768 __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \ 769 __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \ 770 __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)), \ 771 __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \ 772 __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \ 773 __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \ 774 __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2)) 775 776 /* Good thing there are only 3 fundamental XP events... */ 777 #define CMN_EVENT_XP(_name, _event) \ 778 _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \ 779 _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \ 780 _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \ 781 _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \ 782 _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \ 783 _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \ 784 _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)), \ 785 _CMN_EVENT_XP(snp2_##_name, (_event) | (7 << 5)), \ 786 _CMN_EVENT_XP(req2_##_name, (_event) | (8 << 5)) 787 788 789 static struct attribute *arm_cmn_event_attrs[] = { 790 CMN_EVENT_DTC(cycles), 791 792 /* 793 * DVM node events conflict with HN-I events in the equivalent PMU 794 * slot, but our lazy short-cut of using the DTM counter index for 795 * the PMU index as well happens to avoid that by construction. 796 */ 797 CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01), 798 CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02), 799 CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03), 800 CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04), 801 CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy, 0x05), 802 CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi, 0x01), 803 CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi, 0x02), 804 CMN_EVENT_DVM(NOT_CMN600, dvmop_pici, 0x03), 805 CMN_EVENT_DVM(NOT_CMN600, dvmop_vici, 0x04), 806 CMN_EVENT_DVM(NOT_CMN600, dvmsync, 0x05), 807 CMN_EVENT_DVM(NOT_CMN600, vmid_filtered, 0x06), 808 CMN_EVENT_DVM(NOT_CMN600, rndop_filtered, 0x07), 809 CMN_EVENT_DVM(NOT_CMN600, retry, 0x08), 810 CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv, 0x09), 811 CMN_EVENT_DVM(NOT_CMN600, txsnp_stall, 0x0a), 812 CMN_EVENT_DVM(NOT_CMN600, trkfull, 0x0b), 813 CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy, 0x0c), 814 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_cxha, 0x0d), 815 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_pdn, 0x0e), 816 CMN_EVENT_DVM(CMN700, trk_alloc, 0x0f), 817 CMN_EVENT_DVM(CMN700, trk_cxha_alloc, 0x10), 818 CMN_EVENT_DVM(CMN700, trk_pdn_alloc, 0x11), 819 CMN_EVENT_DVM(CMN700, txsnp_stall_limit, 0x12), 820 CMN_EVENT_DVM(CMN700, rxsnp_stall_starv, 0x13), 821 CMN_EVENT_DVM(CMN700, txsnp_sync_stall_op, 0x14), 822 823 CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01), 824 CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02), 825 CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03), 826 CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04), 827 CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05), 828 CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06), 829 CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07), 830 CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08), 831 CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09), 832 CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a), 833 CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b), 834 CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c), 835 CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d), 836 CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e), 837 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_all, 0x0f, 0, SEL_OCCUP1ID), 838 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_read, 0x0f, 1, SEL_OCCUP1ID), 839 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_write, 0x0f, 2, SEL_OCCUP1ID), 840 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_atomic, 0x0f, 3, SEL_OCCUP1ID), 841 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_stash, 0x0f, 4, SEL_OCCUP1ID), 842 CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10), 843 CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11), 844 CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12), 845 CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13), 846 CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14), 847 CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15), 848 CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16), 849 CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17), 850 CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18), 851 CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19), 852 CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a), 853 CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b), 854 CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c), 855 CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d), 856 CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e), 857 CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f), 858 CMN_EVENT_HNF(NOT_CMN600, atomic_fwd, 0x20), 859 CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim, 0x21), 860 CMN_EVENT_HNF(NOT_CMN600, mpam_softlim, 0x22), 861 CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster, 0x23), 862 CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict, 0x24), 863 CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line, 0x25), 864 CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup, 0x26), 865 CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry, 0x27), 866 CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs, 0x28), 867 CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin, 0x29), 868 CMN_EVENT_HNF_SNT(CMN700, sn_throttle, 0x2a), 869 CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min, 0x2b), 870 CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise, 0x2c), 871 CMN_EVENT_HNF(CMN700, snp_intv_cln, 0x2d), 872 CMN_EVENT_HNF(CMN700, nc_excl, 0x2e), 873 CMN_EVENT_HNF(CMN700, excl_mon_ovfl, 0x2f), 874 875 CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), 876 CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), 877 CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22), 878 CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23), 879 CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24), 880 CMN_EVENT_HNI(rrt_rd_alloc, 0x25), 881 CMN_EVENT_HNI(rrt_wr_alloc, 0x26), 882 CMN_EVENT_HNI(rdt_rd_alloc, 0x27), 883 CMN_EVENT_HNI(rdt_wr_alloc, 0x28), 884 CMN_EVENT_HNI(wdb_alloc, 0x29), 885 CMN_EVENT_HNI(txrsp_retryack, 0x2a), 886 CMN_EVENT_HNI(arvalid_no_arready, 0x2b), 887 CMN_EVENT_HNI(arready_no_arvalid, 0x2c), 888 CMN_EVENT_HNI(awvalid_no_awready, 0x2d), 889 CMN_EVENT_HNI(awready_no_awvalid, 0x2e), 890 CMN_EVENT_HNI(wvalid_no_wready, 0x2f), 891 CMN_EVENT_HNI(txdat_stall, 0x30), 892 CMN_EVENT_HNI(nonpcie_serialization, 0x31), 893 CMN_EVENT_HNI(pcie_serialization, 0x32), 894 895 /* 896 * HN-P events squat on top of the HN-I similarly to DVM events, except 897 * for being crammed into the same physical node as well. And of course 898 * where would the fun be if the same events were in the same order... 899 */ 900 CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl, 0x01), 901 CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl, 0x02), 902 CMN_EVENT_HNP(wdb_occ_cnt_ovfl, 0x03), 903 CMN_EVENT_HNP(rrt_wr_alloc, 0x04), 904 CMN_EVENT_HNP(rdt_wr_alloc, 0x05), 905 CMN_EVENT_HNP(wdb_alloc, 0x06), 906 CMN_EVENT_HNP(awvalid_no_awready, 0x07), 907 CMN_EVENT_HNP(awready_no_awvalid, 0x08), 908 CMN_EVENT_HNP(wvalid_no_wready, 0x09), 909 CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl, 0x11), 910 CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl, 0x12), 911 CMN_EVENT_HNP(rrt_rd_alloc, 0x13), 912 CMN_EVENT_HNP(rdt_rd_alloc, 0x14), 913 CMN_EVENT_HNP(arvalid_no_arready, 0x15), 914 CMN_EVENT_HNP(arready_no_arvalid, 0x16), 915 916 CMN_EVENT_XP(txflit_valid, 0x01), 917 CMN_EVENT_XP(txflit_stall, 0x02), 918 CMN_EVENT_XP(partial_dat_flit, 0x03), 919 /* We treat watchpoints as a special made-up class of XP events */ 920 CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP), 921 CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN), 922 923 CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01), 924 CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02), 925 CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03), 926 CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04), 927 CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05), 928 CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06), 929 CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11), 930 CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12), 931 CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13), 932 CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14), 933 CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15), 934 CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16), 935 CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl, 0x17), 936 CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21), 937 CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22), 938 CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23), 939 CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24), 940 CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25), 941 942 CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01), 943 CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02), 944 CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03), 945 CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04), 946 CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05), 947 CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06), 948 CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07), 949 CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08), 950 CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09), 951 CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a), 952 CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b), 953 CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c), 954 CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d), 955 CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e), 956 CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f), 957 CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10), 958 CMN_EVENT_RNID(CMN600, rdb_unord, 0x11), 959 CMN_EVENT_RNID(CMN600, rdb_replay, 0x12), 960 CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13), 961 CMN_EVENT_RNID(CMN600, rdb_ord, 0x14), 962 CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl, 0x11), 963 CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl, 0x12), 964 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13), 965 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14), 966 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15), 967 CMN_EVENT_RNID(NOT_CMN600, wrt_throttled, 0x16), 968 CMN_EVENT_RNID(CMN700, ldb_full, 0x17), 969 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18), 970 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19), 971 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a), 972 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b), 973 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c), 974 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d), 975 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e), 976 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f), 977 CMN_EVENT_RNID(CMN700, rrt_burst_alloc, 0x20), 978 CMN_EVENT_RNID(CMN700, awid_hash, 0x21), 979 CMN_EVENT_RNID(CMN700, atomic_alloc, 0x22), 980 CMN_EVENT_RNID(CMN700, atomic_occ_ovfl, 0x23), 981 982 CMN_EVENT_MTSX(tc_lookup, 0x01), 983 CMN_EVENT_MTSX(tc_fill, 0x02), 984 CMN_EVENT_MTSX(tc_miss, 0x03), 985 CMN_EVENT_MTSX(tdb_forward, 0x04), 986 CMN_EVENT_MTSX(tcq_hazard, 0x05), 987 CMN_EVENT_MTSX(tcq_rd_alloc, 0x06), 988 CMN_EVENT_MTSX(tcq_wr_alloc, 0x07), 989 CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08), 990 CMN_EVENT_MTSX(axi_rd_req, 0x09), 991 CMN_EVENT_MTSX(axi_wr_req, 0x0a), 992 CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b), 993 CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c), 994 995 CMN_EVENT_CXRA(CMN_ANY, rht_occ, 0x01), 996 CMN_EVENT_CXRA(CMN_ANY, sht_occ, 0x02), 997 CMN_EVENT_CXRA(CMN_ANY, rdb_occ, 0x03), 998 CMN_EVENT_CXRA(CMN_ANY, wdb_occ, 0x04), 999 CMN_EVENT_CXRA(CMN_ANY, ssb_occ, 0x05), 1000 CMN_EVENT_CXRA(CMN_ANY, snp_bcasts, 0x06), 1001 CMN_EVENT_CXRA(CMN_ANY, req_chains, 0x07), 1002 CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen, 0x08), 1003 CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls, 0x09), 1004 CMN_EVENT_CXRA(CMN_ANY, chidat_stalls, 0x0a), 1005 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b), 1006 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c), 1007 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d), 1008 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e), 1009 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f), 1010 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10), 1011 CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11), 1012 CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12), 1013 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13), 1014 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14), 1015 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15), 1016 1017 CMN_EVENT_CXHA(rddatbyp, 0x21), 1018 CMN_EVENT_CXHA(chirsp_up_stall, 0x22), 1019 CMN_EVENT_CXHA(chidat_up_stall, 0x23), 1020 CMN_EVENT_CXHA(snppcrd_link0_stall, 0x24), 1021 CMN_EVENT_CXHA(snppcrd_link1_stall, 0x25), 1022 CMN_EVENT_CXHA(snppcrd_link2_stall, 0x26), 1023 CMN_EVENT_CXHA(reqtrk_occ, 0x27), 1024 CMN_EVENT_CXHA(rdb_occ, 0x28), 1025 CMN_EVENT_CXHA(rdbyp_occ, 0x29), 1026 CMN_EVENT_CXHA(wdb_occ, 0x2a), 1027 CMN_EVENT_CXHA(snptrk_occ, 0x2b), 1028 CMN_EVENT_CXHA(sdb_occ, 0x2c), 1029 CMN_EVENT_CXHA(snphaz_occ, 0x2d), 1030 1031 CMN_EVENT_CCRA(rht_occ, 0x41), 1032 CMN_EVENT_CCRA(sht_occ, 0x42), 1033 CMN_EVENT_CCRA(rdb_occ, 0x43), 1034 CMN_EVENT_CCRA(wdb_occ, 0x44), 1035 CMN_EVENT_CCRA(ssb_occ, 0x45), 1036 CMN_EVENT_CCRA(snp_bcasts, 0x46), 1037 CMN_EVENT_CCRA(req_chains, 0x47), 1038 CMN_EVENT_CCRA(req_chain_avglen, 0x48), 1039 CMN_EVENT_CCRA(chirsp_stalls, 0x49), 1040 CMN_EVENT_CCRA(chidat_stalls, 0x4a), 1041 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0, 0x4b), 1042 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1, 0x4c), 1043 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2, 0x4d), 1044 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0, 0x4e), 1045 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1, 0x4f), 1046 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2, 0x50), 1047 CMN_EVENT_CCRA(external_chirsp_stalls, 0x51), 1048 CMN_EVENT_CCRA(external_chidat_stalls, 0x52), 1049 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0, 0x53), 1050 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1, 0x54), 1051 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2, 0x55), 1052 CMN_EVENT_CCRA(rht_alloc, 0x56), 1053 CMN_EVENT_CCRA(sht_alloc, 0x57), 1054 CMN_EVENT_CCRA(rdb_alloc, 0x58), 1055 CMN_EVENT_CCRA(wdb_alloc, 0x59), 1056 CMN_EVENT_CCRA(ssb_alloc, 0x5a), 1057 1058 CMN_EVENT_CCHA(rddatbyp, 0x61), 1059 CMN_EVENT_CCHA(chirsp_up_stall, 0x62), 1060 CMN_EVENT_CCHA(chidat_up_stall, 0x63), 1061 CMN_EVENT_CCHA(snppcrd_link0_stall, 0x64), 1062 CMN_EVENT_CCHA(snppcrd_link1_stall, 0x65), 1063 CMN_EVENT_CCHA(snppcrd_link2_stall, 0x66), 1064 CMN_EVENT_CCHA(reqtrk_occ, 0x67), 1065 CMN_EVENT_CCHA(rdb_occ, 0x68), 1066 CMN_EVENT_CCHA(rdbyp_occ, 0x69), 1067 CMN_EVENT_CCHA(wdb_occ, 0x6a), 1068 CMN_EVENT_CCHA(snptrk_occ, 0x6b), 1069 CMN_EVENT_CCHA(sdb_occ, 0x6c), 1070 CMN_EVENT_CCHA(snphaz_occ, 0x6d), 1071 CMN_EVENT_CCHA(reqtrk_alloc, 0x6e), 1072 CMN_EVENT_CCHA(rdb_alloc, 0x6f), 1073 CMN_EVENT_CCHA(rdbyp_alloc, 0x70), 1074 CMN_EVENT_CCHA(wdb_alloc, 0x71), 1075 CMN_EVENT_CCHA(snptrk_alloc, 0x72), 1076 CMN_EVENT_CCHA(sdb_alloc, 0x73), 1077 CMN_EVENT_CCHA(snphaz_alloc, 0x74), 1078 CMN_EVENT_CCHA(pb_rhu_req_occ, 0x75), 1079 CMN_EVENT_CCHA(pb_rhu_req_alloc, 0x76), 1080 CMN_EVENT_CCHA(pb_rhu_pcie_req_occ, 0x77), 1081 CMN_EVENT_CCHA(pb_rhu_pcie_req_alloc, 0x78), 1082 CMN_EVENT_CCHA(pb_pcie_wr_req_occ, 0x79), 1083 CMN_EVENT_CCHA(pb_pcie_wr_req_alloc, 0x7a), 1084 CMN_EVENT_CCHA(pb_pcie_reg_req_occ, 0x7b), 1085 CMN_EVENT_CCHA(pb_pcie_reg_req_alloc, 0x7c), 1086 CMN_EVENT_CCHA(pb_pcie_rsvd_req_occ, 0x7d), 1087 CMN_EVENT_CCHA(pb_pcie_rsvd_req_alloc, 0x7e), 1088 CMN_EVENT_CCHA(pb_rhu_dat_occ, 0x7f), 1089 CMN_EVENT_CCHA(pb_rhu_dat_alloc, 0x80), 1090 CMN_EVENT_CCHA(pb_rhu_pcie_dat_occ, 0x81), 1091 CMN_EVENT_CCHA(pb_rhu_pcie_dat_alloc, 0x82), 1092 CMN_EVENT_CCHA(pb_pcie_wr_dat_occ, 0x83), 1093 CMN_EVENT_CCHA(pb_pcie_wr_dat_alloc, 0x84), 1094 1095 CMN_EVENT_CCLA(rx_cxs, 0x21), 1096 CMN_EVENT_CCLA(tx_cxs, 0x22), 1097 CMN_EVENT_CCLA(rx_cxs_avg_size, 0x23), 1098 CMN_EVENT_CCLA(tx_cxs_avg_size, 0x24), 1099 CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure, 0x25), 1100 CMN_EVENT_CCLA(link_crdbuf_occ, 0x26), 1101 CMN_EVENT_CCLA(link_crdbuf_alloc, 0x27), 1102 CMN_EVENT_CCLA(pfwd_rcvr_cxs, 0x28), 1103 CMN_EVENT_CCLA(pfwd_sndr_num_flits, 0x29), 1104 CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd, 0x2a), 1105 CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd, 0x2b), 1106 1107 NULL 1108 }; 1109 1110 static const struct attribute_group arm_cmn_event_attrs_group = { 1111 .name = "events", 1112 .attrs = arm_cmn_event_attrs, 1113 .is_visible = arm_cmn_event_attr_is_visible, 1114 }; 1115 1116 static ssize_t arm_cmn_format_show(struct device *dev, 1117 struct device_attribute *attr, char *buf) 1118 { 1119 struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr); 1120 int lo = __ffs(fmt->field), hi = __fls(fmt->field); 1121 1122 if (lo == hi) 1123 return sysfs_emit(buf, "config:%d\n", lo); 1124 1125 if (!fmt->config) 1126 return sysfs_emit(buf, "config:%d-%d\n", lo, hi); 1127 1128 return sysfs_emit(buf, "config%d:%d-%d\n", fmt->config, lo, hi); 1129 } 1130 1131 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \ 1132 (&((struct arm_cmn_format_attr[]) {{ \ 1133 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \ 1134 .config = _cfg, \ 1135 .field = _fld, \ 1136 }})[0].attr.attr) 1137 #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld) 1138 1139 static struct attribute *arm_cmn_format_attrs[] = { 1140 CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE), 1141 CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID), 1142 CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID), 1143 CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID), 1144 CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID), 1145 1146 CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL), 1147 CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL), 1148 CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP), 1149 CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE), 1150 CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE), 1151 1152 _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL), 1153 _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK), 1154 1155 NULL 1156 }; 1157 1158 static const struct attribute_group arm_cmn_format_attrs_group = { 1159 .name = "format", 1160 .attrs = arm_cmn_format_attrs, 1161 }; 1162 1163 static ssize_t arm_cmn_cpumask_show(struct device *dev, 1164 struct device_attribute *attr, char *buf) 1165 { 1166 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1167 1168 return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu)); 1169 } 1170 1171 static struct device_attribute arm_cmn_cpumask_attr = 1172 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL); 1173 1174 static struct attribute *arm_cmn_cpumask_attrs[] = { 1175 &arm_cmn_cpumask_attr.attr, 1176 NULL, 1177 }; 1178 1179 static const struct attribute_group arm_cmn_cpumask_attr_group = { 1180 .attrs = arm_cmn_cpumask_attrs, 1181 }; 1182 1183 static const struct attribute_group *arm_cmn_attr_groups[] = { 1184 &arm_cmn_event_attrs_group, 1185 &arm_cmn_format_attrs_group, 1186 &arm_cmn_cpumask_attr_group, 1187 NULL 1188 }; 1189 1190 static int arm_cmn_wp_idx(struct perf_event *event) 1191 { 1192 return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event); 1193 } 1194 1195 static u32 arm_cmn_wp_config(struct perf_event *event) 1196 { 1197 u32 config; 1198 u32 dev = CMN_EVENT_WP_DEV_SEL(event); 1199 u32 chn = CMN_EVENT_WP_CHN_SEL(event); 1200 u32 grp = CMN_EVENT_WP_GRP(event); 1201 u32 exc = CMN_EVENT_WP_EXCLUSIVE(event); 1202 u32 combine = CMN_EVENT_WP_COMBINE(event); 1203 bool is_cmn600 = to_cmn(event->pmu)->model == CMN600; 1204 1205 config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) | 1206 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) | 1207 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) | 1208 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1); 1209 if (exc) 1210 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE : 1211 CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE; 1212 if (combine && !grp) 1213 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE : 1214 CMN_DTM_WPn_CONFIG_WP_COMBINE; 1215 return config; 1216 } 1217 1218 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state) 1219 { 1220 if (!cmn->state) 1221 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR); 1222 cmn->state |= state; 1223 } 1224 1225 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state) 1226 { 1227 cmn->state &= ~state; 1228 if (!cmn->state) 1229 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, 1230 cmn->dtc[0].base + CMN_DT_PMCR); 1231 } 1232 1233 static void arm_cmn_pmu_enable(struct pmu *pmu) 1234 { 1235 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED); 1236 } 1237 1238 static void arm_cmn_pmu_disable(struct pmu *pmu) 1239 { 1240 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED); 1241 } 1242 1243 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, 1244 bool snapshot) 1245 { 1246 struct arm_cmn_dtm *dtm = NULL; 1247 struct arm_cmn_node *dn; 1248 unsigned int i, offset, dtm_idx; 1249 u64 reg, count = 0; 1250 1251 offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; 1252 for_each_hw_dn(hw, dn, i) { 1253 if (dtm != &cmn->dtms[dn->dtm]) { 1254 dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1255 reg = readq_relaxed(dtm->base + offset); 1256 } 1257 dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1258 count += (u16)(reg >> (dtm_idx * 16)); 1259 } 1260 return count; 1261 } 1262 1263 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc) 1264 { 1265 u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR); 1266 1267 writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR); 1268 return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1); 1269 } 1270 1271 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx) 1272 { 1273 u32 val, pmevcnt = CMN_DT_PMEVCNT(idx); 1274 1275 val = readl_relaxed(dtc->base + pmevcnt); 1276 writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt); 1277 return val - CMN_COUNTER_INIT; 1278 } 1279 1280 static void arm_cmn_init_counter(struct perf_event *event) 1281 { 1282 struct arm_cmn *cmn = to_cmn(event->pmu); 1283 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1284 unsigned int i, pmevcnt = CMN_DT_PMEVCNT(hw->dtc_idx); 1285 u64 count; 1286 1287 for (i = 0; hw->dtcs_used & (1U << i); i++) { 1288 writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + pmevcnt); 1289 cmn->dtc[i].counters[hw->dtc_idx] = event; 1290 } 1291 1292 count = arm_cmn_read_dtm(cmn, hw, false); 1293 local64_set(&event->hw.prev_count, count); 1294 } 1295 1296 static void arm_cmn_event_read(struct perf_event *event) 1297 { 1298 struct arm_cmn *cmn = to_cmn(event->pmu); 1299 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1300 u64 delta, new, prev; 1301 unsigned long flags; 1302 unsigned int i; 1303 1304 if (hw->dtc_idx == CMN_DT_NUM_COUNTERS) { 1305 i = __ffs(hw->dtcs_used); 1306 delta = arm_cmn_read_cc(cmn->dtc + i); 1307 local64_add(delta, &event->count); 1308 return; 1309 } 1310 new = arm_cmn_read_dtm(cmn, hw, false); 1311 prev = local64_xchg(&event->hw.prev_count, new); 1312 1313 delta = new - prev; 1314 1315 local_irq_save(flags); 1316 for (i = 0; hw->dtcs_used & (1U << i); i++) { 1317 new = arm_cmn_read_counter(cmn->dtc + i, hw->dtc_idx); 1318 delta += new << 16; 1319 } 1320 local_irq_restore(flags); 1321 local64_add(delta, &event->count); 1322 } 1323 1324 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn, 1325 enum cmn_filter_select fsel, u8 occupid) 1326 { 1327 u64 reg; 1328 1329 if (fsel == SEL_NONE) 1330 return 0; 1331 1332 if (!dn->occupid[fsel].count) { 1333 dn->occupid[fsel].val = occupid; 1334 reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL, 1335 dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) | 1336 FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID, 1337 dn->occupid[SEL_CLASS_OCCUP_ID].val) | 1338 FIELD_PREP(CMN__PMU_OCCUP1_ID, 1339 dn->occupid[SEL_OCCUP1ID].val); 1340 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4); 1341 } else if (dn->occupid[fsel].val != occupid) { 1342 return -EBUSY; 1343 } 1344 dn->occupid[fsel].count++; 1345 return 0; 1346 } 1347 1348 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx, 1349 int eventid, bool wide_sel) 1350 { 1351 if (wide_sel) { 1352 dn->event_w[dtm_idx] = eventid; 1353 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); 1354 } else { 1355 dn->event[dtm_idx] = eventid; 1356 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); 1357 } 1358 } 1359 1360 static void arm_cmn_event_start(struct perf_event *event, int flags) 1361 { 1362 struct arm_cmn *cmn = to_cmn(event->pmu); 1363 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1364 struct arm_cmn_node *dn; 1365 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1366 int i; 1367 1368 if (type == CMN_TYPE_DTC) { 1369 i = __ffs(hw->dtcs_used); 1370 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR); 1371 cmn->dtc[i].cc_active = true; 1372 } else if (type == CMN_TYPE_WP) { 1373 int wp_idx = arm_cmn_wp_idx(event); 1374 u64 val = CMN_EVENT_WP_VAL(event); 1375 u64 mask = CMN_EVENT_WP_MASK(event); 1376 1377 for_each_hw_dn(hw, dn, i) { 1378 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1379 1380 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); 1381 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); 1382 } 1383 } else for_each_hw_dn(hw, dn, i) { 1384 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1385 1386 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event), 1387 hw->wide_sel); 1388 } 1389 } 1390 1391 static void arm_cmn_event_stop(struct perf_event *event, int flags) 1392 { 1393 struct arm_cmn *cmn = to_cmn(event->pmu); 1394 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1395 struct arm_cmn_node *dn; 1396 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1397 int i; 1398 1399 if (type == CMN_TYPE_DTC) { 1400 i = __ffs(hw->dtcs_used); 1401 cmn->dtc[i].cc_active = false; 1402 } else if (type == CMN_TYPE_WP) { 1403 int wp_idx = arm_cmn_wp_idx(event); 1404 1405 for_each_hw_dn(hw, dn, i) { 1406 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1407 1408 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); 1409 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); 1410 } 1411 } else for_each_hw_dn(hw, dn, i) { 1412 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1413 1414 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel); 1415 } 1416 1417 arm_cmn_event_read(event); 1418 } 1419 1420 struct arm_cmn_val { 1421 u8 dtm_count[CMN_MAX_DTMS]; 1422 u8 occupid[CMN_MAX_DTMS][SEL_MAX]; 1423 u8 wp[CMN_MAX_DTMS][4]; 1424 int dtc_count; 1425 bool cycles; 1426 }; 1427 1428 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val, 1429 struct perf_event *event) 1430 { 1431 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1432 struct arm_cmn_node *dn; 1433 enum cmn_node_type type; 1434 int i; 1435 1436 if (is_software_event(event)) 1437 return; 1438 1439 type = CMN_EVENT_TYPE(event); 1440 if (type == CMN_TYPE_DTC) { 1441 val->cycles = true; 1442 return; 1443 } 1444 1445 val->dtc_count++; 1446 1447 for_each_hw_dn(hw, dn, i) { 1448 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel; 1449 1450 val->dtm_count[dtm]++; 1451 1452 if (sel > SEL_NONE) 1453 val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1; 1454 1455 if (type != CMN_TYPE_WP) 1456 continue; 1457 1458 wp_idx = arm_cmn_wp_idx(event); 1459 val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1; 1460 } 1461 } 1462 1463 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event) 1464 { 1465 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1466 struct arm_cmn_node *dn; 1467 struct perf_event *sibling, *leader = event->group_leader; 1468 enum cmn_node_type type; 1469 struct arm_cmn_val *val; 1470 int i, ret = -EINVAL; 1471 1472 if (leader == event) 1473 return 0; 1474 1475 if (event->pmu != leader->pmu && !is_software_event(leader)) 1476 return -EINVAL; 1477 1478 val = kzalloc(sizeof(*val), GFP_KERNEL); 1479 if (!val) 1480 return -ENOMEM; 1481 1482 arm_cmn_val_add_event(cmn, val, leader); 1483 for_each_sibling_event(sibling, leader) 1484 arm_cmn_val_add_event(cmn, val, sibling); 1485 1486 type = CMN_EVENT_TYPE(event); 1487 if (type == CMN_TYPE_DTC) { 1488 ret = val->cycles ? -EINVAL : 0; 1489 goto done; 1490 } 1491 1492 if (val->dtc_count == CMN_DT_NUM_COUNTERS) 1493 goto done; 1494 1495 for_each_hw_dn(hw, dn, i) { 1496 int wp_idx, wp_cmb, dtm = dn->dtm, sel = hw->filter_sel; 1497 1498 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS) 1499 goto done; 1500 1501 if (sel > SEL_NONE && val->occupid[dtm][sel] && 1502 val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1) 1503 goto done; 1504 1505 if (type != CMN_TYPE_WP) 1506 continue; 1507 1508 wp_idx = arm_cmn_wp_idx(event); 1509 if (val->wp[dtm][wp_idx]) 1510 goto done; 1511 1512 wp_cmb = val->wp[dtm][wp_idx ^ 1]; 1513 if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1) 1514 goto done; 1515 } 1516 1517 ret = 0; 1518 done: 1519 kfree(val); 1520 return ret; 1521 } 1522 1523 static enum cmn_filter_select arm_cmn_filter_sel(enum cmn_model model, 1524 enum cmn_node_type type, 1525 unsigned int eventid) 1526 { 1527 struct arm_cmn_event_attr *e; 1528 int i; 1529 1530 for (i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) { 1531 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr); 1532 if (e->model & model && e->type == type && e->eventid == eventid) 1533 return e->fsel; 1534 } 1535 return SEL_NONE; 1536 } 1537 1538 1539 static int arm_cmn_event_init(struct perf_event *event) 1540 { 1541 struct arm_cmn *cmn = to_cmn(event->pmu); 1542 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1543 struct arm_cmn_node *dn; 1544 enum cmn_node_type type; 1545 bool bynodeid; 1546 u16 nodeid, eventid; 1547 1548 if (event->attr.type != event->pmu->type) 1549 return -ENOENT; 1550 1551 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 1552 return -EINVAL; 1553 1554 event->cpu = cmn->cpu; 1555 if (event->cpu < 0) 1556 return -EINVAL; 1557 1558 type = CMN_EVENT_TYPE(event); 1559 /* DTC events (i.e. cycles) already have everything they need */ 1560 if (type == CMN_TYPE_DTC) 1561 return arm_cmn_validate_group(cmn, event); 1562 1563 eventid = CMN_EVENT_EVENTID(event); 1564 /* For watchpoints we need the actual XP node here */ 1565 if (type == CMN_TYPE_WP) { 1566 type = CMN_TYPE_XP; 1567 /* ...and we need a "real" direction */ 1568 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN) 1569 return -EINVAL; 1570 /* ...but the DTM may depend on which port we're watching */ 1571 if (cmn->multi_dtm) 1572 hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2; 1573 } else if (type == CMN_TYPE_XP && cmn->model == CMN700) { 1574 hw->wide_sel = true; 1575 } 1576 1577 /* This is sufficiently annoying to recalculate, so cache it */ 1578 hw->filter_sel = arm_cmn_filter_sel(cmn->model, type, eventid); 1579 1580 bynodeid = CMN_EVENT_BYNODEID(event); 1581 nodeid = CMN_EVENT_NODEID(event); 1582 1583 hw->dn = arm_cmn_node(cmn, type); 1584 if (!hw->dn) 1585 return -EINVAL; 1586 for (dn = hw->dn; dn->type == type; dn++) { 1587 if (bynodeid && dn->id != nodeid) { 1588 hw->dn++; 1589 continue; 1590 } 1591 hw->num_dns++; 1592 if (bynodeid) 1593 break; 1594 } 1595 1596 if (!hw->num_dns) { 1597 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, nodeid); 1598 1599 dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n", 1600 nodeid, nid.x, nid.y, nid.port, nid.dev, type); 1601 return -EINVAL; 1602 } 1603 /* 1604 * Keep assuming non-cycles events count in all DTC domains; turns out 1605 * it's hard to make a worthwhile optimisation around this, short of 1606 * going all-in with domain-local counter allocation as well. 1607 */ 1608 hw->dtcs_used = (1U << cmn->num_dtcs) - 1; 1609 1610 return arm_cmn_validate_group(cmn, event); 1611 } 1612 1613 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, 1614 int i) 1615 { 1616 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1617 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1618 1619 while (i--) { 1620 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset; 1621 unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1622 1623 if (type == CMN_TYPE_WP) 1624 dtm->wp_event[arm_cmn_wp_idx(event)] = -1; 1625 1626 if (hw->filter_sel > SEL_NONE) 1627 hw->dn[i].occupid[hw->filter_sel].count--; 1628 1629 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); 1630 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 1631 } 1632 memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx)); 1633 1634 for (i = 0; hw->dtcs_used & (1U << i); i++) 1635 cmn->dtc[i].counters[hw->dtc_idx] = NULL; 1636 } 1637 1638 static int arm_cmn_event_add(struct perf_event *event, int flags) 1639 { 1640 struct arm_cmn *cmn = to_cmn(event->pmu); 1641 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1642 struct arm_cmn_dtc *dtc = &cmn->dtc[0]; 1643 struct arm_cmn_node *dn; 1644 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1645 unsigned int i, dtc_idx, input_sel; 1646 1647 if (type == CMN_TYPE_DTC) { 1648 i = 0; 1649 while (cmn->dtc[i].cycles) 1650 if (++i == cmn->num_dtcs) 1651 return -ENOSPC; 1652 1653 cmn->dtc[i].cycles = event; 1654 hw->dtc_idx = CMN_DT_NUM_COUNTERS; 1655 hw->dtcs_used = 1U << i; 1656 1657 if (flags & PERF_EF_START) 1658 arm_cmn_event_start(event, 0); 1659 return 0; 1660 } 1661 1662 /* Grab a free global counter first... */ 1663 dtc_idx = 0; 1664 while (dtc->counters[dtc_idx]) 1665 if (++dtc_idx == CMN_DT_NUM_COUNTERS) 1666 return -ENOSPC; 1667 1668 hw->dtc_idx = dtc_idx; 1669 1670 /* ...then the local counters to feed it. */ 1671 for_each_hw_dn(hw, dn, i) { 1672 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1673 unsigned int dtm_idx, shift; 1674 u64 reg; 1675 1676 dtm_idx = 0; 1677 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx)) 1678 if (++dtm_idx == CMN_DTM_NUM_COUNTERS) 1679 goto free_dtms; 1680 1681 if (type == CMN_TYPE_XP) { 1682 input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx; 1683 } else if (type == CMN_TYPE_WP) { 1684 int tmp, wp_idx = arm_cmn_wp_idx(event); 1685 u32 cfg = arm_cmn_wp_config(event); 1686 1687 if (dtm->wp_event[wp_idx] >= 0) 1688 goto free_dtms; 1689 1690 tmp = dtm->wp_event[wp_idx ^ 1]; 1691 if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) != 1692 CMN_EVENT_WP_COMBINE(dtc->counters[tmp])) 1693 goto free_dtms; 1694 1695 input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx; 1696 dtm->wp_event[wp_idx] = dtc_idx; 1697 writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx)); 1698 } else { 1699 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); 1700 1701 if (cmn->multi_dtm) 1702 nid.port %= 2; 1703 1704 input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx + 1705 (nid.port << 4) + (nid.dev << 2); 1706 1707 if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event))) 1708 goto free_dtms; 1709 } 1710 1711 arm_cmn_set_index(hw->dtm_idx, i, dtm_idx); 1712 1713 dtm->input_sel[dtm_idx] = input_sel; 1714 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx); 1715 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift); 1716 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift; 1717 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx); 1718 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low; 1719 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); 1720 } 1721 1722 /* Go go go! */ 1723 arm_cmn_init_counter(event); 1724 1725 if (flags & PERF_EF_START) 1726 arm_cmn_event_start(event, 0); 1727 1728 return 0; 1729 1730 free_dtms: 1731 arm_cmn_event_clear(cmn, event, i); 1732 return -ENOSPC; 1733 } 1734 1735 static void arm_cmn_event_del(struct perf_event *event, int flags) 1736 { 1737 struct arm_cmn *cmn = to_cmn(event->pmu); 1738 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1739 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1740 1741 arm_cmn_event_stop(event, PERF_EF_UPDATE); 1742 1743 if (type == CMN_TYPE_DTC) 1744 cmn->dtc[__ffs(hw->dtcs_used)].cycles = NULL; 1745 else 1746 arm_cmn_event_clear(cmn, event, hw->num_dns); 1747 } 1748 1749 /* 1750 * We stop the PMU for both add and read, to avoid skew across DTM counters. 1751 * In theory we could use snapshots to read without stopping, but then it 1752 * becomes a lot trickier to deal with overlow and racing against interrupts, 1753 * plus it seems they don't work properly on some hardware anyway :( 1754 */ 1755 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags) 1756 { 1757 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN); 1758 } 1759 1760 static void arm_cmn_end_txn(struct pmu *pmu) 1761 { 1762 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN); 1763 } 1764 1765 static int arm_cmn_commit_txn(struct pmu *pmu) 1766 { 1767 arm_cmn_end_txn(pmu); 1768 return 0; 1769 } 1770 1771 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu) 1772 { 1773 unsigned int i; 1774 1775 perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu); 1776 for (i = 0; i < cmn->num_dtcs; i++) 1777 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu)); 1778 cmn->cpu = cpu; 1779 } 1780 1781 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 1782 { 1783 struct arm_cmn *cmn; 1784 int node; 1785 1786 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 1787 node = dev_to_node(cmn->dev); 1788 if (node != NUMA_NO_NODE && cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node) 1789 arm_cmn_migrate(cmn, cpu); 1790 return 0; 1791 } 1792 1793 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 1794 { 1795 struct arm_cmn *cmn; 1796 unsigned int target; 1797 int node; 1798 cpumask_t mask; 1799 1800 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 1801 if (cpu != cmn->cpu) 1802 return 0; 1803 1804 node = dev_to_node(cmn->dev); 1805 if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) && 1806 cpumask_andnot(&mask, &mask, cpumask_of(cpu))) 1807 target = cpumask_any(&mask); 1808 else 1809 target = cpumask_any_but(cpu_online_mask, cpu); 1810 if (target < nr_cpu_ids) 1811 arm_cmn_migrate(cmn, target); 1812 return 0; 1813 } 1814 1815 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id) 1816 { 1817 struct arm_cmn_dtc *dtc = dev_id; 1818 irqreturn_t ret = IRQ_NONE; 1819 1820 for (;;) { 1821 u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR); 1822 u64 delta; 1823 int i; 1824 1825 for (i = 0; i < CMN_DTM_NUM_COUNTERS; i++) { 1826 if (status & (1U << i)) { 1827 ret = IRQ_HANDLED; 1828 if (WARN_ON(!dtc->counters[i])) 1829 continue; 1830 delta = (u64)arm_cmn_read_counter(dtc, i) << 16; 1831 local64_add(delta, &dtc->counters[i]->count); 1832 } 1833 } 1834 1835 if (status & (1U << CMN_DT_NUM_COUNTERS)) { 1836 ret = IRQ_HANDLED; 1837 if (dtc->cc_active && !WARN_ON(!dtc->cycles)) { 1838 delta = arm_cmn_read_cc(dtc); 1839 local64_add(delta, &dtc->cycles->count); 1840 } 1841 } 1842 1843 writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR); 1844 1845 if (!dtc->irq_friend) 1846 return ret; 1847 dtc += dtc->irq_friend; 1848 } 1849 } 1850 1851 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */ 1852 static int arm_cmn_init_irqs(struct arm_cmn *cmn) 1853 { 1854 int i, j, irq, err; 1855 1856 for (i = 0; i < cmn->num_dtcs; i++) { 1857 irq = cmn->dtc[i].irq; 1858 for (j = i; j--; ) { 1859 if (cmn->dtc[j].irq == irq) { 1860 cmn->dtc[j].irq_friend = i - j; 1861 goto next; 1862 } 1863 } 1864 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq, 1865 IRQF_NOBALANCING | IRQF_NO_THREAD, 1866 dev_name(cmn->dev), &cmn->dtc[i]); 1867 if (err) 1868 return err; 1869 1870 err = irq_set_affinity(irq, cpumask_of(cmn->cpu)); 1871 if (err) 1872 return err; 1873 next: 1874 ; /* isn't C great? */ 1875 } 1876 return 0; 1877 } 1878 1879 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx) 1880 { 1881 int i; 1882 1883 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx); 1884 dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; 1885 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 1886 for (i = 0; i < 4; i++) { 1887 dtm->wp_event[i] = -1; 1888 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i)); 1889 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i)); 1890 } 1891 } 1892 1893 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx) 1894 { 1895 struct arm_cmn_dtc *dtc = cmn->dtc + idx; 1896 1897 dtc->base = dn->pmu_base - CMN_PMU_OFFSET; 1898 dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx); 1899 if (dtc->irq < 0) 1900 return dtc->irq; 1901 1902 writel_relaxed(0, dtc->base + CMN_DT_PMCR); 1903 writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR); 1904 writel_relaxed(CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR); 1905 1906 return 0; 1907 } 1908 1909 static int arm_cmn_node_cmp(const void *a, const void *b) 1910 { 1911 const struct arm_cmn_node *dna = a, *dnb = b; 1912 int cmp; 1913 1914 cmp = dna->type - dnb->type; 1915 if (!cmp) 1916 cmp = dna->logid - dnb->logid; 1917 return cmp; 1918 } 1919 1920 static int arm_cmn_init_dtcs(struct arm_cmn *cmn) 1921 { 1922 struct arm_cmn_node *dn, *xp; 1923 int dtc_idx = 0; 1924 u8 dtcs_present = (1 << cmn->num_dtcs) - 1; 1925 1926 cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL); 1927 if (!cmn->dtc) 1928 return -ENOMEM; 1929 1930 sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL); 1931 1932 cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP); 1933 1934 for (dn = cmn->dns; dn->type; dn++) { 1935 if (dn->type == CMN_TYPE_XP) { 1936 dn->dtc &= dtcs_present; 1937 continue; 1938 } 1939 1940 xp = arm_cmn_node_to_xp(cmn, dn); 1941 dn->dtm = xp->dtm; 1942 if (cmn->multi_dtm) 1943 dn->dtm += arm_cmn_nid(cmn, dn->id).port / 2; 1944 1945 if (dn->type == CMN_TYPE_DTC) { 1946 int err; 1947 /* We do at least know that a DTC's XP must be in that DTC's domain */ 1948 if (xp->dtc == 0xf) 1949 xp->dtc = 1 << dtc_idx; 1950 err = arm_cmn_init_dtc(cmn, dn, dtc_idx++); 1951 if (err) 1952 return err; 1953 } 1954 1955 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */ 1956 if (dn->type == CMN_TYPE_RND) 1957 dn->type = CMN_TYPE_RNI; 1958 1959 /* We split the RN-I off already, so let the CCLA part match CCLA events */ 1960 if (dn->type == CMN_TYPE_CCLA_RNI) 1961 dn->type = CMN_TYPE_CCLA; 1962 } 1963 1964 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, cmn->dtc[0].base + CMN_DT_DTC_CTL); 1965 1966 return 0; 1967 } 1968 1969 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node) 1970 { 1971 int level; 1972 u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO); 1973 1974 node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg); 1975 node->id = FIELD_GET(CMN_NI_NODE_ID, reg); 1976 node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg); 1977 1978 node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET; 1979 1980 if (node->type == CMN_TYPE_CFG) 1981 level = 0; 1982 else if (node->type == CMN_TYPE_XP) 1983 level = 1; 1984 else 1985 level = 2; 1986 1987 dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n", 1988 (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ', 1989 node->type, node->logid, offset); 1990 } 1991 1992 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type) 1993 { 1994 switch (type) { 1995 case CMN_TYPE_HNP: 1996 return CMN_TYPE_HNI; 1997 case CMN_TYPE_CCLA_RNI: 1998 return CMN_TYPE_RNI; 1999 default: 2000 return CMN_TYPE_INVALID; 2001 } 2002 } 2003 2004 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) 2005 { 2006 void __iomem *cfg_region; 2007 struct arm_cmn_node cfg, *dn; 2008 struct arm_cmn_dtm *dtm; 2009 u16 child_count, child_poff; 2010 u32 xp_offset[CMN_MAX_XPS]; 2011 u64 reg; 2012 int i, j; 2013 size_t sz; 2014 2015 arm_cmn_init_node_info(cmn, rgn_offset, &cfg); 2016 if (cfg.type != CMN_TYPE_CFG) 2017 return -ENODEV; 2018 2019 cfg_region = cmn->base + rgn_offset; 2020 reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_2); 2021 cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); 2022 2023 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL); 2024 cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN; 2025 cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg); 2026 cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg); 2027 2028 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1); 2029 cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg); 2030 cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg); 2031 2032 reg = readq_relaxed(cfg_region + CMN_CHILD_INFO); 2033 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2034 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2035 2036 cmn->num_xps = child_count; 2037 cmn->num_dns = cmn->num_xps; 2038 2039 /* Pass 1: visit the XPs, enumerate their children */ 2040 for (i = 0; i < cmn->num_xps; i++) { 2041 reg = readq_relaxed(cfg_region + child_poff + i * 8); 2042 xp_offset[i] = reg & CMN_CHILD_NODE_ADDR; 2043 2044 reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO); 2045 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2046 } 2047 2048 /* 2049 * Some nodes effectively have two separate types, which we'll handle 2050 * by creating one of each internally. For a (very) safe initial upper 2051 * bound, account for double the number of non-XP nodes. 2052 */ 2053 dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps, 2054 sizeof(*dn), GFP_KERNEL); 2055 if (!dn) 2056 return -ENOMEM; 2057 2058 /* Initial safe upper bound on DTMs for any possible mesh layout */ 2059 i = cmn->num_xps; 2060 if (cmn->multi_dtm) 2061 i += cmn->num_xps + 1; 2062 dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL); 2063 if (!dtm) 2064 return -ENOMEM; 2065 2066 /* Pass 2: now we can actually populate the nodes */ 2067 cmn->dns = dn; 2068 cmn->dtms = dtm; 2069 for (i = 0; i < cmn->num_xps; i++) { 2070 void __iomem *xp_region = cmn->base + xp_offset[i]; 2071 struct arm_cmn_node *xp = dn++; 2072 unsigned int xp_ports = 0; 2073 2074 arm_cmn_init_node_info(cmn, xp_offset[i], xp); 2075 /* 2076 * Thanks to the order in which XP logical IDs seem to be 2077 * assigned, we can handily infer the mesh X dimension by 2078 * looking out for the XP at (0,1) without needing to know 2079 * the exact node ID format, which we can later derive. 2080 */ 2081 if (xp->id == (1 << 3)) 2082 cmn->mesh_x = xp->logid; 2083 2084 if (cmn->model == CMN600) 2085 xp->dtc = 0xf; 2086 else 2087 xp->dtc = 1 << readl_relaxed(xp_region + CMN_DTM_UNIT_INFO); 2088 2089 xp->dtm = dtm - cmn->dtms; 2090 arm_cmn_init_dtm(dtm++, xp, 0); 2091 /* 2092 * Keeping track of connected ports will let us filter out 2093 * unnecessary XP events easily. We can also reliably infer the 2094 * "extra device ports" configuration for the node ID format 2095 * from this, since in that case we will see at least one XP 2096 * with port 2 connected, for the HN-D. 2097 */ 2098 for (int p = 0; p < CMN_MAX_PORTS; p++) 2099 if (arm_cmn_device_connect_info(cmn, xp, p)) 2100 xp_ports |= BIT(p); 2101 2102 if (cmn->multi_dtm && (xp_ports & 0xc)) 2103 arm_cmn_init_dtm(dtm++, xp, 1); 2104 if (cmn->multi_dtm && (xp_ports & 0x30)) 2105 arm_cmn_init_dtm(dtm++, xp, 2); 2106 2107 cmn->ports_used |= xp_ports; 2108 2109 reg = readq_relaxed(xp_region + CMN_CHILD_INFO); 2110 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2111 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2112 2113 for (j = 0; j < child_count; j++) { 2114 reg = readq_relaxed(xp_region + child_poff + j * 8); 2115 /* 2116 * Don't even try to touch anything external, since in general 2117 * we haven't a clue how to power up arbitrary CHI requesters. 2118 * As of CMN-600r1 these could only be RN-SAMs or CXLAs, 2119 * neither of which have any PMU events anyway. 2120 * (Actually, CXLAs do seem to have grown some events in r1p2, 2121 * but they don't go to regular XP DTMs, and they depend on 2122 * secure configuration which we can't easily deal with) 2123 */ 2124 if (reg & CMN_CHILD_NODE_EXTERNAL) { 2125 dev_dbg(cmn->dev, "ignoring external node %llx\n", reg); 2126 continue; 2127 } 2128 2129 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn); 2130 2131 switch (dn->type) { 2132 case CMN_TYPE_DTC: 2133 cmn->num_dtcs++; 2134 dn++; 2135 break; 2136 /* These guys have PMU events */ 2137 case CMN_TYPE_DVM: 2138 case CMN_TYPE_HNI: 2139 case CMN_TYPE_HNF: 2140 case CMN_TYPE_SBSX: 2141 case CMN_TYPE_RNI: 2142 case CMN_TYPE_RND: 2143 case CMN_TYPE_MTSX: 2144 case CMN_TYPE_CXRA: 2145 case CMN_TYPE_CXHA: 2146 case CMN_TYPE_CCRA: 2147 case CMN_TYPE_CCHA: 2148 case CMN_TYPE_CCLA: 2149 dn++; 2150 break; 2151 /* Nothing to see here */ 2152 case CMN_TYPE_MPAM_S: 2153 case CMN_TYPE_MPAM_NS: 2154 case CMN_TYPE_RNSAM: 2155 case CMN_TYPE_CXLA: 2156 break; 2157 /* 2158 * Split "optimised" combination nodes into separate 2159 * types for the different event sets. Offsetting the 2160 * base address lets us handle the second pmu_event_sel 2161 * register via the normal mechanism later. 2162 */ 2163 case CMN_TYPE_HNP: 2164 case CMN_TYPE_CCLA_RNI: 2165 dn[1] = dn[0]; 2166 dn[0].pmu_base += CMN_HNP_PMU_EVENT_SEL; 2167 dn[1].type = arm_cmn_subtype(dn->type); 2168 dn += 2; 2169 break; 2170 /* Something has gone horribly wrong */ 2171 default: 2172 dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type); 2173 return -ENODEV; 2174 } 2175 } 2176 } 2177 2178 /* Correct for any nodes we added or skipped */ 2179 cmn->num_dns = dn - cmn->dns; 2180 2181 /* Cheeky +1 to help terminate pointer-based iteration later */ 2182 sz = (void *)(dn + 1) - (void *)cmn->dns; 2183 dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL); 2184 if (dn) 2185 cmn->dns = dn; 2186 2187 sz = (void *)dtm - (void *)cmn->dtms; 2188 dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL); 2189 if (dtm) 2190 cmn->dtms = dtm; 2191 2192 /* 2193 * If mesh_x wasn't set during discovery then we never saw 2194 * an XP at (0,1), thus we must have an Nx1 configuration. 2195 */ 2196 if (!cmn->mesh_x) 2197 cmn->mesh_x = cmn->num_xps; 2198 cmn->mesh_y = cmn->num_xps / cmn->mesh_x; 2199 2200 /* 1x1 config plays havoc with XP event encodings */ 2201 if (cmn->num_xps == 1) 2202 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n"); 2203 2204 dev_dbg(cmn->dev, "model %d, periph_id_2 revision %d\n", cmn->model, cmn->rev); 2205 reg = cmn->ports_used; 2206 dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n", 2207 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), ®, 2208 cmn->multi_dtm ? ", multi-DTM" : ""); 2209 2210 return 0; 2211 } 2212 2213 static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn) 2214 { 2215 struct resource *cfg, *root; 2216 2217 cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2218 if (!cfg) 2219 return -EINVAL; 2220 2221 root = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2222 if (!root) 2223 return -EINVAL; 2224 2225 if (!resource_contains(cfg, root)) 2226 swap(cfg, root); 2227 /* 2228 * Note that devm_ioremap_resource() is dumb and won't let the platform 2229 * device claim cfg when the ACPI companion device has already claimed 2230 * root within it. But since they *are* already both claimed in the 2231 * appropriate name, we don't really need to do it again here anyway. 2232 */ 2233 cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg)); 2234 if (!cmn->base) 2235 return -ENOMEM; 2236 2237 return root->start - cfg->start; 2238 } 2239 2240 static int arm_cmn600_of_probe(struct device_node *np) 2241 { 2242 u32 rootnode; 2243 2244 return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode; 2245 } 2246 2247 static int arm_cmn_probe(struct platform_device *pdev) 2248 { 2249 struct arm_cmn *cmn; 2250 const char *name; 2251 static atomic_t id; 2252 int err, rootnode, this_id; 2253 2254 cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); 2255 if (!cmn) 2256 return -ENOMEM; 2257 2258 cmn->dev = &pdev->dev; 2259 cmn->model = (unsigned long)device_get_match_data(cmn->dev); 2260 platform_set_drvdata(pdev, cmn); 2261 2262 if (cmn->model == CMN600 && has_acpi_companion(cmn->dev)) { 2263 rootnode = arm_cmn600_acpi_probe(pdev, cmn); 2264 } else { 2265 rootnode = 0; 2266 cmn->base = devm_platform_ioremap_resource(pdev, 0); 2267 if (IS_ERR(cmn->base)) 2268 return PTR_ERR(cmn->base); 2269 if (cmn->model == CMN600) 2270 rootnode = arm_cmn600_of_probe(pdev->dev.of_node); 2271 } 2272 if (rootnode < 0) 2273 return rootnode; 2274 2275 err = arm_cmn_discover(cmn, rootnode); 2276 if (err) 2277 return err; 2278 2279 err = arm_cmn_init_dtcs(cmn); 2280 if (err) 2281 return err; 2282 2283 err = arm_cmn_init_irqs(cmn); 2284 if (err) 2285 return err; 2286 2287 cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev)); 2288 cmn->pmu = (struct pmu) { 2289 .module = THIS_MODULE, 2290 .attr_groups = arm_cmn_attr_groups, 2291 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 2292 .task_ctx_nr = perf_invalid_context, 2293 .pmu_enable = arm_cmn_pmu_enable, 2294 .pmu_disable = arm_cmn_pmu_disable, 2295 .event_init = arm_cmn_event_init, 2296 .add = arm_cmn_event_add, 2297 .del = arm_cmn_event_del, 2298 .start = arm_cmn_event_start, 2299 .stop = arm_cmn_event_stop, 2300 .read = arm_cmn_event_read, 2301 .start_txn = arm_cmn_start_txn, 2302 .commit_txn = arm_cmn_commit_txn, 2303 .cancel_txn = arm_cmn_end_txn, 2304 }; 2305 2306 this_id = atomic_fetch_inc(&id); 2307 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id); 2308 if (!name) 2309 return -ENOMEM; 2310 2311 err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node); 2312 if (err) 2313 return err; 2314 2315 err = perf_pmu_register(&cmn->pmu, name, -1); 2316 if (err) 2317 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2318 else 2319 arm_cmn_debugfs_init(cmn, this_id); 2320 2321 return err; 2322 } 2323 2324 static int arm_cmn_remove(struct platform_device *pdev) 2325 { 2326 struct arm_cmn *cmn = platform_get_drvdata(pdev); 2327 2328 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL); 2329 2330 perf_pmu_unregister(&cmn->pmu); 2331 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2332 debugfs_remove(cmn->debug); 2333 return 0; 2334 } 2335 2336 #ifdef CONFIG_OF 2337 static const struct of_device_id arm_cmn_of_match[] = { 2338 { .compatible = "arm,cmn-600", .data = (void *)CMN600 }, 2339 { .compatible = "arm,cmn-650", .data = (void *)CMN650 }, 2340 { .compatible = "arm,cmn-700", .data = (void *)CMN700 }, 2341 { .compatible = "arm,ci-700", .data = (void *)CI700 }, 2342 {} 2343 }; 2344 MODULE_DEVICE_TABLE(of, arm_cmn_of_match); 2345 #endif 2346 2347 #ifdef CONFIG_ACPI 2348 static const struct acpi_device_id arm_cmn_acpi_match[] = { 2349 { "ARMHC600", CMN600 }, 2350 { "ARMHC650", CMN650 }, 2351 { "ARMHC700", CMN700 }, 2352 {} 2353 }; 2354 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match); 2355 #endif 2356 2357 static struct platform_driver arm_cmn_driver = { 2358 .driver = { 2359 .name = "arm-cmn", 2360 .of_match_table = of_match_ptr(arm_cmn_of_match), 2361 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match), 2362 }, 2363 .probe = arm_cmn_probe, 2364 .remove = arm_cmn_remove, 2365 }; 2366 2367 static int __init arm_cmn_init(void) 2368 { 2369 int ret; 2370 2371 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 2372 "perf/arm/cmn:online", 2373 arm_cmn_pmu_online_cpu, 2374 arm_cmn_pmu_offline_cpu); 2375 if (ret < 0) 2376 return ret; 2377 2378 arm_cmn_hp_state = ret; 2379 arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL); 2380 2381 ret = platform_driver_register(&arm_cmn_driver); 2382 if (ret) { 2383 cpuhp_remove_multi_state(arm_cmn_hp_state); 2384 debugfs_remove(arm_cmn_debugfs); 2385 } 2386 return ret; 2387 } 2388 2389 static void __exit arm_cmn_exit(void) 2390 { 2391 platform_driver_unregister(&arm_cmn_driver); 2392 cpuhp_remove_multi_state(arm_cmn_hp_state); 2393 debugfs_remove(arm_cmn_debugfs); 2394 } 2395 2396 module_init(arm_cmn_init); 2397 module_exit(arm_cmn_exit); 2398 2399 MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>"); 2400 MODULE_DESCRIPTION("Arm CMN-600 PMU driver"); 2401 MODULE_LICENSE("GPL v2"); 2402