1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2016-2020 Arm Limited 3 // ARM CMN/CI interconnect PMU driver 4 5 #include <linux/acpi.h> 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/debugfs.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/perf_event.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/sort.h> 20 21 /* Common register stuff */ 22 #define CMN_NODE_INFO 0x0000 23 #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0) 24 #define CMN_NI_NODE_ID GENMASK_ULL(31, 16) 25 #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) 26 27 #define CMN_CHILD_INFO 0x0080 28 #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0) 29 #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16) 30 31 #define CMN_CHILD_NODE_ADDR GENMASK(29, 0) 32 #define CMN_CHILD_NODE_EXTERNAL BIT(31) 33 34 #define CMN_MAX_DIMENSION 12 35 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION) 36 #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4) 37 38 /* Currently XPs are the node type we can have most of; others top out at 128 */ 39 #define CMN_MAX_NODES_PER_EVENT CMN_MAX_XPS 40 41 /* The CFG node has various info besides the discovery tree */ 42 #define CMN_CFGM_PERIPH_ID_01 0x0008 43 #define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7, 0) 44 #define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35, 32) 45 #define CMN_CFGM_PERIPH_ID_23 0x0010 46 #define CMN_CFGM_PID2_REVISION GENMASK_ULL(7, 4) 47 48 #define CMN_CFGM_INFO_GLOBAL 0x0900 49 #define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63) 50 #define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52) 51 #define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50) 52 #define CMN_INFO_DEVICE_ISO_ENABLE BIT_ULL(44) 53 54 #define CMN_CFGM_INFO_GLOBAL_1 0x0908 55 #define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2) 56 #define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0) 57 58 /* XPs also have some local topology info which has uses too */ 59 #define CMN_MXP__CONNECT_INFO(p) (0x0008 + 8 * (p)) 60 #define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(5, 0) 61 62 #define CMN_MAX_PORTS 6 63 #define CI700_CONNECT_INFO_P2_5_OFFSET 0x10 64 65 /* PMU registers occupy the 3rd 4KB page of each node's region */ 66 #define CMN_PMU_OFFSET 0x2000 67 /* ...except when they don't :( */ 68 #define CMN_S3_R1_DTM_OFFSET 0xa000 69 #define CMN_S3_PMU_OFFSET 0xd900 70 71 /* For most nodes, this is all there is */ 72 #define CMN_PMU_EVENT_SEL 0x000 73 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42) 74 #define CMN__PMU_SN_HOME_SEL GENMASK_ULL(40, 39) 75 #define CMN__PMU_HBT_LBT_SEL GENMASK_ULL(38, 37) 76 #define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35) 77 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */ 78 #define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32) 79 80 /* Some types are designed to coexist with another device in the same node */ 81 #define CMN_CCLA_PMU_EVENT_SEL 0x008 82 #define CMN_HNP_PMU_EVENT_SEL 0x008 83 84 /* DTMs live in the PMU space of XP registers */ 85 #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18) 86 #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00) 87 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19) 88 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17) 89 #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9) 90 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8) 91 #define CMN600_WPn_CONFIG_WP_COMBINE BIT(6) 92 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5) 93 #define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4) 94 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1) 95 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0) 96 #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08) 97 #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10) 98 99 #define CMN_DTM_PMU_CONFIG 0x210 100 #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32) 101 #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00 102 #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04 103 #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10 104 #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16) 105 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4) 106 #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n)) 107 #define CMN__PMEVCNT23_COMBINED BIT(2) 108 #define CMN__PMEVCNT01_COMBINED BIT(1) 109 #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0) 110 111 #define CMN_DTM_PMEVCNT 0x220 112 113 #define CMN_DTM_PMEVCNTSR 0x240 114 115 #define CMN650_DTM_UNIT_INFO 0x0910 116 #define CMN_DTM_UNIT_INFO 0x0960 117 #define CMN_DTM_UNIT_INFO_DTC_DOMAIN GENMASK_ULL(1, 0) 118 119 #define CMN_DTM_NUM_COUNTERS 4 120 /* Want more local counters? Why not replicate the whole DTM! Ugh... */ 121 #define CMN_DTM_OFFSET(n) ((n) * 0x200) 122 123 /* The DTC node is where the magic happens */ 124 #define CMN_DT_DTC_CTL 0x0a00 125 #define CMN_DT_DTC_CTL_DT_EN BIT(0) 126 #define CMN_DT_DTC_CTL_CG_DISABLE BIT(10) 127 128 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */ 129 #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4) 130 #define CMN_DT_PMEVCNT(dtc, n) ((dtc)->pmu_base + _CMN_DT_CNT_REG(n)) 131 #define CMN_DT_PMCCNTR(dtc) ((dtc)->pmu_base + 0x40) 132 133 #define CMN_DT_PMEVCNTSR(dtc, n) ((dtc)->pmu_base + 0x50 + _CMN_DT_CNT_REG(n)) 134 #define CMN_DT_PMCCNTRSR(dtc) ((dtc)->pmu_base + 0x90) 135 136 #define CMN_DT_PMCR(dtc) ((dtc)->pmu_base + 0x100) 137 #define CMN_DT_PMCR_PMU_EN BIT(0) 138 #define CMN_DT_PMCR_CNTR_RST BIT(5) 139 #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6) 140 141 #define CMN_DT_PMOVSR(dtc) ((dtc)->pmu_base + 0x118) 142 #define CMN_DT_PMOVSR_CLR(dtc) ((dtc)->pmu_base + 0x120) 143 144 #define CMN_DT_PMSSR(dtc) ((dtc)->pmu_base + 0x128) 145 #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n) 146 147 #define CMN_DT_PMSRR(dtc) ((dtc)->pmu_base + 0x130) 148 #define CMN_DT_PMSRR_SS_REQ BIT(0) 149 150 #define CMN_DT_NUM_COUNTERS 8 151 #define CMN_MAX_DTCS 4 152 153 /* 154 * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles, 155 * so throwing away one bit to make overflow handling easy is no big deal. 156 */ 157 #define CMN_COUNTER_INIT 0x80000000 158 /* Similarly for the 40-bit cycle counter */ 159 #define CMN_CC_INIT 0x8000000000ULL 160 161 162 /* Event attributes */ 163 #define CMN_CONFIG_TYPE GENMASK_ULL(15, 0) 164 #define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16) 165 #define CMN_CONFIG_OCCUPID GENMASK_ULL(30, 27) 166 #define CMN_CONFIG_BYNODEID BIT_ULL(31) 167 #define CMN_CONFIG_NODEID GENMASK_ULL(47, 32) 168 169 #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config) 170 #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config) 171 #define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config) 172 #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config) 173 #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config) 174 175 #define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27) 176 #define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48) 177 #define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51) 178 #define CMN_CONFIG_WP_GRP GENMASK_ULL(57, 56) 179 #define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(58) 180 #define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0) 181 #define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0) 182 183 #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config) 184 #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config) 185 #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config) 186 #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config) 187 #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config) 188 #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1) 189 #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2) 190 191 /* Made-up event IDs for watchpoint direction */ 192 #define CMN_WP_UP 0 193 #define CMN_WP_DOWN 2 194 195 196 /* Internal values for encoding event support */ 197 enum cmn_model { 198 CMN600 = 1, 199 CMN650 = 2, 200 CI700 = 4, 201 CMN700 = 8, 202 CMNS3 = 16, 203 /* ...and then we can use bitmap tricks for commonality */ 204 CMN_ANY = -1, 205 NOT_CMN600 = -2, 206 CMN_700ON = ~(CMN700 - 1), 207 CMN_650ON = CMN_700ON | CMN650, 208 }; 209 210 /* Actual part numbers and revision IDs defined by the hardware */ 211 enum cmn_part { 212 PART_CMN600 = 0x434, 213 PART_CMN650 = 0x436, 214 PART_CMN600AE = 0x438, 215 PART_CMN700 = 0x43c, 216 PART_CI700 = 0x43a, 217 PART_CMN_S3 = 0x43e, 218 }; 219 220 /* CMN-600 r0px shouldn't exist in silicon, thankfully */ 221 enum cmn_revision { 222 REV_CMN600_R1P0, 223 REV_CMN600_R1P1, 224 REV_CMN600_R1P2, 225 REV_CMN600_R1P3, 226 REV_CMN600_R2P0, 227 REV_CMN600_R3P0, 228 REV_CMN600_R3P1, 229 REV_CMN650_R0P0 = 0, 230 REV_CMN650_R1P0, 231 REV_CMN650_R1P1, 232 REV_CMN650_R2P0, 233 REV_CMN650_R1P2, 234 REV_CMN700_R0P0 = 0, 235 REV_CMN700_R1P0, 236 REV_CMN700_R2P0, 237 REV_CMN700_R3P0, 238 REV_CMNS3_R0P0 = 0, 239 REV_CMNS3_R0P1, 240 REV_CMNS3_R1P0, 241 REV_CI700_R0P0 = 0, 242 REV_CI700_R1P0, 243 REV_CI700_R2P0, 244 }; 245 246 enum cmn_node_type { 247 CMN_TYPE_INVALID, 248 CMN_TYPE_DVM, 249 CMN_TYPE_CFG, 250 CMN_TYPE_DTC, 251 CMN_TYPE_HNI, 252 CMN_TYPE_HNF, 253 CMN_TYPE_XP, 254 CMN_TYPE_SBSX, 255 CMN_TYPE_MPAM_S, 256 CMN_TYPE_MPAM_NS, 257 CMN_TYPE_RNI, 258 CMN_TYPE_RND = 0xd, 259 CMN_TYPE_RNSAM = 0xf, 260 CMN_TYPE_MTSX, 261 CMN_TYPE_HNP, 262 CMN_TYPE_CXRA = 0x100, 263 CMN_TYPE_CXHA, 264 CMN_TYPE_CXLA, 265 CMN_TYPE_CCRA, 266 CMN_TYPE_CCHA, 267 CMN_TYPE_CCLA, 268 CMN_TYPE_CCLA_RNI, 269 CMN_TYPE_HNS = 0x200, 270 CMN_TYPE_HNS_MPAM_S, 271 CMN_TYPE_HNS_MPAM_NS, 272 CMN_TYPE_APB = 0x1000, 273 /* Not a real node type */ 274 CMN_TYPE_WP = 0x7770 275 }; 276 277 enum cmn_filter_select { 278 SEL_NONE = -1, 279 SEL_OCCUP1ID, 280 SEL_CLASS_OCCUP_ID, 281 SEL_CBUSY_SNTHROTTLE_SEL, 282 SEL_HBT_LBT_SEL, 283 SEL_SN_HOME_SEL, 284 SEL_MAX 285 }; 286 287 struct arm_cmn_node { 288 void __iomem *pmu_base; 289 u16 id, logid; 290 enum cmn_node_type type; 291 292 /* XP properties really, but replicated to children for convenience */ 293 u8 dtm; 294 s8 dtc; 295 u8 portid_bits:4; 296 u8 deviceid_bits:4; 297 /* DN/HN-F/CXHA */ 298 struct { 299 u8 val : 4; 300 u8 count : 4; 301 } occupid[SEL_MAX]; 302 union { 303 u8 event[4]; 304 __le32 event_sel; 305 u16 event_w[4]; 306 __le64 event_sel_w; 307 }; 308 }; 309 310 struct arm_cmn_dtm { 311 void __iomem *base; 312 u32 pmu_config_low; 313 union { 314 u8 input_sel[4]; 315 __le32 pmu_config_high; 316 }; 317 s8 wp_event[4]; 318 }; 319 320 struct arm_cmn_dtc { 321 void __iomem *base; 322 void __iomem *pmu_base; 323 int irq; 324 s8 irq_friend; 325 bool cc_active; 326 327 struct perf_event *counters[CMN_DT_NUM_COUNTERS]; 328 struct perf_event *cycles; 329 }; 330 331 #define CMN_STATE_DISABLED BIT(0) 332 #define CMN_STATE_TXN BIT(1) 333 334 struct arm_cmn { 335 struct device *dev; 336 void __iomem *base; 337 unsigned int state; 338 339 enum cmn_revision rev; 340 enum cmn_part part; 341 u8 mesh_x; 342 u8 mesh_y; 343 u16 num_xps; 344 u16 num_dns; 345 bool multi_dtm; 346 u8 ports_used; 347 struct { 348 unsigned int rsp_vc_num : 2; 349 unsigned int dat_vc_num : 2; 350 unsigned int snp_vc_num : 2; 351 unsigned int req_vc_num : 2; 352 }; 353 354 struct arm_cmn_node *xps; 355 struct arm_cmn_node *dns; 356 357 struct arm_cmn_dtm *dtms; 358 struct arm_cmn_dtc *dtc; 359 unsigned int num_dtcs; 360 361 int cpu; 362 struct hlist_node cpuhp_node; 363 364 struct pmu pmu; 365 struct dentry *debug; 366 }; 367 368 #define to_cmn(p) container_of(p, struct arm_cmn, pmu) 369 370 static int arm_cmn_hp_state; 371 372 struct arm_cmn_nodeid { 373 u8 port; 374 u8 dev; 375 }; 376 377 static int arm_cmn_xyidbits(const struct arm_cmn *cmn) 378 { 379 return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1)); 380 } 381 382 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn_node *dn) 383 { 384 struct arm_cmn_nodeid nid; 385 386 nid.dev = dn->id & ((1U << dn->deviceid_bits) - 1); 387 nid.port = (dn->id >> dn->deviceid_bits) & ((1U << dn->portid_bits) - 1); 388 return nid; 389 } 390 391 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn, 392 const struct arm_cmn_node *dn) 393 { 394 int id = dn->id >> (dn->portid_bits + dn->deviceid_bits); 395 int bits = arm_cmn_xyidbits(cmn); 396 int x = id >> bits; 397 int y = id & ((1U << bits) - 1); 398 399 return cmn->xps + cmn->mesh_x * y + x; 400 } 401 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, 402 enum cmn_node_type type) 403 { 404 struct arm_cmn_node *dn; 405 406 for (dn = cmn->dns; dn->type; dn++) 407 if (dn->type == type) 408 return dn; 409 return NULL; 410 } 411 412 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn) 413 { 414 switch (cmn->part) { 415 case PART_CMN600: 416 return CMN600; 417 case PART_CMN650: 418 return CMN650; 419 case PART_CMN700: 420 return CMN700; 421 case PART_CI700: 422 return CI700; 423 case PART_CMN_S3: 424 return CMNS3; 425 default: 426 return 0; 427 }; 428 } 429 430 static int arm_cmn_pmu_offset(const struct arm_cmn *cmn, const struct arm_cmn_node *dn) 431 { 432 if (cmn->part == PART_CMN_S3) { 433 if (cmn->rev >= REV_CMNS3_R1P0 && dn->type == CMN_TYPE_XP) 434 return CMN_S3_R1_DTM_OFFSET; 435 return CMN_S3_PMU_OFFSET; 436 } 437 return CMN_PMU_OFFSET; 438 } 439 440 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn, 441 const struct arm_cmn_node *xp, int port) 442 { 443 int offset = CMN_MXP__CONNECT_INFO(port) - arm_cmn_pmu_offset(cmn, xp); 444 445 if (port >= 2) { 446 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650) 447 return 0; 448 /* 449 * CI-700 may have extra ports, but still has the 450 * mesh_port_connect_info registers in the way. 451 */ 452 if (cmn->part == PART_CI700) 453 offset += CI700_CONNECT_INFO_P2_5_OFFSET; 454 } 455 456 return readl_relaxed(xp->pmu_base + offset); 457 } 458 459 static struct dentry *arm_cmn_debugfs; 460 461 #ifdef CONFIG_DEBUG_FS 462 static const char *arm_cmn_device_type(u8 type) 463 { 464 switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) { 465 case 0x00: return " |"; 466 case 0x01: return " RN-I |"; 467 case 0x02: return " RN-D |"; 468 case 0x04: return " RN-F_B |"; 469 case 0x05: return "RN-F_B_E|"; 470 case 0x06: return " RN-F_A |"; 471 case 0x07: return "RN-F_A_E|"; 472 case 0x08: return " HN-T |"; 473 case 0x09: return " HN-I |"; 474 case 0x0a: return " HN-D |"; 475 case 0x0b: return " HN-P |"; 476 case 0x0c: return " SN-F |"; 477 case 0x0d: return " SBSX |"; 478 case 0x0e: return " HN-F |"; 479 case 0x0f: return " SN-F_E |"; 480 case 0x10: return " SN-F_D |"; 481 case 0x11: return " CXHA |"; 482 case 0x12: return " CXRA |"; 483 case 0x13: return " CXRH |"; 484 case 0x14: return " RN-F_D |"; 485 case 0x15: return "RN-F_D_E|"; 486 case 0x16: return " RN-F_C |"; 487 case 0x17: return "RN-F_C_E|"; 488 case 0x18: return " RN-F_E |"; 489 case 0x19: return "RN-F_E_E|"; 490 case 0x1a: return " HN-S |"; 491 case 0x1b: return " LCN |"; 492 case 0x1c: return " MTSX |"; 493 case 0x1d: return " HN-V |"; 494 case 0x1e: return " CCG |"; 495 case 0x20: return " RN-F_F |"; 496 case 0x21: return "RN-F_F_E|"; 497 case 0x22: return " SN-F_F |"; 498 default: return " ???? |"; 499 } 500 } 501 502 static void arm_cmn_show_logid(struct seq_file *s, const struct arm_cmn_node *xp, int p, int d) 503 { 504 struct arm_cmn *cmn = s->private; 505 struct arm_cmn_node *dn; 506 u16 id = xp->id | d | (p << xp->deviceid_bits); 507 508 for (dn = cmn->dns; dn->type; dn++) { 509 int pad = dn->logid < 10; 510 511 if (dn->type == CMN_TYPE_XP) 512 continue; 513 /* Ignore the extra components that will overlap on some ports */ 514 if (dn->type < CMN_TYPE_HNI) 515 continue; 516 517 if (dn->id != id) 518 continue; 519 520 seq_printf(s, " %*c#%-*d |", pad + 1, ' ', 3 - pad, dn->logid); 521 return; 522 } 523 seq_puts(s, " |"); 524 } 525 526 static int arm_cmn_map_show(struct seq_file *s, void *data) 527 { 528 struct arm_cmn *cmn = s->private; 529 int x, y, p, pmax = fls(cmn->ports_used); 530 531 seq_puts(s, " X"); 532 for (x = 0; x < cmn->mesh_x; x++) 533 seq_printf(s, " %-2d ", x); 534 seq_puts(s, "\nY P D+"); 535 y = cmn->mesh_y; 536 while (y--) { 537 int xp_base = cmn->mesh_x * y; 538 struct arm_cmn_node *xp = cmn->xps + xp_base; 539 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION]; 540 541 for (x = 0; x < cmn->mesh_x; x++) 542 seq_puts(s, "--------+"); 543 544 seq_printf(s, "\n%-2d |", y); 545 for (x = 0; x < cmn->mesh_x; x++) { 546 for (p = 0; p < CMN_MAX_PORTS; p++) 547 port[p][x] = arm_cmn_device_connect_info(cmn, xp + x, p); 548 seq_printf(s, " XP #%-3d|", xp_base + x); 549 } 550 551 seq_puts(s, "\n |"); 552 for (x = 0; x < cmn->mesh_x; x++) { 553 s8 dtc = xp[x].dtc; 554 555 if (dtc < 0) 556 seq_puts(s, " DTC ?? |"); 557 else 558 seq_printf(s, " DTC %d |", dtc); 559 } 560 seq_puts(s, "\n |"); 561 for (x = 0; x < cmn->mesh_x; x++) 562 seq_puts(s, "........|"); 563 564 for (p = 0; p < pmax; p++) { 565 seq_printf(s, "\n %d |", p); 566 for (x = 0; x < cmn->mesh_x; x++) 567 seq_puts(s, arm_cmn_device_type(port[p][x])); 568 seq_puts(s, "\n 0|"); 569 for (x = 0; x < cmn->mesh_x; x++) 570 arm_cmn_show_logid(s, xp + x, p, 0); 571 seq_puts(s, "\n 1|"); 572 for (x = 0; x < cmn->mesh_x; x++) 573 arm_cmn_show_logid(s, xp + x, p, 1); 574 } 575 seq_puts(s, "\n-----+"); 576 } 577 for (x = 0; x < cmn->mesh_x; x++) 578 seq_puts(s, "--------+"); 579 seq_puts(s, "\n"); 580 return 0; 581 } 582 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map); 583 584 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) 585 { 586 const char *name = "map"; 587 588 if (id > 0) 589 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id); 590 if (!name) 591 return; 592 593 cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops); 594 } 595 #else 596 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {} 597 #endif 598 599 struct arm_cmn_hw_event { 600 struct arm_cmn_node *dn; 601 u64 dtm_idx[DIV_ROUND_UP(CMN_MAX_NODES_PER_EVENT * 2, 64)]; 602 s8 dtc_idx[CMN_MAX_DTCS]; 603 u8 num_dns; 604 u8 dtm_offset; 605 606 /* 607 * WP config registers are divided to UP and DOWN events. We need to 608 * keep to track only one of them. 609 */ 610 DECLARE_BITMAP(wp_idx, CMN_MAX_XPS); 611 612 bool wide_sel; 613 enum cmn_filter_select filter_sel; 614 }; 615 static_assert(sizeof(struct arm_cmn_hw_event) <= offsetof(struct hw_perf_event, target)); 616 617 #define for_each_hw_dn(hw, dn, i) \ 618 for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++) 619 620 /* @i is the DTC number, @idx is the counter index on that DTC */ 621 #define for_each_hw_dtc_idx(hw, i, idx) \ 622 for (int i = 0, idx; i < CMN_MAX_DTCS; i++) if ((idx = hw->dtc_idx[i]) >= 0) 623 624 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event) 625 { 626 return (struct arm_cmn_hw_event *)&event->hw; 627 } 628 629 static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val) 630 { 631 x[pos / 32] |= (u64)val << ((pos % 32) * 2); 632 } 633 634 static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos) 635 { 636 return (x[pos / 32] >> ((pos % 32) * 2)) & 3; 637 } 638 639 static void arm_cmn_set_wp_idx(unsigned long *wp_idx, unsigned int pos, bool val) 640 { 641 if (val) 642 set_bit(pos, wp_idx); 643 } 644 645 static unsigned int arm_cmn_get_wp_idx(unsigned long *wp_idx, unsigned int pos) 646 { 647 return test_bit(pos, wp_idx); 648 } 649 650 struct arm_cmn_event_attr { 651 struct device_attribute attr; 652 enum cmn_model model; 653 enum cmn_node_type type; 654 enum cmn_filter_select fsel; 655 u16 eventid; 656 u8 occupid; 657 }; 658 659 struct arm_cmn_format_attr { 660 struct device_attribute attr; 661 u64 field; 662 int config; 663 }; 664 665 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\ 666 (&((struct arm_cmn_event_attr[]) {{ \ 667 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \ 668 .model = _model, \ 669 .type = _type, \ 670 .eventid = _eventid, \ 671 .occupid = _occupid, \ 672 .fsel = _fsel, \ 673 }})[0].attr.attr) 674 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid) \ 675 _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE) 676 677 static ssize_t arm_cmn_event_show(struct device *dev, 678 struct device_attribute *attr, char *buf) 679 { 680 struct arm_cmn_event_attr *eattr; 681 682 eattr = container_of(attr, typeof(*eattr), attr); 683 684 if (eattr->type == CMN_TYPE_DTC) 685 return sysfs_emit(buf, "type=0x%x\n", eattr->type); 686 687 if (eattr->type == CMN_TYPE_WP) 688 return sysfs_emit(buf, 689 "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n", 690 eattr->type, eattr->eventid); 691 692 if (eattr->fsel > SEL_NONE) 693 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n", 694 eattr->type, eattr->eventid, eattr->occupid); 695 696 return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type, 697 eattr->eventid); 698 } 699 700 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, 701 struct attribute *attr, 702 int unused) 703 { 704 struct device *dev = kobj_to_dev(kobj); 705 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 706 struct arm_cmn_event_attr *eattr; 707 enum cmn_node_type type; 708 u16 eventid; 709 710 eattr = container_of(attr, typeof(*eattr), attr.attr); 711 712 if (!(eattr->model & arm_cmn_model(cmn))) 713 return 0; 714 715 type = eattr->type; 716 eventid = eattr->eventid; 717 718 /* Watchpoints aren't nodes, so avoid confusion */ 719 if (type == CMN_TYPE_WP) 720 return attr->mode; 721 722 /* Hide XP events for unused interfaces/channels */ 723 if (type == CMN_TYPE_XP) { 724 unsigned int intf = (eventid >> 2) & 7; 725 unsigned int chan = eventid >> 5; 726 727 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3))) 728 return 0; 729 730 if (chan == 4 && cmn->part == PART_CMN600) 731 return 0; 732 733 if ((chan == 5 && cmn->rsp_vc_num < 2) || 734 (chan == 6 && cmn->dat_vc_num < 2) || 735 (chan == 7 && cmn->req_vc_num < 2) || 736 (chan == 8 && cmn->snp_vc_num < 2)) 737 return 0; 738 } 739 740 /* Revision-specific differences */ 741 if (cmn->part == PART_CMN600) { 742 if (cmn->rev < REV_CMN600_R1P3) { 743 if (type == CMN_TYPE_CXRA && eventid > 0x10) 744 return 0; 745 } 746 if (cmn->rev < REV_CMN600_R1P2) { 747 if (type == CMN_TYPE_HNF && eventid == 0x1b) 748 return 0; 749 if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA) 750 return 0; 751 } 752 } else if (cmn->part == PART_CMN650) { 753 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) { 754 if (type == CMN_TYPE_HNF && eventid > 0x22) 755 return 0; 756 if (type == CMN_TYPE_SBSX && eventid == 0x17) 757 return 0; 758 if (type == CMN_TYPE_RNI && eventid > 0x10) 759 return 0; 760 } 761 } else if (cmn->part == PART_CMN700) { 762 if (cmn->rev < REV_CMN700_R2P0) { 763 if (type == CMN_TYPE_HNF && eventid > 0x2c) 764 return 0; 765 if (type == CMN_TYPE_CCHA && eventid > 0x74) 766 return 0; 767 if (type == CMN_TYPE_CCLA && eventid > 0x27) 768 return 0; 769 } 770 if (cmn->rev < REV_CMN700_R1P0) { 771 if (type == CMN_TYPE_HNF && eventid > 0x2b) 772 return 0; 773 } 774 } 775 776 if (!arm_cmn_node(cmn, type)) 777 return 0; 778 779 return attr->mode; 780 } 781 782 #define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel) \ 783 _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel) 784 #define CMN_EVENT_DTC(_name) \ 785 CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0) 786 #define CMN_EVENT_HNF(_model, _name, _event) \ 787 CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event) 788 #define CMN_EVENT_HNI(_name, _event) \ 789 CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event) 790 #define CMN_EVENT_HNP(_name, _event) \ 791 CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event) 792 #define __CMN_EVENT_XP(_name, _event) \ 793 CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event) 794 #define CMN_EVENT_SBSX(_model, _name, _event) \ 795 CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event) 796 #define CMN_EVENT_RNID(_model, _name, _event) \ 797 CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event) 798 #define CMN_EVENT_MTSX(_name, _event) \ 799 CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event) 800 #define CMN_EVENT_CXRA(_model, _name, _event) \ 801 CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event) 802 #define CMN_EVENT_CXHA(_name, _event) \ 803 CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event) 804 #define CMN_EVENT_CCRA(_name, _event) \ 805 CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event) 806 #define CMN_EVENT_CCHA(_model, _name, _event) \ 807 CMN_EVENT_ATTR(_model, ccha_##_name, CMN_TYPE_CCHA, _event) 808 #define CMN_EVENT_CCLA(_name, _event) \ 809 CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event) 810 #define CMN_EVENT_HNS(_name, _event) \ 811 CMN_EVENT_ATTR(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event) 812 813 #define CMN_EVENT_DVM(_model, _name, _event) \ 814 _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE) 815 #define CMN_EVENT_DVM_OCC(_model, _name, _event) \ 816 _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID), \ 817 _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \ 818 _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID) 819 820 #define CMN_EVENT_HN_OCC(_model, _name, _type, _event) \ 821 _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_OCCUP1ID), \ 822 _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 1, SEL_OCCUP1ID), \ 823 _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 2, SEL_OCCUP1ID), \ 824 _CMN_EVENT_ATTR(_model, _name##_atomic, _type, _event, 3, SEL_OCCUP1ID), \ 825 _CMN_EVENT_ATTR(_model, _name##_stash, _type, _event, 4, SEL_OCCUP1ID) 826 #define CMN_EVENT_HN_CLS(_model, _name, _type, _event) \ 827 _CMN_EVENT_ATTR(_model, _name##_class0, _type, _event, 0, SEL_CLASS_OCCUP_ID), \ 828 _CMN_EVENT_ATTR(_model, _name##_class1, _type, _event, 1, SEL_CLASS_OCCUP_ID), \ 829 _CMN_EVENT_ATTR(_model, _name##_class2, _type, _event, 2, SEL_CLASS_OCCUP_ID), \ 830 _CMN_EVENT_ATTR(_model, _name##_class3, _type, _event, 3, SEL_CLASS_OCCUP_ID) 831 #define CMN_EVENT_HN_SNT(_model, _name, _type, _event) \ 832 _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \ 833 _CMN_EVENT_ATTR(_model, _name##_group0_read, _type, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \ 834 _CMN_EVENT_ATTR(_model, _name##_group0_write, _type, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \ 835 _CMN_EVENT_ATTR(_model, _name##_group1_read, _type, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \ 836 _CMN_EVENT_ATTR(_model, _name##_group1_write, _type, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \ 837 _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \ 838 _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL) 839 840 #define CMN_EVENT_HNF_OCC(_model, _name, _event) \ 841 CMN_EVENT_HN_OCC(_model, hnf_##_name, CMN_TYPE_HNF, _event) 842 #define CMN_EVENT_HNF_CLS(_model, _name, _event) \ 843 CMN_EVENT_HN_CLS(_model, hnf_##_name, CMN_TYPE_HNF, _event) 844 #define CMN_EVENT_HNF_SNT(_model, _name, _event) \ 845 CMN_EVENT_HN_SNT(_model, hnf_##_name, CMN_TYPE_HNF, _event) 846 847 #define CMN_EVENT_HNS_OCC(_name, _event) \ 848 CMN_EVENT_HN_OCC(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event), \ 849 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_rxsnp, CMN_TYPE_HNS, _event, 5, SEL_OCCUP1ID), \ 850 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 6, SEL_OCCUP1ID), \ 851 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 7, SEL_OCCUP1ID) 852 #define CMN_EVENT_HNS_CLS( _name, _event) \ 853 CMN_EVENT_HN_CLS(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event) 854 #define CMN_EVENT_HNS_SNT(_name, _event) \ 855 CMN_EVENT_HN_SNT(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event) 856 #define CMN_EVENT_HNS_HBT(_name, _event) \ 857 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_HBT_LBT_SEL), \ 858 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 1, SEL_HBT_LBT_SEL), \ 859 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 2, SEL_HBT_LBT_SEL) 860 #define CMN_EVENT_HNS_SNH(_name, _event) \ 861 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_SN_HOME_SEL), \ 862 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_sn, CMN_TYPE_HNS, _event, 1, SEL_SN_HOME_SEL), \ 863 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_home, CMN_TYPE_HNS, _event, 2, SEL_SN_HOME_SEL) 864 865 #define _CMN_EVENT_XP_MESH(_name, _event) \ 866 __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \ 867 __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \ 868 __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \ 869 __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)) 870 871 #define _CMN_EVENT_XP_PORT(_name, _event) \ 872 __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \ 873 __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \ 874 __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \ 875 __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2)) 876 877 #define _CMN_EVENT_XP(_name, _event) \ 878 _CMN_EVENT_XP_MESH(_name, _event), \ 879 _CMN_EVENT_XP_PORT(_name, _event) 880 881 /* Good thing there are only 3 fundamental XP events... */ 882 #define CMN_EVENT_XP(_name, _event) \ 883 _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \ 884 _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \ 885 _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \ 886 _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \ 887 _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \ 888 _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \ 889 _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)), \ 890 _CMN_EVENT_XP(req2_##_name, (_event) | (7 << 5)), \ 891 _CMN_EVENT_XP(snp2_##_name, (_event) | (8 << 5)) 892 893 #define CMN_EVENT_XP_DAT(_name, _event) \ 894 _CMN_EVENT_XP_PORT(dat_##_name, (_event) | (3 << 5)), \ 895 _CMN_EVENT_XP_PORT(dat2_##_name, (_event) | (6 << 5)) 896 897 898 static struct attribute *arm_cmn_event_attrs[] = { 899 CMN_EVENT_DTC(cycles), 900 901 /* 902 * DVM node events conflict with HN-I events in the equivalent PMU 903 * slot, but our lazy short-cut of using the DTM counter index for 904 * the PMU index as well happens to avoid that by construction. 905 */ 906 CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01), 907 CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02), 908 CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03), 909 CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04), 910 CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy, 0x05), 911 CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi, 0x01), 912 CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi, 0x02), 913 CMN_EVENT_DVM(NOT_CMN600, dvmop_pici, 0x03), 914 CMN_EVENT_DVM(NOT_CMN600, dvmop_vici, 0x04), 915 CMN_EVENT_DVM(NOT_CMN600, dvmsync, 0x05), 916 CMN_EVENT_DVM(NOT_CMN600, vmid_filtered, 0x06), 917 CMN_EVENT_DVM(NOT_CMN600, rndop_filtered, 0x07), 918 CMN_EVENT_DVM(NOT_CMN600, retry, 0x08), 919 CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv, 0x09), 920 CMN_EVENT_DVM(NOT_CMN600, txsnp_stall, 0x0a), 921 CMN_EVENT_DVM(NOT_CMN600, trkfull, 0x0b), 922 CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy, 0x0c), 923 CMN_EVENT_DVM_OCC(CMN_700ON, trk_occupancy_cxha, 0x0d), 924 CMN_EVENT_DVM_OCC(CMN_700ON, trk_occupancy_pdn, 0x0e), 925 CMN_EVENT_DVM(CMN_700ON, trk_alloc, 0x0f), 926 CMN_EVENT_DVM(CMN_700ON, trk_cxha_alloc, 0x10), 927 CMN_EVENT_DVM(CMN_700ON, trk_pdn_alloc, 0x11), 928 CMN_EVENT_DVM(CMN_700ON, txsnp_stall_limit, 0x12), 929 CMN_EVENT_DVM(CMN_700ON, rxsnp_stall_starv, 0x13), 930 CMN_EVENT_DVM(CMN_700ON, txsnp_sync_stall_op, 0x14), 931 932 CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01), 933 CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02), 934 CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03), 935 CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04), 936 CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05), 937 CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06), 938 CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07), 939 CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08), 940 CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09), 941 CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a), 942 CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b), 943 CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c), 944 CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d), 945 CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e), 946 CMN_EVENT_HNF_OCC(CMN_ANY, qos_pocq_occupancy, 0x0f), 947 CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10), 948 CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11), 949 CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12), 950 CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13), 951 CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14), 952 CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15), 953 CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16), 954 CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17), 955 CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18), 956 CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19), 957 CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a), 958 CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b), 959 CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c), 960 CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d), 961 CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e), 962 CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f), 963 CMN_EVENT_HNF(NOT_CMN600, atomic_fwd, 0x20), 964 CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim, 0x21), 965 CMN_EVENT_HNF(NOT_CMN600, mpam_softlim, 0x22), 966 CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster, 0x23), 967 CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict, 0x24), 968 CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line, 0x25), 969 CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup, 0x26), 970 CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry, 0x27), 971 CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs, 0x28), 972 CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin, 0x29), 973 CMN_EVENT_HNF_SNT(CMN700, sn_throttle, 0x2a), 974 CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min, 0x2b), 975 CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise, 0x2c), 976 CMN_EVENT_HNF(CMN700, snp_intv_cln, 0x2d), 977 CMN_EVENT_HNF(CMN700, nc_excl, 0x2e), 978 CMN_EVENT_HNF(CMN700, excl_mon_ovfl, 0x2f), 979 980 CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), 981 CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), 982 CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22), 983 CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23), 984 CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24), 985 CMN_EVENT_HNI(rrt_rd_alloc, 0x25), 986 CMN_EVENT_HNI(rrt_wr_alloc, 0x26), 987 CMN_EVENT_HNI(rdt_rd_alloc, 0x27), 988 CMN_EVENT_HNI(rdt_wr_alloc, 0x28), 989 CMN_EVENT_HNI(wdb_alloc, 0x29), 990 CMN_EVENT_HNI(txrsp_retryack, 0x2a), 991 CMN_EVENT_HNI(arvalid_no_arready, 0x2b), 992 CMN_EVENT_HNI(arready_no_arvalid, 0x2c), 993 CMN_EVENT_HNI(awvalid_no_awready, 0x2d), 994 CMN_EVENT_HNI(awready_no_awvalid, 0x2e), 995 CMN_EVENT_HNI(wvalid_no_wready, 0x2f), 996 CMN_EVENT_HNI(txdat_stall, 0x30), 997 CMN_EVENT_HNI(nonpcie_serialization, 0x31), 998 CMN_EVENT_HNI(pcie_serialization, 0x32), 999 1000 /* 1001 * HN-P events squat on top of the HN-I similarly to DVM events, except 1002 * for being crammed into the same physical node as well. And of course 1003 * where would the fun be if the same events were in the same order... 1004 */ 1005 CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl, 0x01), 1006 CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl, 0x02), 1007 CMN_EVENT_HNP(wdb_occ_cnt_ovfl, 0x03), 1008 CMN_EVENT_HNP(rrt_wr_alloc, 0x04), 1009 CMN_EVENT_HNP(rdt_wr_alloc, 0x05), 1010 CMN_EVENT_HNP(wdb_alloc, 0x06), 1011 CMN_EVENT_HNP(awvalid_no_awready, 0x07), 1012 CMN_EVENT_HNP(awready_no_awvalid, 0x08), 1013 CMN_EVENT_HNP(wvalid_no_wready, 0x09), 1014 CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl, 0x11), 1015 CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl, 0x12), 1016 CMN_EVENT_HNP(rrt_rd_alloc, 0x13), 1017 CMN_EVENT_HNP(rdt_rd_alloc, 0x14), 1018 CMN_EVENT_HNP(arvalid_no_arready, 0x15), 1019 CMN_EVENT_HNP(arready_no_arvalid, 0x16), 1020 1021 CMN_EVENT_XP(txflit_valid, 0x01), 1022 CMN_EVENT_XP(txflit_stall, 0x02), 1023 CMN_EVENT_XP_DAT(partial_dat_flit, 0x03), 1024 /* We treat watchpoints as a special made-up class of XP events */ 1025 CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP), 1026 CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN), 1027 1028 CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01), 1029 CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02), 1030 CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03), 1031 CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04), 1032 CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05), 1033 CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06), 1034 CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11), 1035 CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12), 1036 CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13), 1037 CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14), 1038 CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15), 1039 CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16), 1040 CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl, 0x17), 1041 CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21), 1042 CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22), 1043 CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23), 1044 CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24), 1045 CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25), 1046 1047 CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01), 1048 CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02), 1049 CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03), 1050 CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04), 1051 CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05), 1052 CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06), 1053 CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07), 1054 CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08), 1055 CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09), 1056 CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a), 1057 CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b), 1058 CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c), 1059 CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d), 1060 CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e), 1061 CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f), 1062 CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10), 1063 CMN_EVENT_RNID(CMN600, rdb_unord, 0x11), 1064 CMN_EVENT_RNID(CMN600, rdb_replay, 0x12), 1065 CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13), 1066 CMN_EVENT_RNID(CMN600, rdb_ord, 0x14), 1067 CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl, 0x11), 1068 CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl, 0x12), 1069 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13), 1070 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14), 1071 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15), 1072 CMN_EVENT_RNID(NOT_CMN600, wrt_throttled, 0x16), 1073 CMN_EVENT_RNID(CMN700, ldb_full, 0x17), 1074 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18), 1075 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19), 1076 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a), 1077 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b), 1078 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c), 1079 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d), 1080 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e), 1081 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f), 1082 CMN_EVENT_RNID(CMN700, rrt_burst_alloc, 0x20), 1083 CMN_EVENT_RNID(CMN700, awid_hash, 0x21), 1084 CMN_EVENT_RNID(CMN700, atomic_alloc, 0x22), 1085 CMN_EVENT_RNID(CMN700, atomic_occ_ovfl, 0x23), 1086 1087 CMN_EVENT_MTSX(tc_lookup, 0x01), 1088 CMN_EVENT_MTSX(tc_fill, 0x02), 1089 CMN_EVENT_MTSX(tc_miss, 0x03), 1090 CMN_EVENT_MTSX(tdb_forward, 0x04), 1091 CMN_EVENT_MTSX(tcq_hazard, 0x05), 1092 CMN_EVENT_MTSX(tcq_rd_alloc, 0x06), 1093 CMN_EVENT_MTSX(tcq_wr_alloc, 0x07), 1094 CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08), 1095 CMN_EVENT_MTSX(axi_rd_req, 0x09), 1096 CMN_EVENT_MTSX(axi_wr_req, 0x0a), 1097 CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b), 1098 CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c), 1099 1100 CMN_EVENT_CXRA(CMN_ANY, rht_occ, 0x01), 1101 CMN_EVENT_CXRA(CMN_ANY, sht_occ, 0x02), 1102 CMN_EVENT_CXRA(CMN_ANY, rdb_occ, 0x03), 1103 CMN_EVENT_CXRA(CMN_ANY, wdb_occ, 0x04), 1104 CMN_EVENT_CXRA(CMN_ANY, ssb_occ, 0x05), 1105 CMN_EVENT_CXRA(CMN_ANY, snp_bcasts, 0x06), 1106 CMN_EVENT_CXRA(CMN_ANY, req_chains, 0x07), 1107 CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen, 0x08), 1108 CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls, 0x09), 1109 CMN_EVENT_CXRA(CMN_ANY, chidat_stalls, 0x0a), 1110 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b), 1111 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c), 1112 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d), 1113 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e), 1114 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f), 1115 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10), 1116 CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11), 1117 CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12), 1118 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13), 1119 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14), 1120 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15), 1121 1122 CMN_EVENT_CXHA(rddatbyp, 0x21), 1123 CMN_EVENT_CXHA(chirsp_up_stall, 0x22), 1124 CMN_EVENT_CXHA(chidat_up_stall, 0x23), 1125 CMN_EVENT_CXHA(snppcrd_link0_stall, 0x24), 1126 CMN_EVENT_CXHA(snppcrd_link1_stall, 0x25), 1127 CMN_EVENT_CXHA(snppcrd_link2_stall, 0x26), 1128 CMN_EVENT_CXHA(reqtrk_occ, 0x27), 1129 CMN_EVENT_CXHA(rdb_occ, 0x28), 1130 CMN_EVENT_CXHA(rdbyp_occ, 0x29), 1131 CMN_EVENT_CXHA(wdb_occ, 0x2a), 1132 CMN_EVENT_CXHA(snptrk_occ, 0x2b), 1133 CMN_EVENT_CXHA(sdb_occ, 0x2c), 1134 CMN_EVENT_CXHA(snphaz_occ, 0x2d), 1135 1136 CMN_EVENT_CCRA(rht_occ, 0x41), 1137 CMN_EVENT_CCRA(sht_occ, 0x42), 1138 CMN_EVENT_CCRA(rdb_occ, 0x43), 1139 CMN_EVENT_CCRA(wdb_occ, 0x44), 1140 CMN_EVENT_CCRA(ssb_occ, 0x45), 1141 CMN_EVENT_CCRA(snp_bcasts, 0x46), 1142 CMN_EVENT_CCRA(req_chains, 0x47), 1143 CMN_EVENT_CCRA(req_chain_avglen, 0x48), 1144 CMN_EVENT_CCRA(chirsp_stalls, 0x49), 1145 CMN_EVENT_CCRA(chidat_stalls, 0x4a), 1146 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0, 0x4b), 1147 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1, 0x4c), 1148 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2, 0x4d), 1149 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0, 0x4e), 1150 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1, 0x4f), 1151 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2, 0x50), 1152 CMN_EVENT_CCRA(external_chirsp_stalls, 0x51), 1153 CMN_EVENT_CCRA(external_chidat_stalls, 0x52), 1154 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0, 0x53), 1155 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1, 0x54), 1156 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2, 0x55), 1157 CMN_EVENT_CCRA(rht_alloc, 0x56), 1158 CMN_EVENT_CCRA(sht_alloc, 0x57), 1159 CMN_EVENT_CCRA(rdb_alloc, 0x58), 1160 CMN_EVENT_CCRA(wdb_alloc, 0x59), 1161 CMN_EVENT_CCRA(ssb_alloc, 0x5a), 1162 1163 CMN_EVENT_CCHA(CMN_ANY, rddatbyp, 0x61), 1164 CMN_EVENT_CCHA(CMN_ANY, chirsp_up_stall, 0x62), 1165 CMN_EVENT_CCHA(CMN_ANY, chidat_up_stall, 0x63), 1166 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link0_stall, 0x64), 1167 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link1_stall, 0x65), 1168 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link2_stall, 0x66), 1169 CMN_EVENT_CCHA(CMN_ANY, reqtrk_occ, 0x67), 1170 CMN_EVENT_CCHA(CMN_ANY, rdb_occ, 0x68), 1171 CMN_EVENT_CCHA(CMN_ANY, rdbyp_occ, 0x69), 1172 CMN_EVENT_CCHA(CMN_ANY, wdb_occ, 0x6a), 1173 CMN_EVENT_CCHA(CMN_ANY, snptrk_occ, 0x6b), 1174 CMN_EVENT_CCHA(CMN_ANY, sdb_occ, 0x6c), 1175 CMN_EVENT_CCHA(CMN_ANY, snphaz_occ, 0x6d), 1176 CMN_EVENT_CCHA(CMN_ANY, reqtrk_alloc, 0x6e), 1177 CMN_EVENT_CCHA(CMN_ANY, rdb_alloc, 0x6f), 1178 CMN_EVENT_CCHA(CMN_ANY, rdbyp_alloc, 0x70), 1179 CMN_EVENT_CCHA(CMN_ANY, wdb_alloc, 0x71), 1180 CMN_EVENT_CCHA(CMN_ANY, snptrk_alloc, 0x72), 1181 CMN_EVENT_CCHA(CMN_ANY, db_alloc, 0x73), 1182 CMN_EVENT_CCHA(CMN_ANY, snphaz_alloc, 0x74), 1183 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_req_occ, 0x75), 1184 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_req_alloc, 0x76), 1185 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_req_occ, 0x77), 1186 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_req_alloc, 0x78), 1187 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_req_occ, 0x79), 1188 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_req_alloc, 0x7a), 1189 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_reg_req_occ, 0x7b), 1190 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_reg_req_alloc, 0x7c), 1191 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_rsvd_req_occ, 0x7d), 1192 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_rsvd_req_alloc, 0x7e), 1193 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_dat_occ, 0x7f), 1194 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_dat_alloc, 0x80), 1195 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_dat_occ, 0x81), 1196 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_dat_alloc, 0x82), 1197 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_dat_occ, 0x83), 1198 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_dat_alloc, 0x84), 1199 CMN_EVENT_CCHA(CMNS3, chirsp1_up_stall, 0x85), 1200 1201 CMN_EVENT_CCLA(rx_cxs, 0x21), 1202 CMN_EVENT_CCLA(tx_cxs, 0x22), 1203 CMN_EVENT_CCLA(rx_cxs_avg_size, 0x23), 1204 CMN_EVENT_CCLA(tx_cxs_avg_size, 0x24), 1205 CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure, 0x25), 1206 CMN_EVENT_CCLA(link_crdbuf_occ, 0x26), 1207 CMN_EVENT_CCLA(link_crdbuf_alloc, 0x27), 1208 CMN_EVENT_CCLA(pfwd_rcvr_cxs, 0x28), 1209 CMN_EVENT_CCLA(pfwd_sndr_num_flits, 0x29), 1210 CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd, 0x2a), 1211 CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd, 0x2b), 1212 1213 CMN_EVENT_HNS_HBT(cache_miss, 0x01), 1214 CMN_EVENT_HNS_HBT(slc_sf_cache_access, 0x02), 1215 CMN_EVENT_HNS_HBT(cache_fill, 0x03), 1216 CMN_EVENT_HNS_HBT(pocq_retry, 0x04), 1217 CMN_EVENT_HNS_HBT(pocq_reqs_recvd, 0x05), 1218 CMN_EVENT_HNS_HBT(sf_hit, 0x06), 1219 CMN_EVENT_HNS_HBT(sf_evictions, 0x07), 1220 CMN_EVENT_HNS(dir_snoops_sent, 0x08), 1221 CMN_EVENT_HNS(brd_snoops_sent, 0x09), 1222 CMN_EVENT_HNS_HBT(slc_eviction, 0x0a), 1223 CMN_EVENT_HNS_HBT(slc_fill_invalid_way, 0x0b), 1224 CMN_EVENT_HNS(mc_retries_local, 0x0c), 1225 CMN_EVENT_HNS_SNH(mc_reqs_local, 0x0d), 1226 CMN_EVENT_HNS(qos_hh_retry, 0x0e), 1227 CMN_EVENT_HNS_OCC(qos_pocq_occupancy, 0x0f), 1228 CMN_EVENT_HNS(pocq_addrhaz, 0x10), 1229 CMN_EVENT_HNS(pocq_atomic_addrhaz, 0x11), 1230 CMN_EVENT_HNS(ld_st_swp_adq_full, 0x12), 1231 CMN_EVENT_HNS(cmp_adq_full, 0x13), 1232 CMN_EVENT_HNS(txdat_stall, 0x14), 1233 CMN_EVENT_HNS(txrsp_stall, 0x15), 1234 CMN_EVENT_HNS(seq_full, 0x16), 1235 CMN_EVENT_HNS(seq_hit, 0x17), 1236 CMN_EVENT_HNS(snp_sent, 0x18), 1237 CMN_EVENT_HNS(sfbi_dir_snp_sent, 0x19), 1238 CMN_EVENT_HNS(sfbi_brd_snp_sent, 0x1a), 1239 CMN_EVENT_HNS(intv_dirty, 0x1c), 1240 CMN_EVENT_HNS(stash_snp_sent, 0x1d), 1241 CMN_EVENT_HNS(stash_data_pull, 0x1e), 1242 CMN_EVENT_HNS(snp_fwded, 0x1f), 1243 CMN_EVENT_HNS(atomic_fwd, 0x20), 1244 CMN_EVENT_HNS(mpam_hardlim, 0x21), 1245 CMN_EVENT_HNS(mpam_softlim, 0x22), 1246 CMN_EVENT_HNS(snp_sent_cluster, 0x23), 1247 CMN_EVENT_HNS(sf_imprecise_evict, 0x24), 1248 CMN_EVENT_HNS(sf_evict_shared_line, 0x25), 1249 CMN_EVENT_HNS_CLS(pocq_class_occup, 0x26), 1250 CMN_EVENT_HNS_CLS(pocq_class_retry, 0x27), 1251 CMN_EVENT_HNS_CLS(class_mc_reqs_local, 0x28), 1252 CMN_EVENT_HNS_CLS(class_cgnt_cmin, 0x29), 1253 CMN_EVENT_HNS_SNT(sn_throttle, 0x2a), 1254 CMN_EVENT_HNS_SNT(sn_throttle_min, 0x2b), 1255 CMN_EVENT_HNS(sf_precise_to_imprecise, 0x2c), 1256 CMN_EVENT_HNS(snp_intv_cln, 0x2d), 1257 CMN_EVENT_HNS(nc_excl, 0x2e), 1258 CMN_EVENT_HNS(excl_mon_ovfl, 0x2f), 1259 CMN_EVENT_HNS(snp_req_recvd, 0x30), 1260 CMN_EVENT_HNS(snp_req_byp_pocq, 0x31), 1261 CMN_EVENT_HNS(dir_ccgha_snp_sent, 0x32), 1262 CMN_EVENT_HNS(brd_ccgha_snp_sent, 0x33), 1263 CMN_EVENT_HNS(ccgha_snp_stall, 0x34), 1264 CMN_EVENT_HNS(lbt_req_hardlim, 0x35), 1265 CMN_EVENT_HNS(hbt_req_hardlim, 0x36), 1266 CMN_EVENT_HNS(sf_reupdate, 0x37), 1267 CMN_EVENT_HNS(excl_sf_imprecise, 0x38), 1268 CMN_EVENT_HNS(snp_pocq_addrhaz, 0x39), 1269 CMN_EVENT_HNS(mc_retries_remote, 0x3a), 1270 CMN_EVENT_HNS_SNH(mc_reqs_remote, 0x3b), 1271 CMN_EVENT_HNS_CLS(class_mc_reqs_remote, 0x3c), 1272 1273 NULL 1274 }; 1275 1276 static const struct attribute_group arm_cmn_event_attrs_group = { 1277 .name = "events", 1278 .attrs = arm_cmn_event_attrs, 1279 .is_visible = arm_cmn_event_attr_is_visible, 1280 }; 1281 1282 static ssize_t arm_cmn_format_show(struct device *dev, 1283 struct device_attribute *attr, char *buf) 1284 { 1285 struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr); 1286 1287 if (!fmt->config) 1288 return sysfs_emit(buf, "config:%*pbl\n", 64, &fmt->field); 1289 1290 return sysfs_emit(buf, "config%d:%*pbl\n", fmt->config, 64, &fmt->field); 1291 } 1292 1293 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \ 1294 (&((struct arm_cmn_format_attr[]) {{ \ 1295 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \ 1296 .config = _cfg, \ 1297 .field = _fld, \ 1298 }})[0].attr.attr) 1299 #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld) 1300 1301 static struct attribute *arm_cmn_format_attrs[] = { 1302 CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE), 1303 CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID), 1304 CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID), 1305 CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID), 1306 CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID), 1307 1308 CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL), 1309 CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL), 1310 CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP), 1311 CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE), 1312 CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE), 1313 1314 _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL), 1315 _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK), 1316 1317 NULL 1318 }; 1319 1320 static const struct attribute_group arm_cmn_format_attrs_group = { 1321 .name = "format", 1322 .attrs = arm_cmn_format_attrs, 1323 }; 1324 1325 static ssize_t arm_cmn_cpumask_show(struct device *dev, 1326 struct device_attribute *attr, char *buf) 1327 { 1328 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1329 1330 return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu)); 1331 } 1332 1333 static struct device_attribute arm_cmn_cpumask_attr = 1334 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL); 1335 1336 static ssize_t arm_cmn_identifier_show(struct device *dev, 1337 struct device_attribute *attr, char *buf) 1338 { 1339 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1340 1341 return sysfs_emit(buf, "%03x%02x\n", cmn->part, cmn->rev); 1342 } 1343 1344 static struct device_attribute arm_cmn_identifier_attr = 1345 __ATTR(identifier, 0444, arm_cmn_identifier_show, NULL); 1346 1347 static struct attribute *arm_cmn_other_attrs[] = { 1348 &arm_cmn_cpumask_attr.attr, 1349 &arm_cmn_identifier_attr.attr, 1350 NULL, 1351 }; 1352 1353 static const struct attribute_group arm_cmn_other_attrs_group = { 1354 .attrs = arm_cmn_other_attrs, 1355 }; 1356 1357 static const struct attribute_group *arm_cmn_attr_groups[] = { 1358 &arm_cmn_event_attrs_group, 1359 &arm_cmn_format_attrs_group, 1360 &arm_cmn_other_attrs_group, 1361 NULL 1362 }; 1363 1364 static int arm_cmn_find_free_wp_idx(struct arm_cmn_dtm *dtm, 1365 struct perf_event *event) 1366 { 1367 int wp_idx = CMN_EVENT_EVENTID(event); 1368 1369 if (dtm->wp_event[wp_idx] >= 0) 1370 if (dtm->wp_event[++wp_idx] >= 0) 1371 return -ENOSPC; 1372 1373 return wp_idx; 1374 } 1375 1376 static int arm_cmn_get_assigned_wp_idx(struct perf_event *event, 1377 struct arm_cmn_hw_event *hw, 1378 unsigned int pos) 1379 { 1380 return CMN_EVENT_EVENTID(event) + arm_cmn_get_wp_idx(hw->wp_idx, pos); 1381 } 1382 1383 static void arm_cmn_claim_wp_idx(struct arm_cmn_dtm *dtm, 1384 struct perf_event *event, 1385 unsigned int dtc, int wp_idx, 1386 unsigned int pos) 1387 { 1388 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1389 1390 dtm->wp_event[wp_idx] = hw->dtc_idx[dtc]; 1391 arm_cmn_set_wp_idx(hw->wp_idx, pos, wp_idx - CMN_EVENT_EVENTID(event)); 1392 } 1393 1394 static u32 arm_cmn_wp_config(struct perf_event *event, int wp_idx) 1395 { 1396 u32 config; 1397 u32 dev = CMN_EVENT_WP_DEV_SEL(event); 1398 u32 chn = CMN_EVENT_WP_CHN_SEL(event); 1399 u32 grp = CMN_EVENT_WP_GRP(event); 1400 u32 exc = CMN_EVENT_WP_EXCLUSIVE(event); 1401 u32 combine = CMN_EVENT_WP_COMBINE(event); 1402 bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600; 1403 1404 /* CMN-600 supports only primary and secondary matching groups */ 1405 if (is_cmn600) 1406 grp &= 1; 1407 1408 config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) | 1409 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) | 1410 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) | 1411 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1); 1412 if (exc) 1413 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE : 1414 CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE; 1415 1416 /* wp_combine is available only on WP0 and WP2 */ 1417 if (combine && !(wp_idx & 0x1)) 1418 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE : 1419 CMN_DTM_WPn_CONFIG_WP_COMBINE; 1420 return config; 1421 } 1422 1423 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state) 1424 { 1425 if (!cmn->state) 1426 writel_relaxed(0, CMN_DT_PMCR(&cmn->dtc[0])); 1427 cmn->state |= state; 1428 } 1429 1430 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state) 1431 { 1432 cmn->state &= ~state; 1433 if (!cmn->state) 1434 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, 1435 CMN_DT_PMCR(&cmn->dtc[0])); 1436 } 1437 1438 static void arm_cmn_pmu_enable(struct pmu *pmu) 1439 { 1440 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED); 1441 } 1442 1443 static void arm_cmn_pmu_disable(struct pmu *pmu) 1444 { 1445 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED); 1446 } 1447 1448 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, 1449 bool snapshot) 1450 { 1451 struct arm_cmn_dtm *dtm = NULL; 1452 struct arm_cmn_node *dn; 1453 unsigned int i, offset, dtm_idx; 1454 u64 reg, count = 0; 1455 1456 offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; 1457 for_each_hw_dn(hw, dn, i) { 1458 if (dtm != &cmn->dtms[dn->dtm]) { 1459 dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1460 reg = readq_relaxed(dtm->base + offset); 1461 } 1462 dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1463 count += (u16)(reg >> (dtm_idx * 16)); 1464 } 1465 return count; 1466 } 1467 1468 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc) 1469 { 1470 void __iomem *pmccntr = CMN_DT_PMCCNTR(dtc); 1471 u64 val = readq_relaxed(pmccntr); 1472 1473 writeq_relaxed(CMN_CC_INIT, pmccntr); 1474 return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1); 1475 } 1476 1477 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx) 1478 { 1479 void __iomem *pmevcnt = CMN_DT_PMEVCNT(dtc, idx); 1480 u32 val = readl_relaxed(pmevcnt); 1481 1482 writel_relaxed(CMN_COUNTER_INIT, pmevcnt); 1483 return val - CMN_COUNTER_INIT; 1484 } 1485 1486 static void arm_cmn_init_counter(struct perf_event *event) 1487 { 1488 struct arm_cmn *cmn = to_cmn(event->pmu); 1489 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1490 u64 count; 1491 1492 for_each_hw_dtc_idx(hw, i, idx) { 1493 writel_relaxed(CMN_COUNTER_INIT, CMN_DT_PMEVCNT(&cmn->dtc[i], idx)); 1494 cmn->dtc[i].counters[idx] = event; 1495 } 1496 1497 count = arm_cmn_read_dtm(cmn, hw, false); 1498 local64_set(&event->hw.prev_count, count); 1499 } 1500 1501 static void arm_cmn_event_read(struct perf_event *event) 1502 { 1503 struct arm_cmn *cmn = to_cmn(event->pmu); 1504 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1505 u64 delta, new, prev; 1506 unsigned long flags; 1507 1508 if (CMN_EVENT_TYPE(event) == CMN_TYPE_DTC) { 1509 delta = arm_cmn_read_cc(cmn->dtc + hw->dtc_idx[0]); 1510 local64_add(delta, &event->count); 1511 return; 1512 } 1513 new = arm_cmn_read_dtm(cmn, hw, false); 1514 prev = local64_xchg(&event->hw.prev_count, new); 1515 1516 delta = new - prev; 1517 1518 local_irq_save(flags); 1519 for_each_hw_dtc_idx(hw, i, idx) { 1520 new = arm_cmn_read_counter(cmn->dtc + i, idx); 1521 delta += new << 16; 1522 } 1523 local_irq_restore(flags); 1524 local64_add(delta, &event->count); 1525 } 1526 1527 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn, 1528 enum cmn_filter_select fsel, u8 occupid) 1529 { 1530 u64 reg; 1531 1532 if (fsel == SEL_NONE) 1533 return 0; 1534 1535 if (!dn->occupid[fsel].count) { 1536 dn->occupid[fsel].val = occupid; 1537 reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL, 1538 dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) | 1539 FIELD_PREP(CMN__PMU_SN_HOME_SEL, 1540 dn->occupid[SEL_SN_HOME_SEL].val) | 1541 FIELD_PREP(CMN__PMU_HBT_LBT_SEL, 1542 dn->occupid[SEL_HBT_LBT_SEL].val) | 1543 FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID, 1544 dn->occupid[SEL_CLASS_OCCUP_ID].val) | 1545 FIELD_PREP(CMN__PMU_OCCUP1_ID, 1546 dn->occupid[SEL_OCCUP1ID].val); 1547 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4); 1548 } else if (dn->occupid[fsel].val != occupid) { 1549 return -EBUSY; 1550 } 1551 dn->occupid[fsel].count++; 1552 return 0; 1553 } 1554 1555 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx, 1556 int eventid, bool wide_sel) 1557 { 1558 if (wide_sel) { 1559 dn->event_w[dtm_idx] = eventid; 1560 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); 1561 } else { 1562 dn->event[dtm_idx] = eventid; 1563 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); 1564 } 1565 } 1566 1567 static void arm_cmn_event_start(struct perf_event *event, int flags) 1568 { 1569 struct arm_cmn *cmn = to_cmn(event->pmu); 1570 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1571 struct arm_cmn_node *dn; 1572 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1573 int i; 1574 1575 if (type == CMN_TYPE_DTC) { 1576 struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0]; 1577 1578 writel_relaxed(CMN_DT_DTC_CTL_DT_EN | CMN_DT_DTC_CTL_CG_DISABLE, 1579 dtc->base + CMN_DT_DTC_CTL); 1580 writeq_relaxed(CMN_CC_INIT, CMN_DT_PMCCNTR(dtc)); 1581 dtc->cc_active = true; 1582 } else if (type == CMN_TYPE_WP) { 1583 u64 val = CMN_EVENT_WP_VAL(event); 1584 u64 mask = CMN_EVENT_WP_MASK(event); 1585 1586 for_each_hw_dn(hw, dn, i) { 1587 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1588 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i); 1589 1590 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); 1591 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); 1592 } 1593 } else for_each_hw_dn(hw, dn, i) { 1594 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1595 1596 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event), 1597 hw->wide_sel); 1598 } 1599 } 1600 1601 static void arm_cmn_event_stop(struct perf_event *event, int flags) 1602 { 1603 struct arm_cmn *cmn = to_cmn(event->pmu); 1604 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1605 struct arm_cmn_node *dn; 1606 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1607 int i; 1608 1609 if (type == CMN_TYPE_DTC) { 1610 struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0]; 1611 1612 dtc->cc_active = false; 1613 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); 1614 } else if (type == CMN_TYPE_WP) { 1615 for_each_hw_dn(hw, dn, i) { 1616 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1617 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i); 1618 1619 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); 1620 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); 1621 } 1622 } else for_each_hw_dn(hw, dn, i) { 1623 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1624 1625 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel); 1626 } 1627 1628 arm_cmn_event_read(event); 1629 } 1630 1631 struct arm_cmn_val { 1632 u8 dtm_count[CMN_MAX_DTMS]; 1633 u8 occupid[CMN_MAX_DTMS][SEL_MAX]; 1634 u8 wp[CMN_MAX_DTMS][4]; 1635 u8 wp_combine[CMN_MAX_DTMS][2]; 1636 int dtc_count[CMN_MAX_DTCS]; 1637 bool cycles; 1638 }; 1639 1640 static int arm_cmn_val_find_free_wp_config(struct perf_event *event, 1641 struct arm_cmn_val *val, int dtm) 1642 { 1643 int wp_idx = CMN_EVENT_EVENTID(event); 1644 1645 if (val->wp[dtm][wp_idx]) 1646 if (val->wp[dtm][++wp_idx]) 1647 return -ENOSPC; 1648 1649 return wp_idx; 1650 } 1651 1652 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val, 1653 struct perf_event *event) 1654 { 1655 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1656 struct arm_cmn_node *dn; 1657 enum cmn_node_type type; 1658 int i; 1659 1660 if (is_software_event(event)) 1661 return; 1662 1663 type = CMN_EVENT_TYPE(event); 1664 if (type == CMN_TYPE_DTC) { 1665 val->cycles = true; 1666 return; 1667 } 1668 1669 for_each_hw_dtc_idx(hw, dtc, idx) 1670 val->dtc_count[dtc]++; 1671 1672 for_each_hw_dn(hw, dn, i) { 1673 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel; 1674 1675 val->dtm_count[dtm]++; 1676 1677 if (sel > SEL_NONE) 1678 val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1; 1679 1680 if (type != CMN_TYPE_WP) 1681 continue; 1682 1683 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm); 1684 val->wp[dtm][wp_idx] = 1; 1685 val->wp_combine[dtm][wp_idx >> 1] += !!CMN_EVENT_WP_COMBINE(event); 1686 } 1687 } 1688 1689 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event) 1690 { 1691 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1692 struct arm_cmn_node *dn; 1693 struct perf_event *sibling, *leader = event->group_leader; 1694 enum cmn_node_type type; 1695 struct arm_cmn_val *val; 1696 int i, ret = -EINVAL; 1697 1698 if (leader == event) 1699 return 0; 1700 1701 if (event->pmu != leader->pmu && !is_software_event(leader)) 1702 return -EINVAL; 1703 1704 val = kzalloc_obj(*val); 1705 if (!val) 1706 return -ENOMEM; 1707 1708 arm_cmn_val_add_event(cmn, val, leader); 1709 1710 for_each_sibling_event(sibling, leader) 1711 arm_cmn_val_add_event(cmn, val, sibling); 1712 1713 type = CMN_EVENT_TYPE(event); 1714 if (type == CMN_TYPE_DTC) { 1715 ret = val->cycles ? -EINVAL : 0; 1716 goto done; 1717 } 1718 1719 for_each_hw_dtc_idx(hw, dtc, idx) 1720 if (val->dtc_count[dtc] == CMN_DT_NUM_COUNTERS) 1721 goto done; 1722 1723 for_each_hw_dn(hw, dn, i) { 1724 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel; 1725 1726 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS) 1727 goto done; 1728 1729 if (sel > SEL_NONE && val->occupid[dtm][sel] && 1730 val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1) 1731 goto done; 1732 1733 if (type != CMN_TYPE_WP) 1734 continue; 1735 1736 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm); 1737 if (wp_idx < 0) 1738 goto done; 1739 1740 if (wp_idx & 1 && 1741 val->wp_combine[dtm][wp_idx >> 1] != !!CMN_EVENT_WP_COMBINE(event)) 1742 goto done; 1743 } 1744 1745 ret = 0; 1746 done: 1747 kfree(val); 1748 return ret; 1749 } 1750 1751 static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn, 1752 enum cmn_node_type type, 1753 unsigned int eventid) 1754 { 1755 struct arm_cmn_event_attr *e; 1756 enum cmn_model model = arm_cmn_model(cmn); 1757 1758 for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) { 1759 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr); 1760 if (e->model & model && e->type == type && e->eventid == eventid) 1761 return e->fsel; 1762 } 1763 return SEL_NONE; 1764 } 1765 1766 1767 static int arm_cmn_event_init(struct perf_event *event) 1768 { 1769 struct arm_cmn *cmn = to_cmn(event->pmu); 1770 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1771 struct arm_cmn_node *dn; 1772 enum cmn_node_type type; 1773 bool bynodeid; 1774 u16 nodeid, eventid; 1775 1776 if (event->attr.type != event->pmu->type) 1777 return -ENOENT; 1778 1779 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 1780 return -EINVAL; 1781 1782 event->cpu = cmn->cpu; 1783 if (event->cpu < 0) 1784 return -EINVAL; 1785 1786 type = CMN_EVENT_TYPE(event); 1787 /* DTC events (i.e. cycles) already have everything they need */ 1788 if (type == CMN_TYPE_DTC) 1789 return arm_cmn_validate_group(cmn, event); 1790 1791 eventid = CMN_EVENT_EVENTID(event); 1792 /* For watchpoints we need the actual XP node here */ 1793 if (type == CMN_TYPE_WP) { 1794 type = CMN_TYPE_XP; 1795 /* ...and we need a "real" direction */ 1796 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN) 1797 return -EINVAL; 1798 /* ...but the DTM may depend on which port we're watching */ 1799 if (cmn->multi_dtm) 1800 hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2; 1801 } else if (type == CMN_TYPE_XP && 1802 (cmn->part == PART_CMN700 || cmn->part == PART_CMN_S3)) { 1803 hw->wide_sel = true; 1804 } else if (type == CMN_TYPE_RND) { 1805 /* Secretly permit this as an alias for "rnid" events */ 1806 type = CMN_TYPE_RNI; 1807 } 1808 1809 /* This is sufficiently annoying to recalculate, so cache it */ 1810 hw->filter_sel = arm_cmn_filter_sel(cmn, type, eventid); 1811 1812 bynodeid = CMN_EVENT_BYNODEID(event); 1813 nodeid = CMN_EVENT_NODEID(event); 1814 1815 hw->dn = arm_cmn_node(cmn, type); 1816 if (!hw->dn) 1817 return -EINVAL; 1818 1819 memset(hw->dtc_idx, -1, sizeof(hw->dtc_idx)); 1820 for (dn = hw->dn; dn->type == type; dn++) { 1821 if (bynodeid && dn->id != nodeid) { 1822 hw->dn++; 1823 continue; 1824 } 1825 hw->num_dns++; 1826 if (dn->dtc < 0) 1827 memset(hw->dtc_idx, 0, cmn->num_dtcs); 1828 else 1829 hw->dtc_idx[dn->dtc] = 0; 1830 1831 if (bynodeid) 1832 break; 1833 } 1834 1835 if (!hw->num_dns) { 1836 dev_dbg(cmn->dev, "invalid node 0x%x type 0x%x\n", nodeid, type); 1837 return -EINVAL; 1838 } 1839 1840 return arm_cmn_validate_group(cmn, event); 1841 } 1842 1843 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, 1844 int i) 1845 { 1846 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1847 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1848 1849 while (i--) { 1850 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset; 1851 unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1852 1853 if (type == CMN_TYPE_WP) { 1854 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i); 1855 1856 dtm->wp_event[wp_idx] = -1; 1857 } 1858 1859 if (hw->filter_sel > SEL_NONE) 1860 hw->dn[i].occupid[hw->filter_sel].count--; 1861 1862 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); 1863 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 1864 } 1865 memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx)); 1866 memset(hw->wp_idx, 0, sizeof(hw->wp_idx)); 1867 1868 for_each_hw_dtc_idx(hw, j, idx) 1869 cmn->dtc[j].counters[idx] = NULL; 1870 } 1871 1872 static int arm_cmn_event_add(struct perf_event *event, int flags) 1873 { 1874 struct arm_cmn *cmn = to_cmn(event->pmu); 1875 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1876 struct arm_cmn_node *dn; 1877 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1878 unsigned int input_sel, i = 0; 1879 1880 if (type == CMN_TYPE_DTC) { 1881 while (cmn->dtc[i].cycles) 1882 if (++i == cmn->num_dtcs) 1883 return -ENOSPC; 1884 1885 cmn->dtc[i].cycles = event; 1886 hw->dtc_idx[0] = i; 1887 1888 if (flags & PERF_EF_START) 1889 arm_cmn_event_start(event, 0); 1890 return 0; 1891 } 1892 1893 /* Grab the global counters first... */ 1894 for_each_hw_dtc_idx(hw, j, idx) { 1895 if (cmn->part == PART_CMN600 && j > 0) { 1896 idx = hw->dtc_idx[0]; 1897 } else { 1898 idx = 0; 1899 while (cmn->dtc[j].counters[idx]) 1900 if (++idx == CMN_DT_NUM_COUNTERS) 1901 return -ENOSPC; 1902 } 1903 hw->dtc_idx[j] = idx; 1904 } 1905 1906 /* ...then the local counters to feed them */ 1907 for_each_hw_dn(hw, dn, i) { 1908 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1909 unsigned int dtm_idx, shift, d = max_t(int, dn->dtc, 0); 1910 u64 reg; 1911 1912 dtm_idx = 0; 1913 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx)) 1914 if (++dtm_idx == CMN_DTM_NUM_COUNTERS) 1915 goto free_dtms; 1916 1917 if (type == CMN_TYPE_XP) { 1918 input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx; 1919 } else if (type == CMN_TYPE_WP) { 1920 int tmp, wp_idx; 1921 u32 cfg; 1922 1923 wp_idx = arm_cmn_find_free_wp_idx(dtm, event); 1924 if (wp_idx < 0) 1925 goto free_dtms; 1926 1927 cfg = arm_cmn_wp_config(event, wp_idx); 1928 1929 tmp = dtm->wp_event[wp_idx ^ 1]; 1930 if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) != 1931 CMN_EVENT_WP_COMBINE(cmn->dtc[d].counters[tmp])) 1932 goto free_dtms; 1933 1934 input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx; 1935 1936 arm_cmn_claim_wp_idx(dtm, event, d, wp_idx, i); 1937 writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx)); 1938 } else { 1939 struct arm_cmn_nodeid nid = arm_cmn_nid(dn); 1940 1941 if (cmn->multi_dtm) 1942 nid.port %= 2; 1943 1944 input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx + 1945 (nid.port << 4) + (nid.dev << 2); 1946 1947 if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event))) 1948 goto free_dtms; 1949 } 1950 1951 arm_cmn_set_index(hw->dtm_idx, i, dtm_idx); 1952 1953 dtm->input_sel[dtm_idx] = input_sel; 1954 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx); 1955 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift); 1956 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, hw->dtc_idx[d]) << shift; 1957 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx); 1958 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low; 1959 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); 1960 } 1961 1962 /* Go go go! */ 1963 arm_cmn_init_counter(event); 1964 1965 if (flags & PERF_EF_START) 1966 arm_cmn_event_start(event, 0); 1967 1968 return 0; 1969 1970 free_dtms: 1971 arm_cmn_event_clear(cmn, event, i); 1972 return -ENOSPC; 1973 } 1974 1975 static void arm_cmn_event_del(struct perf_event *event, int flags) 1976 { 1977 struct arm_cmn *cmn = to_cmn(event->pmu); 1978 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1979 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1980 1981 arm_cmn_event_stop(event, PERF_EF_UPDATE); 1982 1983 if (type == CMN_TYPE_DTC) 1984 cmn->dtc[hw->dtc_idx[0]].cycles = NULL; 1985 else 1986 arm_cmn_event_clear(cmn, event, hw->num_dns); 1987 } 1988 1989 /* 1990 * We stop the PMU for both add and read, to avoid skew across DTM counters. 1991 * In theory we could use snapshots to read without stopping, but then it 1992 * becomes a lot trickier to deal with overlow and racing against interrupts, 1993 * plus it seems they don't work properly on some hardware anyway :( 1994 */ 1995 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags) 1996 { 1997 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN); 1998 } 1999 2000 static void arm_cmn_end_txn(struct pmu *pmu) 2001 { 2002 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN); 2003 } 2004 2005 static int arm_cmn_commit_txn(struct pmu *pmu) 2006 { 2007 arm_cmn_end_txn(pmu); 2008 return 0; 2009 } 2010 2011 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu) 2012 { 2013 unsigned int i; 2014 2015 perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu); 2016 for (i = 0; i < cmn->num_dtcs; i++) 2017 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu)); 2018 cmn->cpu = cpu; 2019 } 2020 2021 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 2022 { 2023 struct arm_cmn *cmn; 2024 int node; 2025 2026 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 2027 node = dev_to_node(cmn->dev); 2028 if (cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node) 2029 arm_cmn_migrate(cmn, cpu); 2030 return 0; 2031 } 2032 2033 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 2034 { 2035 struct arm_cmn *cmn; 2036 unsigned int target; 2037 int node; 2038 2039 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 2040 if (cpu != cmn->cpu) 2041 return 0; 2042 2043 node = dev_to_node(cmn->dev); 2044 2045 target = cpumask_any_and_but(cpumask_of_node(node), cpu_online_mask, cpu); 2046 if (target >= nr_cpu_ids) 2047 target = cpumask_any_but(cpu_online_mask, cpu); 2048 2049 if (target < nr_cpu_ids) 2050 arm_cmn_migrate(cmn, target); 2051 2052 return 0; 2053 } 2054 2055 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id) 2056 { 2057 struct arm_cmn_dtc *dtc = dev_id; 2058 irqreturn_t ret = IRQ_NONE; 2059 2060 for (;;) { 2061 u32 status = readl_relaxed(CMN_DT_PMOVSR(dtc)); 2062 u64 delta; 2063 int i; 2064 2065 for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) { 2066 if (status & (1U << i)) { 2067 ret = IRQ_HANDLED; 2068 if (WARN_ON(!dtc->counters[i])) 2069 continue; 2070 delta = (u64)arm_cmn_read_counter(dtc, i) << 16; 2071 local64_add(delta, &dtc->counters[i]->count); 2072 } 2073 } 2074 2075 if (status & (1U << CMN_DT_NUM_COUNTERS)) { 2076 ret = IRQ_HANDLED; 2077 if (dtc->cc_active && !WARN_ON(!dtc->cycles)) { 2078 delta = arm_cmn_read_cc(dtc); 2079 local64_add(delta, &dtc->cycles->count); 2080 } 2081 } 2082 2083 writel_relaxed(status, CMN_DT_PMOVSR_CLR(dtc)); 2084 2085 if (!dtc->irq_friend) 2086 return ret; 2087 dtc += dtc->irq_friend; 2088 } 2089 } 2090 2091 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */ 2092 static int arm_cmn_init_irqs(struct arm_cmn *cmn) 2093 { 2094 int i, j, irq, err; 2095 2096 for (i = 0; i < cmn->num_dtcs; i++) { 2097 irq = cmn->dtc[i].irq; 2098 for (j = i; j--; ) { 2099 if (cmn->dtc[j].irq == irq) { 2100 cmn->dtc[j].irq_friend = i - j; 2101 goto next; 2102 } 2103 } 2104 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq, 2105 IRQF_NOBALANCING | IRQF_NO_THREAD, 2106 dev_name(cmn->dev), &cmn->dtc[i]); 2107 if (err) 2108 return err; 2109 2110 err = irq_set_affinity(irq, cpumask_of(cmn->cpu)); 2111 if (err) 2112 return err; 2113 next: 2114 ; /* isn't C great? */ 2115 } 2116 return 0; 2117 } 2118 2119 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx) 2120 { 2121 int i; 2122 2123 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx); 2124 dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; 2125 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 2126 for (i = 0; i < 4; i++) { 2127 dtm->wp_event[i] = -1; 2128 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i)); 2129 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i)); 2130 } 2131 } 2132 2133 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx) 2134 { 2135 struct arm_cmn_dtc *dtc = cmn->dtc + idx; 2136 const struct resource *cfg; 2137 resource_size_t base, size; 2138 2139 dtc->pmu_base = dn->pmu_base; 2140 dtc->base = dtc->pmu_base - arm_cmn_pmu_offset(cmn, dn); 2141 dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx); 2142 if (dtc->irq < 0) 2143 return dtc->irq; 2144 2145 cfg = platform_get_resource(to_platform_device(cmn->dev), IORESOURCE_MEM, 0); 2146 base = dtc->base - cmn->base + cfg->start; 2147 size = cmn->part == PART_CMN600 ? SZ_16K : SZ_64K; 2148 if (!devm_request_mem_region(cmn->dev, base, size, dev_name(cmn->dev))) 2149 return dev_err_probe(cmn->dev, -EBUSY, 2150 "Failed to request DTC region 0x%pa\n", &base); 2151 2152 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); 2153 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, CMN_DT_PMCR(dtc)); 2154 writeq_relaxed(0, CMN_DT_PMCCNTR(dtc)); 2155 writel_relaxed(0x1ff, CMN_DT_PMOVSR_CLR(dtc)); 2156 2157 return 0; 2158 } 2159 2160 static int arm_cmn_node_cmp(const void *a, const void *b) 2161 { 2162 const struct arm_cmn_node *dna = a, *dnb = b; 2163 int cmp; 2164 2165 cmp = dna->type - dnb->type; 2166 if (!cmp) 2167 cmp = dna->logid - dnb->logid; 2168 return cmp; 2169 } 2170 2171 static int arm_cmn_init_dtcs(struct arm_cmn *cmn) 2172 { 2173 struct arm_cmn_node *dn, *xp; 2174 int dtc_idx = 0; 2175 2176 cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL); 2177 if (!cmn->dtc) 2178 return -ENOMEM; 2179 2180 sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL); 2181 2182 cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP); 2183 2184 for (dn = cmn->dns; dn->type; dn++) { 2185 if (dn->type == CMN_TYPE_XP) 2186 continue; 2187 2188 xp = arm_cmn_node_to_xp(cmn, dn); 2189 dn->dtc = xp->dtc; 2190 dn->dtm = xp->dtm; 2191 if (cmn->multi_dtm) 2192 dn->dtm += arm_cmn_nid(dn).port / 2; 2193 2194 if (dn->type == CMN_TYPE_DTC) { 2195 int err = arm_cmn_init_dtc(cmn, dn, dtc_idx++); 2196 2197 if (err) 2198 return err; 2199 } 2200 2201 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */ 2202 if (dn->type == CMN_TYPE_RND) 2203 dn->type = CMN_TYPE_RNI; 2204 2205 /* We split the RN-I off already, so let the CCLA part match CCLA events */ 2206 if (dn->type == CMN_TYPE_CCLA_RNI) 2207 dn->type = CMN_TYPE_CCLA; 2208 } 2209 2210 arm_cmn_set_state(cmn, CMN_STATE_DISABLED); 2211 2212 return 0; 2213 } 2214 2215 static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_region) 2216 { 2217 int offset = CMN_DTM_UNIT_INFO; 2218 2219 if (cmn->part == PART_CMN650 || cmn->part == PART_CI700) 2220 offset = CMN650_DTM_UNIT_INFO; 2221 2222 return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset)); 2223 } 2224 2225 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node) 2226 { 2227 int level; 2228 u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO); 2229 2230 node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg); 2231 node->id = FIELD_GET(CMN_NI_NODE_ID, reg); 2232 node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg); 2233 2234 node->pmu_base = cmn->base + offset + arm_cmn_pmu_offset(cmn, node); 2235 2236 if (node->type == CMN_TYPE_CFG) 2237 level = 0; 2238 else if (node->type == CMN_TYPE_XP) 2239 level = 1; 2240 else 2241 level = 2; 2242 2243 dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n", 2244 (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ', 2245 node->type, node->logid, offset); 2246 } 2247 2248 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type) 2249 { 2250 switch (type) { 2251 case CMN_TYPE_HNP: 2252 return CMN_TYPE_HNI; 2253 case CMN_TYPE_CCLA_RNI: 2254 return CMN_TYPE_RNI; 2255 default: 2256 return CMN_TYPE_INVALID; 2257 } 2258 } 2259 2260 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) 2261 { 2262 void __iomem *cfg_region, __iomem *xp_region; 2263 struct arm_cmn_node cfg, *dn; 2264 struct arm_cmn_dtm *dtm; 2265 enum cmn_part part; 2266 u16 child_count, child_poff; 2267 u64 reg; 2268 int i, j; 2269 size_t sz; 2270 2271 arm_cmn_init_node_info(cmn, rgn_offset, &cfg); 2272 if (cfg.type != CMN_TYPE_CFG) 2273 return -ENODEV; 2274 2275 cfg_region = cmn->base + rgn_offset; 2276 2277 reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01); 2278 part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg); 2279 part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8; 2280 /* 600AE is close enough that it's not really worth more complexity */ 2281 if (part == PART_CMN600AE) 2282 part = PART_CMN600; 2283 if (cmn->part && cmn->part != part) 2284 dev_warn(cmn->dev, 2285 "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n", 2286 cmn->part, part); 2287 cmn->part = part; 2288 if (!arm_cmn_model(cmn)) 2289 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part); 2290 2291 reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23); 2292 cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); 2293 2294 /* 2295 * With the device isolation feature, if firmware has neglected to enable 2296 * an XP port then we risk locking up if we try to access anything behind 2297 * it; however we also have no way to tell from Non-Secure whether any 2298 * given port is disabled or not, so the only way to win is not to play... 2299 */ 2300 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL); 2301 if (reg & CMN_INFO_DEVICE_ISO_ENABLE) { 2302 dev_err(cmn->dev, "Device isolation enabled, not continuing due to risk of lockup\n"); 2303 return -ENODEV; 2304 } 2305 cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN; 2306 cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg); 2307 cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg); 2308 2309 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1); 2310 cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg); 2311 cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg); 2312 2313 reg = readq_relaxed(cfg_region + CMN_CHILD_INFO); 2314 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2315 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2316 2317 cmn->num_xps = child_count; 2318 cmn->num_dns = cmn->num_xps; 2319 2320 /* Pass 1: visit the XPs, enumerate their children */ 2321 cfg_region += child_poff; 2322 for (i = 0; i < cmn->num_xps; i++) { 2323 reg = readq_relaxed(cfg_region + i * 8); 2324 xp_region = cmn->base + (reg & CMN_CHILD_NODE_ADDR); 2325 2326 reg = readq_relaxed(xp_region + CMN_CHILD_INFO); 2327 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2328 } 2329 2330 /* 2331 * Some nodes effectively have two separate types, which we'll handle 2332 * by creating one of each internally. For a (very) safe initial upper 2333 * bound, account for double the number of non-XP nodes. 2334 */ 2335 dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps, 2336 sizeof(*dn), GFP_KERNEL); 2337 if (!dn) 2338 return -ENOMEM; 2339 2340 /* Initial safe upper bound on DTMs for any possible mesh layout */ 2341 i = cmn->num_xps; 2342 if (cmn->multi_dtm) 2343 i += cmn->num_xps + 1; 2344 dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL); 2345 if (!dtm) 2346 return -ENOMEM; 2347 2348 /* Pass 2: now we can actually populate the nodes */ 2349 cmn->dns = dn; 2350 cmn->dtms = dtm; 2351 for (i = 0; i < cmn->num_xps; i++) { 2352 struct arm_cmn_node *xp = dn++; 2353 unsigned int xp_ports = 0; 2354 2355 reg = readq_relaxed(cfg_region + i * 8); 2356 xp_region = cmn->base + (reg & CMN_CHILD_NODE_ADDR); 2357 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, xp); 2358 /* 2359 * Thanks to the order in which XP logical IDs seem to be 2360 * assigned, we can handily infer the mesh X dimension by 2361 * looking out for the XP at (0,1) without needing to know 2362 * the exact node ID format, which we can later derive. 2363 */ 2364 if (xp->id == (1 << 3)) 2365 cmn->mesh_x = xp->logid; 2366 2367 if (cmn->part == PART_CMN600) 2368 xp->dtc = -1; 2369 else 2370 xp->dtc = arm_cmn_dtc_domain(cmn, xp_region); 2371 2372 xp->dtm = dtm - cmn->dtms; 2373 arm_cmn_init_dtm(dtm++, xp, 0); 2374 /* 2375 * Keeping track of connected ports will let us filter out 2376 * unnecessary XP events easily, and also infer the per-XP 2377 * part of the node ID format. 2378 */ 2379 for (int p = 0; p < CMN_MAX_PORTS; p++) 2380 if (arm_cmn_device_connect_info(cmn, xp, p)) 2381 xp_ports |= BIT(p); 2382 2383 if (cmn->num_xps == 1) { 2384 xp->portid_bits = 3; 2385 xp->deviceid_bits = 2; 2386 } else if (xp_ports > 0x3) { 2387 xp->portid_bits = 2; 2388 xp->deviceid_bits = 1; 2389 } else { 2390 xp->portid_bits = 1; 2391 xp->deviceid_bits = 2; 2392 } 2393 2394 if (cmn->multi_dtm && (xp_ports > 0x3)) 2395 arm_cmn_init_dtm(dtm++, xp, 1); 2396 if (cmn->multi_dtm && (xp_ports > 0xf)) 2397 arm_cmn_init_dtm(dtm++, xp, 2); 2398 2399 cmn->ports_used |= xp_ports; 2400 2401 reg = readq_relaxed(xp_region + CMN_CHILD_INFO); 2402 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2403 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2404 2405 for (j = 0; j < child_count; j++) { 2406 reg = readq_relaxed(xp_region + child_poff + j * 8); 2407 /* 2408 * Don't even try to touch anything external, since in general 2409 * we haven't a clue how to power up arbitrary CHI requesters. 2410 * As of CMN-600r1 these could only be RN-SAMs or CXLAs, 2411 * neither of which have any PMU events anyway. 2412 * (Actually, CXLAs do seem to have grown some events in r1p2, 2413 * but they don't go to regular XP DTMs, and they depend on 2414 * secure configuration which we can't easily deal with) 2415 */ 2416 if (reg & CMN_CHILD_NODE_EXTERNAL) { 2417 dev_dbg(cmn->dev, "ignoring external node %llx\n", reg); 2418 continue; 2419 } 2420 /* 2421 * AmpereOneX erratum AC04_MESH_1 makes some XPs report a bogus 2422 * child count larger than the number of valid child pointers. 2423 * A child offset of 0 can only occur on CMN-600; otherwise it 2424 * would imply the root node being its own grandchild, which 2425 * we can safely dismiss in general. 2426 */ 2427 if (reg == 0 && cmn->part != PART_CMN600) { 2428 dev_dbg(cmn->dev, "bogus child pointer?\n"); 2429 continue; 2430 } 2431 2432 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn); 2433 dn->portid_bits = xp->portid_bits; 2434 dn->deviceid_bits = xp->deviceid_bits; 2435 /* 2436 * Logical IDs are assigned from 0 per node type, so as 2437 * soon as we see one bigger than expected, we can assume 2438 * there are more than we can cope with. 2439 */ 2440 if (dn->logid > CMN_MAX_NODES_PER_EVENT) { 2441 dev_err(cmn->dev, "Node ID invalid for supported CMN versions: %d\n", dn->logid); 2442 return -ENODEV; 2443 } 2444 2445 switch (dn->type) { 2446 case CMN_TYPE_DTC: 2447 cmn->num_dtcs++; 2448 dn++; 2449 break; 2450 /* These guys have PMU events */ 2451 case CMN_TYPE_DVM: 2452 case CMN_TYPE_HNI: 2453 case CMN_TYPE_HNF: 2454 case CMN_TYPE_SBSX: 2455 case CMN_TYPE_RNI: 2456 case CMN_TYPE_RND: 2457 case CMN_TYPE_MTSX: 2458 case CMN_TYPE_CXRA: 2459 case CMN_TYPE_CXHA: 2460 case CMN_TYPE_CCRA: 2461 case CMN_TYPE_CCHA: 2462 case CMN_TYPE_HNS: 2463 dn++; 2464 break; 2465 case CMN_TYPE_CCLA: 2466 dn->pmu_base += CMN_CCLA_PMU_EVENT_SEL; 2467 dn++; 2468 break; 2469 /* Nothing to see here */ 2470 case CMN_TYPE_MPAM_S: 2471 case CMN_TYPE_MPAM_NS: 2472 case CMN_TYPE_RNSAM: 2473 case CMN_TYPE_CXLA: 2474 case CMN_TYPE_HNS_MPAM_S: 2475 case CMN_TYPE_HNS_MPAM_NS: 2476 case CMN_TYPE_APB: 2477 break; 2478 /* 2479 * Split "optimised" combination nodes into separate 2480 * types for the different event sets. Offsetting the 2481 * base address lets us handle the second pmu_event_sel 2482 * register via the normal mechanism later. 2483 */ 2484 case CMN_TYPE_HNP: 2485 case CMN_TYPE_CCLA_RNI: 2486 dn[1] = dn[0]; 2487 dn[0].pmu_base += CMN_CCLA_PMU_EVENT_SEL; 2488 dn[1].type = arm_cmn_subtype(dn->type); 2489 dn += 2; 2490 break; 2491 /* Something has gone horribly wrong */ 2492 default: 2493 dev_err(cmn->dev, "Device node type invalid for supported CMN versions: 0x%x\n", dn->type); 2494 return -ENODEV; 2495 } 2496 } 2497 } 2498 2499 /* Correct for any nodes we added or skipped */ 2500 cmn->num_dns = dn - cmn->dns; 2501 2502 /* Cheeky +1 to help terminate pointer-based iteration later */ 2503 sz = (void *)(dn + 1) - (void *)cmn->dns; 2504 dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL); 2505 if (dn) 2506 cmn->dns = dn; 2507 2508 sz = (void *)dtm - (void *)cmn->dtms; 2509 dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL); 2510 if (dtm) 2511 cmn->dtms = dtm; 2512 2513 /* 2514 * If mesh_x wasn't set during discovery then we never saw 2515 * an XP at (0,1), thus we must have an Nx1 configuration. 2516 */ 2517 if (!cmn->mesh_x) 2518 cmn->mesh_x = cmn->num_xps; 2519 cmn->mesh_y = cmn->num_xps / cmn->mesh_x; 2520 2521 if (max(cmn->mesh_x, cmn->mesh_y) > CMN_MAX_DIMENSION) { 2522 dev_err(cmn->dev, "Mesh size invalid for supported CMN versions: %dx%d\n", cmn->mesh_x, cmn->mesh_y); 2523 return -ENODEV; 2524 } 2525 /* 1x1 config plays havoc with XP event encodings */ 2526 if (cmn->num_xps == 1) 2527 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n"); 2528 2529 dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev); 2530 reg = cmn->ports_used; 2531 dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n", 2532 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), ®, 2533 cmn->multi_dtm ? ", multi-DTM" : ""); 2534 2535 return 0; 2536 } 2537 2538 static int arm_cmn_get_root(struct arm_cmn *cmn, const struct resource *cfg) 2539 { 2540 const struct device_node *np = cmn->dev->of_node; 2541 const struct resource *root; 2542 u32 rootnode; 2543 2544 if (cmn->part != PART_CMN600) 2545 return 0; 2546 2547 if (np) 2548 return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode; 2549 2550 root = platform_get_resource(to_platform_device(cmn->dev), IORESOURCE_MEM, 1); 2551 return root ? root->start - cfg->start : -EINVAL; 2552 } 2553 2554 static int arm_cmn_probe(struct platform_device *pdev) 2555 { 2556 struct arm_cmn *cmn; 2557 const struct resource *cfg; 2558 const char *name; 2559 static atomic_t id; 2560 int err, rootnode, this_id; 2561 2562 cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); 2563 if (!cmn) 2564 return -ENOMEM; 2565 2566 cmn->dev = &pdev->dev; 2567 cmn->part = (unsigned long)device_get_match_data(cmn->dev); 2568 cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev)); 2569 platform_set_drvdata(pdev, cmn); 2570 2571 cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2572 if (!cfg) 2573 return -EINVAL; 2574 2575 /* Map the whole region now, claim the DTCs once we've found them */ 2576 cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg)); 2577 if (!cmn->base) 2578 return -ENOMEM; 2579 2580 rootnode = arm_cmn_get_root(cmn, cfg); 2581 if (rootnode < 0) 2582 return rootnode; 2583 2584 err = arm_cmn_discover(cmn, rootnode); 2585 if (err) 2586 return err; 2587 2588 err = arm_cmn_init_dtcs(cmn); 2589 if (err) 2590 return err; 2591 2592 err = arm_cmn_init_irqs(cmn); 2593 if (err) 2594 return err; 2595 2596 cmn->pmu = (struct pmu) { 2597 .module = THIS_MODULE, 2598 .parent = cmn->dev, 2599 .attr_groups = arm_cmn_attr_groups, 2600 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 2601 .task_ctx_nr = perf_invalid_context, 2602 .pmu_enable = arm_cmn_pmu_enable, 2603 .pmu_disable = arm_cmn_pmu_disable, 2604 .event_init = arm_cmn_event_init, 2605 .add = arm_cmn_event_add, 2606 .del = arm_cmn_event_del, 2607 .start = arm_cmn_event_start, 2608 .stop = arm_cmn_event_stop, 2609 .read = arm_cmn_event_read, 2610 .start_txn = arm_cmn_start_txn, 2611 .commit_txn = arm_cmn_commit_txn, 2612 .cancel_txn = arm_cmn_end_txn, 2613 }; 2614 2615 this_id = atomic_fetch_inc(&id); 2616 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id); 2617 if (!name) 2618 return -ENOMEM; 2619 2620 err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node); 2621 if (err) 2622 return err; 2623 2624 err = perf_pmu_register(&cmn->pmu, name, -1); 2625 if (err) 2626 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2627 else 2628 arm_cmn_debugfs_init(cmn, this_id); 2629 2630 return err; 2631 } 2632 2633 static void arm_cmn_remove(struct platform_device *pdev) 2634 { 2635 struct arm_cmn *cmn = platform_get_drvdata(pdev); 2636 2637 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL); 2638 2639 perf_pmu_unregister(&cmn->pmu); 2640 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2641 debugfs_remove(cmn->debug); 2642 } 2643 2644 #ifdef CONFIG_OF 2645 static const struct of_device_id arm_cmn_of_match[] = { 2646 { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 }, 2647 { .compatible = "arm,cmn-650" }, 2648 { .compatible = "arm,cmn-700" }, 2649 { .compatible = "arm,cmn-s3" }, 2650 { .compatible = "arm,ci-700" }, 2651 {} 2652 }; 2653 MODULE_DEVICE_TABLE(of, arm_cmn_of_match); 2654 #endif 2655 2656 #ifdef CONFIG_ACPI 2657 static const struct acpi_device_id arm_cmn_acpi_match[] = { 2658 { "ARMHC600", PART_CMN600 }, 2659 { "ARMHC650" }, 2660 { "ARMHC700" }, 2661 { "ARMHC003" }, 2662 {} 2663 }; 2664 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match); 2665 #endif 2666 2667 static struct platform_driver arm_cmn_driver = { 2668 .driver = { 2669 .name = "arm-cmn", 2670 .of_match_table = of_match_ptr(arm_cmn_of_match), 2671 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match), 2672 .suppress_bind_attrs = true, 2673 }, 2674 .probe = arm_cmn_probe, 2675 .remove = arm_cmn_remove, 2676 }; 2677 2678 static int __init arm_cmn_init(void) 2679 { 2680 int ret; 2681 2682 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 2683 "perf/arm/cmn:online", 2684 arm_cmn_pmu_online_cpu, 2685 arm_cmn_pmu_offline_cpu); 2686 if (ret < 0) 2687 return ret; 2688 2689 arm_cmn_hp_state = ret; 2690 arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL); 2691 2692 ret = platform_driver_register(&arm_cmn_driver); 2693 if (ret) { 2694 cpuhp_remove_multi_state(arm_cmn_hp_state); 2695 debugfs_remove(arm_cmn_debugfs); 2696 } 2697 return ret; 2698 } 2699 2700 static void __exit arm_cmn_exit(void) 2701 { 2702 platform_driver_unregister(&arm_cmn_driver); 2703 cpuhp_remove_multi_state(arm_cmn_hp_state); 2704 debugfs_remove(arm_cmn_debugfs); 2705 } 2706 2707 module_init(arm_cmn_init); 2708 module_exit(arm_cmn_exit); 2709 2710 MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>"); 2711 MODULE_DESCRIPTION("Arm CMN/CI interconnect PMU driver"); 2712 MODULE_LICENSE("GPL v2"); 2713