1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2016-2020 Arm Limited 3 // CMN-600 Coherent Mesh Network PMU driver 4 5 #include <linux/acpi.h> 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/debugfs.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/perf_event.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/sort.h> 20 21 /* Common register stuff */ 22 #define CMN_NODE_INFO 0x0000 23 #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0) 24 #define CMN_NI_NODE_ID GENMASK_ULL(31, 16) 25 #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) 26 27 #define CMN_NODEID_DEVID(reg) ((reg) & 3) 28 #define CMN_NODEID_EXT_DEVID(reg) ((reg) & 1) 29 #define CMN_NODEID_PID(reg) (((reg) >> 2) & 1) 30 #define CMN_NODEID_EXT_PID(reg) (((reg) >> 1) & 3) 31 #define CMN_NODEID_1x1_PID(reg) (((reg) >> 2) & 7) 32 #define CMN_NODEID_X(reg, bits) ((reg) >> (3 + (bits))) 33 #define CMN_NODEID_Y(reg, bits) (((reg) >> 3) & ((1U << (bits)) - 1)) 34 35 #define CMN_CHILD_INFO 0x0080 36 #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0) 37 #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16) 38 39 #define CMN_CHILD_NODE_ADDR GENMASK(29, 0) 40 #define CMN_CHILD_NODE_EXTERNAL BIT(31) 41 42 #define CMN_MAX_DIMENSION 12 43 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION) 44 #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4) 45 46 /* The CFG node has various info besides the discovery tree */ 47 #define CMN_CFGM_PERIPH_ID_01 0x0008 48 #define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7, 0) 49 #define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35, 32) 50 #define CMN_CFGM_PERIPH_ID_23 0x0010 51 #define CMN_CFGM_PID2_REVISION GENMASK_ULL(7, 4) 52 53 #define CMN_CFGM_INFO_GLOBAL 0x900 54 #define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63) 55 #define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52) 56 #define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50) 57 58 #define CMN_CFGM_INFO_GLOBAL_1 0x908 59 #define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2) 60 #define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0) 61 62 /* XPs also have some local topology info which has uses too */ 63 #define CMN_MXP__CONNECT_INFO(p) (0x0008 + 8 * (p)) 64 #define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(4, 0) 65 66 #define CMN_MAX_PORTS 6 67 #define CI700_CONNECT_INFO_P2_5_OFFSET 0x10 68 69 /* PMU registers occupy the 3rd 4KB page of each node's region */ 70 #define CMN_PMU_OFFSET 0x2000 71 72 /* For most nodes, this is all there is */ 73 #define CMN_PMU_EVENT_SEL 0x000 74 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42) 75 #define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35) 76 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */ 77 #define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32) 78 79 /* HN-Ps are weird... */ 80 #define CMN_HNP_PMU_EVENT_SEL 0x008 81 82 /* DTMs live in the PMU space of XP registers */ 83 #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18) 84 #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00) 85 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19) 86 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17) 87 #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9) 88 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8) 89 #define CMN600_WPn_CONFIG_WP_COMBINE BIT(6) 90 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5) 91 #define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4) 92 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1) 93 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0) 94 #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08) 95 #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10) 96 97 #define CMN_DTM_PMU_CONFIG 0x210 98 #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32) 99 #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00 100 #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04 101 #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10 102 #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16) 103 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4) 104 #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n)) 105 #define CMN__PMEVCNT23_COMBINED BIT(2) 106 #define CMN__PMEVCNT01_COMBINED BIT(1) 107 #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0) 108 109 #define CMN_DTM_PMEVCNT 0x220 110 111 #define CMN_DTM_PMEVCNTSR 0x240 112 113 #define CMN_DTM_UNIT_INFO 0x0910 114 115 #define CMN_DTM_NUM_COUNTERS 4 116 /* Want more local counters? Why not replicate the whole DTM! Ugh... */ 117 #define CMN_DTM_OFFSET(n) ((n) * 0x200) 118 119 /* The DTC node is where the magic happens */ 120 #define CMN_DT_DTC_CTL 0x0a00 121 #define CMN_DT_DTC_CTL_DT_EN BIT(0) 122 123 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */ 124 #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4) 125 #define CMN_DT_PMEVCNT(n) (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n)) 126 #define CMN_DT_PMCCNTR (CMN_PMU_OFFSET + 0x40) 127 128 #define CMN_DT_PMEVCNTSR(n) (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n)) 129 #define CMN_DT_PMCCNTRSR (CMN_PMU_OFFSET + 0x90) 130 131 #define CMN_DT_PMCR (CMN_PMU_OFFSET + 0x100) 132 #define CMN_DT_PMCR_PMU_EN BIT(0) 133 #define CMN_DT_PMCR_CNTR_RST BIT(5) 134 #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6) 135 136 #define CMN_DT_PMOVSR (CMN_PMU_OFFSET + 0x118) 137 #define CMN_DT_PMOVSR_CLR (CMN_PMU_OFFSET + 0x120) 138 139 #define CMN_DT_PMSSR (CMN_PMU_OFFSET + 0x128) 140 #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n) 141 142 #define CMN_DT_PMSRR (CMN_PMU_OFFSET + 0x130) 143 #define CMN_DT_PMSRR_SS_REQ BIT(0) 144 145 #define CMN_DT_NUM_COUNTERS 8 146 #define CMN_MAX_DTCS 4 147 148 /* 149 * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles, 150 * so throwing away one bit to make overflow handling easy is no big deal. 151 */ 152 #define CMN_COUNTER_INIT 0x80000000 153 /* Similarly for the 40-bit cycle counter */ 154 #define CMN_CC_INIT 0x8000000000ULL 155 156 157 /* Event attributes */ 158 #define CMN_CONFIG_TYPE GENMASK_ULL(15, 0) 159 #define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16) 160 #define CMN_CONFIG_OCCUPID GENMASK_ULL(30, 27) 161 #define CMN_CONFIG_BYNODEID BIT_ULL(31) 162 #define CMN_CONFIG_NODEID GENMASK_ULL(47, 32) 163 164 #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config) 165 #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config) 166 #define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config) 167 #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config) 168 #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config) 169 170 #define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27) 171 #define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48) 172 #define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51) 173 /* Note that we don't yet support the tertiary match group on newer IPs */ 174 #define CMN_CONFIG_WP_GRP BIT_ULL(56) 175 #define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(57) 176 #define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0) 177 #define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0) 178 179 #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config) 180 #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config) 181 #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config) 182 #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config) 183 #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config) 184 #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1) 185 #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2) 186 187 /* Made-up event IDs for watchpoint direction */ 188 #define CMN_WP_UP 0 189 #define CMN_WP_DOWN 2 190 191 192 /* Internal values for encoding event support */ 193 enum cmn_model { 194 CMN600 = 1, 195 CMN650 = 2, 196 CMN700 = 4, 197 CI700 = 8, 198 /* ...and then we can use bitmap tricks for commonality */ 199 CMN_ANY = -1, 200 NOT_CMN600 = -2, 201 CMN_650ON = CMN650 | CMN700, 202 }; 203 204 /* Actual part numbers and revision IDs defined by the hardware */ 205 enum cmn_part { 206 PART_CMN600 = 0x434, 207 PART_CMN650 = 0x436, 208 PART_CMN700 = 0x43c, 209 PART_CI700 = 0x43a, 210 }; 211 212 /* CMN-600 r0px shouldn't exist in silicon, thankfully */ 213 enum cmn_revision { 214 REV_CMN600_R1P0, 215 REV_CMN600_R1P1, 216 REV_CMN600_R1P2, 217 REV_CMN600_R1P3, 218 REV_CMN600_R2P0, 219 REV_CMN600_R3P0, 220 REV_CMN600_R3P1, 221 REV_CMN650_R0P0 = 0, 222 REV_CMN650_R1P0, 223 REV_CMN650_R1P1, 224 REV_CMN650_R2P0, 225 REV_CMN650_R1P2, 226 REV_CMN700_R0P0 = 0, 227 REV_CMN700_R1P0, 228 REV_CMN700_R2P0, 229 REV_CI700_R0P0 = 0, 230 REV_CI700_R1P0, 231 REV_CI700_R2P0, 232 }; 233 234 enum cmn_node_type { 235 CMN_TYPE_INVALID, 236 CMN_TYPE_DVM, 237 CMN_TYPE_CFG, 238 CMN_TYPE_DTC, 239 CMN_TYPE_HNI, 240 CMN_TYPE_HNF, 241 CMN_TYPE_XP, 242 CMN_TYPE_SBSX, 243 CMN_TYPE_MPAM_S, 244 CMN_TYPE_MPAM_NS, 245 CMN_TYPE_RNI, 246 CMN_TYPE_RND = 0xd, 247 CMN_TYPE_RNSAM = 0xf, 248 CMN_TYPE_MTSX, 249 CMN_TYPE_HNP, 250 CMN_TYPE_CXRA = 0x100, 251 CMN_TYPE_CXHA, 252 CMN_TYPE_CXLA, 253 CMN_TYPE_CCRA, 254 CMN_TYPE_CCHA, 255 CMN_TYPE_CCLA, 256 CMN_TYPE_CCLA_RNI, 257 /* Not a real node type */ 258 CMN_TYPE_WP = 0x7770 259 }; 260 261 enum cmn_filter_select { 262 SEL_NONE = -1, 263 SEL_OCCUP1ID, 264 SEL_CLASS_OCCUP_ID, 265 SEL_CBUSY_SNTHROTTLE_SEL, 266 SEL_MAX 267 }; 268 269 struct arm_cmn_node { 270 void __iomem *pmu_base; 271 u16 id, logid; 272 enum cmn_node_type type; 273 274 int dtm; 275 union { 276 /* DN/HN-F/CXHA */ 277 struct { 278 u8 val : 4; 279 u8 count : 4; 280 } occupid[SEL_MAX]; 281 /* XP */ 282 u8 dtc; 283 }; 284 union { 285 u8 event[4]; 286 __le32 event_sel; 287 u16 event_w[4]; 288 __le64 event_sel_w; 289 }; 290 }; 291 292 struct arm_cmn_dtm { 293 void __iomem *base; 294 u32 pmu_config_low; 295 union { 296 u8 input_sel[4]; 297 __le32 pmu_config_high; 298 }; 299 s8 wp_event[4]; 300 }; 301 302 struct arm_cmn_dtc { 303 void __iomem *base; 304 int irq; 305 int irq_friend; 306 bool cc_active; 307 308 struct perf_event *counters[CMN_DT_NUM_COUNTERS]; 309 struct perf_event *cycles; 310 }; 311 312 #define CMN_STATE_DISABLED BIT(0) 313 #define CMN_STATE_TXN BIT(1) 314 315 struct arm_cmn { 316 struct device *dev; 317 void __iomem *base; 318 unsigned int state; 319 320 enum cmn_revision rev; 321 enum cmn_part part; 322 u8 mesh_x; 323 u8 mesh_y; 324 u16 num_xps; 325 u16 num_dns; 326 bool multi_dtm; 327 u8 ports_used; 328 struct { 329 unsigned int rsp_vc_num : 2; 330 unsigned int dat_vc_num : 2; 331 unsigned int snp_vc_num : 2; 332 unsigned int req_vc_num : 2; 333 }; 334 335 struct arm_cmn_node *xps; 336 struct arm_cmn_node *dns; 337 338 struct arm_cmn_dtm *dtms; 339 struct arm_cmn_dtc *dtc; 340 unsigned int num_dtcs; 341 342 int cpu; 343 struct hlist_node cpuhp_node; 344 345 struct pmu pmu; 346 struct dentry *debug; 347 }; 348 349 #define to_cmn(p) container_of(p, struct arm_cmn, pmu) 350 351 static int arm_cmn_hp_state; 352 353 struct arm_cmn_nodeid { 354 u8 x; 355 u8 y; 356 u8 port; 357 u8 dev; 358 }; 359 360 static int arm_cmn_xyidbits(const struct arm_cmn *cmn) 361 { 362 return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1) | 2); 363 } 364 365 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id) 366 { 367 struct arm_cmn_nodeid nid; 368 369 if (cmn->num_xps == 1) { 370 nid.x = 0; 371 nid.y = 0; 372 nid.port = CMN_NODEID_1x1_PID(id); 373 nid.dev = CMN_NODEID_DEVID(id); 374 } else { 375 int bits = arm_cmn_xyidbits(cmn); 376 377 nid.x = CMN_NODEID_X(id, bits); 378 nid.y = CMN_NODEID_Y(id, bits); 379 if (cmn->ports_used & 0xc) { 380 nid.port = CMN_NODEID_EXT_PID(id); 381 nid.dev = CMN_NODEID_EXT_DEVID(id); 382 } else { 383 nid.port = CMN_NODEID_PID(id); 384 nid.dev = CMN_NODEID_DEVID(id); 385 } 386 } 387 return nid; 388 } 389 390 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn, 391 const struct arm_cmn_node *dn) 392 { 393 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); 394 int xp_idx = cmn->mesh_x * nid.y + nid.x; 395 396 return cmn->xps + xp_idx; 397 } 398 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, 399 enum cmn_node_type type) 400 { 401 struct arm_cmn_node *dn; 402 403 for (dn = cmn->dns; dn->type; dn++) 404 if (dn->type == type) 405 return dn; 406 return NULL; 407 } 408 409 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn) 410 { 411 switch (cmn->part) { 412 case PART_CMN600: 413 return CMN600; 414 case PART_CMN650: 415 return CMN650; 416 case PART_CMN700: 417 return CMN700; 418 case PART_CI700: 419 return CI700; 420 default: 421 return 0; 422 }; 423 } 424 425 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn, 426 const struct arm_cmn_node *xp, int port) 427 { 428 int offset = CMN_MXP__CONNECT_INFO(port); 429 430 if (port >= 2) { 431 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650) 432 return 0; 433 /* 434 * CI-700 may have extra ports, but still has the 435 * mesh_port_connect_info registers in the way. 436 */ 437 if (cmn->part == PART_CI700) 438 offset += CI700_CONNECT_INFO_P2_5_OFFSET; 439 } 440 441 return readl_relaxed(xp->pmu_base - CMN_PMU_OFFSET + offset); 442 } 443 444 static struct dentry *arm_cmn_debugfs; 445 446 #ifdef CONFIG_DEBUG_FS 447 static const char *arm_cmn_device_type(u8 type) 448 { 449 switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) { 450 case 0x00: return " |"; 451 case 0x01: return " RN-I |"; 452 case 0x02: return " RN-D |"; 453 case 0x04: return " RN-F_B |"; 454 case 0x05: return "RN-F_B_E|"; 455 case 0x06: return " RN-F_A |"; 456 case 0x07: return "RN-F_A_E|"; 457 case 0x08: return " HN-T |"; 458 case 0x09: return " HN-I |"; 459 case 0x0a: return " HN-D |"; 460 case 0x0b: return " HN-P |"; 461 case 0x0c: return " SN-F |"; 462 case 0x0d: return " SBSX |"; 463 case 0x0e: return " HN-F |"; 464 case 0x0f: return " SN-F_E |"; 465 case 0x10: return " SN-F_D |"; 466 case 0x11: return " CXHA |"; 467 case 0x12: return " CXRA |"; 468 case 0x13: return " CXRH |"; 469 case 0x14: return " RN-F_D |"; 470 case 0x15: return "RN-F_D_E|"; 471 case 0x16: return " RN-F_C |"; 472 case 0x17: return "RN-F_C_E|"; 473 case 0x18: return " RN-F_E |"; 474 case 0x19: return "RN-F_E_E|"; 475 case 0x1c: return " MTSX |"; 476 case 0x1d: return " HN-V |"; 477 case 0x1e: return " CCG |"; 478 default: return " ???? |"; 479 } 480 } 481 482 static void arm_cmn_show_logid(struct seq_file *s, int x, int y, int p, int d) 483 { 484 struct arm_cmn *cmn = s->private; 485 struct arm_cmn_node *dn; 486 487 for (dn = cmn->dns; dn->type; dn++) { 488 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); 489 490 if (dn->type == CMN_TYPE_XP) 491 continue; 492 /* Ignore the extra components that will overlap on some ports */ 493 if (dn->type < CMN_TYPE_HNI) 494 continue; 495 496 if (nid.x != x || nid.y != y || nid.port != p || nid.dev != d) 497 continue; 498 499 seq_printf(s, " #%-2d |", dn->logid); 500 return; 501 } 502 seq_puts(s, " |"); 503 } 504 505 static int arm_cmn_map_show(struct seq_file *s, void *data) 506 { 507 struct arm_cmn *cmn = s->private; 508 int x, y, p, pmax = fls(cmn->ports_used); 509 510 seq_puts(s, " X"); 511 for (x = 0; x < cmn->mesh_x; x++) 512 seq_printf(s, " %d ", x); 513 seq_puts(s, "\nY P D+"); 514 y = cmn->mesh_y; 515 while (y--) { 516 int xp_base = cmn->mesh_x * y; 517 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION]; 518 519 for (x = 0; x < cmn->mesh_x; x++) 520 seq_puts(s, "--------+"); 521 522 seq_printf(s, "\n%d |", y); 523 for (x = 0; x < cmn->mesh_x; x++) { 524 struct arm_cmn_node *xp = cmn->xps + xp_base + x; 525 526 for (p = 0; p < CMN_MAX_PORTS; p++) 527 port[p][x] = arm_cmn_device_connect_info(cmn, xp, p); 528 seq_printf(s, " XP #%-2d |", xp_base + x); 529 } 530 531 seq_puts(s, "\n |"); 532 for (x = 0; x < cmn->mesh_x; x++) { 533 u8 dtc = cmn->xps[xp_base + x].dtc; 534 535 if (dtc & (dtc - 1)) 536 seq_puts(s, " DTC ?? |"); 537 else 538 seq_printf(s, " DTC %ld |", __ffs(dtc)); 539 } 540 seq_puts(s, "\n |"); 541 for (x = 0; x < cmn->mesh_x; x++) 542 seq_puts(s, "........|"); 543 544 for (p = 0; p < pmax; p++) { 545 seq_printf(s, "\n %d |", p); 546 for (x = 0; x < cmn->mesh_x; x++) 547 seq_puts(s, arm_cmn_device_type(port[p][x])); 548 seq_puts(s, "\n 0|"); 549 for (x = 0; x < cmn->mesh_x; x++) 550 arm_cmn_show_logid(s, x, y, p, 0); 551 seq_puts(s, "\n 1|"); 552 for (x = 0; x < cmn->mesh_x; x++) 553 arm_cmn_show_logid(s, x, y, p, 1); 554 } 555 seq_puts(s, "\n-----+"); 556 } 557 for (x = 0; x < cmn->mesh_x; x++) 558 seq_puts(s, "--------+"); 559 seq_puts(s, "\n"); 560 return 0; 561 } 562 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map); 563 564 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) 565 { 566 const char *name = "map"; 567 568 if (id > 0) 569 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id); 570 if (!name) 571 return; 572 573 cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops); 574 } 575 #else 576 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {} 577 #endif 578 579 struct arm_cmn_hw_event { 580 struct arm_cmn_node *dn; 581 u64 dtm_idx[4]; 582 unsigned int dtc_idx; 583 u8 dtcs_used; 584 u8 num_dns; 585 u8 dtm_offset; 586 bool wide_sel; 587 enum cmn_filter_select filter_sel; 588 }; 589 590 #define for_each_hw_dn(hw, dn, i) \ 591 for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++) 592 593 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event) 594 { 595 BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target)); 596 return (struct arm_cmn_hw_event *)&event->hw; 597 } 598 599 static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val) 600 { 601 x[pos / 32] |= (u64)val << ((pos % 32) * 2); 602 } 603 604 static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos) 605 { 606 return (x[pos / 32] >> ((pos % 32) * 2)) & 3; 607 } 608 609 struct arm_cmn_event_attr { 610 struct device_attribute attr; 611 enum cmn_model model; 612 enum cmn_node_type type; 613 enum cmn_filter_select fsel; 614 u16 eventid; 615 u8 occupid; 616 }; 617 618 struct arm_cmn_format_attr { 619 struct device_attribute attr; 620 u64 field; 621 int config; 622 }; 623 624 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\ 625 (&((struct arm_cmn_event_attr[]) {{ \ 626 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \ 627 .model = _model, \ 628 .type = _type, \ 629 .eventid = _eventid, \ 630 .occupid = _occupid, \ 631 .fsel = _fsel, \ 632 }})[0].attr.attr) 633 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid) \ 634 _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE) 635 636 static ssize_t arm_cmn_event_show(struct device *dev, 637 struct device_attribute *attr, char *buf) 638 { 639 struct arm_cmn_event_attr *eattr; 640 641 eattr = container_of(attr, typeof(*eattr), attr); 642 643 if (eattr->type == CMN_TYPE_DTC) 644 return sysfs_emit(buf, "type=0x%x\n", eattr->type); 645 646 if (eattr->type == CMN_TYPE_WP) 647 return sysfs_emit(buf, 648 "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n", 649 eattr->type, eattr->eventid); 650 651 if (eattr->fsel > SEL_NONE) 652 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n", 653 eattr->type, eattr->eventid, eattr->occupid); 654 655 return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type, 656 eattr->eventid); 657 } 658 659 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, 660 struct attribute *attr, 661 int unused) 662 { 663 struct device *dev = kobj_to_dev(kobj); 664 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 665 struct arm_cmn_event_attr *eattr; 666 enum cmn_node_type type; 667 u16 eventid; 668 669 eattr = container_of(attr, typeof(*eattr), attr.attr); 670 671 if (!(eattr->model & arm_cmn_model(cmn))) 672 return 0; 673 674 type = eattr->type; 675 eventid = eattr->eventid; 676 677 /* Watchpoints aren't nodes, so avoid confusion */ 678 if (type == CMN_TYPE_WP) 679 return attr->mode; 680 681 /* Hide XP events for unused interfaces/channels */ 682 if (type == CMN_TYPE_XP) { 683 unsigned int intf = (eventid >> 2) & 7; 684 unsigned int chan = eventid >> 5; 685 686 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3))) 687 return 0; 688 689 if (chan == 4 && cmn->part == PART_CMN600) 690 return 0; 691 692 if ((chan == 5 && cmn->rsp_vc_num < 2) || 693 (chan == 6 && cmn->dat_vc_num < 2) || 694 (chan == 7 && cmn->snp_vc_num < 2) || 695 (chan == 8 && cmn->req_vc_num < 2)) 696 return 0; 697 } 698 699 /* Revision-specific differences */ 700 if (cmn->part == PART_CMN600) { 701 if (cmn->rev < REV_CMN600_R1P3) { 702 if (type == CMN_TYPE_CXRA && eventid > 0x10) 703 return 0; 704 } 705 if (cmn->rev < REV_CMN600_R1P2) { 706 if (type == CMN_TYPE_HNF && eventid == 0x1b) 707 return 0; 708 if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA) 709 return 0; 710 } 711 } else if (cmn->part == PART_CMN650) { 712 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) { 713 if (type == CMN_TYPE_HNF && eventid > 0x22) 714 return 0; 715 if (type == CMN_TYPE_SBSX && eventid == 0x17) 716 return 0; 717 if (type == CMN_TYPE_RNI && eventid > 0x10) 718 return 0; 719 } 720 } else if (cmn->part == PART_CMN700) { 721 if (cmn->rev < REV_CMN700_R2P0) { 722 if (type == CMN_TYPE_HNF && eventid > 0x2c) 723 return 0; 724 if (type == CMN_TYPE_CCHA && eventid > 0x74) 725 return 0; 726 if (type == CMN_TYPE_CCLA && eventid > 0x27) 727 return 0; 728 } 729 if (cmn->rev < REV_CMN700_R1P0) { 730 if (type == CMN_TYPE_HNF && eventid > 0x2b) 731 return 0; 732 } 733 } 734 735 if (!arm_cmn_node(cmn, type)) 736 return 0; 737 738 return attr->mode; 739 } 740 741 #define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel) \ 742 _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel) 743 #define CMN_EVENT_DTC(_name) \ 744 CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0) 745 #define _CMN_EVENT_HNF(_model, _name, _event, _occup, _fsel) \ 746 _CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event, _occup, _fsel) 747 #define CMN_EVENT_HNI(_name, _event) \ 748 CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event) 749 #define CMN_EVENT_HNP(_name, _event) \ 750 CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event) 751 #define __CMN_EVENT_XP(_name, _event) \ 752 CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event) 753 #define CMN_EVENT_SBSX(_model, _name, _event) \ 754 CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event) 755 #define CMN_EVENT_RNID(_model, _name, _event) \ 756 CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event) 757 #define CMN_EVENT_MTSX(_name, _event) \ 758 CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event) 759 #define CMN_EVENT_CXRA(_model, _name, _event) \ 760 CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event) 761 #define CMN_EVENT_CXHA(_name, _event) \ 762 CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event) 763 #define CMN_EVENT_CCRA(_name, _event) \ 764 CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event) 765 #define CMN_EVENT_CCHA(_name, _event) \ 766 CMN_EVENT_ATTR(CMN_ANY, ccha_##_name, CMN_TYPE_CCHA, _event) 767 #define CMN_EVENT_CCLA(_name, _event) \ 768 CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event) 769 #define CMN_EVENT_CCLA_RNI(_name, _event) \ 770 CMN_EVENT_ATTR(CMN_ANY, ccla_rni_##_name, CMN_TYPE_CCLA_RNI, _event) 771 772 #define CMN_EVENT_DVM(_model, _name, _event) \ 773 _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE) 774 #define CMN_EVENT_DVM_OCC(_model, _name, _event) \ 775 _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID), \ 776 _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \ 777 _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID) 778 #define CMN_EVENT_HNF(_model, _name, _event) \ 779 _CMN_EVENT_HNF(_model, _name, _event, 0, SEL_NONE) 780 #define CMN_EVENT_HNF_CLS(_model, _name, _event) \ 781 _CMN_EVENT_HNF(_model, _name##_class0, _event, 0, SEL_CLASS_OCCUP_ID), \ 782 _CMN_EVENT_HNF(_model, _name##_class1, _event, 1, SEL_CLASS_OCCUP_ID), \ 783 _CMN_EVENT_HNF(_model, _name##_class2, _event, 2, SEL_CLASS_OCCUP_ID), \ 784 _CMN_EVENT_HNF(_model, _name##_class3, _event, 3, SEL_CLASS_OCCUP_ID) 785 #define CMN_EVENT_HNF_SNT(_model, _name, _event) \ 786 _CMN_EVENT_HNF(_model, _name##_all, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \ 787 _CMN_EVENT_HNF(_model, _name##_group0_read, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \ 788 _CMN_EVENT_HNF(_model, _name##_group0_write, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \ 789 _CMN_EVENT_HNF(_model, _name##_group1_read, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \ 790 _CMN_EVENT_HNF(_model, _name##_group1_write, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \ 791 _CMN_EVENT_HNF(_model, _name##_read, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \ 792 _CMN_EVENT_HNF(_model, _name##_write, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL) 793 794 #define _CMN_EVENT_XP(_name, _event) \ 795 __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \ 796 __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \ 797 __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \ 798 __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)), \ 799 __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \ 800 __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \ 801 __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \ 802 __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2)) 803 804 /* Good thing there are only 3 fundamental XP events... */ 805 #define CMN_EVENT_XP(_name, _event) \ 806 _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \ 807 _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \ 808 _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \ 809 _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \ 810 _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \ 811 _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \ 812 _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)), \ 813 _CMN_EVENT_XP(snp2_##_name, (_event) | (7 << 5)), \ 814 _CMN_EVENT_XP(req2_##_name, (_event) | (8 << 5)) 815 816 817 static struct attribute *arm_cmn_event_attrs[] = { 818 CMN_EVENT_DTC(cycles), 819 820 /* 821 * DVM node events conflict with HN-I events in the equivalent PMU 822 * slot, but our lazy short-cut of using the DTM counter index for 823 * the PMU index as well happens to avoid that by construction. 824 */ 825 CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01), 826 CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02), 827 CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03), 828 CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04), 829 CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy, 0x05), 830 CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi, 0x01), 831 CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi, 0x02), 832 CMN_EVENT_DVM(NOT_CMN600, dvmop_pici, 0x03), 833 CMN_EVENT_DVM(NOT_CMN600, dvmop_vici, 0x04), 834 CMN_EVENT_DVM(NOT_CMN600, dvmsync, 0x05), 835 CMN_EVENT_DVM(NOT_CMN600, vmid_filtered, 0x06), 836 CMN_EVENT_DVM(NOT_CMN600, rndop_filtered, 0x07), 837 CMN_EVENT_DVM(NOT_CMN600, retry, 0x08), 838 CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv, 0x09), 839 CMN_EVENT_DVM(NOT_CMN600, txsnp_stall, 0x0a), 840 CMN_EVENT_DVM(NOT_CMN600, trkfull, 0x0b), 841 CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy, 0x0c), 842 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_cxha, 0x0d), 843 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_pdn, 0x0e), 844 CMN_EVENT_DVM(CMN700, trk_alloc, 0x0f), 845 CMN_EVENT_DVM(CMN700, trk_cxha_alloc, 0x10), 846 CMN_EVENT_DVM(CMN700, trk_pdn_alloc, 0x11), 847 CMN_EVENT_DVM(CMN700, txsnp_stall_limit, 0x12), 848 CMN_EVENT_DVM(CMN700, rxsnp_stall_starv, 0x13), 849 CMN_EVENT_DVM(CMN700, txsnp_sync_stall_op, 0x14), 850 851 CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01), 852 CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02), 853 CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03), 854 CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04), 855 CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05), 856 CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06), 857 CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07), 858 CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08), 859 CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09), 860 CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a), 861 CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b), 862 CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c), 863 CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d), 864 CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e), 865 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_all, 0x0f, 0, SEL_OCCUP1ID), 866 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_read, 0x0f, 1, SEL_OCCUP1ID), 867 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_write, 0x0f, 2, SEL_OCCUP1ID), 868 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_atomic, 0x0f, 3, SEL_OCCUP1ID), 869 _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_stash, 0x0f, 4, SEL_OCCUP1ID), 870 CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10), 871 CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11), 872 CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12), 873 CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13), 874 CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14), 875 CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15), 876 CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16), 877 CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17), 878 CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18), 879 CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19), 880 CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a), 881 CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b), 882 CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c), 883 CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d), 884 CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e), 885 CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f), 886 CMN_EVENT_HNF(NOT_CMN600, atomic_fwd, 0x20), 887 CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim, 0x21), 888 CMN_EVENT_HNF(NOT_CMN600, mpam_softlim, 0x22), 889 CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster, 0x23), 890 CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict, 0x24), 891 CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line, 0x25), 892 CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup, 0x26), 893 CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry, 0x27), 894 CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs, 0x28), 895 CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin, 0x29), 896 CMN_EVENT_HNF_SNT(CMN700, sn_throttle, 0x2a), 897 CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min, 0x2b), 898 CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise, 0x2c), 899 CMN_EVENT_HNF(CMN700, snp_intv_cln, 0x2d), 900 CMN_EVENT_HNF(CMN700, nc_excl, 0x2e), 901 CMN_EVENT_HNF(CMN700, excl_mon_ovfl, 0x2f), 902 903 CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), 904 CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), 905 CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22), 906 CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23), 907 CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24), 908 CMN_EVENT_HNI(rrt_rd_alloc, 0x25), 909 CMN_EVENT_HNI(rrt_wr_alloc, 0x26), 910 CMN_EVENT_HNI(rdt_rd_alloc, 0x27), 911 CMN_EVENT_HNI(rdt_wr_alloc, 0x28), 912 CMN_EVENT_HNI(wdb_alloc, 0x29), 913 CMN_EVENT_HNI(txrsp_retryack, 0x2a), 914 CMN_EVENT_HNI(arvalid_no_arready, 0x2b), 915 CMN_EVENT_HNI(arready_no_arvalid, 0x2c), 916 CMN_EVENT_HNI(awvalid_no_awready, 0x2d), 917 CMN_EVENT_HNI(awready_no_awvalid, 0x2e), 918 CMN_EVENT_HNI(wvalid_no_wready, 0x2f), 919 CMN_EVENT_HNI(txdat_stall, 0x30), 920 CMN_EVENT_HNI(nonpcie_serialization, 0x31), 921 CMN_EVENT_HNI(pcie_serialization, 0x32), 922 923 /* 924 * HN-P events squat on top of the HN-I similarly to DVM events, except 925 * for being crammed into the same physical node as well. And of course 926 * where would the fun be if the same events were in the same order... 927 */ 928 CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl, 0x01), 929 CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl, 0x02), 930 CMN_EVENT_HNP(wdb_occ_cnt_ovfl, 0x03), 931 CMN_EVENT_HNP(rrt_wr_alloc, 0x04), 932 CMN_EVENT_HNP(rdt_wr_alloc, 0x05), 933 CMN_EVENT_HNP(wdb_alloc, 0x06), 934 CMN_EVENT_HNP(awvalid_no_awready, 0x07), 935 CMN_EVENT_HNP(awready_no_awvalid, 0x08), 936 CMN_EVENT_HNP(wvalid_no_wready, 0x09), 937 CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl, 0x11), 938 CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl, 0x12), 939 CMN_EVENT_HNP(rrt_rd_alloc, 0x13), 940 CMN_EVENT_HNP(rdt_rd_alloc, 0x14), 941 CMN_EVENT_HNP(arvalid_no_arready, 0x15), 942 CMN_EVENT_HNP(arready_no_arvalid, 0x16), 943 944 CMN_EVENT_XP(txflit_valid, 0x01), 945 CMN_EVENT_XP(txflit_stall, 0x02), 946 CMN_EVENT_XP(partial_dat_flit, 0x03), 947 /* We treat watchpoints as a special made-up class of XP events */ 948 CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP), 949 CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN), 950 951 CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01), 952 CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02), 953 CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03), 954 CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04), 955 CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05), 956 CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06), 957 CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11), 958 CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12), 959 CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13), 960 CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14), 961 CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15), 962 CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16), 963 CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl, 0x17), 964 CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21), 965 CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22), 966 CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23), 967 CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24), 968 CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25), 969 970 CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01), 971 CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02), 972 CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03), 973 CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04), 974 CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05), 975 CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06), 976 CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07), 977 CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08), 978 CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09), 979 CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a), 980 CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b), 981 CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c), 982 CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d), 983 CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e), 984 CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f), 985 CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10), 986 CMN_EVENT_RNID(CMN600, rdb_unord, 0x11), 987 CMN_EVENT_RNID(CMN600, rdb_replay, 0x12), 988 CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13), 989 CMN_EVENT_RNID(CMN600, rdb_ord, 0x14), 990 CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl, 0x11), 991 CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl, 0x12), 992 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13), 993 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14), 994 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15), 995 CMN_EVENT_RNID(NOT_CMN600, wrt_throttled, 0x16), 996 CMN_EVENT_RNID(CMN700, ldb_full, 0x17), 997 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18), 998 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19), 999 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a), 1000 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b), 1001 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c), 1002 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d), 1003 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e), 1004 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f), 1005 CMN_EVENT_RNID(CMN700, rrt_burst_alloc, 0x20), 1006 CMN_EVENT_RNID(CMN700, awid_hash, 0x21), 1007 CMN_EVENT_RNID(CMN700, atomic_alloc, 0x22), 1008 CMN_EVENT_RNID(CMN700, atomic_occ_ovfl, 0x23), 1009 1010 CMN_EVENT_MTSX(tc_lookup, 0x01), 1011 CMN_EVENT_MTSX(tc_fill, 0x02), 1012 CMN_EVENT_MTSX(tc_miss, 0x03), 1013 CMN_EVENT_MTSX(tdb_forward, 0x04), 1014 CMN_EVENT_MTSX(tcq_hazard, 0x05), 1015 CMN_EVENT_MTSX(tcq_rd_alloc, 0x06), 1016 CMN_EVENT_MTSX(tcq_wr_alloc, 0x07), 1017 CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08), 1018 CMN_EVENT_MTSX(axi_rd_req, 0x09), 1019 CMN_EVENT_MTSX(axi_wr_req, 0x0a), 1020 CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b), 1021 CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c), 1022 1023 CMN_EVENT_CXRA(CMN_ANY, rht_occ, 0x01), 1024 CMN_EVENT_CXRA(CMN_ANY, sht_occ, 0x02), 1025 CMN_EVENT_CXRA(CMN_ANY, rdb_occ, 0x03), 1026 CMN_EVENT_CXRA(CMN_ANY, wdb_occ, 0x04), 1027 CMN_EVENT_CXRA(CMN_ANY, ssb_occ, 0x05), 1028 CMN_EVENT_CXRA(CMN_ANY, snp_bcasts, 0x06), 1029 CMN_EVENT_CXRA(CMN_ANY, req_chains, 0x07), 1030 CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen, 0x08), 1031 CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls, 0x09), 1032 CMN_EVENT_CXRA(CMN_ANY, chidat_stalls, 0x0a), 1033 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b), 1034 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c), 1035 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d), 1036 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e), 1037 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f), 1038 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10), 1039 CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11), 1040 CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12), 1041 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13), 1042 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14), 1043 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15), 1044 1045 CMN_EVENT_CXHA(rddatbyp, 0x21), 1046 CMN_EVENT_CXHA(chirsp_up_stall, 0x22), 1047 CMN_EVENT_CXHA(chidat_up_stall, 0x23), 1048 CMN_EVENT_CXHA(snppcrd_link0_stall, 0x24), 1049 CMN_EVENT_CXHA(snppcrd_link1_stall, 0x25), 1050 CMN_EVENT_CXHA(snppcrd_link2_stall, 0x26), 1051 CMN_EVENT_CXHA(reqtrk_occ, 0x27), 1052 CMN_EVENT_CXHA(rdb_occ, 0x28), 1053 CMN_EVENT_CXHA(rdbyp_occ, 0x29), 1054 CMN_EVENT_CXHA(wdb_occ, 0x2a), 1055 CMN_EVENT_CXHA(snptrk_occ, 0x2b), 1056 CMN_EVENT_CXHA(sdb_occ, 0x2c), 1057 CMN_EVENT_CXHA(snphaz_occ, 0x2d), 1058 1059 CMN_EVENT_CCRA(rht_occ, 0x41), 1060 CMN_EVENT_CCRA(sht_occ, 0x42), 1061 CMN_EVENT_CCRA(rdb_occ, 0x43), 1062 CMN_EVENT_CCRA(wdb_occ, 0x44), 1063 CMN_EVENT_CCRA(ssb_occ, 0x45), 1064 CMN_EVENT_CCRA(snp_bcasts, 0x46), 1065 CMN_EVENT_CCRA(req_chains, 0x47), 1066 CMN_EVENT_CCRA(req_chain_avglen, 0x48), 1067 CMN_EVENT_CCRA(chirsp_stalls, 0x49), 1068 CMN_EVENT_CCRA(chidat_stalls, 0x4a), 1069 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0, 0x4b), 1070 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1, 0x4c), 1071 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2, 0x4d), 1072 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0, 0x4e), 1073 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1, 0x4f), 1074 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2, 0x50), 1075 CMN_EVENT_CCRA(external_chirsp_stalls, 0x51), 1076 CMN_EVENT_CCRA(external_chidat_stalls, 0x52), 1077 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0, 0x53), 1078 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1, 0x54), 1079 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2, 0x55), 1080 CMN_EVENT_CCRA(rht_alloc, 0x56), 1081 CMN_EVENT_CCRA(sht_alloc, 0x57), 1082 CMN_EVENT_CCRA(rdb_alloc, 0x58), 1083 CMN_EVENT_CCRA(wdb_alloc, 0x59), 1084 CMN_EVENT_CCRA(ssb_alloc, 0x5a), 1085 1086 CMN_EVENT_CCHA(rddatbyp, 0x61), 1087 CMN_EVENT_CCHA(chirsp_up_stall, 0x62), 1088 CMN_EVENT_CCHA(chidat_up_stall, 0x63), 1089 CMN_EVENT_CCHA(snppcrd_link0_stall, 0x64), 1090 CMN_EVENT_CCHA(snppcrd_link1_stall, 0x65), 1091 CMN_EVENT_CCHA(snppcrd_link2_stall, 0x66), 1092 CMN_EVENT_CCHA(reqtrk_occ, 0x67), 1093 CMN_EVENT_CCHA(rdb_occ, 0x68), 1094 CMN_EVENT_CCHA(rdbyp_occ, 0x69), 1095 CMN_EVENT_CCHA(wdb_occ, 0x6a), 1096 CMN_EVENT_CCHA(snptrk_occ, 0x6b), 1097 CMN_EVENT_CCHA(sdb_occ, 0x6c), 1098 CMN_EVENT_CCHA(snphaz_occ, 0x6d), 1099 CMN_EVENT_CCHA(reqtrk_alloc, 0x6e), 1100 CMN_EVENT_CCHA(rdb_alloc, 0x6f), 1101 CMN_EVENT_CCHA(rdbyp_alloc, 0x70), 1102 CMN_EVENT_CCHA(wdb_alloc, 0x71), 1103 CMN_EVENT_CCHA(snptrk_alloc, 0x72), 1104 CMN_EVENT_CCHA(sdb_alloc, 0x73), 1105 CMN_EVENT_CCHA(snphaz_alloc, 0x74), 1106 CMN_EVENT_CCHA(pb_rhu_req_occ, 0x75), 1107 CMN_EVENT_CCHA(pb_rhu_req_alloc, 0x76), 1108 CMN_EVENT_CCHA(pb_rhu_pcie_req_occ, 0x77), 1109 CMN_EVENT_CCHA(pb_rhu_pcie_req_alloc, 0x78), 1110 CMN_EVENT_CCHA(pb_pcie_wr_req_occ, 0x79), 1111 CMN_EVENT_CCHA(pb_pcie_wr_req_alloc, 0x7a), 1112 CMN_EVENT_CCHA(pb_pcie_reg_req_occ, 0x7b), 1113 CMN_EVENT_CCHA(pb_pcie_reg_req_alloc, 0x7c), 1114 CMN_EVENT_CCHA(pb_pcie_rsvd_req_occ, 0x7d), 1115 CMN_EVENT_CCHA(pb_pcie_rsvd_req_alloc, 0x7e), 1116 CMN_EVENT_CCHA(pb_rhu_dat_occ, 0x7f), 1117 CMN_EVENT_CCHA(pb_rhu_dat_alloc, 0x80), 1118 CMN_EVENT_CCHA(pb_rhu_pcie_dat_occ, 0x81), 1119 CMN_EVENT_CCHA(pb_rhu_pcie_dat_alloc, 0x82), 1120 CMN_EVENT_CCHA(pb_pcie_wr_dat_occ, 0x83), 1121 CMN_EVENT_CCHA(pb_pcie_wr_dat_alloc, 0x84), 1122 1123 CMN_EVENT_CCLA(rx_cxs, 0x21), 1124 CMN_EVENT_CCLA(tx_cxs, 0x22), 1125 CMN_EVENT_CCLA(rx_cxs_avg_size, 0x23), 1126 CMN_EVENT_CCLA(tx_cxs_avg_size, 0x24), 1127 CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure, 0x25), 1128 CMN_EVENT_CCLA(link_crdbuf_occ, 0x26), 1129 CMN_EVENT_CCLA(link_crdbuf_alloc, 0x27), 1130 CMN_EVENT_CCLA(pfwd_rcvr_cxs, 0x28), 1131 CMN_EVENT_CCLA(pfwd_sndr_num_flits, 0x29), 1132 CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd, 0x2a), 1133 CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd, 0x2b), 1134 1135 NULL 1136 }; 1137 1138 static const struct attribute_group arm_cmn_event_attrs_group = { 1139 .name = "events", 1140 .attrs = arm_cmn_event_attrs, 1141 .is_visible = arm_cmn_event_attr_is_visible, 1142 }; 1143 1144 static ssize_t arm_cmn_format_show(struct device *dev, 1145 struct device_attribute *attr, char *buf) 1146 { 1147 struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr); 1148 int lo = __ffs(fmt->field), hi = __fls(fmt->field); 1149 1150 if (lo == hi) 1151 return sysfs_emit(buf, "config:%d\n", lo); 1152 1153 if (!fmt->config) 1154 return sysfs_emit(buf, "config:%d-%d\n", lo, hi); 1155 1156 return sysfs_emit(buf, "config%d:%d-%d\n", fmt->config, lo, hi); 1157 } 1158 1159 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \ 1160 (&((struct arm_cmn_format_attr[]) {{ \ 1161 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \ 1162 .config = _cfg, \ 1163 .field = _fld, \ 1164 }})[0].attr.attr) 1165 #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld) 1166 1167 static struct attribute *arm_cmn_format_attrs[] = { 1168 CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE), 1169 CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID), 1170 CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID), 1171 CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID), 1172 CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID), 1173 1174 CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL), 1175 CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL), 1176 CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP), 1177 CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE), 1178 CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE), 1179 1180 _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL), 1181 _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK), 1182 1183 NULL 1184 }; 1185 1186 static const struct attribute_group arm_cmn_format_attrs_group = { 1187 .name = "format", 1188 .attrs = arm_cmn_format_attrs, 1189 }; 1190 1191 static ssize_t arm_cmn_cpumask_show(struct device *dev, 1192 struct device_attribute *attr, char *buf) 1193 { 1194 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1195 1196 return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu)); 1197 } 1198 1199 static struct device_attribute arm_cmn_cpumask_attr = 1200 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL); 1201 1202 static ssize_t arm_cmn_identifier_show(struct device *dev, 1203 struct device_attribute *attr, char *buf) 1204 { 1205 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1206 1207 return sysfs_emit(buf, "%03x%02x\n", cmn->part, cmn->rev); 1208 } 1209 1210 static struct device_attribute arm_cmn_identifier_attr = 1211 __ATTR(identifier, 0444, arm_cmn_identifier_show, NULL); 1212 1213 static struct attribute *arm_cmn_other_attrs[] = { 1214 &arm_cmn_cpumask_attr.attr, 1215 &arm_cmn_identifier_attr.attr, 1216 NULL, 1217 }; 1218 1219 static const struct attribute_group arm_cmn_other_attrs_group = { 1220 .attrs = arm_cmn_other_attrs, 1221 }; 1222 1223 static const struct attribute_group *arm_cmn_attr_groups[] = { 1224 &arm_cmn_event_attrs_group, 1225 &arm_cmn_format_attrs_group, 1226 &arm_cmn_other_attrs_group, 1227 NULL 1228 }; 1229 1230 static int arm_cmn_wp_idx(struct perf_event *event) 1231 { 1232 return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event); 1233 } 1234 1235 static u32 arm_cmn_wp_config(struct perf_event *event) 1236 { 1237 u32 config; 1238 u32 dev = CMN_EVENT_WP_DEV_SEL(event); 1239 u32 chn = CMN_EVENT_WP_CHN_SEL(event); 1240 u32 grp = CMN_EVENT_WP_GRP(event); 1241 u32 exc = CMN_EVENT_WP_EXCLUSIVE(event); 1242 u32 combine = CMN_EVENT_WP_COMBINE(event); 1243 bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600; 1244 1245 config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) | 1246 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) | 1247 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) | 1248 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1); 1249 if (exc) 1250 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE : 1251 CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE; 1252 if (combine && !grp) 1253 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE : 1254 CMN_DTM_WPn_CONFIG_WP_COMBINE; 1255 return config; 1256 } 1257 1258 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state) 1259 { 1260 if (!cmn->state) 1261 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR); 1262 cmn->state |= state; 1263 } 1264 1265 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state) 1266 { 1267 cmn->state &= ~state; 1268 if (!cmn->state) 1269 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, 1270 cmn->dtc[0].base + CMN_DT_PMCR); 1271 } 1272 1273 static void arm_cmn_pmu_enable(struct pmu *pmu) 1274 { 1275 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED); 1276 } 1277 1278 static void arm_cmn_pmu_disable(struct pmu *pmu) 1279 { 1280 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED); 1281 } 1282 1283 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, 1284 bool snapshot) 1285 { 1286 struct arm_cmn_dtm *dtm = NULL; 1287 struct arm_cmn_node *dn; 1288 unsigned int i, offset, dtm_idx; 1289 u64 reg, count = 0; 1290 1291 offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; 1292 for_each_hw_dn(hw, dn, i) { 1293 if (dtm != &cmn->dtms[dn->dtm]) { 1294 dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1295 reg = readq_relaxed(dtm->base + offset); 1296 } 1297 dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1298 count += (u16)(reg >> (dtm_idx * 16)); 1299 } 1300 return count; 1301 } 1302 1303 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc) 1304 { 1305 u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR); 1306 1307 writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR); 1308 return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1); 1309 } 1310 1311 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx) 1312 { 1313 u32 val, pmevcnt = CMN_DT_PMEVCNT(idx); 1314 1315 val = readl_relaxed(dtc->base + pmevcnt); 1316 writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt); 1317 return val - CMN_COUNTER_INIT; 1318 } 1319 1320 static void arm_cmn_init_counter(struct perf_event *event) 1321 { 1322 struct arm_cmn *cmn = to_cmn(event->pmu); 1323 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1324 unsigned int i, pmevcnt = CMN_DT_PMEVCNT(hw->dtc_idx); 1325 u64 count; 1326 1327 for (i = 0; hw->dtcs_used & (1U << i); i++) { 1328 writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + pmevcnt); 1329 cmn->dtc[i].counters[hw->dtc_idx] = event; 1330 } 1331 1332 count = arm_cmn_read_dtm(cmn, hw, false); 1333 local64_set(&event->hw.prev_count, count); 1334 } 1335 1336 static void arm_cmn_event_read(struct perf_event *event) 1337 { 1338 struct arm_cmn *cmn = to_cmn(event->pmu); 1339 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1340 u64 delta, new, prev; 1341 unsigned long flags; 1342 unsigned int i; 1343 1344 if (hw->dtc_idx == CMN_DT_NUM_COUNTERS) { 1345 i = __ffs(hw->dtcs_used); 1346 delta = arm_cmn_read_cc(cmn->dtc + i); 1347 local64_add(delta, &event->count); 1348 return; 1349 } 1350 new = arm_cmn_read_dtm(cmn, hw, false); 1351 prev = local64_xchg(&event->hw.prev_count, new); 1352 1353 delta = new - prev; 1354 1355 local_irq_save(flags); 1356 for (i = 0; hw->dtcs_used & (1U << i); i++) { 1357 new = arm_cmn_read_counter(cmn->dtc + i, hw->dtc_idx); 1358 delta += new << 16; 1359 } 1360 local_irq_restore(flags); 1361 local64_add(delta, &event->count); 1362 } 1363 1364 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn, 1365 enum cmn_filter_select fsel, u8 occupid) 1366 { 1367 u64 reg; 1368 1369 if (fsel == SEL_NONE) 1370 return 0; 1371 1372 if (!dn->occupid[fsel].count) { 1373 dn->occupid[fsel].val = occupid; 1374 reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL, 1375 dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) | 1376 FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID, 1377 dn->occupid[SEL_CLASS_OCCUP_ID].val) | 1378 FIELD_PREP(CMN__PMU_OCCUP1_ID, 1379 dn->occupid[SEL_OCCUP1ID].val); 1380 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4); 1381 } else if (dn->occupid[fsel].val != occupid) { 1382 return -EBUSY; 1383 } 1384 dn->occupid[fsel].count++; 1385 return 0; 1386 } 1387 1388 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx, 1389 int eventid, bool wide_sel) 1390 { 1391 if (wide_sel) { 1392 dn->event_w[dtm_idx] = eventid; 1393 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); 1394 } else { 1395 dn->event[dtm_idx] = eventid; 1396 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); 1397 } 1398 } 1399 1400 static void arm_cmn_event_start(struct perf_event *event, int flags) 1401 { 1402 struct arm_cmn *cmn = to_cmn(event->pmu); 1403 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1404 struct arm_cmn_node *dn; 1405 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1406 int i; 1407 1408 if (type == CMN_TYPE_DTC) { 1409 i = __ffs(hw->dtcs_used); 1410 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR); 1411 cmn->dtc[i].cc_active = true; 1412 } else if (type == CMN_TYPE_WP) { 1413 int wp_idx = arm_cmn_wp_idx(event); 1414 u64 val = CMN_EVENT_WP_VAL(event); 1415 u64 mask = CMN_EVENT_WP_MASK(event); 1416 1417 for_each_hw_dn(hw, dn, i) { 1418 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1419 1420 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); 1421 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); 1422 } 1423 } else for_each_hw_dn(hw, dn, i) { 1424 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1425 1426 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event), 1427 hw->wide_sel); 1428 } 1429 } 1430 1431 static void arm_cmn_event_stop(struct perf_event *event, int flags) 1432 { 1433 struct arm_cmn *cmn = to_cmn(event->pmu); 1434 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1435 struct arm_cmn_node *dn; 1436 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1437 int i; 1438 1439 if (type == CMN_TYPE_DTC) { 1440 i = __ffs(hw->dtcs_used); 1441 cmn->dtc[i].cc_active = false; 1442 } else if (type == CMN_TYPE_WP) { 1443 int wp_idx = arm_cmn_wp_idx(event); 1444 1445 for_each_hw_dn(hw, dn, i) { 1446 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1447 1448 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); 1449 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); 1450 } 1451 } else for_each_hw_dn(hw, dn, i) { 1452 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1453 1454 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel); 1455 } 1456 1457 arm_cmn_event_read(event); 1458 } 1459 1460 struct arm_cmn_val { 1461 u8 dtm_count[CMN_MAX_DTMS]; 1462 u8 occupid[CMN_MAX_DTMS][SEL_MAX]; 1463 u8 wp[CMN_MAX_DTMS][4]; 1464 int dtc_count; 1465 bool cycles; 1466 }; 1467 1468 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val, 1469 struct perf_event *event) 1470 { 1471 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1472 struct arm_cmn_node *dn; 1473 enum cmn_node_type type; 1474 int i; 1475 1476 if (is_software_event(event)) 1477 return; 1478 1479 type = CMN_EVENT_TYPE(event); 1480 if (type == CMN_TYPE_DTC) { 1481 val->cycles = true; 1482 return; 1483 } 1484 1485 val->dtc_count++; 1486 1487 for_each_hw_dn(hw, dn, i) { 1488 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel; 1489 1490 val->dtm_count[dtm]++; 1491 1492 if (sel > SEL_NONE) 1493 val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1; 1494 1495 if (type != CMN_TYPE_WP) 1496 continue; 1497 1498 wp_idx = arm_cmn_wp_idx(event); 1499 val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1; 1500 } 1501 } 1502 1503 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event) 1504 { 1505 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1506 struct arm_cmn_node *dn; 1507 struct perf_event *sibling, *leader = event->group_leader; 1508 enum cmn_node_type type; 1509 struct arm_cmn_val *val; 1510 int i, ret = -EINVAL; 1511 1512 if (leader == event) 1513 return 0; 1514 1515 if (event->pmu != leader->pmu && !is_software_event(leader)) 1516 return -EINVAL; 1517 1518 val = kzalloc(sizeof(*val), GFP_KERNEL); 1519 if (!val) 1520 return -ENOMEM; 1521 1522 arm_cmn_val_add_event(cmn, val, leader); 1523 for_each_sibling_event(sibling, leader) 1524 arm_cmn_val_add_event(cmn, val, sibling); 1525 1526 type = CMN_EVENT_TYPE(event); 1527 if (type == CMN_TYPE_DTC) { 1528 ret = val->cycles ? -EINVAL : 0; 1529 goto done; 1530 } 1531 1532 if (val->dtc_count == CMN_DT_NUM_COUNTERS) 1533 goto done; 1534 1535 for_each_hw_dn(hw, dn, i) { 1536 int wp_idx, wp_cmb, dtm = dn->dtm, sel = hw->filter_sel; 1537 1538 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS) 1539 goto done; 1540 1541 if (sel > SEL_NONE && val->occupid[dtm][sel] && 1542 val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1) 1543 goto done; 1544 1545 if (type != CMN_TYPE_WP) 1546 continue; 1547 1548 wp_idx = arm_cmn_wp_idx(event); 1549 if (val->wp[dtm][wp_idx]) 1550 goto done; 1551 1552 wp_cmb = val->wp[dtm][wp_idx ^ 1]; 1553 if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1) 1554 goto done; 1555 } 1556 1557 ret = 0; 1558 done: 1559 kfree(val); 1560 return ret; 1561 } 1562 1563 static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn, 1564 enum cmn_node_type type, 1565 unsigned int eventid) 1566 { 1567 struct arm_cmn_event_attr *e; 1568 enum cmn_model model = arm_cmn_model(cmn); 1569 1570 for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) { 1571 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr); 1572 if (e->model & model && e->type == type && e->eventid == eventid) 1573 return e->fsel; 1574 } 1575 return SEL_NONE; 1576 } 1577 1578 1579 static int arm_cmn_event_init(struct perf_event *event) 1580 { 1581 struct arm_cmn *cmn = to_cmn(event->pmu); 1582 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1583 struct arm_cmn_node *dn; 1584 enum cmn_node_type type; 1585 bool bynodeid; 1586 u16 nodeid, eventid; 1587 1588 if (event->attr.type != event->pmu->type) 1589 return -ENOENT; 1590 1591 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 1592 return -EINVAL; 1593 1594 event->cpu = cmn->cpu; 1595 if (event->cpu < 0) 1596 return -EINVAL; 1597 1598 type = CMN_EVENT_TYPE(event); 1599 /* DTC events (i.e. cycles) already have everything they need */ 1600 if (type == CMN_TYPE_DTC) 1601 return arm_cmn_validate_group(cmn, event); 1602 1603 eventid = CMN_EVENT_EVENTID(event); 1604 /* For watchpoints we need the actual XP node here */ 1605 if (type == CMN_TYPE_WP) { 1606 type = CMN_TYPE_XP; 1607 /* ...and we need a "real" direction */ 1608 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN) 1609 return -EINVAL; 1610 /* ...but the DTM may depend on which port we're watching */ 1611 if (cmn->multi_dtm) 1612 hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2; 1613 } else if (type == CMN_TYPE_XP && cmn->part == PART_CMN700) { 1614 hw->wide_sel = true; 1615 } 1616 1617 /* This is sufficiently annoying to recalculate, so cache it */ 1618 hw->filter_sel = arm_cmn_filter_sel(cmn, type, eventid); 1619 1620 bynodeid = CMN_EVENT_BYNODEID(event); 1621 nodeid = CMN_EVENT_NODEID(event); 1622 1623 hw->dn = arm_cmn_node(cmn, type); 1624 if (!hw->dn) 1625 return -EINVAL; 1626 for (dn = hw->dn; dn->type == type; dn++) { 1627 if (bynodeid && dn->id != nodeid) { 1628 hw->dn++; 1629 continue; 1630 } 1631 hw->num_dns++; 1632 if (bynodeid) 1633 break; 1634 } 1635 1636 if (!hw->num_dns) { 1637 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, nodeid); 1638 1639 dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n", 1640 nodeid, nid.x, nid.y, nid.port, nid.dev, type); 1641 return -EINVAL; 1642 } 1643 /* 1644 * Keep assuming non-cycles events count in all DTC domains; turns out 1645 * it's hard to make a worthwhile optimisation around this, short of 1646 * going all-in with domain-local counter allocation as well. 1647 */ 1648 hw->dtcs_used = (1U << cmn->num_dtcs) - 1; 1649 1650 return arm_cmn_validate_group(cmn, event); 1651 } 1652 1653 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, 1654 int i) 1655 { 1656 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1657 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1658 1659 while (i--) { 1660 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset; 1661 unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1662 1663 if (type == CMN_TYPE_WP) 1664 dtm->wp_event[arm_cmn_wp_idx(event)] = -1; 1665 1666 if (hw->filter_sel > SEL_NONE) 1667 hw->dn[i].occupid[hw->filter_sel].count--; 1668 1669 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); 1670 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 1671 } 1672 memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx)); 1673 1674 for (i = 0; hw->dtcs_used & (1U << i); i++) 1675 cmn->dtc[i].counters[hw->dtc_idx] = NULL; 1676 } 1677 1678 static int arm_cmn_event_add(struct perf_event *event, int flags) 1679 { 1680 struct arm_cmn *cmn = to_cmn(event->pmu); 1681 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1682 struct arm_cmn_dtc *dtc = &cmn->dtc[0]; 1683 struct arm_cmn_node *dn; 1684 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1685 unsigned int i, dtc_idx, input_sel; 1686 1687 if (type == CMN_TYPE_DTC) { 1688 i = 0; 1689 while (cmn->dtc[i].cycles) 1690 if (++i == cmn->num_dtcs) 1691 return -ENOSPC; 1692 1693 cmn->dtc[i].cycles = event; 1694 hw->dtc_idx = CMN_DT_NUM_COUNTERS; 1695 hw->dtcs_used = 1U << i; 1696 1697 if (flags & PERF_EF_START) 1698 arm_cmn_event_start(event, 0); 1699 return 0; 1700 } 1701 1702 /* Grab a free global counter first... */ 1703 dtc_idx = 0; 1704 while (dtc->counters[dtc_idx]) 1705 if (++dtc_idx == CMN_DT_NUM_COUNTERS) 1706 return -ENOSPC; 1707 1708 hw->dtc_idx = dtc_idx; 1709 1710 /* ...then the local counters to feed it. */ 1711 for_each_hw_dn(hw, dn, i) { 1712 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1713 unsigned int dtm_idx, shift; 1714 u64 reg; 1715 1716 dtm_idx = 0; 1717 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx)) 1718 if (++dtm_idx == CMN_DTM_NUM_COUNTERS) 1719 goto free_dtms; 1720 1721 if (type == CMN_TYPE_XP) { 1722 input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx; 1723 } else if (type == CMN_TYPE_WP) { 1724 int tmp, wp_idx = arm_cmn_wp_idx(event); 1725 u32 cfg = arm_cmn_wp_config(event); 1726 1727 if (dtm->wp_event[wp_idx] >= 0) 1728 goto free_dtms; 1729 1730 tmp = dtm->wp_event[wp_idx ^ 1]; 1731 if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) != 1732 CMN_EVENT_WP_COMBINE(dtc->counters[tmp])) 1733 goto free_dtms; 1734 1735 input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx; 1736 dtm->wp_event[wp_idx] = dtc_idx; 1737 writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx)); 1738 } else { 1739 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id); 1740 1741 if (cmn->multi_dtm) 1742 nid.port %= 2; 1743 1744 input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx + 1745 (nid.port << 4) + (nid.dev << 2); 1746 1747 if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event))) 1748 goto free_dtms; 1749 } 1750 1751 arm_cmn_set_index(hw->dtm_idx, i, dtm_idx); 1752 1753 dtm->input_sel[dtm_idx] = input_sel; 1754 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx); 1755 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift); 1756 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift; 1757 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx); 1758 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low; 1759 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); 1760 } 1761 1762 /* Go go go! */ 1763 arm_cmn_init_counter(event); 1764 1765 if (flags & PERF_EF_START) 1766 arm_cmn_event_start(event, 0); 1767 1768 return 0; 1769 1770 free_dtms: 1771 arm_cmn_event_clear(cmn, event, i); 1772 return -ENOSPC; 1773 } 1774 1775 static void arm_cmn_event_del(struct perf_event *event, int flags) 1776 { 1777 struct arm_cmn *cmn = to_cmn(event->pmu); 1778 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1779 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1780 1781 arm_cmn_event_stop(event, PERF_EF_UPDATE); 1782 1783 if (type == CMN_TYPE_DTC) 1784 cmn->dtc[__ffs(hw->dtcs_used)].cycles = NULL; 1785 else 1786 arm_cmn_event_clear(cmn, event, hw->num_dns); 1787 } 1788 1789 /* 1790 * We stop the PMU for both add and read, to avoid skew across DTM counters. 1791 * In theory we could use snapshots to read without stopping, but then it 1792 * becomes a lot trickier to deal with overlow and racing against interrupts, 1793 * plus it seems they don't work properly on some hardware anyway :( 1794 */ 1795 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags) 1796 { 1797 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN); 1798 } 1799 1800 static void arm_cmn_end_txn(struct pmu *pmu) 1801 { 1802 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN); 1803 } 1804 1805 static int arm_cmn_commit_txn(struct pmu *pmu) 1806 { 1807 arm_cmn_end_txn(pmu); 1808 return 0; 1809 } 1810 1811 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu) 1812 { 1813 unsigned int i; 1814 1815 perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu); 1816 for (i = 0; i < cmn->num_dtcs; i++) 1817 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu)); 1818 cmn->cpu = cpu; 1819 } 1820 1821 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 1822 { 1823 struct arm_cmn *cmn; 1824 int node; 1825 1826 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 1827 node = dev_to_node(cmn->dev); 1828 if (node != NUMA_NO_NODE && cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node) 1829 arm_cmn_migrate(cmn, cpu); 1830 return 0; 1831 } 1832 1833 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 1834 { 1835 struct arm_cmn *cmn; 1836 unsigned int target; 1837 int node; 1838 cpumask_t mask; 1839 1840 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 1841 if (cpu != cmn->cpu) 1842 return 0; 1843 1844 node = dev_to_node(cmn->dev); 1845 if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) && 1846 cpumask_andnot(&mask, &mask, cpumask_of(cpu))) 1847 target = cpumask_any(&mask); 1848 else 1849 target = cpumask_any_but(cpu_online_mask, cpu); 1850 if (target < nr_cpu_ids) 1851 arm_cmn_migrate(cmn, target); 1852 return 0; 1853 } 1854 1855 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id) 1856 { 1857 struct arm_cmn_dtc *dtc = dev_id; 1858 irqreturn_t ret = IRQ_NONE; 1859 1860 for (;;) { 1861 u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR); 1862 u64 delta; 1863 int i; 1864 1865 for (i = 0; i < CMN_DTM_NUM_COUNTERS; i++) { 1866 if (status & (1U << i)) { 1867 ret = IRQ_HANDLED; 1868 if (WARN_ON(!dtc->counters[i])) 1869 continue; 1870 delta = (u64)arm_cmn_read_counter(dtc, i) << 16; 1871 local64_add(delta, &dtc->counters[i]->count); 1872 } 1873 } 1874 1875 if (status & (1U << CMN_DT_NUM_COUNTERS)) { 1876 ret = IRQ_HANDLED; 1877 if (dtc->cc_active && !WARN_ON(!dtc->cycles)) { 1878 delta = arm_cmn_read_cc(dtc); 1879 local64_add(delta, &dtc->cycles->count); 1880 } 1881 } 1882 1883 writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR); 1884 1885 if (!dtc->irq_friend) 1886 return ret; 1887 dtc += dtc->irq_friend; 1888 } 1889 } 1890 1891 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */ 1892 static int arm_cmn_init_irqs(struct arm_cmn *cmn) 1893 { 1894 int i, j, irq, err; 1895 1896 for (i = 0; i < cmn->num_dtcs; i++) { 1897 irq = cmn->dtc[i].irq; 1898 for (j = i; j--; ) { 1899 if (cmn->dtc[j].irq == irq) { 1900 cmn->dtc[j].irq_friend = i - j; 1901 goto next; 1902 } 1903 } 1904 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq, 1905 IRQF_NOBALANCING | IRQF_NO_THREAD, 1906 dev_name(cmn->dev), &cmn->dtc[i]); 1907 if (err) 1908 return err; 1909 1910 err = irq_set_affinity(irq, cpumask_of(cmn->cpu)); 1911 if (err) 1912 return err; 1913 next: 1914 ; /* isn't C great? */ 1915 } 1916 return 0; 1917 } 1918 1919 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx) 1920 { 1921 int i; 1922 1923 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx); 1924 dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; 1925 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 1926 for (i = 0; i < 4; i++) { 1927 dtm->wp_event[i] = -1; 1928 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i)); 1929 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i)); 1930 } 1931 } 1932 1933 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx) 1934 { 1935 struct arm_cmn_dtc *dtc = cmn->dtc + idx; 1936 1937 dtc->base = dn->pmu_base - CMN_PMU_OFFSET; 1938 dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx); 1939 if (dtc->irq < 0) 1940 return dtc->irq; 1941 1942 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); 1943 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR); 1944 writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR); 1945 writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR); 1946 1947 return 0; 1948 } 1949 1950 static int arm_cmn_node_cmp(const void *a, const void *b) 1951 { 1952 const struct arm_cmn_node *dna = a, *dnb = b; 1953 int cmp; 1954 1955 cmp = dna->type - dnb->type; 1956 if (!cmp) 1957 cmp = dna->logid - dnb->logid; 1958 return cmp; 1959 } 1960 1961 static int arm_cmn_init_dtcs(struct arm_cmn *cmn) 1962 { 1963 struct arm_cmn_node *dn, *xp; 1964 int dtc_idx = 0; 1965 u8 dtcs_present = (1 << cmn->num_dtcs) - 1; 1966 1967 cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL); 1968 if (!cmn->dtc) 1969 return -ENOMEM; 1970 1971 sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL); 1972 1973 cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP); 1974 1975 for (dn = cmn->dns; dn->type; dn++) { 1976 if (dn->type == CMN_TYPE_XP) { 1977 dn->dtc &= dtcs_present; 1978 continue; 1979 } 1980 1981 xp = arm_cmn_node_to_xp(cmn, dn); 1982 dn->dtm = xp->dtm; 1983 if (cmn->multi_dtm) 1984 dn->dtm += arm_cmn_nid(cmn, dn->id).port / 2; 1985 1986 if (dn->type == CMN_TYPE_DTC) { 1987 int err; 1988 /* We do at least know that a DTC's XP must be in that DTC's domain */ 1989 if (xp->dtc == 0xf) 1990 xp->dtc = 1 << dtc_idx; 1991 err = arm_cmn_init_dtc(cmn, dn, dtc_idx++); 1992 if (err) 1993 return err; 1994 } 1995 1996 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */ 1997 if (dn->type == CMN_TYPE_RND) 1998 dn->type = CMN_TYPE_RNI; 1999 2000 /* We split the RN-I off already, so let the CCLA part match CCLA events */ 2001 if (dn->type == CMN_TYPE_CCLA_RNI) 2002 dn->type = CMN_TYPE_CCLA; 2003 } 2004 2005 arm_cmn_set_state(cmn, CMN_STATE_DISABLED); 2006 2007 return 0; 2008 } 2009 2010 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node) 2011 { 2012 int level; 2013 u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO); 2014 2015 node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg); 2016 node->id = FIELD_GET(CMN_NI_NODE_ID, reg); 2017 node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg); 2018 2019 node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET; 2020 2021 if (node->type == CMN_TYPE_CFG) 2022 level = 0; 2023 else if (node->type == CMN_TYPE_XP) 2024 level = 1; 2025 else 2026 level = 2; 2027 2028 dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n", 2029 (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ', 2030 node->type, node->logid, offset); 2031 } 2032 2033 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type) 2034 { 2035 switch (type) { 2036 case CMN_TYPE_HNP: 2037 return CMN_TYPE_HNI; 2038 case CMN_TYPE_CCLA_RNI: 2039 return CMN_TYPE_RNI; 2040 default: 2041 return CMN_TYPE_INVALID; 2042 } 2043 } 2044 2045 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) 2046 { 2047 void __iomem *cfg_region; 2048 struct arm_cmn_node cfg, *dn; 2049 struct arm_cmn_dtm *dtm; 2050 enum cmn_part part; 2051 u16 child_count, child_poff; 2052 u32 xp_offset[CMN_MAX_XPS]; 2053 u64 reg; 2054 int i, j; 2055 size_t sz; 2056 2057 arm_cmn_init_node_info(cmn, rgn_offset, &cfg); 2058 if (cfg.type != CMN_TYPE_CFG) 2059 return -ENODEV; 2060 2061 cfg_region = cmn->base + rgn_offset; 2062 2063 reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01); 2064 part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg); 2065 part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8; 2066 if (cmn->part && cmn->part != part) 2067 dev_warn(cmn->dev, 2068 "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n", 2069 cmn->part, part); 2070 cmn->part = part; 2071 if (!arm_cmn_model(cmn)) 2072 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part); 2073 2074 reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23); 2075 cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); 2076 2077 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL); 2078 cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN; 2079 cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg); 2080 cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg); 2081 2082 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1); 2083 cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg); 2084 cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg); 2085 2086 reg = readq_relaxed(cfg_region + CMN_CHILD_INFO); 2087 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2088 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2089 2090 cmn->num_xps = child_count; 2091 cmn->num_dns = cmn->num_xps; 2092 2093 /* Pass 1: visit the XPs, enumerate their children */ 2094 for (i = 0; i < cmn->num_xps; i++) { 2095 reg = readq_relaxed(cfg_region + child_poff + i * 8); 2096 xp_offset[i] = reg & CMN_CHILD_NODE_ADDR; 2097 2098 reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO); 2099 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2100 } 2101 2102 /* 2103 * Some nodes effectively have two separate types, which we'll handle 2104 * by creating one of each internally. For a (very) safe initial upper 2105 * bound, account for double the number of non-XP nodes. 2106 */ 2107 dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps, 2108 sizeof(*dn), GFP_KERNEL); 2109 if (!dn) 2110 return -ENOMEM; 2111 2112 /* Initial safe upper bound on DTMs for any possible mesh layout */ 2113 i = cmn->num_xps; 2114 if (cmn->multi_dtm) 2115 i += cmn->num_xps + 1; 2116 dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL); 2117 if (!dtm) 2118 return -ENOMEM; 2119 2120 /* Pass 2: now we can actually populate the nodes */ 2121 cmn->dns = dn; 2122 cmn->dtms = dtm; 2123 for (i = 0; i < cmn->num_xps; i++) { 2124 void __iomem *xp_region = cmn->base + xp_offset[i]; 2125 struct arm_cmn_node *xp = dn++; 2126 unsigned int xp_ports = 0; 2127 2128 arm_cmn_init_node_info(cmn, xp_offset[i], xp); 2129 /* 2130 * Thanks to the order in which XP logical IDs seem to be 2131 * assigned, we can handily infer the mesh X dimension by 2132 * looking out for the XP at (0,1) without needing to know 2133 * the exact node ID format, which we can later derive. 2134 */ 2135 if (xp->id == (1 << 3)) 2136 cmn->mesh_x = xp->logid; 2137 2138 if (cmn->part == PART_CMN600) 2139 xp->dtc = 0xf; 2140 else 2141 xp->dtc = 1 << readl_relaxed(xp_region + CMN_DTM_UNIT_INFO); 2142 2143 xp->dtm = dtm - cmn->dtms; 2144 arm_cmn_init_dtm(dtm++, xp, 0); 2145 /* 2146 * Keeping track of connected ports will let us filter out 2147 * unnecessary XP events easily. We can also reliably infer the 2148 * "extra device ports" configuration for the node ID format 2149 * from this, since in that case we will see at least one XP 2150 * with port 2 connected, for the HN-D. 2151 */ 2152 for (int p = 0; p < CMN_MAX_PORTS; p++) 2153 if (arm_cmn_device_connect_info(cmn, xp, p)) 2154 xp_ports |= BIT(p); 2155 2156 if (cmn->multi_dtm && (xp_ports & 0xc)) 2157 arm_cmn_init_dtm(dtm++, xp, 1); 2158 if (cmn->multi_dtm && (xp_ports & 0x30)) 2159 arm_cmn_init_dtm(dtm++, xp, 2); 2160 2161 cmn->ports_used |= xp_ports; 2162 2163 reg = readq_relaxed(xp_region + CMN_CHILD_INFO); 2164 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2165 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2166 2167 for (j = 0; j < child_count; j++) { 2168 reg = readq_relaxed(xp_region + child_poff + j * 8); 2169 /* 2170 * Don't even try to touch anything external, since in general 2171 * we haven't a clue how to power up arbitrary CHI requesters. 2172 * As of CMN-600r1 these could only be RN-SAMs or CXLAs, 2173 * neither of which have any PMU events anyway. 2174 * (Actually, CXLAs do seem to have grown some events in r1p2, 2175 * but they don't go to regular XP DTMs, and they depend on 2176 * secure configuration which we can't easily deal with) 2177 */ 2178 if (reg & CMN_CHILD_NODE_EXTERNAL) { 2179 dev_dbg(cmn->dev, "ignoring external node %llx\n", reg); 2180 continue; 2181 } 2182 2183 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn); 2184 2185 switch (dn->type) { 2186 case CMN_TYPE_DTC: 2187 cmn->num_dtcs++; 2188 dn++; 2189 break; 2190 /* These guys have PMU events */ 2191 case CMN_TYPE_DVM: 2192 case CMN_TYPE_HNI: 2193 case CMN_TYPE_HNF: 2194 case CMN_TYPE_SBSX: 2195 case CMN_TYPE_RNI: 2196 case CMN_TYPE_RND: 2197 case CMN_TYPE_MTSX: 2198 case CMN_TYPE_CXRA: 2199 case CMN_TYPE_CXHA: 2200 case CMN_TYPE_CCRA: 2201 case CMN_TYPE_CCHA: 2202 case CMN_TYPE_CCLA: 2203 dn++; 2204 break; 2205 /* Nothing to see here */ 2206 case CMN_TYPE_MPAM_S: 2207 case CMN_TYPE_MPAM_NS: 2208 case CMN_TYPE_RNSAM: 2209 case CMN_TYPE_CXLA: 2210 break; 2211 /* 2212 * Split "optimised" combination nodes into separate 2213 * types for the different event sets. Offsetting the 2214 * base address lets us handle the second pmu_event_sel 2215 * register via the normal mechanism later. 2216 */ 2217 case CMN_TYPE_HNP: 2218 case CMN_TYPE_CCLA_RNI: 2219 dn[1] = dn[0]; 2220 dn[0].pmu_base += CMN_HNP_PMU_EVENT_SEL; 2221 dn[1].type = arm_cmn_subtype(dn->type); 2222 dn += 2; 2223 break; 2224 /* Something has gone horribly wrong */ 2225 default: 2226 dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type); 2227 return -ENODEV; 2228 } 2229 } 2230 } 2231 2232 /* Correct for any nodes we added or skipped */ 2233 cmn->num_dns = dn - cmn->dns; 2234 2235 /* Cheeky +1 to help terminate pointer-based iteration later */ 2236 sz = (void *)(dn + 1) - (void *)cmn->dns; 2237 dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL); 2238 if (dn) 2239 cmn->dns = dn; 2240 2241 sz = (void *)dtm - (void *)cmn->dtms; 2242 dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL); 2243 if (dtm) 2244 cmn->dtms = dtm; 2245 2246 /* 2247 * If mesh_x wasn't set during discovery then we never saw 2248 * an XP at (0,1), thus we must have an Nx1 configuration. 2249 */ 2250 if (!cmn->mesh_x) 2251 cmn->mesh_x = cmn->num_xps; 2252 cmn->mesh_y = cmn->num_xps / cmn->mesh_x; 2253 2254 /* 1x1 config plays havoc with XP event encodings */ 2255 if (cmn->num_xps == 1) 2256 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n"); 2257 2258 dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev); 2259 reg = cmn->ports_used; 2260 dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n", 2261 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), ®, 2262 cmn->multi_dtm ? ", multi-DTM" : ""); 2263 2264 return 0; 2265 } 2266 2267 static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn) 2268 { 2269 struct resource *cfg, *root; 2270 2271 cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2272 if (!cfg) 2273 return -EINVAL; 2274 2275 root = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2276 if (!root) 2277 return -EINVAL; 2278 2279 if (!resource_contains(cfg, root)) 2280 swap(cfg, root); 2281 /* 2282 * Note that devm_ioremap_resource() is dumb and won't let the platform 2283 * device claim cfg when the ACPI companion device has already claimed 2284 * root within it. But since they *are* already both claimed in the 2285 * appropriate name, we don't really need to do it again here anyway. 2286 */ 2287 cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg)); 2288 if (!cmn->base) 2289 return -ENOMEM; 2290 2291 return root->start - cfg->start; 2292 } 2293 2294 static int arm_cmn600_of_probe(struct device_node *np) 2295 { 2296 u32 rootnode; 2297 2298 return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode; 2299 } 2300 2301 static int arm_cmn_probe(struct platform_device *pdev) 2302 { 2303 struct arm_cmn *cmn; 2304 const char *name; 2305 static atomic_t id; 2306 int err, rootnode, this_id; 2307 2308 cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); 2309 if (!cmn) 2310 return -ENOMEM; 2311 2312 cmn->dev = &pdev->dev; 2313 cmn->part = (unsigned long)device_get_match_data(cmn->dev); 2314 platform_set_drvdata(pdev, cmn); 2315 2316 if (cmn->part == PART_CMN600 && has_acpi_companion(cmn->dev)) { 2317 rootnode = arm_cmn600_acpi_probe(pdev, cmn); 2318 } else { 2319 rootnode = 0; 2320 cmn->base = devm_platform_ioremap_resource(pdev, 0); 2321 if (IS_ERR(cmn->base)) 2322 return PTR_ERR(cmn->base); 2323 if (cmn->part == PART_CMN600) 2324 rootnode = arm_cmn600_of_probe(pdev->dev.of_node); 2325 } 2326 if (rootnode < 0) 2327 return rootnode; 2328 2329 err = arm_cmn_discover(cmn, rootnode); 2330 if (err) 2331 return err; 2332 2333 err = arm_cmn_init_dtcs(cmn); 2334 if (err) 2335 return err; 2336 2337 err = arm_cmn_init_irqs(cmn); 2338 if (err) 2339 return err; 2340 2341 cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev)); 2342 cmn->pmu = (struct pmu) { 2343 .module = THIS_MODULE, 2344 .attr_groups = arm_cmn_attr_groups, 2345 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 2346 .task_ctx_nr = perf_invalid_context, 2347 .pmu_enable = arm_cmn_pmu_enable, 2348 .pmu_disable = arm_cmn_pmu_disable, 2349 .event_init = arm_cmn_event_init, 2350 .add = arm_cmn_event_add, 2351 .del = arm_cmn_event_del, 2352 .start = arm_cmn_event_start, 2353 .stop = arm_cmn_event_stop, 2354 .read = arm_cmn_event_read, 2355 .start_txn = arm_cmn_start_txn, 2356 .commit_txn = arm_cmn_commit_txn, 2357 .cancel_txn = arm_cmn_end_txn, 2358 }; 2359 2360 this_id = atomic_fetch_inc(&id); 2361 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id); 2362 if (!name) 2363 return -ENOMEM; 2364 2365 err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node); 2366 if (err) 2367 return err; 2368 2369 err = perf_pmu_register(&cmn->pmu, name, -1); 2370 if (err) 2371 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2372 else 2373 arm_cmn_debugfs_init(cmn, this_id); 2374 2375 return err; 2376 } 2377 2378 static int arm_cmn_remove(struct platform_device *pdev) 2379 { 2380 struct arm_cmn *cmn = platform_get_drvdata(pdev); 2381 2382 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL); 2383 2384 perf_pmu_unregister(&cmn->pmu); 2385 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2386 debugfs_remove(cmn->debug); 2387 return 0; 2388 } 2389 2390 #ifdef CONFIG_OF 2391 static const struct of_device_id arm_cmn_of_match[] = { 2392 { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 }, 2393 { .compatible = "arm,cmn-650" }, 2394 { .compatible = "arm,cmn-700" }, 2395 { .compatible = "arm,ci-700" }, 2396 {} 2397 }; 2398 MODULE_DEVICE_TABLE(of, arm_cmn_of_match); 2399 #endif 2400 2401 #ifdef CONFIG_ACPI 2402 static const struct acpi_device_id arm_cmn_acpi_match[] = { 2403 { "ARMHC600", PART_CMN600 }, 2404 { "ARMHC650" }, 2405 { "ARMHC700" }, 2406 {} 2407 }; 2408 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match); 2409 #endif 2410 2411 static struct platform_driver arm_cmn_driver = { 2412 .driver = { 2413 .name = "arm-cmn", 2414 .of_match_table = of_match_ptr(arm_cmn_of_match), 2415 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match), 2416 }, 2417 .probe = arm_cmn_probe, 2418 .remove = arm_cmn_remove, 2419 }; 2420 2421 static int __init arm_cmn_init(void) 2422 { 2423 int ret; 2424 2425 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 2426 "perf/arm/cmn:online", 2427 arm_cmn_pmu_online_cpu, 2428 arm_cmn_pmu_offline_cpu); 2429 if (ret < 0) 2430 return ret; 2431 2432 arm_cmn_hp_state = ret; 2433 arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL); 2434 2435 ret = platform_driver_register(&arm_cmn_driver); 2436 if (ret) { 2437 cpuhp_remove_multi_state(arm_cmn_hp_state); 2438 debugfs_remove(arm_cmn_debugfs); 2439 } 2440 return ret; 2441 } 2442 2443 static void __exit arm_cmn_exit(void) 2444 { 2445 platform_driver_unregister(&arm_cmn_driver); 2446 cpuhp_remove_multi_state(arm_cmn_hp_state); 2447 debugfs_remove(arm_cmn_debugfs); 2448 } 2449 2450 module_init(arm_cmn_init); 2451 module_exit(arm_cmn_exit); 2452 2453 MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>"); 2454 MODULE_DESCRIPTION("Arm CMN-600 PMU driver"); 2455 MODULE_LICENSE("GPL v2"); 2456