1b2441318SGreg Kroah-Hartman# SPDX-License-Identifier: GPL-2.0 23de6be7aSRobin Murphyobj-$(CONFIG_ARM_CCI_PMU) += arm-cci.o 31888d3ddSRobin Murphyobj-$(CONFIG_ARM_CCN) += arm-ccn.o 40ba64770SRobin Murphyobj-$(CONFIG_ARM_CMN) += arm-cmn.o 57520fa99SSuzuki K Pouloseobj-$(CONFIG_ARM_DSU_PMU) += arm_dsu_pmu.o 6*4d5a7680SRobin Murphyobj-$(CONFIG_ARM_NI) += arm-ni.o 718bfcfe5SMark Rutlandobj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o 845736a72SMark Rutlandobj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o 97755cec6SMarc Zyngierobj-$(CONFIG_ARM_PMUV3) += arm_pmuv3.o 108d75537bSRob Herring (Arm)obj-$(CONFIG_ARM_V6_PMU) += arm_v6_pmu.o 118d75537bSRob Herring (Arm)obj-$(CONFIG_ARM_V7_PMU) += arm_v7_pmu.o 128d75537bSRob Herring (Arm)obj-$(CONFIG_ARM_XSCALE_PMU) += arm_xscale_pmu.o 137d839b4bSNeil Leederobj-$(CONFIG_ARM_SMMU_V3_PMU) += arm_smmuv3_pmu.o 149a66d36cSFrank Liobj-$(CONFIG_FSL_IMX8_DDR_PMU) += fsl_imx8_ddr_perf.o 1555691f99SXu Yangobj-$(CONFIG_FSL_IMX9_DDR_PMU) += fsl_imx9_ddr_perf.o 166ce4ef94SShaokun Zhangobj-$(CONFIG_HISI_PMU) += hisilicon/ 1721bdbb71SNeil Leederobj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o 183071f13dSAgustin Vega-Friasobj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o 19f5bfa23fSAtish Patraobj-$(CONFIG_RISCV_PMU) += riscv_pmu.o 209b3e150eSAtish Patraobj-$(CONFIG_RISCV_PMU_LEGACY) += riscv_pmu_legacy.o 21e9991434SAtish Patraobj-$(CONFIG_RISCV_PMU_SBI) += riscv_pmu_sbi.o 22c2b24812SJi Sheng Teohobj-$(CONFIG_STARFIVE_STARLINK_PMU) += starfive_starlink_pmu.o 2369c32972SKulkarni, Ganapatraoobj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o 24832c927dSTai Nguyenobj-$(CONFIG_XGENE_PMU) += xgene_pmu.o 25d5d9696bSWill Deaconobj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o 2653c218daSTuan Phanobj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o 27036a7584SBhaskara Budiredlaobj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o 287cf83e22SBharat Bhushanobj-$(CONFIG_MARVELL_CN10K_DDR_PMU) += marvell_cn10k_ddr_pmu.o 29a639027aSMarc Zyngierobj-$(CONFIG_MARVELL_PEM_PMU) += marvell_pem_pmu.o 30cf7b6107SShuai Xueobj-$(CONFIG_APPLE_M1_CPU_PMU) += apple_m1_cpu_pmu.o 31af9597adSShuai Xueobj-$(CONFIG_ALIBABA_UNCORE_DRW_PMU) += alibaba_uncore_drw_pmu.o 32e37dfd65SBesar Wicaksonoobj-$(CONFIG_DWC_PCIE_PMU) += dwc_pcie_pmu.o 332016e211SJiucheng Xuobj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += arm_cspmu/ 345d7107c7SJonathan Cameronobj-$(CONFIG_MESON_DDR_PMU) += amlogic/ 35obj-$(CONFIG_CXL_PMU) += cxl_pmu.o 36