1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Performance Monitor Drivers 4# 5 6menu "Performance monitor support" 7 depends on PERF_EVENTS 8 9config ARM_CCI_PMU 10 tristate "ARM CCI PMU driver" 11 depends on (ARM && CPU_V7) || ARM64 12 select ARM_CCI 13 help 14 Support for PMU events monitoring on the ARM CCI (Cache Coherent 15 Interconnect) family of products. 16 17 If compiled as a module, it will be called arm-cci. 18 19config ARM_CCI400_PMU 20 bool "support CCI-400" 21 default y 22 depends on ARM_CCI_PMU 23 select ARM_CCI400_COMMON 24 help 25 CCI-400 provides 4 independent event counters counting events related 26 to the connected slave/master interfaces, plus a cycle counter. 27 28config ARM_CCI5xx_PMU 29 bool "support CCI-500/CCI-550" 30 default y 31 depends on ARM_CCI_PMU 32 help 33 CCI-500/CCI-550 both provide 8 independent event counters, which can 34 count events pertaining to the slave/master interfaces as well as the 35 internal events to the CCI. 36 37config ARM_CCN 38 tristate "ARM CCN driver support" 39 depends on ARM || ARM64 || COMPILE_TEST 40 help 41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 42 interconnect. 43 44config ARM_CMN 45 tristate "Arm CMN-600 PMU support" 46 depends on ARM64 || COMPILE_TEST 47 help 48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 49 Network interconnect. 50 51config ARM_PMU 52 depends on ARM || ARM64 53 bool "ARM PMU framework" 54 default y 55 help 56 Say y if you want to use CPU performance monitors on ARM-based 57 systems. 58 59config RISCV_PMU 60 depends on RISCV 61 bool "RISC-V PMU framework" 62 default y 63 help 64 Say y if you want to use CPU performance monitors on RISCV-based 65 systems. This provides the core PMU framework that abstracts common 66 PMU functionalities in a core library so that different PMU drivers 67 can reuse it. 68 69config RISCV_PMU_LEGACY 70 depends on RISCV_PMU 71 bool "RISC-V legacy PMU implementation" 72 default y 73 help 74 Say y if you want to use the legacy CPU performance monitor 75 implementation on RISC-V based systems. This only allows counting 76 of cycle/instruction counter and doesn't support counter overflow, 77 or programmable counters. It will be removed in future. 78 79config RISCV_PMU_SBI 80 depends on RISCV_PMU && RISCV_SBI 81 bool "RISC-V PMU based on SBI PMU extension" 82 default y 83 help 84 Say y if you want to use the CPU performance monitor 85 using SBI PMU extension on RISC-V based systems. This option provides 86 full perf feature support i.e. counter overflow, privilege mode 87 filtering, counter configuration. 88 89config STARFIVE_STARLINK_PMU 90 depends on ARCH_STARFIVE || (COMPILE_TEST && 64BIT) 91 bool "StarFive StarLink PMU" 92 help 93 Provide support for StarLink Performance Monitor Unit. 94 StarLink Performance Monitor Unit integrates one or more cores with 95 an L3 memory system. The L3 cache events are added into perf event 96 subsystem, allowing monitoring of various L3 cache perf events. 97 98config ARM_PMU_ACPI 99 depends on ARM_PMU && ACPI 100 def_bool y 101 102config ARM_SMMU_V3_PMU 103 tristate "ARM SMMUv3 Performance Monitors Extension" 104 depends on ARM64 || (COMPILE_TEST && 64BIT) 105 depends on GENERIC_MSI_IRQ 106 help 107 Provides support for the ARM SMMUv3 Performance Monitor Counter 108 Groups (PMCG), which provide monitoring of transactions passing 109 through the SMMU and allow the resulting information to be filtered 110 based on the Stream ID of the corresponding master. 111 112config ARM_PMUV3 113 depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64) 114 bool "ARM PMUv3 support" if !ARM64 115 default ARM64 116 help 117 Say y if you want to use the ARM performance monitor unit (PMU) 118 version 3. The PMUv3 is the CPU performance monitors on ARMv8 119 (aarch32 and aarch64) systems that implement the PMUv3 120 architecture. 121 122config ARM_DSU_PMU 123 tristate "ARM DynamIQ Shared Unit (DSU) PMU" 124 depends on ARM64 125 help 126 Provides support for performance monitor unit in ARM DynamIQ Shared 127 Unit (DSU). The DSU integrates one or more cores with an L3 memory 128 system, control logic. The PMU allows counting various events related 129 to DSU. 130 131config FSL_IMX8_DDR_PMU 132 tristate "Freescale i.MX8 DDR perf monitor" 133 depends on ARCH_MXC || COMPILE_TEST 134 help 135 Provides support for the DDR performance monitor in i.MX8, which 136 can give information about memory throughput and other related 137 events. 138 139config FSL_IMX9_DDR_PMU 140 tristate "Freescale i.MX9 DDR perf monitor" 141 depends on ARCH_MXC 142 help 143 Provides support for the DDR performance monitor in i.MX9, which 144 can give information about memory throughput and other related 145 events. 146 147config QCOM_L2_PMU 148 bool "Qualcomm Technologies L2-cache PMU" 149 depends on ARCH_QCOM && ARM64 && ACPI 150 select QCOM_KRYO_L2_ACCESSORS 151 help 152 Provides support for the L2 cache performance monitor unit (PMU) 153 in Qualcomm Technologies processors. 154 Adds the L2 cache PMU into the perf events subsystem for 155 monitoring L2 cache events. 156 157config QCOM_L3_PMU 158 bool "Qualcomm Technologies L3-cache PMU" 159 depends on ARCH_QCOM && ARM64 && ACPI 160 select QCOM_IRQ_COMBINER 161 help 162 Provides support for the L3 cache performance monitor unit (PMU) 163 in Qualcomm Technologies processors. 164 Adds the L3 cache PMU into the perf events subsystem for 165 monitoring L3 cache events. 166 167config THUNDERX2_PMU 168 tristate "Cavium ThunderX2 SoC PMU UNCORE" 169 depends on ARCH_THUNDER2 || COMPILE_TEST 170 depends on NUMA && ACPI 171 default m 172 help 173 Provides support for ThunderX2 UNCORE events. 174 The SoC has PMU support in its L3 cache controller (L3C) and 175 in the DDR4 Memory Controller (DMC). 176 177config XGENE_PMU 178 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 179 bool "APM X-Gene SoC PMU" 180 default n 181 help 182 Say y if you want to use APM X-Gene SoC performance monitors. 183 184config ARM_SPE_PMU 185 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 186 depends on ARM64 187 help 188 Enable perf support for the ARMv8.2 Statistical Profiling 189 Extension, which provides periodic sampling of operations in 190 the CPU pipeline and reports this via the perf AUX interface. 191 192config ARM_DMC620_PMU 193 tristate "Enable PMU support for the ARM DMC-620 memory controller" 194 depends on (ARM64 && ACPI) || COMPILE_TEST 195 help 196 Support for PMU events monitoring on the ARM DMC-620 memory 197 controller. 198 199config MARVELL_CN10K_TAD_PMU 200 tristate "Marvell CN10K LLC-TAD PMU" 201 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 202 help 203 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 204 performance monitors on CN10K family silicons. 205 206config APPLE_M1_CPU_PMU 207 bool "Apple M1 CPU PMU support" 208 depends on ARM_PMU && ARCH_APPLE 209 help 210 Provides support for the non-architectural CPU PMUs present on 211 the Apple M1 SoCs and derivatives. 212 213config ALIBABA_UNCORE_DRW_PMU 214 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver" 215 depends on (ARM64 && ACPI) || COMPILE_TEST 216 help 217 Support for Driveway PMU events monitoring on Yitian 710 DDR 218 Sub-system. 219 220source "drivers/perf/hisilicon/Kconfig" 221 222config MARVELL_CN10K_DDR_PMU 223 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support" 224 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 225 help 226 Enable perf support for Marvell DDR Performance monitoring 227 event on CN10K platform. 228 229config DWC_PCIE_PMU 230 tristate "Synopsys DesignWare PCIe PMU" 231 depends on PCI 232 help 233 Enable perf support for Synopsys DesignWare PCIe PMU Performance 234 monitoring event on platform including the Alibaba Yitian 710. 235 236source "drivers/perf/arm_cspmu/Kconfig" 237 238source "drivers/perf/amlogic/Kconfig" 239 240config CXL_PMU 241 tristate "CXL Performance Monitoring Unit" 242 depends on CXL_BUS 243 help 244 Support performance monitoring as defined in CXL rev 3.0 245 section 13.2: Performance Monitoring. CXL components may have 246 one or more CXL Performance Monitoring Units (CPMUs). 247 248 Say 'y/m' to enable a driver that will attach to performance 249 monitoring units and provide standard perf based interfaces. 250 251 If unsure say 'm'. 252 253endmenu 254