1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Performance Monitor Drivers 4# 5 6menu "Performance monitor support" 7 depends on PERF_EVENTS 8 9config ARM_CCI_PMU 10 tristate "ARM CCI PMU driver" 11 depends on (ARM && CPU_V7) || ARM64 12 select ARM_CCI 13 help 14 Support for PMU events monitoring on the ARM CCI (Cache Coherent 15 Interconnect) family of products. 16 17 If compiled as a module, it will be called arm-cci. 18 19config ARM_CCI400_PMU 20 bool "support CCI-400" 21 default y 22 depends on ARM_CCI_PMU 23 select ARM_CCI400_COMMON 24 help 25 CCI-400 provides 4 independent event counters counting events related 26 to the connected slave/master interfaces, plus a cycle counter. 27 28config ARM_CCI5xx_PMU 29 bool "support CCI-500/CCI-550" 30 default y 31 depends on ARM_CCI_PMU 32 help 33 CCI-500/CCI-550 both provide 8 independent event counters, which can 34 count events pertaining to the slave/master interfaces as well as the 35 internal events to the CCI. 36 37config ARM_CCN 38 tristate "ARM CCN driver support" 39 depends on ARM || ARM64 || COMPILE_TEST 40 help 41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 42 interconnect. 43 44config ARM_CMN 45 tristate "Arm CMN-600 PMU support" 46 depends on ARM64 || COMPILE_TEST 47 help 48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 49 Network interconnect. 50 51config ARM_PMU 52 depends on ARM || ARM64 53 bool "ARM PMU framework" 54 default y 55 help 56 Say y if you want to use CPU performance monitors on ARM-based 57 systems. 58 59config RISCV_PMU 60 depends on RISCV 61 bool "RISC-V PMU framework" 62 default y 63 help 64 Say y if you want to use CPU performance monitors on RISCV-based 65 systems. This provides the core PMU framework that abstracts common 66 PMU functionalities in a core library so that different PMU drivers 67 can reuse it. 68 69config RISCV_PMU_LEGACY 70 depends on RISCV_PMU 71 bool "RISC-V legacy PMU implementation" 72 default y 73 help 74 Say y if you want to use the legacy CPU performance monitor 75 implementation on RISC-V based systems. This only allows counting 76 of cycle/instruction counter and doesn't support counter overflow, 77 or programmable counters. It will be removed in future. 78 79config RISCV_PMU_SBI 80 depends on RISCV_PMU && RISCV_SBI 81 bool "RISC-V PMU based on SBI PMU extension" 82 default y 83 help 84 Say y if you want to use the CPU performance monitor 85 using SBI PMU extension on RISC-V based systems. This option provides 86 full perf feature support i.e. counter overflow, privilege mode 87 filtering, counter configuration. 88 89config STARFIVE_STARLINK_PMU 90 depends on ARCH_STARFIVE || COMPILE_TEST 91 depends on 64BIT 92 bool "StarFive StarLink PMU" 93 help 94 Provide support for StarLink Performance Monitor Unit. 95 StarLink Performance Monitor Unit integrates one or more cores with 96 an L3 memory system. The L3 cache events are added into perf event 97 subsystem, allowing monitoring of various L3 cache perf events. 98 99config ARM_PMU_ACPI 100 depends on ARM_PMU && ACPI 101 def_bool y 102 103config ARM_SMMU_V3_PMU 104 tristate "ARM SMMUv3 Performance Monitors Extension" 105 depends on ARM64 || (COMPILE_TEST && 64BIT) 106 depends on GENERIC_MSI_IRQ 107 help 108 Provides support for the ARM SMMUv3 Performance Monitor Counter 109 Groups (PMCG), which provide monitoring of transactions passing 110 through the SMMU and allow the resulting information to be filtered 111 based on the Stream ID of the corresponding master. 112 113config ARM_PMUV3 114 depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64) 115 bool "ARM PMUv3 support" if !ARM64 116 default ARM64 117 help 118 Say y if you want to use the ARM performance monitor unit (PMU) 119 version 3. The PMUv3 is the CPU performance monitors on ARMv8 120 (aarch32 and aarch64) systems that implement the PMUv3 121 architecture. 122 123config ARM_DSU_PMU 124 tristate "ARM DynamIQ Shared Unit (DSU) PMU" 125 depends on ARM64 126 help 127 Provides support for performance monitor unit in ARM DynamIQ Shared 128 Unit (DSU). The DSU integrates one or more cores with an L3 memory 129 system, control logic. The PMU allows counting various events related 130 to DSU. 131 132config FSL_IMX8_DDR_PMU 133 tristate "Freescale i.MX8 DDR perf monitor" 134 depends on ARCH_MXC || COMPILE_TEST 135 help 136 Provides support for the DDR performance monitor in i.MX8, which 137 can give information about memory throughput and other related 138 events. 139 140config FSL_IMX9_DDR_PMU 141 tristate "Freescale i.MX9 DDR perf monitor" 142 depends on ARCH_MXC 143 help 144 Provides support for the DDR performance monitor in i.MX9, which 145 can give information about memory throughput and other related 146 events. 147 148config QCOM_L2_PMU 149 bool "Qualcomm Technologies L2-cache PMU" 150 depends on ARCH_QCOM && ARM64 && ACPI 151 select QCOM_KRYO_L2_ACCESSORS 152 help 153 Provides support for the L2 cache performance monitor unit (PMU) 154 in Qualcomm Technologies processors. 155 Adds the L2 cache PMU into the perf events subsystem for 156 monitoring L2 cache events. 157 158config QCOM_L3_PMU 159 bool "Qualcomm Technologies L3-cache PMU" 160 depends on ARCH_QCOM && ARM64 && ACPI 161 select QCOM_IRQ_COMBINER 162 help 163 Provides support for the L3 cache performance monitor unit (PMU) 164 in Qualcomm Technologies processors. 165 Adds the L3 cache PMU into the perf events subsystem for 166 monitoring L3 cache events. 167 168config THUNDERX2_PMU 169 tristate "Cavium ThunderX2 SoC PMU UNCORE" 170 depends on ARCH_THUNDER2 || COMPILE_TEST 171 depends on NUMA && ACPI 172 default m 173 help 174 Provides support for ThunderX2 UNCORE events. 175 The SoC has PMU support in its L3 cache controller (L3C) and 176 in the DDR4 Memory Controller (DMC). 177 178config XGENE_PMU 179 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 180 bool "APM X-Gene SoC PMU" 181 default n 182 help 183 Say y if you want to use APM X-Gene SoC performance monitors. 184 185config ARM_SPE_PMU 186 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 187 depends on ARM64 188 help 189 Enable perf support for the ARMv8.2 Statistical Profiling 190 Extension, which provides periodic sampling of operations in 191 the CPU pipeline and reports this via the perf AUX interface. 192 193config ARM_DMC620_PMU 194 tristate "Enable PMU support for the ARM DMC-620 memory controller" 195 depends on (ARM64 && ACPI) || COMPILE_TEST 196 help 197 Support for PMU events monitoring on the ARM DMC-620 memory 198 controller. 199 200config MARVELL_CN10K_TAD_PMU 201 tristate "Marvell CN10K LLC-TAD PMU" 202 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 203 help 204 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 205 performance monitors on CN10K family silicons. 206 207config APPLE_M1_CPU_PMU 208 bool "Apple M1 CPU PMU support" 209 depends on ARM_PMU && ARCH_APPLE 210 help 211 Provides support for the non-architectural CPU PMUs present on 212 the Apple M1 SoCs and derivatives. 213 214config ALIBABA_UNCORE_DRW_PMU 215 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver" 216 depends on (ARM64 && ACPI) || COMPILE_TEST 217 help 218 Support for Driveway PMU events monitoring on Yitian 710 DDR 219 Sub-system. 220 221source "drivers/perf/hisilicon/Kconfig" 222 223config MARVELL_CN10K_DDR_PMU 224 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support" 225 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 226 help 227 Enable perf support for Marvell DDR Performance monitoring 228 event on CN10K platform. 229 230config DWC_PCIE_PMU 231 tristate "Synopsys DesignWare PCIe PMU" 232 depends on PCI 233 help 234 Enable perf support for Synopsys DesignWare PCIe PMU Performance 235 monitoring event on platform including the Alibaba Yitian 710. 236 237source "drivers/perf/arm_cspmu/Kconfig" 238 239source "drivers/perf/amlogic/Kconfig" 240 241config CXL_PMU 242 tristate "CXL Performance Monitoring Unit" 243 depends on CXL_BUS 244 help 245 Support performance monitoring as defined in CXL rev 3.0 246 section 13.2: Performance Monitoring. CXL components may have 247 one or more CXL Performance Monitoring Units (CPMUs). 248 249 Say 'y/m' to enable a driver that will attach to performance 250 monitoring units and provide standard perf based interfaces. 251 252 If unsure say 'm'. 253 254endmenu 255