1# 2# Performance Monitor Drivers 3# 4 5menu "Performance monitor support" 6 depends on PERF_EVENTS 7 8config ARM_CCI_PMU 9 tristate "ARM CCI PMU driver" 10 depends on (ARM && CPU_V7) || ARM64 11 select ARM_CCI 12 help 13 Support for PMU events monitoring on the ARM CCI (Cache Coherent 14 Interconnect) family of products. 15 16 If compiled as a module, it will be called arm-cci. 17 18config ARM_CCI400_PMU 19 bool "support CCI-400" 20 default y 21 depends on ARM_CCI_PMU 22 select ARM_CCI400_COMMON 23 help 24 CCI-400 provides 4 independent event counters counting events related 25 to the connected slave/master interfaces, plus a cycle counter. 26 27config ARM_CCI5xx_PMU 28 bool "support CCI-500/CCI-550" 29 default y 30 depends on ARM_CCI_PMU 31 help 32 CCI-500/CCI-550 both provide 8 independent event counters, which can 33 count events pertaining to the slave/master interfaces as well as the 34 internal events to the CCI. 35 36config ARM_CCN 37 tristate "ARM CCN driver support" 38 depends on ARM || ARM64 39 help 40 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 41 interconnect. 42 43config ARM_PMU 44 depends on ARM || ARM64 45 bool "ARM PMU framework" 46 default y 47 help 48 Say y if you want to use CPU performance monitors on ARM-based 49 systems. 50 51config ARM_PMU_ACPI 52 depends on ARM_PMU && ACPI 53 def_bool y 54 55config ARM_DSU_PMU 56 tristate "ARM DynamIQ Shared Unit (DSU) PMU" 57 depends on ARM64 58 help 59 Provides support for performance monitor unit in ARM DynamIQ Shared 60 Unit (DSU). The DSU integrates one or more cores with an L3 memory 61 system, control logic. The PMU allows counting various events related 62 to DSU. 63 64config HISI_PMU 65 bool "HiSilicon SoC PMU" 66 depends on ARM64 && ACPI 67 help 68 Support for HiSilicon SoC uncore performance monitoring 69 unit (PMU), such as: L3C, HHA and DDRC. 70 71config QCOM_L2_PMU 72 bool "Qualcomm Technologies L2-cache PMU" 73 depends on ARCH_QCOM && ARM64 && ACPI 74 help 75 Provides support for the L2 cache performance monitor unit (PMU) 76 in Qualcomm Technologies processors. 77 Adds the L2 cache PMU into the perf events subsystem for 78 monitoring L2 cache events. 79 80config QCOM_L3_PMU 81 bool "Qualcomm Technologies L3-cache PMU" 82 depends on ARCH_QCOM && ARM64 && ACPI 83 select QCOM_IRQ_COMBINER 84 help 85 Provides support for the L3 cache performance monitor unit (PMU) 86 in Qualcomm Technologies processors. 87 Adds the L3 cache PMU into the perf events subsystem for 88 monitoring L3 cache events. 89 90config XGENE_PMU 91 depends on ARCH_XGENE 92 bool "APM X-Gene SoC PMU" 93 default n 94 help 95 Say y if you want to use APM X-Gene SoC performance monitors. 96 97config ARM_SPE_PMU 98 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 99 depends on ARM64 100 help 101 Enable perf support for the ARMv8.2 Statistical Profiling 102 Extension, which provides periodic sampling of operations in 103 the CPU pipeline and reports this via the perf AUX interface. 104 105endmenu 106