1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Performance Monitor Drivers 4# 5 6menu "Performance monitor support" 7 depends on PERF_EVENTS 8 9config ARM_CCI_PMU 10 tristate "ARM CCI PMU driver" 11 depends on (ARM && CPU_V7) || ARM64 12 select ARM_CCI 13 help 14 Support for PMU events monitoring on the ARM CCI (Cache Coherent 15 Interconnect) family of products. 16 17 If compiled as a module, it will be called arm-cci. 18 19config ARM_CCI400_PMU 20 bool "support CCI-400" 21 default y 22 depends on ARM_CCI_PMU 23 select ARM_CCI400_COMMON 24 help 25 CCI-400 provides 4 independent event counters counting events related 26 to the connected slave/master interfaces, plus a cycle counter. 27 28config ARM_CCI5xx_PMU 29 bool "support CCI-500/CCI-550" 30 default y 31 depends on ARM_CCI_PMU 32 help 33 CCI-500/CCI-550 both provide 8 independent event counters, which can 34 count events pertaining to the slave/master interfaces as well as the 35 internal events to the CCI. 36 37config ARM_CCN 38 tristate "ARM CCN driver support" 39 depends on ARM || ARM64 || COMPILE_TEST 40 help 41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 42 interconnect. 43 44config ARM_CMN 45 tristate "Arm CMN-600 PMU support" 46 depends on ARM64 || COMPILE_TEST 47 help 48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 49 Network interconnect. 50 51config ARM_PMU 52 depends on ARM || ARM64 53 bool "ARM PMU framework" 54 default y 55 help 56 Say y if you want to use CPU performance monitors on ARM-based 57 systems. 58 59config ARM_V6_PMU 60 depends on ARM_PMU && (CPU_V6 || CPU_V6K) 61 def_bool y 62 63config ARM_V7_PMU 64 depends on ARM_PMU && CPU_V7 65 def_bool y 66 67config ARM_XSCALE_PMU 68 depends on ARM_PMU && CPU_XSCALE 69 def_bool y 70 71config RISCV_PMU 72 depends on RISCV 73 bool "RISC-V PMU framework" 74 default y 75 help 76 Say y if you want to use CPU performance monitors on RISCV-based 77 systems. This provides the core PMU framework that abstracts common 78 PMU functionalities in a core library so that different PMU drivers 79 can reuse it. 80 81config RISCV_PMU_LEGACY 82 depends on RISCV_PMU 83 bool "RISC-V legacy PMU implementation" 84 default y 85 help 86 Say y if you want to use the legacy CPU performance monitor 87 implementation on RISC-V based systems. This only allows counting 88 of cycle/instruction counter and doesn't support counter overflow, 89 or programmable counters. It will be removed in future. 90 91config RISCV_PMU_SBI 92 depends on RISCV_PMU && RISCV_SBI 93 bool "RISC-V PMU based on SBI PMU extension" 94 default y 95 help 96 Say y if you want to use the CPU performance monitor 97 using SBI PMU extension on RISC-V based systems. This option provides 98 full perf feature support i.e. counter overflow, privilege mode 99 filtering, counter configuration. 100 101config STARFIVE_STARLINK_PMU 102 depends on ARCH_STARFIVE || COMPILE_TEST 103 depends on 64BIT 104 bool "StarFive StarLink PMU" 105 help 106 Provide support for StarLink Performance Monitor Unit. 107 StarLink Performance Monitor Unit integrates one or more cores with 108 an L3 memory system. The L3 cache events are added into perf event 109 subsystem, allowing monitoring of various L3 cache perf events. 110 111config ANDES_CUSTOM_PMU 112 bool "Andes custom PMU support" 113 depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI 114 default y 115 help 116 The Andes cores implement the PMU overflow extension very 117 similar to the standard Sscofpmf and Smcntrpmf extension. 118 119 This will patch the overflow and pending CSRs and handle the 120 non-standard behaviour via the regular SBI PMU driver and 121 interface. 122 123 If you don't know what to do here, say "Y". 124 125config ARM_PMU_ACPI 126 depends on ARM_PMU && ACPI 127 def_bool y 128 129config ARM_SMMU_V3_PMU 130 tristate "ARM SMMUv3 Performance Monitors Extension" 131 depends on ARM64 || (COMPILE_TEST && 64BIT) 132 depends on GENERIC_MSI_IRQ 133 help 134 Provides support for the ARM SMMUv3 Performance Monitor Counter 135 Groups (PMCG), which provide monitoring of transactions passing 136 through the SMMU and allow the resulting information to be filtered 137 based on the Stream ID of the corresponding master. 138 139config ARM_PMUV3 140 depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64) 141 bool "ARM PMUv3 support" if !ARM64 142 default ARM64 143 help 144 Say y if you want to use the ARM performance monitor unit (PMU) 145 version 3. The PMUv3 is the CPU performance monitors on ARMv8 146 (aarch32 and aarch64) systems that implement the PMUv3 147 architecture. 148 149config ARM_DSU_PMU 150 tristate "ARM DynamIQ Shared Unit (DSU) PMU" 151 depends on ARM64 152 help 153 Provides support for performance monitor unit in ARM DynamIQ Shared 154 Unit (DSU). The DSU integrates one or more cores with an L3 memory 155 system, control logic. The PMU allows counting various events related 156 to DSU. 157 158config FSL_IMX8_DDR_PMU 159 tristate "Freescale i.MX8 DDR perf monitor" 160 depends on ARCH_MXC || COMPILE_TEST 161 help 162 Provides support for the DDR performance monitor in i.MX8, which 163 can give information about memory throughput and other related 164 events. 165 166config FSL_IMX9_DDR_PMU 167 tristate "Freescale i.MX9 DDR perf monitor" 168 depends on ARCH_MXC 169 help 170 Provides support for the DDR performance monitor in i.MX9, which 171 can give information about memory throughput and other related 172 events. 173 174config QCOM_L2_PMU 175 bool "Qualcomm Technologies L2-cache PMU" 176 depends on ARCH_QCOM && ARM64 && ACPI 177 select QCOM_KRYO_L2_ACCESSORS 178 help 179 Provides support for the L2 cache performance monitor unit (PMU) 180 in Qualcomm Technologies processors. 181 Adds the L2 cache PMU into the perf events subsystem for 182 monitoring L2 cache events. 183 184config QCOM_L3_PMU 185 bool "Qualcomm Technologies L3-cache PMU" 186 depends on ARCH_QCOM && ARM64 && ACPI 187 select QCOM_IRQ_COMBINER 188 help 189 Provides support for the L3 cache performance monitor unit (PMU) 190 in Qualcomm Technologies processors. 191 Adds the L3 cache PMU into the perf events subsystem for 192 monitoring L3 cache events. 193 194config THUNDERX2_PMU 195 tristate "Cavium ThunderX2 SoC PMU UNCORE" 196 depends on ARCH_THUNDER2 || COMPILE_TEST 197 depends on NUMA && ACPI 198 default m 199 help 200 Provides support for ThunderX2 UNCORE events. 201 The SoC has PMU support in its L3 cache controller (L3C) and 202 in the DDR4 Memory Controller (DMC). 203 204config XGENE_PMU 205 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 206 bool "APM X-Gene SoC PMU" 207 default n 208 help 209 Say y if you want to use APM X-Gene SoC performance monitors. 210 211config ARM_SPE_PMU 212 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 213 depends on ARM64 214 help 215 Enable perf support for the ARMv8.2 Statistical Profiling 216 Extension, which provides periodic sampling of operations in 217 the CPU pipeline and reports this via the perf AUX interface. 218 219config ARM_DMC620_PMU 220 tristate "Enable PMU support for the ARM DMC-620 memory controller" 221 depends on (ARM64 && ACPI) || COMPILE_TEST 222 help 223 Support for PMU events monitoring on the ARM DMC-620 memory 224 controller. 225 226config MARVELL_CN10K_TAD_PMU 227 tristate "Marvell CN10K LLC-TAD PMU" 228 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 229 help 230 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 231 performance monitors on CN10K family silicons. 232 233config APPLE_M1_CPU_PMU 234 bool "Apple M1 CPU PMU support" 235 depends on ARM_PMU && ARCH_APPLE 236 help 237 Provides support for the non-architectural CPU PMUs present on 238 the Apple M1 SoCs and derivatives. 239 240config ALIBABA_UNCORE_DRW_PMU 241 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver" 242 depends on (ARM64 && ACPI) || COMPILE_TEST 243 help 244 Support for Driveway PMU events monitoring on Yitian 710 DDR 245 Sub-system. 246 247source "drivers/perf/hisilicon/Kconfig" 248 249config MARVELL_CN10K_DDR_PMU 250 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support" 251 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 252 help 253 Enable perf support for Marvell DDR Performance monitoring 254 event on CN10K platform. 255 256config DWC_PCIE_PMU 257 tristate "Synopsys DesignWare PCIe PMU" 258 depends on PCI 259 help 260 Enable perf support for Synopsys DesignWare PCIe PMU Performance 261 monitoring event on platform including the Alibaba Yitian 710. 262 263source "drivers/perf/arm_cspmu/Kconfig" 264 265source "drivers/perf/amlogic/Kconfig" 266 267config CXL_PMU 268 tristate "CXL Performance Monitoring Unit" 269 depends on CXL_BUS 270 help 271 Support performance monitoring as defined in CXL rev 3.0 272 section 13.2: Performance Monitoring. CXL components may have 273 one or more CXL Performance Monitoring Units (CPMUs). 274 275 Say 'y/m' to enable a driver that will attach to performance 276 monitoring units and provide standard perf based interfaces. 277 278 If unsure say 'm'. 279 280endmenu 281