1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Performance Monitor Drivers 4# 5 6menu "Performance monitor support" 7 depends on PERF_EVENTS 8 9config ARM_CCI_PMU 10 tristate "ARM CCI PMU driver" 11 depends on (ARM && CPU_V7) || ARM64 12 select ARM_CCI 13 help 14 Support for PMU events monitoring on the ARM CCI (Cache Coherent 15 Interconnect) family of products. 16 17 If compiled as a module, it will be called arm-cci. 18 19config ARM_CCI400_PMU 20 bool "support CCI-400" 21 default y 22 depends on ARM_CCI_PMU 23 select ARM_CCI400_COMMON 24 help 25 CCI-400 provides 4 independent event counters counting events related 26 to the connected slave/master interfaces, plus a cycle counter. 27 28config ARM_CCI5xx_PMU 29 bool "support CCI-500/CCI-550" 30 default y 31 depends on ARM_CCI_PMU 32 help 33 CCI-500/CCI-550 both provide 8 independent event counters, which can 34 count events pertaining to the slave/master interfaces as well as the 35 internal events to the CCI. 36 37config ARM_CCN 38 tristate "ARM CCN driver support" 39 depends on ARM || ARM64 40 help 41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 42 interconnect. 43 44config ARM_PMU 45 depends on ARM || ARM64 46 bool "ARM PMU framework" 47 default y 48 help 49 Say y if you want to use CPU performance monitors on ARM-based 50 systems. 51 52config ARM_PMU_ACPI 53 depends on ARM_PMU && ACPI 54 def_bool y 55 56config ARM_SMMU_V3_PMU 57 tristate "ARM SMMUv3 Performance Monitors Extension" 58 depends on ARM64 && ACPI && ARM_SMMU_V3 59 help 60 Provides support for the ARM SMMUv3 Performance Monitor Counter 61 Groups (PMCG), which provide monitoring of transactions passing 62 through the SMMU and allow the resulting information to be filtered 63 based on the Stream ID of the corresponding master. 64 65config ARM_DSU_PMU 66 tristate "ARM DynamIQ Shared Unit (DSU) PMU" 67 depends on ARM64 68 help 69 Provides support for performance monitor unit in ARM DynamIQ Shared 70 Unit (DSU). The DSU integrates one or more cores with an L3 memory 71 system, control logic. The PMU allows counting various events related 72 to DSU. 73 74config FSL_IMX8_DDR_PMU 75 tristate "Freescale i.MX8 DDR perf monitor" 76 depends on ARCH_MXC 77 help 78 Provides support for the DDR performance monitor in i.MX8, which 79 can give information about memory throughput and other related 80 events. 81 82config QCOM_L2_PMU 83 bool "Qualcomm Technologies L2-cache PMU" 84 depends on ARCH_QCOM && ARM64 && ACPI 85 help 86 Provides support for the L2 cache performance monitor unit (PMU) 87 in Qualcomm Technologies processors. 88 Adds the L2 cache PMU into the perf events subsystem for 89 monitoring L2 cache events. 90 91config QCOM_L3_PMU 92 bool "Qualcomm Technologies L3-cache PMU" 93 depends on ARCH_QCOM && ARM64 && ACPI 94 select QCOM_IRQ_COMBINER 95 help 96 Provides support for the L3 cache performance monitor unit (PMU) 97 in Qualcomm Technologies processors. 98 Adds the L3 cache PMU into the perf events subsystem for 99 monitoring L3 cache events. 100 101config THUNDERX2_PMU 102 tristate "Cavium ThunderX2 SoC PMU UNCORE" 103 depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA 104 default m 105 help 106 Provides support for ThunderX2 UNCORE events. 107 The SoC has PMU support in its L3 cache controller (L3C) and 108 in the DDR4 Memory Controller (DMC). 109 110config XGENE_PMU 111 depends on ARCH_XGENE 112 bool "APM X-Gene SoC PMU" 113 default n 114 help 115 Say y if you want to use APM X-Gene SoC performance monitors. 116 117config ARM_SPE_PMU 118 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 119 depends on ARM64 120 help 121 Enable perf support for the ARMv8.2 Statistical Profiling 122 Extension, which provides periodic sampling of operations in 123 the CPU pipeline and reports this via the perf AUX interface. 124 125source "drivers/perf/hisilicon/Kconfig" 126 127endmenu 128