1 /*====================================================================== 2 3 Device driver for Intel 82365 and compatible PC Card controllers. 4 5 i82365.c 1.265 1999/11/10 18:36:21 6 7 The contents of this file are subject to the Mozilla Public 8 License Version 1.1 (the "License"); you may not use this file 9 except in compliance with the License. You may obtain a copy of 10 the License at http://www.mozilla.org/MPL/ 11 12 Software distributed under the License is distributed on an "AS 13 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or 14 implied. See the License for the specific language governing 15 rights and limitations under the License. 16 17 The initial developer of the original code is David A. Hinds 18 <dahinds@users.sourceforge.net>. Portions created by David A. Hinds 19 are Copyright (C) 1999 David A. Hinds. All Rights Reserved. 20 21 Alternatively, the contents of this file may be used under the 22 terms of the GNU General Public License version 2 (the "GPL"), in which 23 case the provisions of the GPL are applicable instead of the 24 above. If you wish to allow the use of your version of this file 25 only under the terms of the GPL and not to allow others to use 26 your version of this file under the MPL, indicate your decision 27 by deleting the provisions above and replace them with the notice 28 and other provisions required by the GPL. If you do not delete 29 the provisions above, a recipient may use your version of this 30 file under either the MPL or the GPL. 31 32 ======================================================================*/ 33 34 #include <linux/module.h> 35 #include <linux/moduleparam.h> 36 #include <linux/init.h> 37 #include <linux/config.h> 38 #include <linux/types.h> 39 #include <linux/fcntl.h> 40 #include <linux/string.h> 41 #include <linux/kernel.h> 42 #include <linux/errno.h> 43 #include <linux/timer.h> 44 #include <linux/sched.h> 45 #include <linux/slab.h> 46 #include <linux/ioport.h> 47 #include <linux/delay.h> 48 #include <linux/workqueue.h> 49 #include <linux/interrupt.h> 50 #include <linux/device.h> 51 #include <linux/bitops.h> 52 #include <asm/irq.h> 53 #include <asm/io.h> 54 #include <asm/system.h> 55 56 #include <pcmcia/version.h> 57 #include <pcmcia/cs_types.h> 58 #include <pcmcia/ss.h> 59 #include <pcmcia/cs.h> 60 61 #include <linux/isapnp.h> 62 63 /* ISA-bus controllers */ 64 #include "i82365.h" 65 #include "cirrus.h" 66 #include "vg468.h" 67 #include "ricoh.h" 68 69 #ifdef DEBUG 70 static const char version[] = 71 "i82365.c 1.265 1999/11/10 18:36:21 (David Hinds)"; 72 73 static int pc_debug; 74 75 module_param(pc_debug, int, 0644); 76 77 #define debug(lvl, fmt, arg...) do { \ 78 if (pc_debug > (lvl)) \ 79 printk(KERN_DEBUG "i82365: " fmt , ## arg); \ 80 } while (0) 81 #else 82 #define debug(lvl, fmt, arg...) do { } while (0) 83 #endif 84 85 static irqreturn_t i365_count_irq(int, void *, struct pt_regs *); 86 static inline int _check_irq(int irq, int flags) 87 { 88 if (request_irq(irq, i365_count_irq, flags, "x", i365_count_irq) != 0) 89 return -1; 90 free_irq(irq, i365_count_irq); 91 return 0; 92 } 93 94 /*====================================================================*/ 95 96 /* Parameters that can be set with 'insmod' */ 97 98 /* Default base address for i82365sl and other ISA chips */ 99 static unsigned long i365_base = 0x3e0; 100 /* Should we probe at 0x3e2 for an extra ISA controller? */ 101 static int extra_sockets = 0; 102 /* Specify a socket number to ignore */ 103 static int ignore = -1; 104 /* Bit map or list of interrupts to choose from */ 105 static u_int irq_mask = 0xffff; 106 static int irq_list[16]; 107 static int irq_list_count; 108 /* The card status change interrupt -- 0 means autoselect */ 109 static int cs_irq = 0; 110 111 /* Probe for safe interrupts? */ 112 static int do_scan = 1; 113 /* Poll status interval -- 0 means default to interrupt */ 114 static int poll_interval = 0; 115 /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ 116 static int cycle_time = 120; 117 118 /* Cirrus options */ 119 static int has_dma = -1; 120 static int has_led = -1; 121 static int has_ring = -1; 122 static int dynamic_mode = 0; 123 static int freq_bypass = -1; 124 static int setup_time = -1; 125 static int cmd_time = -1; 126 static int recov_time = -1; 127 128 /* Vadem options */ 129 static int async_clock = -1; 130 static int cable_mode = -1; 131 static int wakeup = 0; 132 133 module_param(i365_base, ulong, 0444); 134 module_param(ignore, int, 0444); 135 module_param(extra_sockets, int, 0444); 136 module_param(irq_mask, int, 0444); 137 module_param_array(irq_list, int, &irq_list_count, 0444); 138 module_param(cs_irq, int, 0444); 139 module_param(async_clock, int, 0444); 140 module_param(cable_mode, int, 0444); 141 module_param(wakeup, int, 0444); 142 143 module_param(do_scan, int, 0444); 144 module_param(poll_interval, int, 0444); 145 module_param(cycle_time, int, 0444); 146 module_param(has_dma, int, 0444); 147 module_param(has_led, int, 0444); 148 module_param(has_ring, int, 0444); 149 module_param(dynamic_mode, int, 0444); 150 module_param(freq_bypass, int, 0444); 151 module_param(setup_time, int, 0444); 152 module_param(cmd_time, int, 0444); 153 module_param(recov_time, int, 0444); 154 155 /*====================================================================*/ 156 157 typedef struct cirrus_state_t { 158 u_char misc1, misc2; 159 u_char timer[6]; 160 } cirrus_state_t; 161 162 typedef struct vg46x_state_t { 163 u_char ctl, ema; 164 } vg46x_state_t; 165 166 struct i82365_socket { 167 u_short type, flags; 168 struct pcmcia_socket socket; 169 unsigned int number; 170 kio_addr_t ioaddr; 171 u_short psock; 172 u_char cs_irq, intr; 173 union { 174 cirrus_state_t cirrus; 175 vg46x_state_t vg46x; 176 } state; 177 }; 178 179 /* Where we keep track of our sockets... */ 180 static int sockets = 0; 181 static struct i82365_socket socket[8] = { 182 { 0, }, /* ... */ 183 }; 184 185 /* Default ISA interrupt mask */ 186 #define I365_MASK 0xdeb8 /* irq 15,14,12,11,10,9,7,5,4,3 */ 187 188 static int grab_irq; 189 static DEFINE_SPINLOCK(isa_lock); 190 #define ISA_LOCK(n, f) spin_lock_irqsave(&isa_lock, f) 191 #define ISA_UNLOCK(n, f) spin_unlock_irqrestore(&isa_lock, f) 192 193 static struct timer_list poll_timer; 194 195 /*====================================================================*/ 196 197 /* These definitions must match the pcic table! */ 198 typedef enum pcic_id { 199 IS_I82365A, IS_I82365B, IS_I82365DF, 200 IS_IBM, IS_RF5Cx96, IS_VLSI, IS_VG468, IS_VG469, 201 IS_PD6710, IS_PD672X, IS_VT83C469, 202 } pcic_id; 203 204 /* Flags for classifying groups of controllers */ 205 #define IS_VADEM 0x0001 206 #define IS_CIRRUS 0x0002 207 #define IS_VIA 0x0010 208 #define IS_UNKNOWN 0x0400 209 #define IS_VG_PWR 0x0800 210 #define IS_DF_PWR 0x1000 211 #define IS_REGISTERED 0x2000 212 #define IS_ALIVE 0x8000 213 214 typedef struct pcic_t { 215 char *name; 216 u_short flags; 217 } pcic_t; 218 219 static pcic_t pcic[] = { 220 { "Intel i82365sl A step", 0 }, 221 { "Intel i82365sl B step", 0 }, 222 { "Intel i82365sl DF", IS_DF_PWR }, 223 { "IBM Clone", 0 }, 224 { "Ricoh RF5C296/396", 0 }, 225 { "VLSI 82C146", 0 }, 226 { "Vadem VG-468", IS_VADEM }, 227 { "Vadem VG-469", IS_VADEM|IS_VG_PWR }, 228 { "Cirrus PD6710", IS_CIRRUS }, 229 { "Cirrus PD672x", IS_CIRRUS }, 230 { "VIA VT83C469", IS_CIRRUS|IS_VIA }, 231 }; 232 233 #define PCIC_COUNT (sizeof(pcic)/sizeof(pcic_t)) 234 235 /*====================================================================*/ 236 237 static DEFINE_SPINLOCK(bus_lock); 238 239 static u_char i365_get(u_short sock, u_short reg) 240 { 241 unsigned long flags; 242 spin_lock_irqsave(&bus_lock,flags); 243 { 244 kio_addr_t port = socket[sock].ioaddr; 245 u_char val; 246 reg = I365_REG(socket[sock].psock, reg); 247 outb(reg, port); val = inb(port+1); 248 spin_unlock_irqrestore(&bus_lock,flags); 249 return val; 250 } 251 } 252 253 static void i365_set(u_short sock, u_short reg, u_char data) 254 { 255 unsigned long flags; 256 spin_lock_irqsave(&bus_lock,flags); 257 { 258 kio_addr_t port = socket[sock].ioaddr; 259 u_char val = I365_REG(socket[sock].psock, reg); 260 outb(val, port); outb(data, port+1); 261 spin_unlock_irqrestore(&bus_lock,flags); 262 } 263 } 264 265 static void i365_bset(u_short sock, u_short reg, u_char mask) 266 { 267 u_char d = i365_get(sock, reg); 268 d |= mask; 269 i365_set(sock, reg, d); 270 } 271 272 static void i365_bclr(u_short sock, u_short reg, u_char mask) 273 { 274 u_char d = i365_get(sock, reg); 275 d &= ~mask; 276 i365_set(sock, reg, d); 277 } 278 279 static void i365_bflip(u_short sock, u_short reg, u_char mask, int b) 280 { 281 u_char d = i365_get(sock, reg); 282 if (b) 283 d |= mask; 284 else 285 d &= ~mask; 286 i365_set(sock, reg, d); 287 } 288 289 static u_short i365_get_pair(u_short sock, u_short reg) 290 { 291 u_short a, b; 292 a = i365_get(sock, reg); 293 b = i365_get(sock, reg+1); 294 return (a + (b<<8)); 295 } 296 297 static void i365_set_pair(u_short sock, u_short reg, u_short data) 298 { 299 i365_set(sock, reg, data & 0xff); 300 i365_set(sock, reg+1, data >> 8); 301 } 302 303 /*====================================================================== 304 305 Code to save and restore global state information for Cirrus 306 PD67xx controllers, and to set and report global configuration 307 options. 308 309 The VIA controllers also use these routines, as they are mostly 310 Cirrus lookalikes, without the timing registers. 311 312 ======================================================================*/ 313 314 #define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b)))) 315 316 static void cirrus_get_state(u_short s) 317 { 318 int i; 319 cirrus_state_t *p = &socket[s].state.cirrus; 320 p->misc1 = i365_get(s, PD67_MISC_CTL_1); 321 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); 322 p->misc2 = i365_get(s, PD67_MISC_CTL_2); 323 for (i = 0; i < 6; i++) 324 p->timer[i] = i365_get(s, PD67_TIME_SETUP(0)+i); 325 } 326 327 static void cirrus_set_state(u_short s) 328 { 329 int i; 330 u_char misc; 331 cirrus_state_t *p = &socket[s].state.cirrus; 332 333 misc = i365_get(s, PD67_MISC_CTL_2); 334 i365_set(s, PD67_MISC_CTL_2, p->misc2); 335 if (misc & PD67_MC2_SUSPEND) mdelay(50); 336 misc = i365_get(s, PD67_MISC_CTL_1); 337 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); 338 i365_set(s, PD67_MISC_CTL_1, misc | p->misc1); 339 for (i = 0; i < 6; i++) 340 i365_set(s, PD67_TIME_SETUP(0)+i, p->timer[i]); 341 } 342 343 static u_int __init cirrus_set_opts(u_short s, char *buf) 344 { 345 struct i82365_socket *t = &socket[s]; 346 cirrus_state_t *p = &socket[s].state.cirrus; 347 u_int mask = 0xffff; 348 349 if (has_ring == -1) has_ring = 1; 350 flip(p->misc2, PD67_MC2_IRQ15_RI, has_ring); 351 flip(p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode); 352 flip(p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass); 353 if (p->misc2 & PD67_MC2_IRQ15_RI) 354 strcat(buf, " [ring]"); 355 if (p->misc2 & PD67_MC2_DYNAMIC_MODE) 356 strcat(buf, " [dyn mode]"); 357 if (p->misc2 & PD67_MC2_FREQ_BYPASS) 358 strcat(buf, " [freq bypass]"); 359 if (p->misc1 & PD67_MC1_INPACK_ENA) 360 strcat(buf, " [inpack]"); 361 if (p->misc2 & PD67_MC2_IRQ15_RI) 362 mask &= ~0x8000; 363 if (has_led > 0) { 364 strcat(buf, " [led]"); 365 mask &= ~0x1000; 366 } 367 if (has_dma > 0) { 368 strcat(buf, " [dma]"); 369 mask &= ~0x0600; 370 } 371 if (!(t->flags & IS_VIA)) { 372 if (setup_time >= 0) 373 p->timer[0] = p->timer[3] = setup_time; 374 if (cmd_time > 0) { 375 p->timer[1] = cmd_time; 376 p->timer[4] = cmd_time*2+4; 377 } 378 if (p->timer[1] == 0) { 379 p->timer[1] = 6; p->timer[4] = 16; 380 if (p->timer[0] == 0) 381 p->timer[0] = p->timer[3] = 1; 382 } 383 if (recov_time >= 0) 384 p->timer[2] = p->timer[5] = recov_time; 385 buf += strlen(buf); 386 sprintf(buf, " [%d/%d/%d] [%d/%d/%d]", p->timer[0], p->timer[1], 387 p->timer[2], p->timer[3], p->timer[4], p->timer[5]); 388 } 389 return mask; 390 } 391 392 /*====================================================================== 393 394 Code to save and restore global state information for Vadem VG468 395 and VG469 controllers, and to set and report global configuration 396 options. 397 398 ======================================================================*/ 399 400 static void vg46x_get_state(u_short s) 401 { 402 vg46x_state_t *p = &socket[s].state.vg46x; 403 p->ctl = i365_get(s, VG468_CTL); 404 if (socket[s].type == IS_VG469) 405 p->ema = i365_get(s, VG469_EXT_MODE); 406 } 407 408 static void vg46x_set_state(u_short s) 409 { 410 vg46x_state_t *p = &socket[s].state.vg46x; 411 i365_set(s, VG468_CTL, p->ctl); 412 if (socket[s].type == IS_VG469) 413 i365_set(s, VG469_EXT_MODE, p->ema); 414 } 415 416 static u_int __init vg46x_set_opts(u_short s, char *buf) 417 { 418 vg46x_state_t *p = &socket[s].state.vg46x; 419 420 flip(p->ctl, VG468_CTL_ASYNC, async_clock); 421 flip(p->ema, VG469_MODE_CABLE, cable_mode); 422 if (p->ctl & VG468_CTL_ASYNC) 423 strcat(buf, " [async]"); 424 if (p->ctl & VG468_CTL_INPACK) 425 strcat(buf, " [inpack]"); 426 if (socket[s].type == IS_VG469) { 427 u_char vsel = i365_get(s, VG469_VSELECT); 428 if (vsel & VG469_VSEL_EXT_STAT) { 429 strcat(buf, " [ext mode]"); 430 if (vsel & VG469_VSEL_EXT_BUS) 431 strcat(buf, " [isa buf]"); 432 } 433 if (p->ema & VG469_MODE_CABLE) 434 strcat(buf, " [cable]"); 435 if (p->ema & VG469_MODE_COMPAT) 436 strcat(buf, " [c step]"); 437 } 438 return 0xffff; 439 } 440 441 /*====================================================================== 442 443 Generic routines to get and set controller options 444 445 ======================================================================*/ 446 447 static void get_bridge_state(u_short s) 448 { 449 struct i82365_socket *t = &socket[s]; 450 if (t->flags & IS_CIRRUS) 451 cirrus_get_state(s); 452 else if (t->flags & IS_VADEM) 453 vg46x_get_state(s); 454 } 455 456 static void set_bridge_state(u_short s) 457 { 458 struct i82365_socket *t = &socket[s]; 459 if (t->flags & IS_CIRRUS) 460 cirrus_set_state(s); 461 else { 462 i365_set(s, I365_GBLCTL, 0x00); 463 i365_set(s, I365_GENCTL, 0x00); 464 } 465 i365_bflip(s, I365_INTCTL, I365_INTR_ENA, t->intr); 466 if (t->flags & IS_VADEM) 467 vg46x_set_state(s); 468 } 469 470 static u_int __init set_bridge_opts(u_short s, u_short ns) 471 { 472 u_short i; 473 u_int m = 0xffff; 474 char buf[128]; 475 476 for (i = s; i < s+ns; i++) { 477 if (socket[i].flags & IS_ALIVE) { 478 printk(KERN_INFO " host opts [%d]: already alive!\n", i); 479 continue; 480 } 481 buf[0] = '\0'; 482 get_bridge_state(i); 483 if (socket[i].flags & IS_CIRRUS) 484 m = cirrus_set_opts(i, buf); 485 else if (socket[i].flags & IS_VADEM) 486 m = vg46x_set_opts(i, buf); 487 set_bridge_state(i); 488 printk(KERN_INFO " host opts [%d]:%s\n", i, 489 (*buf) ? buf : " none"); 490 } 491 return m; 492 } 493 494 /*====================================================================== 495 496 Interrupt testing code, for ISA and PCI interrupts 497 498 ======================================================================*/ 499 500 static volatile u_int irq_hits; 501 static u_short irq_sock; 502 503 static irqreturn_t i365_count_irq(int irq, void *dev, struct pt_regs *regs) 504 { 505 i365_get(irq_sock, I365_CSC); 506 irq_hits++; 507 debug(2, "-> hit on irq %d\n", irq); 508 return IRQ_HANDLED; 509 } 510 511 static u_int __init test_irq(u_short sock, int irq) 512 { 513 debug(2, " testing ISA irq %d\n", irq); 514 if (request_irq(irq, i365_count_irq, 0, "scan", i365_count_irq) != 0) 515 return 1; 516 irq_hits = 0; irq_sock = sock; 517 msleep(10); 518 if (irq_hits) { 519 free_irq(irq, i365_count_irq); 520 debug(2, " spurious hit!\n"); 521 return 1; 522 } 523 524 /* Generate one interrupt */ 525 i365_set(sock, I365_CSCINT, I365_CSC_DETECT | (irq << 4)); 526 i365_bset(sock, I365_GENCTL, I365_CTL_SW_IRQ); 527 udelay(1000); 528 529 free_irq(irq, i365_count_irq); 530 531 /* mask all interrupts */ 532 i365_set(sock, I365_CSCINT, 0); 533 debug(2, " hits = %d\n", irq_hits); 534 535 return (irq_hits != 1); 536 } 537 538 static u_int __init isa_scan(u_short sock, u_int mask0) 539 { 540 u_int mask1 = 0; 541 int i; 542 543 #ifdef __alpha__ 544 #define PIC 0x4d0 545 /* Don't probe level-triggered interrupts -- reserved for PCI */ 546 mask0 &= ~(inb(PIC) | (inb(PIC+1) << 8)); 547 #endif 548 549 if (do_scan) { 550 set_bridge_state(sock); 551 i365_set(sock, I365_CSCINT, 0); 552 for (i = 0; i < 16; i++) 553 if ((mask0 & (1 << i)) && (test_irq(sock, i) == 0)) 554 mask1 |= (1 << i); 555 for (i = 0; i < 16; i++) 556 if ((mask1 & (1 << i)) && (test_irq(sock, i) != 0)) 557 mask1 ^= (1 << i); 558 } 559 560 printk(KERN_INFO " ISA irqs ("); 561 if (mask1) { 562 printk("scanned"); 563 } else { 564 /* Fallback: just find interrupts that aren't in use */ 565 for (i = 0; i < 16; i++) 566 if ((mask0 & (1 << i)) && (_check_irq(i, 0) == 0)) 567 mask1 |= (1 << i); 568 printk("default"); 569 /* If scan failed, default to polled status */ 570 if (!cs_irq && (poll_interval == 0)) poll_interval = HZ; 571 } 572 printk(") = "); 573 574 for (i = 0; i < 16; i++) 575 if (mask1 & (1<<i)) 576 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i); 577 if (mask1 == 0) printk("none!"); 578 579 return mask1; 580 } 581 582 /*====================================================================*/ 583 584 /* Time conversion functions */ 585 586 static int to_cycles(int ns) 587 { 588 return ns/cycle_time; 589 } 590 591 /*====================================================================*/ 592 593 static int __init identify(kio_addr_t port, u_short sock) 594 { 595 u_char val; 596 int type = -1; 597 598 /* Use the next free entry in the socket table */ 599 socket[sockets].ioaddr = port; 600 socket[sockets].psock = sock; 601 602 /* Wake up a sleepy Cirrus controller */ 603 if (wakeup) { 604 i365_bclr(sockets, PD67_MISC_CTL_2, PD67_MC2_SUSPEND); 605 /* Pause at least 50 ms */ 606 mdelay(50); 607 } 608 609 if ((val = i365_get(sockets, I365_IDENT)) & 0x70) 610 return -1; 611 switch (val) { 612 case 0x82: 613 type = IS_I82365A; break; 614 case 0x83: 615 type = IS_I82365B; break; 616 case 0x84: 617 type = IS_I82365DF; break; 618 case 0x88: case 0x89: case 0x8a: 619 type = IS_IBM; break; 620 } 621 622 /* Check for Vadem VG-468 chips */ 623 outb(0x0e, port); 624 outb(0x37, port); 625 i365_bset(sockets, VG468_MISC, VG468_MISC_VADEMREV); 626 val = i365_get(sockets, I365_IDENT); 627 if (val & I365_IDENT_VADEM) { 628 i365_bclr(sockets, VG468_MISC, VG468_MISC_VADEMREV); 629 type = ((val & 7) >= 4) ? IS_VG469 : IS_VG468; 630 } 631 632 /* Check for Ricoh chips */ 633 val = i365_get(sockets, RF5C_CHIP_ID); 634 if ((val == RF5C_CHIP_RF5C296) || (val == RF5C_CHIP_RF5C396)) 635 type = IS_RF5Cx96; 636 637 /* Check for Cirrus CL-PD67xx chips */ 638 i365_set(sockets, PD67_CHIP_INFO, 0); 639 val = i365_get(sockets, PD67_CHIP_INFO); 640 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { 641 val = i365_get(sockets, PD67_CHIP_INFO); 642 if ((val & PD67_INFO_CHIP_ID) == 0) { 643 type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; 644 i365_set(sockets, PD67_EXT_INDEX, 0xe5); 645 if (i365_get(sockets, PD67_EXT_INDEX) != 0xe5) 646 type = IS_VT83C469; 647 } 648 } 649 return type; 650 } /* identify */ 651 652 /*====================================================================== 653 654 See if a card is present, powered up, in IO mode, and already 655 bound to a (non PC Card) Linux driver. We leave these alone. 656 657 We make an exception for cards that seem to be serial devices. 658 659 ======================================================================*/ 660 661 static int __init is_alive(u_short sock) 662 { 663 u_char stat; 664 kio_addr_t start, stop; 665 666 stat = i365_get(sock, I365_STATUS); 667 start = i365_get_pair(sock, I365_IO(0)+I365_W_START); 668 stop = i365_get_pair(sock, I365_IO(0)+I365_W_STOP); 669 if ((stat & I365_CS_DETECT) && (stat & I365_CS_POWERON) && 670 (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD) && 671 (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(0)) && 672 ((start & 0xfeef) != 0x02e8)) { 673 if (!request_region(start, stop-start+1, "i82365")) 674 return 1; 675 release_region(start, stop-start+1); 676 } 677 678 return 0; 679 } 680 681 /*====================================================================*/ 682 683 static void __init add_socket(kio_addr_t port, int psock, int type) 684 { 685 socket[sockets].ioaddr = port; 686 socket[sockets].psock = psock; 687 socket[sockets].type = type; 688 socket[sockets].flags = pcic[type].flags; 689 if (is_alive(sockets)) 690 socket[sockets].flags |= IS_ALIVE; 691 sockets++; 692 } 693 694 static void __init add_pcic(int ns, int type) 695 { 696 u_int mask = 0, i, base; 697 int isa_irq = 0; 698 struct i82365_socket *t = &socket[sockets-ns]; 699 700 base = sockets-ns; 701 if (t->ioaddr > 0) { 702 if (!request_region(t->ioaddr, 2, "i82365")) { 703 printk(KERN_ERR "i82365: IO region conflict at %#lx, not available\n", 704 t->ioaddr); 705 return; 706 } 707 } 708 709 if (base == 0) printk("\n"); 710 printk(KERN_INFO " %s", pcic[type].name); 711 printk(" ISA-to-PCMCIA at port %#lx ofs 0x%02x", 712 t->ioaddr, t->psock*0x40); 713 printk(", %d socket%s\n", ns, ((ns > 1) ? "s" : "")); 714 715 /* Set host options, build basic interrupt mask */ 716 if (irq_list_count == 0) 717 mask = irq_mask; 718 else 719 for (i = mask = 0; i < irq_list_count; i++) 720 mask |= (1<<irq_list[i]); 721 mask &= I365_MASK & set_bridge_opts(base, ns); 722 /* Scan for ISA interrupts */ 723 mask = isa_scan(base, mask); 724 725 /* Poll if only two interrupts available */ 726 if (!poll_interval) { 727 u_int tmp = (mask & 0xff20); 728 tmp = tmp & (tmp-1); 729 if ((tmp & (tmp-1)) == 0) 730 poll_interval = HZ; 731 } 732 /* Only try an ISA cs_irq if this is the first controller */ 733 if (!grab_irq && (cs_irq || !poll_interval)) { 734 /* Avoid irq 12 unless it is explicitly requested */ 735 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12)); 736 for (cs_irq = 15; cs_irq > 0; cs_irq--) 737 if ((cs_mask & (1 << cs_irq)) && 738 (_check_irq(cs_irq, 0) == 0)) 739 break; 740 if (cs_irq) { 741 grab_irq = 1; 742 isa_irq = cs_irq; 743 printk(" status change on irq %d\n", cs_irq); 744 } 745 } 746 747 if (!isa_irq) { 748 if (poll_interval == 0) 749 poll_interval = HZ; 750 printk(" polling interval = %d ms\n", 751 poll_interval * 1000 / HZ); 752 753 } 754 755 /* Update socket interrupt information, capabilities */ 756 for (i = 0; i < ns; i++) { 757 t[i].socket.features |= SS_CAP_PCCARD; 758 t[i].socket.map_size = 0x1000; 759 t[i].socket.irq_mask = mask; 760 t[i].cs_irq = isa_irq; 761 } 762 763 } /* add_pcic */ 764 765 /*====================================================================*/ 766 767 #ifdef CONFIG_PNP 768 static struct isapnp_device_id id_table[] __initdata = { 769 { ISAPNP_ANY_ID, ISAPNP_ANY_ID, ISAPNP_VENDOR('P', 'N', 'P'), 770 ISAPNP_FUNCTION(0x0e00), (unsigned long) "Intel 82365-Compatible" }, 771 { ISAPNP_ANY_ID, ISAPNP_ANY_ID, ISAPNP_VENDOR('P', 'N', 'P'), 772 ISAPNP_FUNCTION(0x0e01), (unsigned long) "Cirrus Logic CL-PD6720" }, 773 { ISAPNP_ANY_ID, ISAPNP_ANY_ID, ISAPNP_VENDOR('P', 'N', 'P'), 774 ISAPNP_FUNCTION(0x0e02), (unsigned long) "VLSI VL82C146" }, 775 { 0 } 776 }; 777 MODULE_DEVICE_TABLE(isapnp, id_table); 778 779 static struct pnp_dev *i82365_pnpdev; 780 #endif 781 782 static void __init isa_probe(void) 783 { 784 int i, j, sock, k, ns, id; 785 kio_addr_t port; 786 #ifdef CONFIG_PNP 787 struct isapnp_device_id *devid; 788 struct pnp_dev *dev; 789 790 for (devid = id_table; devid->vendor; devid++) { 791 if ((dev = pnp_find_dev(NULL, devid->vendor, devid->function, NULL))) { 792 793 if (pnp_device_attach(dev) < 0) 794 continue; 795 796 if (pnp_activate_dev(dev) < 0) { 797 printk("activate failed\n"); 798 pnp_device_detach(dev); 799 break; 800 } 801 802 if (!pnp_port_valid(dev, 0)) { 803 printk("invalid resources ?\n"); 804 pnp_device_detach(dev); 805 break; 806 } 807 i365_base = pnp_port_start(dev, 0); 808 i82365_pnpdev = dev; 809 break; 810 } 811 } 812 #endif 813 814 if (!request_region(i365_base, 2, "i82365")) { 815 if (sockets == 0) 816 printk("port conflict at %#lx\n", i365_base); 817 return; 818 } 819 820 id = identify(i365_base, 0); 821 if ((id == IS_I82365DF) && (identify(i365_base, 1) != id)) { 822 for (i = 0; i < 4; i++) { 823 if (i == ignore) continue; 824 port = i365_base + ((i & 1) << 2) + ((i & 2) << 1); 825 sock = (i & 1) << 1; 826 if (identify(port, sock) == IS_I82365DF) { 827 add_socket(port, sock, IS_VLSI); 828 add_pcic(1, IS_VLSI); 829 } 830 } 831 } else { 832 for (i = 0; i < 8; i += 2) { 833 if (sockets && !extra_sockets && (i == 4)) 834 break; 835 port = i365_base + 2*(i>>2); 836 sock = (i & 3); 837 id = identify(port, sock); 838 if (id < 0) continue; 839 840 for (j = ns = 0; j < 2; j++) { 841 /* Does the socket exist? */ 842 if ((ignore == i+j) || (identify(port, sock+j) < 0)) 843 continue; 844 /* Check for bad socket decode */ 845 for (k = 0; k <= sockets; k++) 846 i365_set(k, I365_MEM(0)+I365_W_OFF, k); 847 for (k = 0; k <= sockets; k++) 848 if (i365_get(k, I365_MEM(0)+I365_W_OFF) != k) 849 break; 850 if (k <= sockets) break; 851 add_socket(port, sock+j, id); ns++; 852 } 853 if (ns != 0) add_pcic(ns, id); 854 } 855 } 856 } 857 858 /*====================================================================*/ 859 860 static irqreturn_t pcic_interrupt(int irq, void *dev, 861 struct pt_regs *regs) 862 { 863 int i, j, csc; 864 u_int events, active; 865 u_long flags = 0; 866 int handled = 0; 867 868 debug(4, "pcic_interrupt(%d)\n", irq); 869 870 for (j = 0; j < 20; j++) { 871 active = 0; 872 for (i = 0; i < sockets; i++) { 873 if (socket[i].cs_irq != irq) 874 continue; 875 handled = 1; 876 ISA_LOCK(i, flags); 877 csc = i365_get(i, I365_CSC); 878 if ((csc == 0) || (i365_get(i, I365_IDENT) & 0x70)) { 879 ISA_UNLOCK(i, flags); 880 continue; 881 } 882 events = (csc & I365_CSC_DETECT) ? SS_DETECT : 0; 883 884 if (i365_get(i, I365_INTCTL) & I365_PC_IOCARD) 885 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; 886 else { 887 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; 888 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; 889 events |= (csc & I365_CSC_READY) ? SS_READY : 0; 890 } 891 ISA_UNLOCK(i, flags); 892 debug(2, "socket %d event 0x%02x\n", i, events); 893 894 if (events) 895 pcmcia_parse_events(&socket[i].socket, events); 896 897 active |= events; 898 } 899 if (!active) break; 900 } 901 if (j == 20) 902 printk(KERN_NOTICE "i82365: infinite loop in interrupt handler\n"); 903 904 debug(4, "interrupt done\n"); 905 return IRQ_RETVAL(handled); 906 } /* pcic_interrupt */ 907 908 static void pcic_interrupt_wrapper(u_long data) 909 { 910 pcic_interrupt(0, NULL, NULL); 911 poll_timer.expires = jiffies + poll_interval; 912 add_timer(&poll_timer); 913 } 914 915 /*====================================================================*/ 916 917 static int i365_get_status(u_short sock, u_int *value) 918 { 919 u_int status; 920 921 status = i365_get(sock, I365_STATUS); 922 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) 923 ? SS_DETECT : 0; 924 925 if (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD) 926 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; 927 else { 928 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; 929 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; 930 } 931 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; 932 *value |= (status & I365_CS_READY) ? SS_READY : 0; 933 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; 934 935 if (socket[sock].type == IS_VG469) { 936 status = i365_get(sock, VG469_VSENSE); 937 if (socket[sock].psock & 1) { 938 *value |= (status & VG469_VSENSE_B_VS1) ? 0 : SS_3VCARD; 939 *value |= (status & VG469_VSENSE_B_VS2) ? 0 : SS_XVCARD; 940 } else { 941 *value |= (status & VG469_VSENSE_A_VS1) ? 0 : SS_3VCARD; 942 *value |= (status & VG469_VSENSE_A_VS2) ? 0 : SS_XVCARD; 943 } 944 } 945 946 debug(1, "GetStatus(%d) = %#4.4x\n", sock, *value); 947 return 0; 948 } /* i365_get_status */ 949 950 /*====================================================================*/ 951 952 static int i365_get_socket(u_short sock, socket_state_t *state) 953 { 954 struct i82365_socket *t = &socket[sock]; 955 u_char reg, vcc, vpp; 956 957 reg = i365_get(sock, I365_POWER); 958 state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0; 959 state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0; 960 vcc = reg & I365_VCC_MASK; vpp = reg & I365_VPP1_MASK; 961 state->Vcc = state->Vpp = 0; 962 if (t->flags & IS_CIRRUS) { 963 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) { 964 if (reg & I365_VCC_5V) state->Vcc = 33; 965 if (vpp == I365_VPP1_5V) state->Vpp = 33; 966 } else { 967 if (reg & I365_VCC_5V) state->Vcc = 50; 968 if (vpp == I365_VPP1_5V) state->Vpp = 50; 969 } 970 if (vpp == I365_VPP1_12V) state->Vpp = 120; 971 } else if (t->flags & IS_VG_PWR) { 972 if (i365_get(sock, VG469_VSELECT) & VG469_VSEL_VCC) { 973 if (reg & I365_VCC_5V) state->Vcc = 33; 974 if (vpp == I365_VPP1_5V) state->Vpp = 33; 975 } else { 976 if (reg & I365_VCC_5V) state->Vcc = 50; 977 if (vpp == I365_VPP1_5V) state->Vpp = 50; 978 } 979 if (vpp == I365_VPP1_12V) state->Vpp = 120; 980 } else if (t->flags & IS_DF_PWR) { 981 if (vcc == I365_VCC_3V) state->Vcc = 33; 982 if (vcc == I365_VCC_5V) state->Vcc = 50; 983 if (vpp == I365_VPP1_5V) state->Vpp = 50; 984 if (vpp == I365_VPP1_12V) state->Vpp = 120; 985 } else { 986 if (reg & I365_VCC_5V) { 987 state->Vcc = 50; 988 if (vpp == I365_VPP1_5V) state->Vpp = 50; 989 if (vpp == I365_VPP1_12V) state->Vpp = 120; 990 } 991 } 992 993 /* IO card, RESET flags, IO interrupt */ 994 reg = i365_get(sock, I365_INTCTL); 995 state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET; 996 if (reg & I365_PC_IOCARD) state->flags |= SS_IOCARD; 997 state->io_irq = reg & I365_IRQ_MASK; 998 999 /* speaker control */ 1000 if (t->flags & IS_CIRRUS) { 1001 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_SPKR_ENA) 1002 state->flags |= SS_SPKR_ENA; 1003 } 1004 1005 /* Card status change mask */ 1006 reg = i365_get(sock, I365_CSCINT); 1007 state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0; 1008 if (state->flags & SS_IOCARD) 1009 state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0; 1010 else { 1011 state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0; 1012 state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0; 1013 state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0; 1014 } 1015 1016 debug(1, "GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, " 1017 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags, 1018 state->Vcc, state->Vpp, state->io_irq, state->csc_mask); 1019 return 0; 1020 } /* i365_get_socket */ 1021 1022 /*====================================================================*/ 1023 1024 static int i365_set_socket(u_short sock, socket_state_t *state) 1025 { 1026 struct i82365_socket *t = &socket[sock]; 1027 u_char reg; 1028 1029 debug(1, "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " 1030 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags, 1031 state->Vcc, state->Vpp, state->io_irq, state->csc_mask); 1032 1033 /* First set global controller options */ 1034 set_bridge_state(sock); 1035 1036 /* IO card, RESET flag, IO interrupt */ 1037 reg = t->intr; 1038 reg |= state->io_irq; 1039 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; 1040 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; 1041 i365_set(sock, I365_INTCTL, reg); 1042 1043 reg = I365_PWR_NORESET; 1044 if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO; 1045 if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT; 1046 1047 if (t->flags & IS_CIRRUS) { 1048 if (state->Vpp != 0) { 1049 if (state->Vpp == 120) 1050 reg |= I365_VPP1_12V; 1051 else if (state->Vpp == state->Vcc) 1052 reg |= I365_VPP1_5V; 1053 else return -EINVAL; 1054 } 1055 if (state->Vcc != 0) { 1056 reg |= I365_VCC_5V; 1057 if (state->Vcc == 33) 1058 i365_bset(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); 1059 else if (state->Vcc == 50) 1060 i365_bclr(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); 1061 else return -EINVAL; 1062 } 1063 } else if (t->flags & IS_VG_PWR) { 1064 if (state->Vpp != 0) { 1065 if (state->Vpp == 120) 1066 reg |= I365_VPP1_12V; 1067 else if (state->Vpp == state->Vcc) 1068 reg |= I365_VPP1_5V; 1069 else return -EINVAL; 1070 } 1071 if (state->Vcc != 0) { 1072 reg |= I365_VCC_5V; 1073 if (state->Vcc == 33) 1074 i365_bset(sock, VG469_VSELECT, VG469_VSEL_VCC); 1075 else if (state->Vcc == 50) 1076 i365_bclr(sock, VG469_VSELECT, VG469_VSEL_VCC); 1077 else return -EINVAL; 1078 } 1079 } else if (t->flags & IS_DF_PWR) { 1080 switch (state->Vcc) { 1081 case 0: break; 1082 case 33: reg |= I365_VCC_3V; break; 1083 case 50: reg |= I365_VCC_5V; break; 1084 default: return -EINVAL; 1085 } 1086 switch (state->Vpp) { 1087 case 0: break; 1088 case 50: reg |= I365_VPP1_5V; break; 1089 case 120: reg |= I365_VPP1_12V; break; 1090 default: return -EINVAL; 1091 } 1092 } else { 1093 switch (state->Vcc) { 1094 case 0: break; 1095 case 50: reg |= I365_VCC_5V; break; 1096 default: return -EINVAL; 1097 } 1098 switch (state->Vpp) { 1099 case 0: break; 1100 case 50: reg |= I365_VPP1_5V | I365_VPP2_5V; break; 1101 case 120: reg |= I365_VPP1_12V | I365_VPP2_12V; break; 1102 default: return -EINVAL; 1103 } 1104 } 1105 1106 if (reg != i365_get(sock, I365_POWER)) 1107 i365_set(sock, I365_POWER, reg); 1108 1109 /* Chipset-specific functions */ 1110 if (t->flags & IS_CIRRUS) { 1111 /* Speaker control */ 1112 i365_bflip(sock, PD67_MISC_CTL_1, PD67_MC1_SPKR_ENA, 1113 state->flags & SS_SPKR_ENA); 1114 } 1115 1116 /* Card status change interrupt mask */ 1117 reg = t->cs_irq << 4; 1118 if (state->csc_mask & SS_DETECT) reg |= I365_CSC_DETECT; 1119 if (state->flags & SS_IOCARD) { 1120 if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG; 1121 } else { 1122 if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1; 1123 if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2; 1124 if (state->csc_mask & SS_READY) reg |= I365_CSC_READY; 1125 } 1126 i365_set(sock, I365_CSCINT, reg); 1127 i365_get(sock, I365_CSC); 1128 1129 return 0; 1130 } /* i365_set_socket */ 1131 1132 /*====================================================================*/ 1133 1134 static int i365_set_io_map(u_short sock, struct pccard_io_map *io) 1135 { 1136 u_char map, ioctl; 1137 1138 debug(1, "SetIOMap(%d, %d, %#2.2x, %d ns, " 1139 "%#lx-%#lx)\n", sock, io->map, io->flags, 1140 io->speed, io->start, io->stop); 1141 map = io->map; 1142 if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) || 1143 (io->stop < io->start)) return -EINVAL; 1144 /* Turn off the window before changing anything */ 1145 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(map)) 1146 i365_bclr(sock, I365_ADDRWIN, I365_ENA_IO(map)); 1147 i365_set_pair(sock, I365_IO(map)+I365_W_START, io->start); 1148 i365_set_pair(sock, I365_IO(map)+I365_W_STOP, io->stop); 1149 ioctl = i365_get(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map); 1150 if (io->speed) ioctl |= I365_IOCTL_WAIT(map); 1151 if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map); 1152 if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map); 1153 if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map); 1154 i365_set(sock, I365_IOCTL, ioctl); 1155 /* Turn on the window if necessary */ 1156 if (io->flags & MAP_ACTIVE) 1157 i365_bset(sock, I365_ADDRWIN, I365_ENA_IO(map)); 1158 return 0; 1159 } /* i365_set_io_map */ 1160 1161 /*====================================================================*/ 1162 1163 static int i365_set_mem_map(u_short sock, struct pccard_mem_map *mem) 1164 { 1165 u_short base, i; 1166 u_char map; 1167 1168 debug(1, "SetMemMap(%d, %d, %#2.2x, %d ns, %#lx-%#lx, " 1169 "%#x)\n", sock, mem->map, mem->flags, mem->speed, 1170 mem->res->start, mem->res->end, mem->card_start); 1171 1172 map = mem->map; 1173 if ((map > 4) || (mem->card_start > 0x3ffffff) || 1174 (mem->res->start > mem->res->end) || (mem->speed > 1000)) 1175 return -EINVAL; 1176 if ((mem->res->start > 0xffffff) || (mem->res->end > 0xffffff)) 1177 return -EINVAL; 1178 1179 /* Turn off the window before changing anything */ 1180 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) 1181 i365_bclr(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 1182 1183 base = I365_MEM(map); 1184 i = (mem->res->start >> 12) & 0x0fff; 1185 if (mem->flags & MAP_16BIT) i |= I365_MEM_16BIT; 1186 if (mem->flags & MAP_0WS) i |= I365_MEM_0WS; 1187 i365_set_pair(sock, base+I365_W_START, i); 1188 1189 i = (mem->res->end >> 12) & 0x0fff; 1190 switch (to_cycles(mem->speed)) { 1191 case 0: break; 1192 case 1: i |= I365_MEM_WS0; break; 1193 case 2: i |= I365_MEM_WS1; break; 1194 default: i |= I365_MEM_WS1 | I365_MEM_WS0; break; 1195 } 1196 i365_set_pair(sock, base+I365_W_STOP, i); 1197 1198 i = ((mem->card_start - mem->res->start) >> 12) & 0x3fff; 1199 if (mem->flags & MAP_WRPROT) i |= I365_MEM_WRPROT; 1200 if (mem->flags & MAP_ATTRIB) i |= I365_MEM_REG; 1201 i365_set_pair(sock, base+I365_W_OFF, i); 1202 1203 /* Turn on the window if necessary */ 1204 if (mem->flags & MAP_ACTIVE) 1205 i365_bset(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 1206 return 0; 1207 } /* i365_set_mem_map */ 1208 1209 #if 0 /* driver model ordering issue */ 1210 /*====================================================================== 1211 1212 Routines for accessing socket information and register dumps via 1213 /sys/class/pcmcia_socket/... 1214 1215 ======================================================================*/ 1216 1217 static ssize_t show_info(struct class_device *class_dev, char *buf) 1218 { 1219 struct i82365_socket *s = container_of(class_dev, struct i82365_socket, socket.dev); 1220 return sprintf(buf, "type: %s\npsock: %d\n", 1221 pcic[s->type].name, s->psock); 1222 } 1223 1224 static ssize_t show_exca(struct class_device *class_dev, char *buf) 1225 { 1226 struct i82365_socket *s = container_of(class_dev, struct i82365_socket, socket.dev); 1227 unsigned short sock; 1228 int i; 1229 ssize_t ret = 0; 1230 unsigned long flags = 0; 1231 1232 sock = s->number; 1233 1234 ISA_LOCK(sock, flags); 1235 for (i = 0; i < 0x40; i += 4) { 1236 ret += sprintf(buf, "%02x %02x %02x %02x%s", 1237 i365_get(sock,i), i365_get(sock,i+1), 1238 i365_get(sock,i+2), i365_get(sock,i+3), 1239 ((i % 16) == 12) ? "\n" : " "); 1240 buf += ret; 1241 } 1242 ISA_UNLOCK(sock, flags); 1243 1244 return ret; 1245 } 1246 1247 static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL); 1248 static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL); 1249 #endif 1250 1251 /*====================================================================*/ 1252 1253 /* this is horribly ugly... proper locking needs to be done here at 1254 * some time... */ 1255 #define LOCKED(x) do { \ 1256 int retval; \ 1257 unsigned long flags; \ 1258 spin_lock_irqsave(&isa_lock, flags); \ 1259 retval = x; \ 1260 spin_unlock_irqrestore(&isa_lock, flags); \ 1261 return retval; \ 1262 } while (0) 1263 1264 1265 static int pcic_get_status(struct pcmcia_socket *s, u_int *value) 1266 { 1267 unsigned int sock = container_of(s, struct i82365_socket, socket)->number; 1268 1269 if (socket[sock].flags & IS_ALIVE) { 1270 *value = 0; 1271 return -EINVAL; 1272 } 1273 1274 LOCKED(i365_get_status(sock, value)); 1275 } 1276 1277 static int pcic_get_socket(struct pcmcia_socket *s, socket_state_t *state) 1278 { 1279 unsigned int sock = container_of(s, struct i82365_socket, socket)->number; 1280 1281 if (socket[sock].flags & IS_ALIVE) 1282 return -EINVAL; 1283 1284 LOCKED(i365_get_socket(sock, state)); 1285 } 1286 1287 static int pcic_set_socket(struct pcmcia_socket *s, socket_state_t *state) 1288 { 1289 unsigned int sock = container_of(s, struct i82365_socket, socket)->number; 1290 1291 if (socket[sock].flags & IS_ALIVE) 1292 return -EINVAL; 1293 1294 LOCKED(i365_set_socket(sock, state)); 1295 } 1296 1297 static int pcic_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io) 1298 { 1299 unsigned int sock = container_of(s, struct i82365_socket, socket)->number; 1300 if (socket[sock].flags & IS_ALIVE) 1301 return -EINVAL; 1302 1303 LOCKED(i365_set_io_map(sock, io)); 1304 } 1305 1306 static int pcic_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem) 1307 { 1308 unsigned int sock = container_of(s, struct i82365_socket, socket)->number; 1309 if (socket[sock].flags & IS_ALIVE) 1310 return -EINVAL; 1311 1312 LOCKED(i365_set_mem_map(sock, mem)); 1313 } 1314 1315 static int pcic_init(struct pcmcia_socket *s) 1316 { 1317 int i; 1318 struct resource res = { .start = 0, .end = 0x1000 }; 1319 pccard_io_map io = { 0, 0, 0, 0, 1 }; 1320 pccard_mem_map mem = { .res = &res, }; 1321 1322 for (i = 0; i < 2; i++) { 1323 io.map = i; 1324 pcic_set_io_map(s, &io); 1325 } 1326 for (i = 0; i < 5; i++) { 1327 mem.map = i; 1328 pcic_set_mem_map(s, &mem); 1329 } 1330 return 0; 1331 } 1332 1333 static struct pccard_operations pcic_operations = { 1334 .init = pcic_init, 1335 .get_status = pcic_get_status, 1336 .get_socket = pcic_get_socket, 1337 .set_socket = pcic_set_socket, 1338 .set_io_map = pcic_set_io_map, 1339 .set_mem_map = pcic_set_mem_map, 1340 }; 1341 1342 /*====================================================================*/ 1343 1344 static int i82365_suspend(struct device *dev, pm_message_t state, u32 level) 1345 { 1346 int ret = 0; 1347 if (level == SUSPEND_SAVE_STATE) 1348 ret = pcmcia_socket_dev_suspend(dev, state); 1349 return ret; 1350 } 1351 1352 static int i82365_resume(struct device *dev, u32 level) 1353 { 1354 int ret = 0; 1355 if (level == RESUME_RESTORE_STATE) 1356 ret = pcmcia_socket_dev_resume(dev); 1357 return ret; 1358 } 1359 1360 static struct device_driver i82365_driver = { 1361 .name = "i82365", 1362 .bus = &platform_bus_type, 1363 .suspend = i82365_suspend, 1364 .resume = i82365_resume, 1365 }; 1366 1367 static struct platform_device i82365_device = { 1368 .name = "i82365", 1369 .id = 0, 1370 }; 1371 1372 static int __init init_i82365(void) 1373 { 1374 int i, ret; 1375 1376 ret = driver_register(&i82365_driver); 1377 if (ret) 1378 return ret; 1379 1380 ret = platform_device_register(&i82365_device); 1381 if (ret) { 1382 driver_unregister(&i82365_driver); 1383 return ret; 1384 } 1385 1386 printk(KERN_INFO "Intel ISA PCIC probe: "); 1387 sockets = 0; 1388 1389 isa_probe(); 1390 1391 if (sockets == 0) { 1392 printk("not found.\n"); 1393 platform_device_unregister(&i82365_device); 1394 driver_unregister(&i82365_driver); 1395 return -ENODEV; 1396 } 1397 1398 /* Set up interrupt handler(s) */ 1399 if (grab_irq != 0) 1400 request_irq(cs_irq, pcic_interrupt, 0, "i82365", pcic_interrupt); 1401 1402 /* register sockets with the pcmcia core */ 1403 for (i = 0; i < sockets; i++) { 1404 socket[i].socket.dev.dev = &i82365_device.dev; 1405 socket[i].socket.ops = &pcic_operations; 1406 socket[i].socket.resource_ops = &pccard_nonstatic_ops; 1407 socket[i].socket.owner = THIS_MODULE; 1408 socket[i].number = i; 1409 ret = pcmcia_register_socket(&socket[i].socket); 1410 if (!ret) 1411 socket[i].flags |= IS_REGISTERED; 1412 1413 #if 0 /* driver model ordering issue */ 1414 class_device_create_file(&socket[i].socket.dev, 1415 &class_device_attr_info); 1416 class_device_create_file(&socket[i].socket.dev, 1417 &class_device_attr_exca); 1418 #endif 1419 } 1420 1421 /* Finally, schedule a polling interrupt */ 1422 if (poll_interval != 0) { 1423 poll_timer.function = pcic_interrupt_wrapper; 1424 poll_timer.data = 0; 1425 init_timer(&poll_timer); 1426 poll_timer.expires = jiffies + poll_interval; 1427 add_timer(&poll_timer); 1428 } 1429 1430 return 0; 1431 1432 } /* init_i82365 */ 1433 1434 static void __exit exit_i82365(void) 1435 { 1436 int i; 1437 1438 for (i = 0; i < sockets; i++) { 1439 if (socket[i].flags & IS_REGISTERED) 1440 pcmcia_unregister_socket(&socket[i].socket); 1441 } 1442 platform_device_unregister(&i82365_device); 1443 if (poll_interval != 0) 1444 del_timer_sync(&poll_timer); 1445 if (grab_irq != 0) 1446 free_irq(cs_irq, pcic_interrupt); 1447 for (i = 0; i < sockets; i++) { 1448 /* Turn off all interrupt sources! */ 1449 i365_set(i, I365_CSCINT, 0); 1450 release_region(socket[i].ioaddr, 2); 1451 } 1452 release_region(i365_base, 2); 1453 #ifdef CONFIG_PNP 1454 if (i82365_pnpdev) 1455 pnp_disable_dev(i82365_pnpdev); 1456 #endif 1457 driver_unregister(&i82365_driver); 1458 } /* exit_i82365 */ 1459 1460 module_init(init_i82365); 1461 module_exit(exit_i82365); 1462 MODULE_LICENSE("Dual MPL/GPL"); 1463 /*====================================================================*/ 1464