1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microsemi Switchtec(tm) PCIe Management Driver 4 * Copyright (c) 2017, Microsemi Corporation 5 */ 6 7 #include <linux/switchtec.h> 8 #include <linux/switchtec_ioctl.h> 9 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/fs.h> 13 #include <linux/uaccess.h> 14 #include <linux/poll.h> 15 #include <linux/wait.h> 16 #include <linux/io-64-nonatomic-lo-hi.h> 17 #include <linux/nospec.h> 18 19 MODULE_DESCRIPTION("Microsemi Switchtec(tm) PCIe Management Driver"); 20 MODULE_VERSION("0.1"); 21 MODULE_LICENSE("GPL"); 22 MODULE_AUTHOR("Microsemi Corporation"); 23 24 static int max_devices = 16; 25 module_param(max_devices, int, 0644); 26 MODULE_PARM_DESC(max_devices, "max number of switchtec device instances"); 27 28 static bool use_dma_mrpc = true; 29 module_param(use_dma_mrpc, bool, 0644); 30 MODULE_PARM_DESC(use_dma_mrpc, 31 "Enable the use of the DMA MRPC feature"); 32 33 static int nirqs = 32; 34 module_param(nirqs, int, 0644); 35 MODULE_PARM_DESC(nirqs, "number of interrupts to allocate (more may be useful for NTB applications)"); 36 37 static dev_t switchtec_devt; 38 static DEFINE_IDA(switchtec_minor_ida); 39 40 struct class *switchtec_class; 41 EXPORT_SYMBOL_GPL(switchtec_class); 42 43 enum mrpc_state { 44 MRPC_IDLE = 0, 45 MRPC_QUEUED, 46 MRPC_RUNNING, 47 MRPC_DONE, 48 MRPC_IO_ERROR, 49 }; 50 51 struct switchtec_user { 52 struct switchtec_dev *stdev; 53 54 enum mrpc_state state; 55 56 wait_queue_head_t cmd_comp; 57 struct kref kref; 58 struct list_head list; 59 60 bool cmd_done; 61 u32 cmd; 62 u32 status; 63 u32 return_code; 64 size_t data_len; 65 size_t read_len; 66 unsigned char data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 67 int event_cnt; 68 }; 69 70 /* 71 * The MMIO reads to the device_id register should always return the device ID 72 * of the device, otherwise the firmware is probably stuck or unreachable 73 * due to a firmware reset which clears PCI state including the BARs and Memory 74 * Space Enable bits. 75 */ 76 static int is_firmware_running(struct switchtec_dev *stdev) 77 { 78 u32 device = ioread32(&stdev->mmio_sys_info->device_id); 79 80 return stdev->pdev->device == device; 81 } 82 83 static struct switchtec_user *stuser_create(struct switchtec_dev *stdev) 84 { 85 struct switchtec_user *stuser; 86 87 stuser = kzalloc(sizeof(*stuser), GFP_KERNEL); 88 if (!stuser) 89 return ERR_PTR(-ENOMEM); 90 91 get_device(&stdev->dev); 92 stuser->stdev = stdev; 93 kref_init(&stuser->kref); 94 INIT_LIST_HEAD(&stuser->list); 95 init_waitqueue_head(&stuser->cmd_comp); 96 stuser->event_cnt = atomic_read(&stdev->event_cnt); 97 98 dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser); 99 100 return stuser; 101 } 102 103 static void stuser_free(struct kref *kref) 104 { 105 struct switchtec_user *stuser; 106 107 stuser = container_of(kref, struct switchtec_user, kref); 108 109 dev_dbg(&stuser->stdev->dev, "%s: %p\n", __func__, stuser); 110 111 put_device(&stuser->stdev->dev); 112 kfree(stuser); 113 } 114 115 static void stuser_put(struct switchtec_user *stuser) 116 { 117 kref_put(&stuser->kref, stuser_free); 118 } 119 120 static void stuser_set_state(struct switchtec_user *stuser, 121 enum mrpc_state state) 122 { 123 /* requires the mrpc_mutex to already be held when called */ 124 125 const char * const state_names[] = { 126 [MRPC_IDLE] = "IDLE", 127 [MRPC_QUEUED] = "QUEUED", 128 [MRPC_RUNNING] = "RUNNING", 129 [MRPC_DONE] = "DONE", 130 [MRPC_IO_ERROR] = "IO_ERROR", 131 }; 132 133 stuser->state = state; 134 135 dev_dbg(&stuser->stdev->dev, "stuser state %p -> %s", 136 stuser, state_names[state]); 137 } 138 139 static void mrpc_complete_cmd(struct switchtec_dev *stdev); 140 141 static void flush_wc_buf(struct switchtec_dev *stdev) 142 { 143 struct ntb_dbmsg_regs __iomem *mmio_dbmsg; 144 145 /* 146 * odb (outbound doorbell) register is processed by low latency 147 * hardware and w/o side effect 148 */ 149 mmio_dbmsg = (void __iomem *)stdev->mmio_ntb + 150 SWITCHTEC_NTB_REG_DBMSG_OFFSET; 151 ioread32(&mmio_dbmsg->odb); 152 } 153 154 static void mrpc_cmd_submit(struct switchtec_dev *stdev) 155 { 156 /* requires the mrpc_mutex to already be held when called */ 157 158 struct switchtec_user *stuser; 159 160 if (stdev->mrpc_busy) 161 return; 162 163 if (list_empty(&stdev->mrpc_queue)) 164 return; 165 166 stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user, 167 list); 168 169 if (stdev->dma_mrpc) { 170 stdev->dma_mrpc->status = SWITCHTEC_MRPC_STATUS_INPROGRESS; 171 memset(stdev->dma_mrpc->data, 0xFF, SWITCHTEC_MRPC_PAYLOAD_SIZE); 172 } 173 174 stuser_set_state(stuser, MRPC_RUNNING); 175 stdev->mrpc_busy = 1; 176 memcpy_toio(&stdev->mmio_mrpc->input_data, 177 stuser->data, stuser->data_len); 178 flush_wc_buf(stdev); 179 iowrite32(stuser->cmd, &stdev->mmio_mrpc->cmd); 180 181 schedule_delayed_work(&stdev->mrpc_timeout, 182 msecs_to_jiffies(500)); 183 } 184 185 static int mrpc_queue_cmd(struct switchtec_user *stuser) 186 { 187 /* requires the mrpc_mutex to already be held when called */ 188 189 struct switchtec_dev *stdev = stuser->stdev; 190 191 kref_get(&stuser->kref); 192 stuser->read_len = sizeof(stuser->data); 193 stuser_set_state(stuser, MRPC_QUEUED); 194 stuser->cmd_done = false; 195 list_add_tail(&stuser->list, &stdev->mrpc_queue); 196 197 mrpc_cmd_submit(stdev); 198 199 return 0; 200 } 201 202 static void mrpc_cleanup_cmd(struct switchtec_dev *stdev) 203 { 204 /* requires the mrpc_mutex to already be held when called */ 205 206 struct switchtec_user *stuser = list_entry(stdev->mrpc_queue.next, 207 struct switchtec_user, list); 208 209 stuser->cmd_done = true; 210 wake_up_interruptible(&stuser->cmd_comp); 211 list_del_init(&stuser->list); 212 stuser_put(stuser); 213 stdev->mrpc_busy = 0; 214 215 mrpc_cmd_submit(stdev); 216 } 217 218 static void mrpc_complete_cmd(struct switchtec_dev *stdev) 219 { 220 /* requires the mrpc_mutex to already be held when called */ 221 222 struct switchtec_user *stuser; 223 224 if (list_empty(&stdev->mrpc_queue)) 225 return; 226 227 stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user, 228 list); 229 230 if (stdev->dma_mrpc) 231 stuser->status = stdev->dma_mrpc->status; 232 else 233 stuser->status = ioread32(&stdev->mmio_mrpc->status); 234 235 if (stuser->status == SWITCHTEC_MRPC_STATUS_INPROGRESS) 236 return; 237 238 stuser_set_state(stuser, MRPC_DONE); 239 stuser->return_code = 0; 240 241 if (stuser->status != SWITCHTEC_MRPC_STATUS_DONE) 242 goto out; 243 244 if (stdev->dma_mrpc) 245 stuser->return_code = stdev->dma_mrpc->rtn_code; 246 else 247 stuser->return_code = ioread32(&stdev->mmio_mrpc->ret_value); 248 if (stuser->return_code != 0) 249 goto out; 250 251 if (stdev->dma_mrpc) 252 memcpy(stuser->data, &stdev->dma_mrpc->data, 253 stuser->read_len); 254 else 255 memcpy_fromio(stuser->data, &stdev->mmio_mrpc->output_data, 256 stuser->read_len); 257 out: 258 mrpc_cleanup_cmd(stdev); 259 } 260 261 static void mrpc_event_work(struct work_struct *work) 262 { 263 struct switchtec_dev *stdev; 264 265 stdev = container_of(work, struct switchtec_dev, mrpc_work); 266 267 dev_dbg(&stdev->dev, "%s\n", __func__); 268 269 mutex_lock(&stdev->mrpc_mutex); 270 cancel_delayed_work(&stdev->mrpc_timeout); 271 mrpc_complete_cmd(stdev); 272 mutex_unlock(&stdev->mrpc_mutex); 273 } 274 275 static void mrpc_error_complete_cmd(struct switchtec_dev *stdev) 276 { 277 /* requires the mrpc_mutex to already be held when called */ 278 279 struct switchtec_user *stuser; 280 281 if (list_empty(&stdev->mrpc_queue)) 282 return; 283 284 stuser = list_entry(stdev->mrpc_queue.next, 285 struct switchtec_user, list); 286 287 stuser_set_state(stuser, MRPC_IO_ERROR); 288 289 mrpc_cleanup_cmd(stdev); 290 } 291 292 static void mrpc_timeout_work(struct work_struct *work) 293 { 294 struct switchtec_dev *stdev; 295 u32 status; 296 297 stdev = container_of(work, struct switchtec_dev, mrpc_timeout.work); 298 299 dev_dbg(&stdev->dev, "%s\n", __func__); 300 301 mutex_lock(&stdev->mrpc_mutex); 302 303 if (!is_firmware_running(stdev)) { 304 mrpc_error_complete_cmd(stdev); 305 goto out; 306 } 307 308 if (stdev->dma_mrpc) 309 status = stdev->dma_mrpc->status; 310 else 311 status = ioread32(&stdev->mmio_mrpc->status); 312 if (status == SWITCHTEC_MRPC_STATUS_INPROGRESS) { 313 schedule_delayed_work(&stdev->mrpc_timeout, 314 msecs_to_jiffies(500)); 315 goto out; 316 } 317 318 mrpc_complete_cmd(stdev); 319 out: 320 mutex_unlock(&stdev->mrpc_mutex); 321 } 322 323 static ssize_t device_version_show(struct device *dev, 324 struct device_attribute *attr, char *buf) 325 { 326 struct switchtec_dev *stdev = to_stdev(dev); 327 u32 ver; 328 329 ver = ioread32(&stdev->mmio_sys_info->device_version); 330 331 return sysfs_emit(buf, "%x\n", ver); 332 } 333 static DEVICE_ATTR_RO(device_version); 334 335 static ssize_t fw_version_show(struct device *dev, 336 struct device_attribute *attr, char *buf) 337 { 338 struct switchtec_dev *stdev = to_stdev(dev); 339 u32 ver; 340 341 ver = ioread32(&stdev->mmio_sys_info->firmware_version); 342 343 return sysfs_emit(buf, "%08x\n", ver); 344 } 345 static DEVICE_ATTR_RO(fw_version); 346 347 static ssize_t io_string_show(char *buf, void __iomem *attr, size_t len) 348 { 349 int i; 350 351 memcpy_fromio(buf, attr, len); 352 buf[len] = '\n'; 353 buf[len + 1] = 0; 354 355 for (i = len - 1; i > 0; i--) { 356 if (buf[i] != ' ') 357 break; 358 buf[i] = '\n'; 359 buf[i + 1] = 0; 360 } 361 362 return strlen(buf); 363 } 364 365 #define DEVICE_ATTR_SYS_INFO_STR(field) \ 366 static ssize_t field ## _show(struct device *dev, \ 367 struct device_attribute *attr, char *buf) \ 368 { \ 369 struct switchtec_dev *stdev = to_stdev(dev); \ 370 struct sys_info_regs __iomem *si = stdev->mmio_sys_info; \ 371 if (stdev->gen == SWITCHTEC_GEN3) \ 372 return io_string_show(buf, &si->gen3.field, \ 373 sizeof(si->gen3.field)); \ 374 else if (stdev->gen == SWITCHTEC_GEN4) \ 375 return io_string_show(buf, &si->gen4.field, \ 376 sizeof(si->gen4.field)); \ 377 else \ 378 return -ENOTSUPP; \ 379 } \ 380 \ 381 static DEVICE_ATTR_RO(field) 382 383 DEVICE_ATTR_SYS_INFO_STR(vendor_id); 384 DEVICE_ATTR_SYS_INFO_STR(product_id); 385 DEVICE_ATTR_SYS_INFO_STR(product_revision); 386 387 static ssize_t component_vendor_show(struct device *dev, 388 struct device_attribute *attr, char *buf) 389 { 390 struct switchtec_dev *stdev = to_stdev(dev); 391 struct sys_info_regs __iomem *si = stdev->mmio_sys_info; 392 393 /* component_vendor field not supported after gen3 */ 394 if (stdev->gen != SWITCHTEC_GEN3) 395 return sysfs_emit(buf, "none\n"); 396 397 return io_string_show(buf, &si->gen3.component_vendor, 398 sizeof(si->gen3.component_vendor)); 399 } 400 static DEVICE_ATTR_RO(component_vendor); 401 402 static ssize_t component_id_show(struct device *dev, 403 struct device_attribute *attr, char *buf) 404 { 405 struct switchtec_dev *stdev = to_stdev(dev); 406 int id = ioread16(&stdev->mmio_sys_info->gen3.component_id); 407 408 /* component_id field not supported after gen3 */ 409 if (stdev->gen != SWITCHTEC_GEN3) 410 return sysfs_emit(buf, "none\n"); 411 412 return sysfs_emit(buf, "PM%04X\n", id); 413 } 414 static DEVICE_ATTR_RO(component_id); 415 416 static ssize_t component_revision_show(struct device *dev, 417 struct device_attribute *attr, char *buf) 418 { 419 struct switchtec_dev *stdev = to_stdev(dev); 420 int rev = ioread8(&stdev->mmio_sys_info->gen3.component_revision); 421 422 /* component_revision field not supported after gen3 */ 423 if (stdev->gen != SWITCHTEC_GEN3) 424 return sysfs_emit(buf, "255\n"); 425 426 return sysfs_emit(buf, "%d\n", rev); 427 } 428 static DEVICE_ATTR_RO(component_revision); 429 430 static ssize_t partition_show(struct device *dev, 431 struct device_attribute *attr, char *buf) 432 { 433 struct switchtec_dev *stdev = to_stdev(dev); 434 435 return sysfs_emit(buf, "%d\n", stdev->partition); 436 } 437 static DEVICE_ATTR_RO(partition); 438 439 static ssize_t partition_count_show(struct device *dev, 440 struct device_attribute *attr, char *buf) 441 { 442 struct switchtec_dev *stdev = to_stdev(dev); 443 444 return sysfs_emit(buf, "%d\n", stdev->partition_count); 445 } 446 static DEVICE_ATTR_RO(partition_count); 447 448 static struct attribute *switchtec_device_attrs[] = { 449 &dev_attr_device_version.attr, 450 &dev_attr_fw_version.attr, 451 &dev_attr_vendor_id.attr, 452 &dev_attr_product_id.attr, 453 &dev_attr_product_revision.attr, 454 &dev_attr_component_vendor.attr, 455 &dev_attr_component_id.attr, 456 &dev_attr_component_revision.attr, 457 &dev_attr_partition.attr, 458 &dev_attr_partition_count.attr, 459 NULL, 460 }; 461 462 ATTRIBUTE_GROUPS(switchtec_device); 463 464 static int switchtec_dev_open(struct inode *inode, struct file *filp) 465 { 466 struct switchtec_dev *stdev; 467 struct switchtec_user *stuser; 468 469 stdev = container_of(inode->i_cdev, struct switchtec_dev, cdev); 470 471 stuser = stuser_create(stdev); 472 if (IS_ERR(stuser)) 473 return PTR_ERR(stuser); 474 475 filp->private_data = stuser; 476 stream_open(inode, filp); 477 478 dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser); 479 480 return 0; 481 } 482 483 static int switchtec_dev_release(struct inode *inode, struct file *filp) 484 { 485 struct switchtec_user *stuser = filp->private_data; 486 487 stuser_put(stuser); 488 489 return 0; 490 } 491 492 static int lock_mutex_and_test_alive(struct switchtec_dev *stdev) 493 { 494 if (mutex_lock_interruptible(&stdev->mrpc_mutex)) 495 return -EINTR; 496 497 if (!stdev->alive) { 498 mutex_unlock(&stdev->mrpc_mutex); 499 return -ENODEV; 500 } 501 502 return 0; 503 } 504 505 static ssize_t switchtec_dev_write(struct file *filp, const char __user *data, 506 size_t size, loff_t *off) 507 { 508 struct switchtec_user *stuser = filp->private_data; 509 struct switchtec_dev *stdev = stuser->stdev; 510 int rc; 511 512 if (size < sizeof(stuser->cmd) || 513 size > sizeof(stuser->cmd) + sizeof(stuser->data)) 514 return -EINVAL; 515 516 stuser->data_len = size - sizeof(stuser->cmd); 517 518 rc = lock_mutex_and_test_alive(stdev); 519 if (rc) 520 return rc; 521 522 if (stuser->state != MRPC_IDLE) { 523 rc = -EBADE; 524 goto out; 525 } 526 527 rc = copy_from_user(&stuser->cmd, data, sizeof(stuser->cmd)); 528 if (rc) { 529 rc = -EFAULT; 530 goto out; 531 } 532 if (((MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_WRITE) || 533 (MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_READ)) && 534 !capable(CAP_SYS_ADMIN)) { 535 rc = -EPERM; 536 goto out; 537 } 538 539 data += sizeof(stuser->cmd); 540 rc = copy_from_user(&stuser->data, data, size - sizeof(stuser->cmd)); 541 if (rc) { 542 rc = -EFAULT; 543 goto out; 544 } 545 546 rc = mrpc_queue_cmd(stuser); 547 548 out: 549 mutex_unlock(&stdev->mrpc_mutex); 550 551 if (rc) 552 return rc; 553 554 return size; 555 } 556 557 static ssize_t switchtec_dev_read(struct file *filp, char __user *data, 558 size_t size, loff_t *off) 559 { 560 struct switchtec_user *stuser = filp->private_data; 561 struct switchtec_dev *stdev = stuser->stdev; 562 int rc; 563 564 if (size < sizeof(stuser->cmd) || 565 size > sizeof(stuser->cmd) + sizeof(stuser->data)) 566 return -EINVAL; 567 568 rc = lock_mutex_and_test_alive(stdev); 569 if (rc) 570 return rc; 571 572 if (stuser->state == MRPC_IDLE) { 573 mutex_unlock(&stdev->mrpc_mutex); 574 return -EBADE; 575 } 576 577 stuser->read_len = size - sizeof(stuser->return_code); 578 579 mutex_unlock(&stdev->mrpc_mutex); 580 581 if (filp->f_flags & O_NONBLOCK) { 582 if (!stuser->cmd_done) 583 return -EAGAIN; 584 } else { 585 rc = wait_event_interruptible(stuser->cmd_comp, 586 stuser->cmd_done); 587 if (rc < 0) 588 return rc; 589 } 590 591 rc = lock_mutex_and_test_alive(stdev); 592 if (rc) 593 return rc; 594 595 if (stuser->state == MRPC_IO_ERROR) { 596 mutex_unlock(&stdev->mrpc_mutex); 597 return -EIO; 598 } 599 600 if (stuser->state != MRPC_DONE) { 601 mutex_unlock(&stdev->mrpc_mutex); 602 return -EBADE; 603 } 604 605 rc = copy_to_user(data, &stuser->return_code, 606 sizeof(stuser->return_code)); 607 if (rc) { 608 rc = -EFAULT; 609 goto out; 610 } 611 612 data += sizeof(stuser->return_code); 613 rc = copy_to_user(data, &stuser->data, 614 size - sizeof(stuser->return_code)); 615 if (rc) { 616 rc = -EFAULT; 617 goto out; 618 } 619 620 stuser_set_state(stuser, MRPC_IDLE); 621 622 out: 623 mutex_unlock(&stdev->mrpc_mutex); 624 625 if (stuser->status == SWITCHTEC_MRPC_STATUS_DONE) 626 return size; 627 else if (stuser->status == SWITCHTEC_MRPC_STATUS_INTERRUPTED) 628 return -ENXIO; 629 else 630 return -EBADMSG; 631 } 632 633 static __poll_t switchtec_dev_poll(struct file *filp, poll_table *wait) 634 { 635 struct switchtec_user *stuser = filp->private_data; 636 struct switchtec_dev *stdev = stuser->stdev; 637 __poll_t ret = 0; 638 639 poll_wait(filp, &stuser->cmd_comp, wait); 640 poll_wait(filp, &stdev->event_wq, wait); 641 642 if (lock_mutex_and_test_alive(stdev)) 643 return EPOLLIN | EPOLLRDHUP | EPOLLOUT | EPOLLERR | EPOLLHUP; 644 645 mutex_unlock(&stdev->mrpc_mutex); 646 647 if (stuser->cmd_done) 648 ret |= EPOLLIN | EPOLLRDNORM; 649 650 if (stuser->event_cnt != atomic_read(&stdev->event_cnt)) 651 ret |= EPOLLPRI | EPOLLRDBAND; 652 653 return ret; 654 } 655 656 static int ioctl_flash_info(struct switchtec_dev *stdev, 657 struct switchtec_ioctl_flash_info __user *uinfo) 658 { 659 struct switchtec_ioctl_flash_info info = {0}; 660 struct flash_info_regs __iomem *fi = stdev->mmio_flash_info; 661 662 if (stdev->gen == SWITCHTEC_GEN3) { 663 info.flash_length = ioread32(&fi->gen3.flash_length); 664 info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN3; 665 } else if (stdev->gen == SWITCHTEC_GEN4) { 666 info.flash_length = ioread32(&fi->gen4.flash_length); 667 info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN4; 668 } else { 669 return -ENOTSUPP; 670 } 671 672 if (copy_to_user(uinfo, &info, sizeof(info))) 673 return -EFAULT; 674 675 return 0; 676 } 677 678 static void set_fw_info_part(struct switchtec_ioctl_flash_part_info *info, 679 struct partition_info __iomem *pi) 680 { 681 info->address = ioread32(&pi->address); 682 info->length = ioread32(&pi->length); 683 } 684 685 static int flash_part_info_gen3(struct switchtec_dev *stdev, 686 struct switchtec_ioctl_flash_part_info *info) 687 { 688 struct flash_info_regs_gen3 __iomem *fi = 689 &stdev->mmio_flash_info->gen3; 690 struct sys_info_regs_gen3 __iomem *si = &stdev->mmio_sys_info->gen3; 691 u32 active_addr = -1; 692 693 switch (info->flash_partition) { 694 case SWITCHTEC_IOCTL_PART_CFG0: 695 active_addr = ioread32(&fi->active_cfg); 696 set_fw_info_part(info, &fi->cfg0); 697 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG0_RUNNING) 698 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 699 break; 700 case SWITCHTEC_IOCTL_PART_CFG1: 701 active_addr = ioread32(&fi->active_cfg); 702 set_fw_info_part(info, &fi->cfg1); 703 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG1_RUNNING) 704 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 705 break; 706 case SWITCHTEC_IOCTL_PART_IMG0: 707 active_addr = ioread32(&fi->active_img); 708 set_fw_info_part(info, &fi->img0); 709 if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG0_RUNNING) 710 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 711 break; 712 case SWITCHTEC_IOCTL_PART_IMG1: 713 active_addr = ioread32(&fi->active_img); 714 set_fw_info_part(info, &fi->img1); 715 if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG1_RUNNING) 716 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 717 break; 718 case SWITCHTEC_IOCTL_PART_NVLOG: 719 set_fw_info_part(info, &fi->nvlog); 720 break; 721 case SWITCHTEC_IOCTL_PART_VENDOR0: 722 set_fw_info_part(info, &fi->vendor[0]); 723 break; 724 case SWITCHTEC_IOCTL_PART_VENDOR1: 725 set_fw_info_part(info, &fi->vendor[1]); 726 break; 727 case SWITCHTEC_IOCTL_PART_VENDOR2: 728 set_fw_info_part(info, &fi->vendor[2]); 729 break; 730 case SWITCHTEC_IOCTL_PART_VENDOR3: 731 set_fw_info_part(info, &fi->vendor[3]); 732 break; 733 case SWITCHTEC_IOCTL_PART_VENDOR4: 734 set_fw_info_part(info, &fi->vendor[4]); 735 break; 736 case SWITCHTEC_IOCTL_PART_VENDOR5: 737 set_fw_info_part(info, &fi->vendor[5]); 738 break; 739 case SWITCHTEC_IOCTL_PART_VENDOR6: 740 set_fw_info_part(info, &fi->vendor[6]); 741 break; 742 case SWITCHTEC_IOCTL_PART_VENDOR7: 743 set_fw_info_part(info, &fi->vendor[7]); 744 break; 745 default: 746 return -EINVAL; 747 } 748 749 if (info->address == active_addr) 750 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE; 751 752 return 0; 753 } 754 755 static int flash_part_info_gen4(struct switchtec_dev *stdev, 756 struct switchtec_ioctl_flash_part_info *info) 757 { 758 struct flash_info_regs_gen4 __iomem *fi = &stdev->mmio_flash_info->gen4; 759 struct sys_info_regs_gen4 __iomem *si = &stdev->mmio_sys_info->gen4; 760 struct active_partition_info_gen4 __iomem *af = &fi->active_flag; 761 762 switch (info->flash_partition) { 763 case SWITCHTEC_IOCTL_PART_MAP_0: 764 set_fw_info_part(info, &fi->map0); 765 break; 766 case SWITCHTEC_IOCTL_PART_MAP_1: 767 set_fw_info_part(info, &fi->map1); 768 break; 769 case SWITCHTEC_IOCTL_PART_KEY_0: 770 set_fw_info_part(info, &fi->key0); 771 if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY0_ACTIVE) 772 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE; 773 if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY0_RUNNING) 774 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 775 break; 776 case SWITCHTEC_IOCTL_PART_KEY_1: 777 set_fw_info_part(info, &fi->key1); 778 if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY1_ACTIVE) 779 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE; 780 if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY1_RUNNING) 781 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 782 break; 783 case SWITCHTEC_IOCTL_PART_BL2_0: 784 set_fw_info_part(info, &fi->bl2_0); 785 if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_0_ACTIVE) 786 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE; 787 if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_0_RUNNING) 788 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 789 break; 790 case SWITCHTEC_IOCTL_PART_BL2_1: 791 set_fw_info_part(info, &fi->bl2_1); 792 if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_1_ACTIVE) 793 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE; 794 if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_1_RUNNING) 795 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 796 break; 797 case SWITCHTEC_IOCTL_PART_CFG0: 798 set_fw_info_part(info, &fi->cfg0); 799 if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG0_ACTIVE) 800 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE; 801 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG0_RUNNING) 802 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 803 break; 804 case SWITCHTEC_IOCTL_PART_CFG1: 805 set_fw_info_part(info, &fi->cfg1); 806 if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG1_ACTIVE) 807 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE; 808 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG1_RUNNING) 809 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 810 break; 811 case SWITCHTEC_IOCTL_PART_IMG0: 812 set_fw_info_part(info, &fi->img0); 813 if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG0_ACTIVE) 814 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE; 815 if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG0_RUNNING) 816 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 817 break; 818 case SWITCHTEC_IOCTL_PART_IMG1: 819 set_fw_info_part(info, &fi->img1); 820 if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG1_ACTIVE) 821 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE; 822 if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG1_RUNNING) 823 info->active |= SWITCHTEC_IOCTL_PART_RUNNING; 824 break; 825 case SWITCHTEC_IOCTL_PART_NVLOG: 826 set_fw_info_part(info, &fi->nvlog); 827 break; 828 case SWITCHTEC_IOCTL_PART_VENDOR0: 829 set_fw_info_part(info, &fi->vendor[0]); 830 break; 831 case SWITCHTEC_IOCTL_PART_VENDOR1: 832 set_fw_info_part(info, &fi->vendor[1]); 833 break; 834 case SWITCHTEC_IOCTL_PART_VENDOR2: 835 set_fw_info_part(info, &fi->vendor[2]); 836 break; 837 case SWITCHTEC_IOCTL_PART_VENDOR3: 838 set_fw_info_part(info, &fi->vendor[3]); 839 break; 840 case SWITCHTEC_IOCTL_PART_VENDOR4: 841 set_fw_info_part(info, &fi->vendor[4]); 842 break; 843 case SWITCHTEC_IOCTL_PART_VENDOR5: 844 set_fw_info_part(info, &fi->vendor[5]); 845 break; 846 case SWITCHTEC_IOCTL_PART_VENDOR6: 847 set_fw_info_part(info, &fi->vendor[6]); 848 break; 849 case SWITCHTEC_IOCTL_PART_VENDOR7: 850 set_fw_info_part(info, &fi->vendor[7]); 851 break; 852 default: 853 return -EINVAL; 854 } 855 856 return 0; 857 } 858 859 static int ioctl_flash_part_info(struct switchtec_dev *stdev, 860 struct switchtec_ioctl_flash_part_info __user *uinfo) 861 { 862 int ret; 863 struct switchtec_ioctl_flash_part_info info = {0}; 864 865 if (copy_from_user(&info, uinfo, sizeof(info))) 866 return -EFAULT; 867 868 if (stdev->gen == SWITCHTEC_GEN3) { 869 ret = flash_part_info_gen3(stdev, &info); 870 if (ret) 871 return ret; 872 } else if (stdev->gen == SWITCHTEC_GEN4) { 873 ret = flash_part_info_gen4(stdev, &info); 874 if (ret) 875 return ret; 876 } else { 877 return -ENOTSUPP; 878 } 879 880 if (copy_to_user(uinfo, &info, sizeof(info))) 881 return -EFAULT; 882 883 return 0; 884 } 885 886 static int ioctl_event_summary(struct switchtec_dev *stdev, 887 struct switchtec_user *stuser, 888 struct switchtec_ioctl_event_summary __user *usum, 889 size_t size) 890 { 891 struct switchtec_ioctl_event_summary *s; 892 int i; 893 u32 reg; 894 int ret = 0; 895 896 s = kzalloc(sizeof(*s), GFP_KERNEL); 897 if (!s) 898 return -ENOMEM; 899 900 s->global = ioread32(&stdev->mmio_sw_event->global_summary); 901 s->part_bitmap = ioread64(&stdev->mmio_sw_event->part_event_bitmap); 902 s->local_part = ioread32(&stdev->mmio_part_cfg->part_event_summary); 903 904 for (i = 0; i < stdev->partition_count; i++) { 905 reg = ioread32(&stdev->mmio_part_cfg_all[i].part_event_summary); 906 s->part[i] = reg; 907 } 908 909 for (i = 0; i < stdev->pff_csr_count; i++) { 910 reg = ioread32(&stdev->mmio_pff_csr[i].pff_event_summary); 911 s->pff[i] = reg; 912 } 913 914 if (copy_to_user(usum, s, size)) { 915 ret = -EFAULT; 916 goto error_case; 917 } 918 919 stuser->event_cnt = atomic_read(&stdev->event_cnt); 920 921 error_case: 922 kfree(s); 923 return ret; 924 } 925 926 static u32 __iomem *global_ev_reg(struct switchtec_dev *stdev, 927 size_t offset, int index) 928 { 929 return (void __iomem *)stdev->mmio_sw_event + offset; 930 } 931 932 static u32 __iomem *part_ev_reg(struct switchtec_dev *stdev, 933 size_t offset, int index) 934 { 935 return (void __iomem *)&stdev->mmio_part_cfg_all[index] + offset; 936 } 937 938 static u32 __iomem *pff_ev_reg(struct switchtec_dev *stdev, 939 size_t offset, int index) 940 { 941 return (void __iomem *)&stdev->mmio_pff_csr[index] + offset; 942 } 943 944 #define EV_GLB(i, r)[i] = {offsetof(struct sw_event_regs, r), global_ev_reg} 945 #define EV_PAR(i, r)[i] = {offsetof(struct part_cfg_regs, r), part_ev_reg} 946 #define EV_PFF(i, r)[i] = {offsetof(struct pff_csr_regs, r), pff_ev_reg} 947 948 static const struct event_reg { 949 size_t offset; 950 u32 __iomem *(*map_reg)(struct switchtec_dev *stdev, 951 size_t offset, int index); 952 } event_regs[] = { 953 EV_GLB(SWITCHTEC_IOCTL_EVENT_STACK_ERROR, stack_error_event_hdr), 954 EV_GLB(SWITCHTEC_IOCTL_EVENT_PPU_ERROR, ppu_error_event_hdr), 955 EV_GLB(SWITCHTEC_IOCTL_EVENT_ISP_ERROR, isp_error_event_hdr), 956 EV_GLB(SWITCHTEC_IOCTL_EVENT_SYS_RESET, sys_reset_event_hdr), 957 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_EXC, fw_exception_hdr), 958 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_NMI, fw_nmi_hdr), 959 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_NON_FATAL, fw_non_fatal_hdr), 960 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_FATAL, fw_fatal_hdr), 961 EV_GLB(SWITCHTEC_IOCTL_EVENT_TWI_MRPC_COMP, twi_mrpc_comp_hdr), 962 EV_GLB(SWITCHTEC_IOCTL_EVENT_TWI_MRPC_COMP_ASYNC, 963 twi_mrpc_comp_async_hdr), 964 EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP, cli_mrpc_comp_hdr), 965 EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP_ASYNC, 966 cli_mrpc_comp_async_hdr), 967 EV_GLB(SWITCHTEC_IOCTL_EVENT_GPIO_INT, gpio_interrupt_hdr), 968 EV_GLB(SWITCHTEC_IOCTL_EVENT_GFMS, gfms_event_hdr), 969 EV_PAR(SWITCHTEC_IOCTL_EVENT_PART_RESET, part_reset_hdr), 970 EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP, mrpc_comp_hdr), 971 EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP_ASYNC, mrpc_comp_async_hdr), 972 EV_PAR(SWITCHTEC_IOCTL_EVENT_DYN_PART_BIND_COMP, dyn_binding_hdr), 973 EV_PAR(SWITCHTEC_IOCTL_EVENT_INTERCOMM_REQ_NOTIFY, 974 intercomm_notify_hdr), 975 EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_P2P, aer_in_p2p_hdr), 976 EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_VEP, aer_in_vep_hdr), 977 EV_PFF(SWITCHTEC_IOCTL_EVENT_DPC, dpc_hdr), 978 EV_PFF(SWITCHTEC_IOCTL_EVENT_CTS, cts_hdr), 979 EV_PFF(SWITCHTEC_IOCTL_EVENT_UEC, uec_hdr), 980 EV_PFF(SWITCHTEC_IOCTL_EVENT_HOTPLUG, hotplug_hdr), 981 EV_PFF(SWITCHTEC_IOCTL_EVENT_IER, ier_hdr), 982 EV_PFF(SWITCHTEC_IOCTL_EVENT_THRESH, threshold_hdr), 983 EV_PFF(SWITCHTEC_IOCTL_EVENT_POWER_MGMT, power_mgmt_hdr), 984 EV_PFF(SWITCHTEC_IOCTL_EVENT_TLP_THROTTLING, tlp_throttling_hdr), 985 EV_PFF(SWITCHTEC_IOCTL_EVENT_FORCE_SPEED, force_speed_hdr), 986 EV_PFF(SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT, credit_timeout_hdr), 987 EV_PFF(SWITCHTEC_IOCTL_EVENT_LINK_STATE, link_state_hdr), 988 }; 989 990 static u32 __iomem *event_hdr_addr(struct switchtec_dev *stdev, 991 int event_id, int index) 992 { 993 size_t off; 994 995 if (event_id < 0 || event_id >= SWITCHTEC_IOCTL_MAX_EVENTS) 996 return (u32 __iomem *)ERR_PTR(-EINVAL); 997 998 off = event_regs[event_id].offset; 999 1000 if (event_regs[event_id].map_reg == part_ev_reg) { 1001 if (index == SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX) 1002 index = stdev->partition; 1003 else if (index < 0 || index >= stdev->partition_count) 1004 return (u32 __iomem *)ERR_PTR(-EINVAL); 1005 } else if (event_regs[event_id].map_reg == pff_ev_reg) { 1006 if (index < 0 || index >= stdev->pff_csr_count) 1007 return (u32 __iomem *)ERR_PTR(-EINVAL); 1008 } 1009 1010 return event_regs[event_id].map_reg(stdev, off, index); 1011 } 1012 1013 static int event_ctl(struct switchtec_dev *stdev, 1014 struct switchtec_ioctl_event_ctl *ctl) 1015 { 1016 int i; 1017 u32 __iomem *reg; 1018 u32 hdr; 1019 1020 reg = event_hdr_addr(stdev, ctl->event_id, ctl->index); 1021 if (IS_ERR(reg)) 1022 return PTR_ERR(reg); 1023 1024 hdr = ioread32(reg); 1025 for (i = 0; i < ARRAY_SIZE(ctl->data); i++) 1026 ctl->data[i] = ioread32(®[i + 1]); 1027 1028 ctl->occurred = hdr & SWITCHTEC_EVENT_OCCURRED; 1029 ctl->count = (hdr >> 5) & 0xFF; 1030 1031 if (!(ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_CLEAR)) 1032 hdr &= ~SWITCHTEC_EVENT_CLEAR; 1033 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_POLL) 1034 hdr |= SWITCHTEC_EVENT_EN_IRQ; 1035 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_POLL) 1036 hdr &= ~SWITCHTEC_EVENT_EN_IRQ; 1037 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_LOG) 1038 hdr |= SWITCHTEC_EVENT_EN_LOG; 1039 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_LOG) 1040 hdr &= ~SWITCHTEC_EVENT_EN_LOG; 1041 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_CLI) 1042 hdr |= SWITCHTEC_EVENT_EN_CLI; 1043 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_CLI) 1044 hdr &= ~SWITCHTEC_EVENT_EN_CLI; 1045 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_FATAL) 1046 hdr |= SWITCHTEC_EVENT_FATAL; 1047 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_FATAL) 1048 hdr &= ~SWITCHTEC_EVENT_FATAL; 1049 1050 if (ctl->flags) 1051 iowrite32(hdr, reg); 1052 1053 ctl->flags = 0; 1054 if (hdr & SWITCHTEC_EVENT_EN_IRQ) 1055 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_POLL; 1056 if (hdr & SWITCHTEC_EVENT_EN_LOG) 1057 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_LOG; 1058 if (hdr & SWITCHTEC_EVENT_EN_CLI) 1059 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_CLI; 1060 if (hdr & SWITCHTEC_EVENT_FATAL) 1061 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_FATAL; 1062 1063 return 0; 1064 } 1065 1066 static int ioctl_event_ctl(struct switchtec_dev *stdev, 1067 struct switchtec_ioctl_event_ctl __user *uctl) 1068 { 1069 int ret; 1070 int nr_idxs; 1071 unsigned int event_flags; 1072 struct switchtec_ioctl_event_ctl ctl; 1073 1074 if (copy_from_user(&ctl, uctl, sizeof(ctl))) 1075 return -EFAULT; 1076 1077 if (ctl.event_id >= SWITCHTEC_IOCTL_MAX_EVENTS) 1078 return -EINVAL; 1079 1080 if (ctl.flags & SWITCHTEC_IOCTL_EVENT_FLAG_UNUSED) 1081 return -EINVAL; 1082 1083 if (ctl.index == SWITCHTEC_IOCTL_EVENT_IDX_ALL) { 1084 if (event_regs[ctl.event_id].map_reg == global_ev_reg) 1085 nr_idxs = 1; 1086 else if (event_regs[ctl.event_id].map_reg == part_ev_reg) 1087 nr_idxs = stdev->partition_count; 1088 else if (event_regs[ctl.event_id].map_reg == pff_ev_reg) 1089 nr_idxs = stdev->pff_csr_count; 1090 else 1091 return -EINVAL; 1092 1093 event_flags = ctl.flags; 1094 for (ctl.index = 0; ctl.index < nr_idxs; ctl.index++) { 1095 ctl.flags = event_flags; 1096 ret = event_ctl(stdev, &ctl); 1097 if (ret < 0) 1098 return ret; 1099 } 1100 } else { 1101 ret = event_ctl(stdev, &ctl); 1102 if (ret < 0) 1103 return ret; 1104 } 1105 1106 if (copy_to_user(uctl, &ctl, sizeof(ctl))) 1107 return -EFAULT; 1108 1109 return 0; 1110 } 1111 1112 static int ioctl_pff_to_port(struct switchtec_dev *stdev, 1113 struct switchtec_ioctl_pff_port __user *up) 1114 { 1115 int i, part; 1116 u32 reg; 1117 struct part_cfg_regs __iomem *pcfg; 1118 struct switchtec_ioctl_pff_port p; 1119 1120 if (copy_from_user(&p, up, sizeof(p))) 1121 return -EFAULT; 1122 1123 p.port = -1; 1124 for (part = 0; part < stdev->partition_count; part++) { 1125 pcfg = &stdev->mmio_part_cfg_all[part]; 1126 p.partition = part; 1127 1128 reg = ioread32(&pcfg->usp_pff_inst_id); 1129 if (reg == p.pff) { 1130 p.port = 0; 1131 break; 1132 } 1133 1134 reg = ioread32(&pcfg->vep_pff_inst_id); 1135 if (reg == p.pff) { 1136 p.port = SWITCHTEC_IOCTL_PFF_VEP; 1137 break; 1138 } 1139 1140 for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) { 1141 reg = ioread32(&pcfg->dsp_pff_inst_id[i]); 1142 if (reg != p.pff) 1143 continue; 1144 1145 p.port = i + 1; 1146 break; 1147 } 1148 1149 if (p.port != -1) 1150 break; 1151 } 1152 1153 if (copy_to_user(up, &p, sizeof(p))) 1154 return -EFAULT; 1155 1156 return 0; 1157 } 1158 1159 static int ioctl_port_to_pff(struct switchtec_dev *stdev, 1160 struct switchtec_ioctl_pff_port __user *up) 1161 { 1162 struct switchtec_ioctl_pff_port p; 1163 struct part_cfg_regs __iomem *pcfg; 1164 1165 if (copy_from_user(&p, up, sizeof(p))) 1166 return -EFAULT; 1167 1168 if (p.partition == SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX) 1169 pcfg = stdev->mmio_part_cfg; 1170 else if (p.partition < stdev->partition_count) 1171 pcfg = &stdev->mmio_part_cfg_all[p.partition]; 1172 else 1173 return -EINVAL; 1174 1175 switch (p.port) { 1176 case 0: 1177 p.pff = ioread32(&pcfg->usp_pff_inst_id); 1178 break; 1179 case SWITCHTEC_IOCTL_PFF_VEP: 1180 p.pff = ioread32(&pcfg->vep_pff_inst_id); 1181 break; 1182 default: 1183 if (p.port > ARRAY_SIZE(pcfg->dsp_pff_inst_id)) 1184 return -EINVAL; 1185 p.port = array_index_nospec(p.port, 1186 ARRAY_SIZE(pcfg->dsp_pff_inst_id) + 1); 1187 p.pff = ioread32(&pcfg->dsp_pff_inst_id[p.port - 1]); 1188 break; 1189 } 1190 1191 if (copy_to_user(up, &p, sizeof(p))) 1192 return -EFAULT; 1193 1194 return 0; 1195 } 1196 1197 static long switchtec_dev_ioctl(struct file *filp, unsigned int cmd, 1198 unsigned long arg) 1199 { 1200 struct switchtec_user *stuser = filp->private_data; 1201 struct switchtec_dev *stdev = stuser->stdev; 1202 int rc; 1203 void __user *argp = (void __user *)arg; 1204 1205 rc = lock_mutex_and_test_alive(stdev); 1206 if (rc) 1207 return rc; 1208 1209 switch (cmd) { 1210 case SWITCHTEC_IOCTL_FLASH_INFO: 1211 rc = ioctl_flash_info(stdev, argp); 1212 break; 1213 case SWITCHTEC_IOCTL_FLASH_PART_INFO: 1214 rc = ioctl_flash_part_info(stdev, argp); 1215 break; 1216 case SWITCHTEC_IOCTL_EVENT_SUMMARY_LEGACY: 1217 rc = ioctl_event_summary(stdev, stuser, argp, 1218 sizeof(struct switchtec_ioctl_event_summary_legacy)); 1219 break; 1220 case SWITCHTEC_IOCTL_EVENT_CTL: 1221 rc = ioctl_event_ctl(stdev, argp); 1222 break; 1223 case SWITCHTEC_IOCTL_PFF_TO_PORT: 1224 rc = ioctl_pff_to_port(stdev, argp); 1225 break; 1226 case SWITCHTEC_IOCTL_PORT_TO_PFF: 1227 rc = ioctl_port_to_pff(stdev, argp); 1228 break; 1229 case SWITCHTEC_IOCTL_EVENT_SUMMARY: 1230 rc = ioctl_event_summary(stdev, stuser, argp, 1231 sizeof(struct switchtec_ioctl_event_summary)); 1232 break; 1233 default: 1234 rc = -ENOTTY; 1235 break; 1236 } 1237 1238 mutex_unlock(&stdev->mrpc_mutex); 1239 return rc; 1240 } 1241 1242 static const struct file_operations switchtec_fops = { 1243 .owner = THIS_MODULE, 1244 .open = switchtec_dev_open, 1245 .release = switchtec_dev_release, 1246 .write = switchtec_dev_write, 1247 .read = switchtec_dev_read, 1248 .poll = switchtec_dev_poll, 1249 .unlocked_ioctl = switchtec_dev_ioctl, 1250 .compat_ioctl = compat_ptr_ioctl, 1251 }; 1252 1253 static void link_event_work(struct work_struct *work) 1254 { 1255 struct switchtec_dev *stdev; 1256 1257 stdev = container_of(work, struct switchtec_dev, link_event_work); 1258 1259 if (stdev->link_notifier) 1260 stdev->link_notifier(stdev); 1261 } 1262 1263 static void check_link_state_events(struct switchtec_dev *stdev) 1264 { 1265 int idx; 1266 u32 reg; 1267 int count; 1268 int occurred = 0; 1269 1270 for (idx = 0; idx < stdev->pff_csr_count; idx++) { 1271 reg = ioread32(&stdev->mmio_pff_csr[idx].link_state_hdr); 1272 dev_dbg(&stdev->dev, "link_state: %d->%08x\n", idx, reg); 1273 count = (reg >> 5) & 0xFF; 1274 1275 if (count != stdev->link_event_count[idx]) { 1276 occurred = 1; 1277 stdev->link_event_count[idx] = count; 1278 } 1279 } 1280 1281 if (occurred) 1282 schedule_work(&stdev->link_event_work); 1283 } 1284 1285 static void enable_link_state_events(struct switchtec_dev *stdev) 1286 { 1287 int idx; 1288 1289 for (idx = 0; idx < stdev->pff_csr_count; idx++) { 1290 iowrite32(SWITCHTEC_EVENT_CLEAR | 1291 SWITCHTEC_EVENT_EN_IRQ, 1292 &stdev->mmio_pff_csr[idx].link_state_hdr); 1293 } 1294 } 1295 1296 static void enable_dma_mrpc(struct switchtec_dev *stdev) 1297 { 1298 writeq(stdev->dma_mrpc_dma_addr, &stdev->mmio_mrpc->dma_addr); 1299 flush_wc_buf(stdev); 1300 iowrite32(SWITCHTEC_DMA_MRPC_EN, &stdev->mmio_mrpc->dma_en); 1301 } 1302 1303 static void stdev_release(struct device *dev) 1304 { 1305 struct switchtec_dev *stdev = to_stdev(dev); 1306 1307 if (stdev->dma_mrpc) { 1308 iowrite32(0, &stdev->mmio_mrpc->dma_en); 1309 flush_wc_buf(stdev); 1310 writeq(0, &stdev->mmio_mrpc->dma_addr); 1311 dma_free_coherent(&stdev->pdev->dev, sizeof(*stdev->dma_mrpc), 1312 stdev->dma_mrpc, stdev->dma_mrpc_dma_addr); 1313 } 1314 kfree(stdev); 1315 } 1316 1317 static void stdev_kill(struct switchtec_dev *stdev) 1318 { 1319 struct switchtec_user *stuser, *tmpuser; 1320 1321 pci_clear_master(stdev->pdev); 1322 1323 cancel_delayed_work_sync(&stdev->mrpc_timeout); 1324 1325 /* Mark the hardware as unavailable and complete all completions */ 1326 mutex_lock(&stdev->mrpc_mutex); 1327 stdev->alive = false; 1328 1329 /* Wake up and kill any users waiting on an MRPC request */ 1330 list_for_each_entry_safe(stuser, tmpuser, &stdev->mrpc_queue, list) { 1331 stuser->cmd_done = true; 1332 wake_up_interruptible(&stuser->cmd_comp); 1333 list_del_init(&stuser->list); 1334 stuser_put(stuser); 1335 } 1336 1337 mutex_unlock(&stdev->mrpc_mutex); 1338 1339 /* Wake up any users waiting on event_wq */ 1340 wake_up_interruptible(&stdev->event_wq); 1341 } 1342 1343 static struct switchtec_dev *stdev_create(struct pci_dev *pdev) 1344 { 1345 struct switchtec_dev *stdev; 1346 int minor; 1347 struct device *dev; 1348 struct cdev *cdev; 1349 int rc; 1350 1351 stdev = kzalloc_node(sizeof(*stdev), GFP_KERNEL, 1352 dev_to_node(&pdev->dev)); 1353 if (!stdev) 1354 return ERR_PTR(-ENOMEM); 1355 1356 stdev->alive = true; 1357 stdev->pdev = pdev; 1358 INIT_LIST_HEAD(&stdev->mrpc_queue); 1359 mutex_init(&stdev->mrpc_mutex); 1360 stdev->mrpc_busy = 0; 1361 INIT_WORK(&stdev->mrpc_work, mrpc_event_work); 1362 INIT_DELAYED_WORK(&stdev->mrpc_timeout, mrpc_timeout_work); 1363 INIT_WORK(&stdev->link_event_work, link_event_work); 1364 init_waitqueue_head(&stdev->event_wq); 1365 atomic_set(&stdev->event_cnt, 0); 1366 1367 dev = &stdev->dev; 1368 device_initialize(dev); 1369 dev->class = switchtec_class; 1370 dev->parent = &pdev->dev; 1371 dev->groups = switchtec_device_groups; 1372 dev->release = stdev_release; 1373 1374 minor = ida_simple_get(&switchtec_minor_ida, 0, 0, 1375 GFP_KERNEL); 1376 if (minor < 0) { 1377 rc = minor; 1378 goto err_put; 1379 } 1380 1381 dev->devt = MKDEV(MAJOR(switchtec_devt), minor); 1382 dev_set_name(dev, "switchtec%d", minor); 1383 1384 cdev = &stdev->cdev; 1385 cdev_init(cdev, &switchtec_fops); 1386 cdev->owner = THIS_MODULE; 1387 1388 return stdev; 1389 1390 err_put: 1391 put_device(&stdev->dev); 1392 return ERR_PTR(rc); 1393 } 1394 1395 static int mask_event(struct switchtec_dev *stdev, int eid, int idx) 1396 { 1397 size_t off = event_regs[eid].offset; 1398 u32 __iomem *hdr_reg; 1399 u32 hdr; 1400 1401 hdr_reg = event_regs[eid].map_reg(stdev, off, idx); 1402 hdr = ioread32(hdr_reg); 1403 1404 if (!(hdr & SWITCHTEC_EVENT_OCCURRED && hdr & SWITCHTEC_EVENT_EN_IRQ)) 1405 return 0; 1406 1407 dev_dbg(&stdev->dev, "%s: %d %d %x\n", __func__, eid, idx, hdr); 1408 hdr &= ~(SWITCHTEC_EVENT_EN_IRQ | SWITCHTEC_EVENT_OCCURRED); 1409 iowrite32(hdr, hdr_reg); 1410 1411 return 1; 1412 } 1413 1414 static int mask_all_events(struct switchtec_dev *stdev, int eid) 1415 { 1416 int idx; 1417 int count = 0; 1418 1419 if (event_regs[eid].map_reg == part_ev_reg) { 1420 for (idx = 0; idx < stdev->partition_count; idx++) 1421 count += mask_event(stdev, eid, idx); 1422 } else if (event_regs[eid].map_reg == pff_ev_reg) { 1423 for (idx = 0; idx < stdev->pff_csr_count; idx++) { 1424 if (!stdev->pff_local[idx]) 1425 continue; 1426 1427 count += mask_event(stdev, eid, idx); 1428 } 1429 } else { 1430 count += mask_event(stdev, eid, 0); 1431 } 1432 1433 return count; 1434 } 1435 1436 static irqreturn_t switchtec_event_isr(int irq, void *dev) 1437 { 1438 struct switchtec_dev *stdev = dev; 1439 u32 reg; 1440 irqreturn_t ret = IRQ_NONE; 1441 int eid, event_count = 0; 1442 1443 reg = ioread32(&stdev->mmio_part_cfg->mrpc_comp_hdr); 1444 if (reg & SWITCHTEC_EVENT_OCCURRED) { 1445 dev_dbg(&stdev->dev, "%s: mrpc comp\n", __func__); 1446 ret = IRQ_HANDLED; 1447 schedule_work(&stdev->mrpc_work); 1448 iowrite32(reg, &stdev->mmio_part_cfg->mrpc_comp_hdr); 1449 } 1450 1451 check_link_state_events(stdev); 1452 1453 for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++) { 1454 if (eid == SWITCHTEC_IOCTL_EVENT_LINK_STATE || 1455 eid == SWITCHTEC_IOCTL_EVENT_MRPC_COMP) 1456 continue; 1457 1458 event_count += mask_all_events(stdev, eid); 1459 } 1460 1461 if (event_count) { 1462 atomic_inc(&stdev->event_cnt); 1463 wake_up_interruptible(&stdev->event_wq); 1464 dev_dbg(&stdev->dev, "%s: %d events\n", __func__, 1465 event_count); 1466 return IRQ_HANDLED; 1467 } 1468 1469 return ret; 1470 } 1471 1472 1473 static irqreturn_t switchtec_dma_mrpc_isr(int irq, void *dev) 1474 { 1475 struct switchtec_dev *stdev = dev; 1476 irqreturn_t ret = IRQ_NONE; 1477 1478 iowrite32(SWITCHTEC_EVENT_CLEAR | 1479 SWITCHTEC_EVENT_EN_IRQ, 1480 &stdev->mmio_part_cfg->mrpc_comp_hdr); 1481 schedule_work(&stdev->mrpc_work); 1482 1483 ret = IRQ_HANDLED; 1484 return ret; 1485 } 1486 1487 static int switchtec_init_isr(struct switchtec_dev *stdev) 1488 { 1489 int nvecs; 1490 int event_irq; 1491 int dma_mrpc_irq; 1492 int rc; 1493 1494 if (nirqs < 4) 1495 nirqs = 4; 1496 1497 nvecs = pci_alloc_irq_vectors(stdev->pdev, 1, nirqs, 1498 PCI_IRQ_MSIX | PCI_IRQ_MSI | 1499 PCI_IRQ_VIRTUAL); 1500 if (nvecs < 0) 1501 return nvecs; 1502 1503 event_irq = ioread16(&stdev->mmio_part_cfg->vep_vector_number); 1504 if (event_irq < 0 || event_irq >= nvecs) 1505 return -EFAULT; 1506 1507 event_irq = pci_irq_vector(stdev->pdev, event_irq); 1508 if (event_irq < 0) 1509 return event_irq; 1510 1511 rc = devm_request_irq(&stdev->pdev->dev, event_irq, 1512 switchtec_event_isr, 0, 1513 KBUILD_MODNAME, stdev); 1514 1515 if (rc) 1516 return rc; 1517 1518 if (!stdev->dma_mrpc) 1519 return rc; 1520 1521 dma_mrpc_irq = ioread32(&stdev->mmio_mrpc->dma_vector); 1522 if (dma_mrpc_irq < 0 || dma_mrpc_irq >= nvecs) 1523 return -EFAULT; 1524 1525 dma_mrpc_irq = pci_irq_vector(stdev->pdev, dma_mrpc_irq); 1526 if (dma_mrpc_irq < 0) 1527 return dma_mrpc_irq; 1528 1529 rc = devm_request_irq(&stdev->pdev->dev, dma_mrpc_irq, 1530 switchtec_dma_mrpc_isr, 0, 1531 KBUILD_MODNAME, stdev); 1532 1533 return rc; 1534 } 1535 1536 static void init_pff(struct switchtec_dev *stdev) 1537 { 1538 int i; 1539 u32 reg; 1540 struct part_cfg_regs __iomem *pcfg = stdev->mmio_part_cfg; 1541 1542 for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) { 1543 reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id); 1544 if (reg != PCI_VENDOR_ID_MICROSEMI) 1545 break; 1546 } 1547 1548 stdev->pff_csr_count = i; 1549 1550 reg = ioread32(&pcfg->usp_pff_inst_id); 1551 if (reg < stdev->pff_csr_count) 1552 stdev->pff_local[reg] = 1; 1553 1554 reg = ioread32(&pcfg->vep_pff_inst_id); 1555 if (reg < stdev->pff_csr_count) 1556 stdev->pff_local[reg] = 1; 1557 1558 for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) { 1559 reg = ioread32(&pcfg->dsp_pff_inst_id[i]); 1560 if (reg < stdev->pff_csr_count) 1561 stdev->pff_local[reg] = 1; 1562 } 1563 } 1564 1565 static int switchtec_init_pci(struct switchtec_dev *stdev, 1566 struct pci_dev *pdev) 1567 { 1568 int rc; 1569 void __iomem *map; 1570 unsigned long res_start, res_len; 1571 u32 __iomem *part_id; 1572 1573 rc = pcim_enable_device(pdev); 1574 if (rc) 1575 return rc; 1576 1577 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1578 if (rc) 1579 return rc; 1580 1581 pci_set_master(pdev); 1582 1583 res_start = pci_resource_start(pdev, 0); 1584 res_len = pci_resource_len(pdev, 0); 1585 1586 if (!devm_request_mem_region(&pdev->dev, res_start, 1587 res_len, KBUILD_MODNAME)) 1588 return -EBUSY; 1589 1590 stdev->mmio_mrpc = devm_ioremap_wc(&pdev->dev, res_start, 1591 SWITCHTEC_GAS_TOP_CFG_OFFSET); 1592 if (!stdev->mmio_mrpc) 1593 return -ENOMEM; 1594 1595 map = devm_ioremap(&pdev->dev, 1596 res_start + SWITCHTEC_GAS_TOP_CFG_OFFSET, 1597 res_len - SWITCHTEC_GAS_TOP_CFG_OFFSET); 1598 if (!map) 1599 return -ENOMEM; 1600 1601 stdev->mmio = map - SWITCHTEC_GAS_TOP_CFG_OFFSET; 1602 stdev->mmio_sw_event = stdev->mmio + SWITCHTEC_GAS_SW_EVENT_OFFSET; 1603 stdev->mmio_sys_info = stdev->mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET; 1604 stdev->mmio_flash_info = stdev->mmio + SWITCHTEC_GAS_FLASH_INFO_OFFSET; 1605 stdev->mmio_ntb = stdev->mmio + SWITCHTEC_GAS_NTB_OFFSET; 1606 1607 if (stdev->gen == SWITCHTEC_GEN3) 1608 part_id = &stdev->mmio_sys_info->gen3.partition_id; 1609 else if (stdev->gen == SWITCHTEC_GEN4) 1610 part_id = &stdev->mmio_sys_info->gen4.partition_id; 1611 else 1612 return -ENOTSUPP; 1613 1614 stdev->partition = ioread8(part_id); 1615 stdev->partition_count = ioread8(&stdev->mmio_ntb->partition_count); 1616 stdev->mmio_part_cfg_all = stdev->mmio + SWITCHTEC_GAS_PART_CFG_OFFSET; 1617 stdev->mmio_part_cfg = &stdev->mmio_part_cfg_all[stdev->partition]; 1618 stdev->mmio_pff_csr = stdev->mmio + SWITCHTEC_GAS_PFF_CSR_OFFSET; 1619 1620 if (stdev->partition_count < 1) 1621 stdev->partition_count = 1; 1622 1623 init_pff(stdev); 1624 1625 pci_set_drvdata(pdev, stdev); 1626 1627 if (!use_dma_mrpc) 1628 return 0; 1629 1630 if (ioread32(&stdev->mmio_mrpc->dma_ver) == 0) 1631 return 0; 1632 1633 stdev->dma_mrpc = dma_alloc_coherent(&stdev->pdev->dev, 1634 sizeof(*stdev->dma_mrpc), 1635 &stdev->dma_mrpc_dma_addr, 1636 GFP_KERNEL); 1637 if (stdev->dma_mrpc == NULL) 1638 return -ENOMEM; 1639 1640 return 0; 1641 } 1642 1643 static int switchtec_pci_probe(struct pci_dev *pdev, 1644 const struct pci_device_id *id) 1645 { 1646 struct switchtec_dev *stdev; 1647 int rc; 1648 1649 if (pdev->class == (PCI_CLASS_BRIDGE_OTHER << 8)) 1650 request_module_nowait("ntb_hw_switchtec"); 1651 1652 stdev = stdev_create(pdev); 1653 if (IS_ERR(stdev)) 1654 return PTR_ERR(stdev); 1655 1656 stdev->gen = id->driver_data; 1657 1658 rc = switchtec_init_pci(stdev, pdev); 1659 if (rc) 1660 goto err_put; 1661 1662 rc = switchtec_init_isr(stdev); 1663 if (rc) { 1664 dev_err(&stdev->dev, "failed to init isr.\n"); 1665 goto err_put; 1666 } 1667 1668 iowrite32(SWITCHTEC_EVENT_CLEAR | 1669 SWITCHTEC_EVENT_EN_IRQ, 1670 &stdev->mmio_part_cfg->mrpc_comp_hdr); 1671 enable_link_state_events(stdev); 1672 1673 if (stdev->dma_mrpc) 1674 enable_dma_mrpc(stdev); 1675 1676 rc = cdev_device_add(&stdev->cdev, &stdev->dev); 1677 if (rc) 1678 goto err_devadd; 1679 1680 dev_info(&stdev->dev, "Management device registered.\n"); 1681 1682 return 0; 1683 1684 err_devadd: 1685 stdev_kill(stdev); 1686 err_put: 1687 ida_simple_remove(&switchtec_minor_ida, MINOR(stdev->dev.devt)); 1688 put_device(&stdev->dev); 1689 return rc; 1690 } 1691 1692 static void switchtec_pci_remove(struct pci_dev *pdev) 1693 { 1694 struct switchtec_dev *stdev = pci_get_drvdata(pdev); 1695 1696 pci_set_drvdata(pdev, NULL); 1697 1698 cdev_device_del(&stdev->cdev, &stdev->dev); 1699 ida_simple_remove(&switchtec_minor_ida, MINOR(stdev->dev.devt)); 1700 dev_info(&stdev->dev, "unregistered.\n"); 1701 stdev_kill(stdev); 1702 put_device(&stdev->dev); 1703 } 1704 1705 #define SWITCHTEC_PCI_DEVICE(device_id, gen) \ 1706 { \ 1707 .vendor = PCI_VENDOR_ID_MICROSEMI, \ 1708 .device = device_id, \ 1709 .subvendor = PCI_ANY_ID, \ 1710 .subdevice = PCI_ANY_ID, \ 1711 .class = (PCI_CLASS_MEMORY_OTHER << 8), \ 1712 .class_mask = 0xFFFFFFFF, \ 1713 .driver_data = gen, \ 1714 }, \ 1715 { \ 1716 .vendor = PCI_VENDOR_ID_MICROSEMI, \ 1717 .device = device_id, \ 1718 .subvendor = PCI_ANY_ID, \ 1719 .subdevice = PCI_ANY_ID, \ 1720 .class = (PCI_CLASS_BRIDGE_OTHER << 8), \ 1721 .class_mask = 0xFFFFFFFF, \ 1722 .driver_data = gen, \ 1723 } 1724 1725 static const struct pci_device_id switchtec_pci_tbl[] = { 1726 SWITCHTEC_PCI_DEVICE(0x8531, SWITCHTEC_GEN3), //PFX 24xG3 1727 SWITCHTEC_PCI_DEVICE(0x8532, SWITCHTEC_GEN3), //PFX 32xG3 1728 SWITCHTEC_PCI_DEVICE(0x8533, SWITCHTEC_GEN3), //PFX 48xG3 1729 SWITCHTEC_PCI_DEVICE(0x8534, SWITCHTEC_GEN3), //PFX 64xG3 1730 SWITCHTEC_PCI_DEVICE(0x8535, SWITCHTEC_GEN3), //PFX 80xG3 1731 SWITCHTEC_PCI_DEVICE(0x8536, SWITCHTEC_GEN3), //PFX 96xG3 1732 SWITCHTEC_PCI_DEVICE(0x8541, SWITCHTEC_GEN3), //PSX 24xG3 1733 SWITCHTEC_PCI_DEVICE(0x8542, SWITCHTEC_GEN3), //PSX 32xG3 1734 SWITCHTEC_PCI_DEVICE(0x8543, SWITCHTEC_GEN3), //PSX 48xG3 1735 SWITCHTEC_PCI_DEVICE(0x8544, SWITCHTEC_GEN3), //PSX 64xG3 1736 SWITCHTEC_PCI_DEVICE(0x8545, SWITCHTEC_GEN3), //PSX 80xG3 1737 SWITCHTEC_PCI_DEVICE(0x8546, SWITCHTEC_GEN3), //PSX 96xG3 1738 SWITCHTEC_PCI_DEVICE(0x8551, SWITCHTEC_GEN3), //PAX 24XG3 1739 SWITCHTEC_PCI_DEVICE(0x8552, SWITCHTEC_GEN3), //PAX 32XG3 1740 SWITCHTEC_PCI_DEVICE(0x8553, SWITCHTEC_GEN3), //PAX 48XG3 1741 SWITCHTEC_PCI_DEVICE(0x8554, SWITCHTEC_GEN3), //PAX 64XG3 1742 SWITCHTEC_PCI_DEVICE(0x8555, SWITCHTEC_GEN3), //PAX 80XG3 1743 SWITCHTEC_PCI_DEVICE(0x8556, SWITCHTEC_GEN3), //PAX 96XG3 1744 SWITCHTEC_PCI_DEVICE(0x8561, SWITCHTEC_GEN3), //PFXL 24XG3 1745 SWITCHTEC_PCI_DEVICE(0x8562, SWITCHTEC_GEN3), //PFXL 32XG3 1746 SWITCHTEC_PCI_DEVICE(0x8563, SWITCHTEC_GEN3), //PFXL 48XG3 1747 SWITCHTEC_PCI_DEVICE(0x8564, SWITCHTEC_GEN3), //PFXL 64XG3 1748 SWITCHTEC_PCI_DEVICE(0x8565, SWITCHTEC_GEN3), //PFXL 80XG3 1749 SWITCHTEC_PCI_DEVICE(0x8566, SWITCHTEC_GEN3), //PFXL 96XG3 1750 SWITCHTEC_PCI_DEVICE(0x8571, SWITCHTEC_GEN3), //PFXI 24XG3 1751 SWITCHTEC_PCI_DEVICE(0x8572, SWITCHTEC_GEN3), //PFXI 32XG3 1752 SWITCHTEC_PCI_DEVICE(0x8573, SWITCHTEC_GEN3), //PFXI 48XG3 1753 SWITCHTEC_PCI_DEVICE(0x8574, SWITCHTEC_GEN3), //PFXI 64XG3 1754 SWITCHTEC_PCI_DEVICE(0x8575, SWITCHTEC_GEN3), //PFXI 80XG3 1755 SWITCHTEC_PCI_DEVICE(0x8576, SWITCHTEC_GEN3), //PFXI 96XG3 1756 SWITCHTEC_PCI_DEVICE(0x4000, SWITCHTEC_GEN4), //PFX 100XG4 1757 SWITCHTEC_PCI_DEVICE(0x4084, SWITCHTEC_GEN4), //PFX 84XG4 1758 SWITCHTEC_PCI_DEVICE(0x4068, SWITCHTEC_GEN4), //PFX 68XG4 1759 SWITCHTEC_PCI_DEVICE(0x4052, SWITCHTEC_GEN4), //PFX 52XG4 1760 SWITCHTEC_PCI_DEVICE(0x4036, SWITCHTEC_GEN4), //PFX 36XG4 1761 SWITCHTEC_PCI_DEVICE(0x4028, SWITCHTEC_GEN4), //PFX 28XG4 1762 SWITCHTEC_PCI_DEVICE(0x4100, SWITCHTEC_GEN4), //PSX 100XG4 1763 SWITCHTEC_PCI_DEVICE(0x4184, SWITCHTEC_GEN4), //PSX 84XG4 1764 SWITCHTEC_PCI_DEVICE(0x4168, SWITCHTEC_GEN4), //PSX 68XG4 1765 SWITCHTEC_PCI_DEVICE(0x4152, SWITCHTEC_GEN4), //PSX 52XG4 1766 SWITCHTEC_PCI_DEVICE(0x4136, SWITCHTEC_GEN4), //PSX 36XG4 1767 SWITCHTEC_PCI_DEVICE(0x4128, SWITCHTEC_GEN4), //PSX 28XG4 1768 SWITCHTEC_PCI_DEVICE(0x4200, SWITCHTEC_GEN4), //PAX 100XG4 1769 SWITCHTEC_PCI_DEVICE(0x4284, SWITCHTEC_GEN4), //PAX 84XG4 1770 SWITCHTEC_PCI_DEVICE(0x4268, SWITCHTEC_GEN4), //PAX 68XG4 1771 SWITCHTEC_PCI_DEVICE(0x4252, SWITCHTEC_GEN4), //PAX 52XG4 1772 SWITCHTEC_PCI_DEVICE(0x4236, SWITCHTEC_GEN4), //PAX 36XG4 1773 SWITCHTEC_PCI_DEVICE(0x4228, SWITCHTEC_GEN4), //PAX 28XG4 1774 {0} 1775 }; 1776 MODULE_DEVICE_TABLE(pci, switchtec_pci_tbl); 1777 1778 static struct pci_driver switchtec_pci_driver = { 1779 .name = KBUILD_MODNAME, 1780 .id_table = switchtec_pci_tbl, 1781 .probe = switchtec_pci_probe, 1782 .remove = switchtec_pci_remove, 1783 }; 1784 1785 static int __init switchtec_init(void) 1786 { 1787 int rc; 1788 1789 rc = alloc_chrdev_region(&switchtec_devt, 0, max_devices, 1790 "switchtec"); 1791 if (rc) 1792 return rc; 1793 1794 switchtec_class = class_create(THIS_MODULE, "switchtec"); 1795 if (IS_ERR(switchtec_class)) { 1796 rc = PTR_ERR(switchtec_class); 1797 goto err_create_class; 1798 } 1799 1800 rc = pci_register_driver(&switchtec_pci_driver); 1801 if (rc) 1802 goto err_pci_register; 1803 1804 pr_info(KBUILD_MODNAME ": loaded.\n"); 1805 1806 return 0; 1807 1808 err_pci_register: 1809 class_destroy(switchtec_class); 1810 1811 err_create_class: 1812 unregister_chrdev_region(switchtec_devt, max_devices); 1813 1814 return rc; 1815 } 1816 module_init(switchtec_init); 1817 1818 static void __exit switchtec_exit(void) 1819 { 1820 pci_unregister_driver(&switchtec_pci_driver); 1821 class_destroy(switchtec_class); 1822 unregister_chrdev_region(switchtec_devt, max_devices); 1823 ida_destroy(&switchtec_minor_ida); 1824 1825 pr_info(KBUILD_MODNAME ": unloaded.\n"); 1826 } 1827 module_exit(switchtec_exit); 1828