1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support routines for initializing a PCI subsystem 4 * 5 * Extruded from code written by 6 * Dave Rusling (david.rusling@reo.mts.dec.com) 7 * David Mosberger (davidm@cs.arizona.edu) 8 * David Miller (davem@redhat.com) 9 * 10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de> 11 * 12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 13 * Resource sorting 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/errno.h> 20 #include <linux/ioport.h> 21 #include <linux/cache.h> 22 #include <linux/slab.h> 23 #include "pci.h" 24 25 static void pci_std_update_resource(struct pci_dev *dev, int resno) 26 { 27 struct pci_bus_region region; 28 bool disable; 29 u16 cmd; 30 u32 new, check, mask; 31 int reg; 32 struct resource *res = dev->resource + resno; 33 const char *res_name = pci_resource_name(dev, resno); 34 35 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ 36 if (dev->is_virtfn) 37 return; 38 39 /* 40 * Ignore resources for unimplemented BARs and unused resource slots 41 * for 64 bit BARs. 42 */ 43 if (!res->flags) 44 return; 45 46 if (res->flags & IORESOURCE_UNSET) 47 return; 48 49 /* 50 * Ignore non-moveable resources. This might be legacy resources for 51 * which no functional BAR register exists or another important 52 * system resource we shouldn't move around. 53 */ 54 if (res->flags & IORESOURCE_PCI_FIXED) 55 return; 56 57 pcibios_resource_to_bus(dev->bus, ®ion, res); 58 new = region.start; 59 60 if (res->flags & IORESOURCE_IO) { 61 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 62 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK; 63 } else if (resno == PCI_ROM_RESOURCE) { 64 mask = PCI_ROM_ADDRESS_MASK; 65 } else { 66 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 67 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; 68 } 69 70 if (resno < PCI_ROM_RESOURCE) { 71 reg = PCI_BASE_ADDRESS_0 + 4 * resno; 72 } else if (resno == PCI_ROM_RESOURCE) { 73 74 /* 75 * Apparently some Matrox devices have ROM BARs that read 76 * as zero when disabled, so don't update ROM BARs unless 77 * they're enabled. See 78 * https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/ 79 * But we must update ROM BAR for buggy devices where even a 80 * disabled ROM can conflict with other BARs. 81 */ 82 if (!(res->flags & IORESOURCE_ROM_ENABLE) && 83 !dev->rom_bar_overlap) 84 return; 85 86 reg = dev->rom_base_reg; 87 if (res->flags & IORESOURCE_ROM_ENABLE) 88 new |= PCI_ROM_ADDRESS_ENABLE; 89 } else 90 return; 91 92 /* 93 * We can't update a 64-bit BAR atomically, so when possible, 94 * disable decoding so that a half-updated BAR won't conflict 95 * with another device. 96 */ 97 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; 98 if (disable) { 99 pci_read_config_word(dev, PCI_COMMAND, &cmd); 100 pci_write_config_word(dev, PCI_COMMAND, 101 cmd & ~PCI_COMMAND_MEMORY); 102 } 103 104 pci_write_config_dword(dev, reg, new); 105 pci_read_config_dword(dev, reg, &check); 106 107 if ((new ^ check) & mask) { 108 pci_err(dev, "%s: error updating (%#010x != %#010x)\n", 109 res_name, new, check); 110 } 111 112 if (res->flags & IORESOURCE_MEM_64) { 113 new = region.start >> 16 >> 16; 114 pci_write_config_dword(dev, reg + 4, new); 115 pci_read_config_dword(dev, reg + 4, &check); 116 if (check != new) { 117 pci_err(dev, "%s: error updating (high %#010x != %#010x)\n", 118 res_name, new, check); 119 } 120 } 121 122 if (disable) 123 pci_write_config_word(dev, PCI_COMMAND, cmd); 124 } 125 126 void pci_update_resource(struct pci_dev *dev, int resno) 127 { 128 if (resno <= PCI_ROM_RESOURCE) 129 pci_std_update_resource(dev, resno); 130 #ifdef CONFIG_PCI_IOV 131 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 132 pci_iov_update_resource(dev, resno); 133 #endif 134 } 135 136 int pci_claim_resource(struct pci_dev *dev, int resource) 137 { 138 struct resource *res = &dev->resource[resource]; 139 const char *res_name = pci_resource_name(dev, resource); 140 struct resource *root, *conflict; 141 142 if (res->flags & IORESOURCE_UNSET) { 143 pci_info(dev, "%s %pR: can't claim; no address assigned\n", 144 res_name, res); 145 return -EINVAL; 146 } 147 148 /* 149 * If we have a shadow copy in RAM, the PCI device doesn't respond 150 * to the shadow range, so we don't need to claim it, and upstream 151 * bridges don't need to route the range to the device. 152 */ 153 if (res->flags & IORESOURCE_ROM_SHADOW) 154 return 0; 155 156 root = pci_find_parent_resource(dev, res); 157 if (!root) { 158 pci_info(dev, "%s %pR: can't claim; no compatible bridge window\n", 159 res_name, res); 160 res->flags |= IORESOURCE_UNSET; 161 return -EINVAL; 162 } 163 164 conflict = request_resource_conflict(root, res); 165 if (conflict) { 166 pci_info(dev, "%s %pR: can't claim; address conflict with %s %pR\n", 167 res_name, res, conflict->name, conflict); 168 res->flags |= IORESOURCE_UNSET; 169 return -EBUSY; 170 } 171 172 return 0; 173 } 174 EXPORT_SYMBOL(pci_claim_resource); 175 176 void pci_disable_bridge_window(struct pci_dev *dev) 177 { 178 /* MMIO Base/Limit */ 179 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); 180 181 /* Prefetchable MMIO Base/Limit */ 182 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); 183 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); 184 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); 185 } 186 187 /* 188 * Generic function that returns a value indicating that the device's 189 * original BIOS BAR address was not saved and so is not available for 190 * reinstatement. 191 * 192 * Can be over-ridden by architecture specific code that implements 193 * reinstatement functionality rather than leaving it disabled when 194 * normal allocation attempts fail. 195 */ 196 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) 197 { 198 return 0; 199 } 200 201 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 202 int resno, resource_size_t size) 203 { 204 struct resource *root, *conflict; 205 resource_size_t fw_addr, start, end; 206 const char *res_name = pci_resource_name(dev, resno); 207 208 fw_addr = pcibios_retrieve_fw_addr(dev, resno); 209 if (!fw_addr) 210 return -ENOMEM; 211 212 start = res->start; 213 end = res->end; 214 resource_set_range(res, fw_addr, size); 215 res->flags &= ~IORESOURCE_UNSET; 216 217 root = pci_find_parent_resource(dev, res); 218 if (!root) { 219 /* 220 * If dev is behind a bridge, accesses will only reach it 221 * if res is inside the relevant bridge window. 222 */ 223 if (pci_upstream_bridge(dev)) 224 return -ENXIO; 225 226 /* 227 * On the root bus, assume the host bridge will forward 228 * everything. 229 */ 230 if (res->flags & IORESOURCE_IO) 231 root = &ioport_resource; 232 else 233 root = &iomem_resource; 234 } 235 236 pci_info(dev, "%s: trying firmware assignment %pR\n", res_name, res); 237 conflict = request_resource_conflict(root, res); 238 if (conflict) { 239 pci_info(dev, "%s %pR: conflicts with %s %pR\n", res_name, res, 240 conflict->name, conflict); 241 res->start = start; 242 res->end = end; 243 res->flags |= IORESOURCE_UNSET; 244 return -EBUSY; 245 } 246 return 0; 247 } 248 249 /* 250 * We don't have to worry about legacy ISA devices, so nothing to do here. 251 * This is marked as __weak because multiple architectures define it; it should 252 * eventually go away. 253 */ 254 resource_size_t __weak pcibios_align_resource(void *data, 255 const struct resource *res, 256 resource_size_t size, 257 resource_size_t align) 258 { 259 return res->start; 260 } 261 262 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, 263 int resno, resource_size_t size, resource_size_t align) 264 { 265 struct resource *res = dev->resource + resno; 266 resource_size_t min; 267 int ret; 268 269 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 270 271 /* 272 * First, try exact prefetching match. Even if a 64-bit 273 * prefetchable bridge window is below 4GB, we can't put a 32-bit 274 * prefetchable resource in it because pbus_size_mem() assumes a 275 * 64-bit window will contain no 32-bit resources. If we assign 276 * things differently than they were sized, not everything will fit. 277 */ 278 ret = pci_bus_alloc_resource(bus, res, size, align, min, 279 IORESOURCE_PREFETCH | IORESOURCE_MEM_64, 280 pcibios_align_resource, dev); 281 if (ret == 0) 282 return 0; 283 284 /* 285 * If the prefetchable window is only 32 bits wide, we can put 286 * 64-bit prefetchable resources in it. 287 */ 288 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == 289 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { 290 ret = pci_bus_alloc_resource(bus, res, size, align, min, 291 IORESOURCE_PREFETCH, 292 pcibios_align_resource, dev); 293 if (ret == 0) 294 return 0; 295 } 296 297 /* 298 * If we didn't find a better match, we can put any memory resource 299 * in a non-prefetchable window. If this resource is 32 bits and 300 * non-prefetchable, the first call already tried the only possibility 301 * so we don't need to try again. 302 */ 303 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) 304 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, 305 pcibios_align_resource, dev); 306 307 return ret; 308 } 309 310 static int _pci_assign_resource(struct pci_dev *dev, int resno, 311 resource_size_t size, resource_size_t min_align) 312 { 313 struct pci_bus *bus; 314 int ret; 315 316 bus = dev->bus; 317 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { 318 if (!bus->parent || !bus->self->transparent) 319 break; 320 bus = bus->parent; 321 } 322 323 return ret; 324 } 325 326 int pci_assign_resource(struct pci_dev *dev, int resno) 327 { 328 struct resource *res = dev->resource + resno; 329 const char *res_name = pci_resource_name(dev, resno); 330 resource_size_t align, size; 331 int ret; 332 333 if (res->flags & IORESOURCE_PCI_FIXED) 334 return 0; 335 336 res->flags |= IORESOURCE_UNSET; 337 align = pci_resource_alignment(dev, res); 338 if (!align) { 339 pci_info(dev, "%s %pR: can't assign; bogus alignment\n", 340 res_name, res); 341 return -EINVAL; 342 } 343 344 size = resource_size(res); 345 ret = _pci_assign_resource(dev, resno, size, align); 346 347 /* 348 * If we failed to assign anything, let's try the address 349 * where firmware left it. That at least has a chance of 350 * working, which is better than just leaving it disabled. 351 */ 352 if (ret < 0) { 353 pci_info(dev, "%s %pR: can't assign; no space\n", res_name, res); 354 ret = pci_revert_fw_address(res, dev, resno, size); 355 } 356 357 if (ret < 0) { 358 pci_info(dev, "%s %pR: failed to assign\n", res_name, res); 359 return ret; 360 } 361 362 res->flags &= ~IORESOURCE_UNSET; 363 res->flags &= ~IORESOURCE_STARTALIGN; 364 pci_info(dev, "%s %pR: assigned\n", res_name, res); 365 if (resno < PCI_BRIDGE_RESOURCES) 366 pci_update_resource(dev, resno); 367 368 return 0; 369 } 370 EXPORT_SYMBOL(pci_assign_resource); 371 372 int pci_reassign_resource(struct pci_dev *dev, int resno, 373 resource_size_t addsize, resource_size_t min_align) 374 { 375 struct resource *res = dev->resource + resno; 376 const char *res_name = pci_resource_name(dev, resno); 377 unsigned long flags; 378 resource_size_t new_size; 379 int ret; 380 381 if (res->flags & IORESOURCE_PCI_FIXED) 382 return 0; 383 384 flags = res->flags; 385 res->flags |= IORESOURCE_UNSET; 386 if (!res->parent) { 387 pci_info(dev, "%s %pR: can't reassign; unassigned resource\n", 388 res_name, res); 389 return -EINVAL; 390 } 391 392 /* already aligned with min_align */ 393 new_size = resource_size(res) + addsize; 394 ret = _pci_assign_resource(dev, resno, new_size, min_align); 395 if (ret) { 396 res->flags = flags; 397 pci_info(dev, "%s %pR: failed to expand by %#llx\n", 398 res_name, res, (unsigned long long) addsize); 399 return ret; 400 } 401 402 res->flags &= ~IORESOURCE_UNSET; 403 res->flags &= ~IORESOURCE_STARTALIGN; 404 pci_info(dev, "%s %pR: reassigned; expanded by %#llx\n", 405 res_name, res, (unsigned long long) addsize); 406 if (resno < PCI_BRIDGE_RESOURCES) 407 pci_update_resource(dev, resno); 408 409 return 0; 410 } 411 412 void pci_release_resource(struct pci_dev *dev, int resno) 413 { 414 struct resource *res = dev->resource + resno; 415 const char *res_name = pci_resource_name(dev, resno); 416 417 pci_info(dev, "%s %pR: releasing\n", res_name, res); 418 419 if (!res->parent) 420 return; 421 422 release_resource(res); 423 res->end = resource_size(res) - 1; 424 res->start = 0; 425 res->flags |= IORESOURCE_UNSET; 426 } 427 EXPORT_SYMBOL(pci_release_resource); 428 429 int pci_resize_resource(struct pci_dev *dev, int resno, int size) 430 { 431 struct resource *res = dev->resource + resno; 432 struct pci_host_bridge *host; 433 int old, ret; 434 u32 sizes; 435 u16 cmd; 436 437 /* Check if we must preserve the firmware's resource assignment */ 438 host = pci_find_host_bridge(dev->bus); 439 if (host->preserve_config) 440 return -ENOTSUPP; 441 442 /* Make sure the resource isn't assigned before resizing it. */ 443 if (!(res->flags & IORESOURCE_UNSET)) 444 return -EBUSY; 445 446 pci_read_config_word(dev, PCI_COMMAND, &cmd); 447 if (cmd & PCI_COMMAND_MEMORY) 448 return -EBUSY; 449 450 sizes = pci_rebar_get_possible_sizes(dev, resno); 451 if (!sizes) 452 return -ENOTSUPP; 453 454 if (!(sizes & BIT(size))) 455 return -EINVAL; 456 457 old = pci_rebar_get_current_size(dev, resno); 458 if (old < 0) 459 return old; 460 461 ret = pci_rebar_set_size(dev, resno, size); 462 if (ret) 463 return ret; 464 465 resource_set_size(res, pci_rebar_size_to_bytes(size)); 466 467 /* Check if the new config works by trying to assign everything. */ 468 if (dev->bus->self) { 469 ret = pci_reassign_bridge_resources(dev->bus->self, res->flags); 470 if (ret) 471 goto error_resize; 472 } 473 return 0; 474 475 error_resize: 476 pci_rebar_set_size(dev, resno, old); 477 resource_set_size(res, pci_rebar_size_to_bytes(old)); 478 return ret; 479 } 480 EXPORT_SYMBOL(pci_resize_resource); 481 482 int pci_enable_resources(struct pci_dev *dev, int mask) 483 { 484 u16 cmd, old_cmd; 485 int i; 486 struct resource *r; 487 const char *r_name; 488 489 pci_read_config_word(dev, PCI_COMMAND, &cmd); 490 old_cmd = cmd; 491 492 pci_dev_for_each_resource(dev, r, i) { 493 if (!(mask & (1 << i))) 494 continue; 495 496 r_name = pci_resource_name(dev, i); 497 498 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 499 continue; 500 if ((i == PCI_ROM_RESOURCE) && 501 (!(r->flags & IORESOURCE_ROM_ENABLE))) 502 continue; 503 504 if (r->flags & IORESOURCE_UNSET) { 505 pci_err(dev, "%s %pR: not assigned; can't enable device\n", 506 r_name, r); 507 return -EINVAL; 508 } 509 510 if (!r->parent) { 511 pci_err(dev, "%s %pR: not claimed; can't enable device\n", 512 r_name, r); 513 return -EINVAL; 514 } 515 516 if (r->flags & IORESOURCE_IO) 517 cmd |= PCI_COMMAND_IO; 518 if (r->flags & IORESOURCE_MEM) 519 cmd |= PCI_COMMAND_MEMORY; 520 } 521 522 if (cmd != old_cmd) { 523 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); 524 pci_write_config_word(dev, PCI_COMMAND, cmd); 525 } 526 return 0; 527 } 528