1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support routines for initializing a PCI subsystem 4 * 5 * Extruded from code written by 6 * Dave Rusling (david.rusling@reo.mts.dec.com) 7 * David Mosberger (davidm@cs.arizona.edu) 8 * David Miller (davem@redhat.com) 9 * 10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de> 11 * 12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 13 * Resource sorting 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/errno.h> 20 #include <linux/ioport.h> 21 #include <linux/cache.h> 22 #include <linux/slab.h> 23 #include "pci.h" 24 25 static void pci_std_update_resource(struct pci_dev *dev, int resno) 26 { 27 struct pci_bus_region region; 28 bool disable; 29 u16 cmd; 30 u32 new, check, mask; 31 int reg; 32 struct resource *res = pci_resource_n(dev, resno); 33 const char *res_name = pci_resource_name(dev, resno); 34 35 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ 36 if (dev->is_virtfn) 37 return; 38 39 /* 40 * Ignore resources for unimplemented BARs and unused resource slots 41 * for 64 bit BARs. 42 */ 43 if (!res->flags) 44 return; 45 46 if (res->flags & IORESOURCE_UNSET) 47 return; 48 49 /* 50 * Ignore non-moveable resources. This might be legacy resources for 51 * which no functional BAR register exists or another important 52 * system resource we shouldn't move around. 53 */ 54 if (res->flags & IORESOURCE_PCI_FIXED) 55 return; 56 57 pcibios_resource_to_bus(dev->bus, ®ion, res); 58 new = region.start; 59 60 if (res->flags & IORESOURCE_IO) { 61 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 62 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK; 63 } else if (resno == PCI_ROM_RESOURCE) { 64 mask = PCI_ROM_ADDRESS_MASK; 65 } else { 66 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 67 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; 68 } 69 70 if (resno < PCI_ROM_RESOURCE) { 71 reg = PCI_BASE_ADDRESS_0 + 4 * resno; 72 } else if (resno == PCI_ROM_RESOURCE) { 73 74 /* 75 * Apparently some Matrox devices have ROM BARs that read 76 * as zero when disabled, so don't update ROM BARs unless 77 * they're enabled. See 78 * https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/ 79 * But we must update ROM BAR for buggy devices where even a 80 * disabled ROM can conflict with other BARs. 81 */ 82 if (!(res->flags & IORESOURCE_ROM_ENABLE) && 83 !dev->rom_bar_overlap) 84 return; 85 86 reg = dev->rom_base_reg; 87 if (res->flags & IORESOURCE_ROM_ENABLE) 88 new |= PCI_ROM_ADDRESS_ENABLE; 89 } else 90 return; 91 92 /* 93 * We can't update a 64-bit BAR atomically, so when possible, 94 * disable decoding so that a half-updated BAR won't conflict 95 * with another device. 96 */ 97 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; 98 if (disable) { 99 pci_read_config_word(dev, PCI_COMMAND, &cmd); 100 pci_write_config_word(dev, PCI_COMMAND, 101 cmd & ~PCI_COMMAND_MEMORY); 102 } 103 104 pci_write_config_dword(dev, reg, new); 105 pci_read_config_dword(dev, reg, &check); 106 107 if ((new ^ check) & mask) { 108 pci_err(dev, "%s: error updating (%#010x != %#010x)\n", 109 res_name, new, check); 110 } 111 112 if (res->flags & IORESOURCE_MEM_64) { 113 new = region.start >> 16 >> 16; 114 pci_write_config_dword(dev, reg + 4, new); 115 pci_read_config_dword(dev, reg + 4, &check); 116 if (check != new) { 117 pci_err(dev, "%s: error updating (high %#010x != %#010x)\n", 118 res_name, new, check); 119 } 120 } 121 122 if (disable) 123 pci_write_config_word(dev, PCI_COMMAND, cmd); 124 } 125 126 void pci_update_resource(struct pci_dev *dev, int resno) 127 { 128 if (resno <= PCI_ROM_RESOURCE) 129 pci_std_update_resource(dev, resno); 130 else if (pci_resource_is_iov(resno)) 131 pci_iov_update_resource(dev, resno); 132 } 133 134 int pci_claim_resource(struct pci_dev *dev, int resource) 135 { 136 struct resource *res = &dev->resource[resource]; 137 const char *res_name = pci_resource_name(dev, resource); 138 struct resource *root, *conflict; 139 140 if (res->flags & IORESOURCE_UNSET) { 141 pci_info(dev, "%s %pR: can't claim; no address assigned\n", 142 res_name, res); 143 return -EINVAL; 144 } 145 146 /* 147 * If we have a shadow copy in RAM, the PCI device doesn't respond 148 * to the shadow range, so we don't need to claim it, and upstream 149 * bridges don't need to route the range to the device. 150 */ 151 if (res->flags & IORESOURCE_ROM_SHADOW) 152 return 0; 153 154 root = pci_find_parent_resource(dev, res); 155 if (!root) { 156 pci_info(dev, "%s %pR: can't claim; no compatible bridge window\n", 157 res_name, res); 158 res->flags |= IORESOURCE_UNSET; 159 return -EINVAL; 160 } 161 162 conflict = request_resource_conflict(root, res); 163 if (conflict) { 164 pci_info(dev, "%s %pR: can't claim; address conflict with %s %pR\n", 165 res_name, res, conflict->name, conflict); 166 res->flags |= IORESOURCE_UNSET; 167 return -EBUSY; 168 } 169 170 return 0; 171 } 172 EXPORT_SYMBOL(pci_claim_resource); 173 174 void pci_disable_bridge_window(struct pci_dev *dev) 175 { 176 /* MMIO Base/Limit */ 177 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); 178 179 /* Prefetchable MMIO Base/Limit */ 180 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); 181 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); 182 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); 183 } 184 185 /* 186 * Generic function that returns a value indicating that the device's 187 * original BIOS BAR address was not saved and so is not available for 188 * reinstatement. 189 * 190 * Can be over-ridden by architecture specific code that implements 191 * reinstatement functionality rather than leaving it disabled when 192 * normal allocation attempts fail. 193 */ 194 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) 195 { 196 return 0; 197 } 198 199 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 200 int resno, resource_size_t size) 201 { 202 struct resource *root, *conflict; 203 resource_size_t fw_addr, start, end; 204 const char *res_name = pci_resource_name(dev, resno); 205 206 fw_addr = pcibios_retrieve_fw_addr(dev, resno); 207 if (!fw_addr) 208 return -ENOMEM; 209 210 start = res->start; 211 end = res->end; 212 resource_set_range(res, fw_addr, size); 213 res->flags &= ~IORESOURCE_UNSET; 214 215 root = pci_find_parent_resource(dev, res); 216 if (!root) { 217 /* 218 * If dev is behind a bridge, accesses will only reach it 219 * if res is inside the relevant bridge window. 220 */ 221 if (pci_upstream_bridge(dev)) 222 return -ENXIO; 223 224 /* 225 * On the root bus, assume the host bridge will forward 226 * everything. 227 */ 228 if (res->flags & IORESOURCE_IO) 229 root = &ioport_resource; 230 else 231 root = &iomem_resource; 232 } 233 234 pci_info(dev, "%s: trying firmware assignment %pR\n", res_name, res); 235 conflict = request_resource_conflict(root, res); 236 if (conflict) { 237 pci_info(dev, "%s %pR: conflicts with %s %pR\n", res_name, res, 238 conflict->name, conflict); 239 res->start = start; 240 res->end = end; 241 res->flags |= IORESOURCE_UNSET; 242 return -EBUSY; 243 } 244 return 0; 245 } 246 247 /* 248 * For mem bridge windows, try to relocate tail remainder space to space 249 * before res->start if there's enough free space there. This enables 250 * tighter packing for resources. 251 */ 252 resource_size_t pci_align_resource(struct pci_dev *dev, 253 const struct resource *res, 254 const struct resource *empty_res, 255 resource_size_t size, 256 resource_size_t align) 257 { 258 resource_size_t remainder, start_addr; 259 260 if (!(res->flags & IORESOURCE_MEM)) 261 return res->start; 262 263 if (IS_ALIGNED(size, align)) 264 return res->start; 265 266 remainder = size - ALIGN_DOWN(size, align); 267 /* Don't mess with size that doesn't align with window size granularity */ 268 if (!IS_ALIGNED(remainder, pci_min_window_alignment(dev->bus, res->flags))) 269 return res->start; 270 /* Try to place remainder that doesn't fill align before */ 271 if (res->start < remainder) 272 return res->start; 273 start_addr = res->start - remainder; 274 if (empty_res->start > start_addr) 275 return res->start; 276 277 pci_dbg(dev, "%pR: moving candidate start address below align to %llx\n", 278 res, (unsigned long long)start_addr); 279 return start_addr; 280 } 281 282 /* 283 * We don't have to worry about legacy ISA devices, so nothing to do here. 284 * This is marked as __weak because multiple architectures define it; it should 285 * eventually go away. 286 */ 287 resource_size_t __weak pcibios_align_resource(void *data, 288 const struct resource *res, 289 const struct resource *empty_res, 290 resource_size_t size, 291 resource_size_t align) 292 { 293 struct pci_dev *dev = data; 294 295 return pci_align_resource(dev, res, empty_res, size, align); 296 } 297 298 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, 299 int resno, resource_size_t size, resource_size_t align) 300 { 301 struct resource *res = pci_resource_n(dev, resno); 302 resource_size_t min; 303 int ret; 304 305 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 306 307 /* 308 * First, try exact prefetching match. Even if a 64-bit 309 * prefetchable bridge window is below 4GB, we can't put a 32-bit 310 * prefetchable resource in it because pbus_size_mem() assumes a 311 * 64-bit window will contain no 32-bit resources. If we assign 312 * things differently than they were sized, not everything will fit. 313 */ 314 ret = pci_bus_alloc_resource(bus, res, size, align, min, 315 IORESOURCE_PREFETCH | IORESOURCE_MEM_64, 316 pcibios_align_resource, dev); 317 if (ret == 0) 318 return 0; 319 320 /* 321 * If the prefetchable window is only 32 bits wide, we can put 322 * 64-bit prefetchable resources in it. 323 */ 324 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == 325 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { 326 ret = pci_bus_alloc_resource(bus, res, size, align, min, 327 IORESOURCE_PREFETCH, 328 pcibios_align_resource, dev); 329 if (ret == 0) 330 return 0; 331 } 332 333 /* 334 * If we didn't find a better match, we can put any memory resource 335 * in a non-prefetchable window. If this resource is 32 bits and 336 * non-prefetchable, the first call already tried the only possibility 337 * so we don't need to try again. 338 */ 339 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) 340 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, 341 pcibios_align_resource, dev); 342 343 return ret; 344 } 345 346 static int _pci_assign_resource(struct pci_dev *dev, int resno, 347 resource_size_t size, resource_size_t min_align) 348 { 349 struct pci_bus *bus; 350 int ret; 351 352 bus = dev->bus; 353 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { 354 if (!bus->parent || !bus->self->transparent) 355 break; 356 bus = bus->parent; 357 } 358 359 return ret; 360 } 361 362 int pci_assign_resource(struct pci_dev *dev, int resno) 363 { 364 struct resource *res = pci_resource_n(dev, resno); 365 const char *res_name = pci_resource_name(dev, resno); 366 resource_size_t align, size; 367 int ret; 368 369 if (res->flags & IORESOURCE_PCI_FIXED) 370 return 0; 371 372 res->flags |= IORESOURCE_UNSET; 373 align = pci_resource_alignment(dev, res); 374 if (!align) { 375 pci_info(dev, "%s %pR: can't assign; bogus alignment\n", 376 res_name, res); 377 return -EINVAL; 378 } 379 380 size = resource_size(res); 381 ret = _pci_assign_resource(dev, resno, size, align); 382 383 /* 384 * If we failed to assign anything, let's try the address 385 * where firmware left it. That at least has a chance of 386 * working, which is better than just leaving it disabled. 387 */ 388 if (ret < 0) { 389 pci_info(dev, "%s %pR: can't assign; no space\n", res_name, res); 390 ret = pci_revert_fw_address(res, dev, resno, size); 391 } 392 393 if (ret < 0) { 394 pci_info(dev, "%s %pR: failed to assign\n", res_name, res); 395 return ret; 396 } 397 398 res->flags &= ~IORESOURCE_UNSET; 399 res->flags &= ~IORESOURCE_STARTALIGN; 400 if (pci_resource_is_bridge_win(resno)) 401 res->flags &= ~IORESOURCE_DISABLED; 402 403 pci_info(dev, "%s %pR: assigned\n", res_name, res); 404 if (resno < PCI_BRIDGE_RESOURCES) 405 pci_update_resource(dev, resno); 406 407 return 0; 408 } 409 EXPORT_SYMBOL(pci_assign_resource); 410 411 int pci_reassign_resource(struct pci_dev *dev, int resno, 412 resource_size_t addsize, resource_size_t min_align) 413 { 414 struct resource *res = pci_resource_n(dev, resno); 415 const char *res_name = pci_resource_name(dev, resno); 416 unsigned long flags; 417 resource_size_t new_size; 418 int ret; 419 420 if (res->flags & IORESOURCE_PCI_FIXED) 421 return 0; 422 423 flags = res->flags; 424 res->flags |= IORESOURCE_UNSET; 425 if (!res->parent) { 426 pci_info(dev, "%s %pR: can't reassign; unassigned resource\n", 427 res_name, res); 428 return -EINVAL; 429 } 430 431 new_size = resource_size(res) + addsize; 432 ret = _pci_assign_resource(dev, resno, new_size, min_align); 433 if (ret) { 434 res->flags = flags; 435 pci_info(dev, "%s %pR: failed to expand by %#llx\n", 436 res_name, res, (unsigned long long) addsize); 437 return ret; 438 } 439 440 res->flags &= ~IORESOURCE_UNSET; 441 res->flags &= ~IORESOURCE_STARTALIGN; 442 pci_info(dev, "%s %pR: reassigned; expanded by %#llx\n", 443 res_name, res, (unsigned long long) addsize); 444 if (resno < PCI_BRIDGE_RESOURCES) 445 pci_update_resource(dev, resno); 446 447 return 0; 448 } 449 450 int pci_release_resource(struct pci_dev *dev, int resno) 451 { 452 struct resource *res = pci_resource_n(dev, resno); 453 const char *res_name = pci_resource_name(dev, resno); 454 int ret; 455 456 if (!res->parent) 457 return 0; 458 459 pci_info(dev, "%s %pR: releasing\n", res_name, res); 460 461 ret = release_resource(res); 462 if (ret) 463 return ret; 464 res->end = resource_size(res) - 1; 465 res->start = 0; 466 res->flags |= IORESOURCE_UNSET; 467 468 return 0; 469 } 470 EXPORT_SYMBOL(pci_release_resource); 471 472 int pci_enable_resources(struct pci_dev *dev, int mask) 473 { 474 u16 cmd, old_cmd; 475 int i; 476 struct resource *r; 477 const char *r_name; 478 479 pci_read_config_word(dev, PCI_COMMAND, &cmd); 480 old_cmd = cmd; 481 482 pci_dev_for_each_resource(dev, r, i) { 483 if (!(mask & (1 << i))) 484 continue; 485 486 r_name = pci_resource_name(dev, i); 487 488 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 489 continue; 490 if (pci_resource_is_optional(dev, i)) 491 continue; 492 493 if (i < PCI_BRIDGE_RESOURCES) { 494 if (r->flags & IORESOURCE_UNSET) { 495 pci_err(dev, "%s %pR: not assigned; can't enable device\n", 496 r_name, r); 497 return -EINVAL; 498 } 499 500 if (!r->parent) { 501 pci_err(dev, "%s %pR: not claimed; can't enable device\n", 502 r_name, r); 503 return -EINVAL; 504 } 505 } 506 507 if (r->parent) { 508 if (r->flags & IORESOURCE_IO) 509 cmd |= PCI_COMMAND_IO; 510 if (r->flags & IORESOURCE_MEM) 511 cmd |= PCI_COMMAND_MEMORY; 512 } 513 } 514 515 if (cmd != old_cmd) { 516 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); 517 pci_write_config_word(dev, PCI_COMMAND, cmd); 518 } 519 return 0; 520 } 521