1 /* 2 * drivers/pci/setup-bus.c 3 * 4 * Extruded from code written by 5 * Dave Rusling (david.rusling@reo.mts.dec.com) 6 * David Mosberger (davidm@cs.arizona.edu) 7 * David Miller (davem@redhat.com) 8 * 9 * Support routines for initializing a PCI subsystem. 10 */ 11 12 /* 13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 14 * PCI-PCI bridges cleanup, sorted resource allocation. 15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 16 * Converted to allocation in 3 passes, which gives 17 * tighter packing. Prefetchable range support. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/pci.h> 24 #include <linux/errno.h> 25 #include <linux/ioport.h> 26 #include <linux/cache.h> 27 #include <linux/slab.h> 28 29 30 #define DEBUG_CONFIG 1 31 #if DEBUG_CONFIG 32 #define DBG(x...) printk(x) 33 #else 34 #define DBG(x...) 35 #endif 36 37 static void pbus_assign_resources_sorted(struct pci_bus *bus) 38 { 39 struct pci_dev *dev; 40 struct resource *res; 41 struct resource_list head, *list, *tmp; 42 int idx; 43 44 head.next = NULL; 45 list_for_each_entry(dev, &bus->devices, bus_list) { 46 u16 class = dev->class >> 8; 47 48 /* Don't touch classless devices or host bridges or ioapics. */ 49 if (class == PCI_CLASS_NOT_DEFINED || 50 class == PCI_CLASS_BRIDGE_HOST) 51 continue; 52 53 /* Don't touch ioapic devices already enabled by firmware */ 54 if (class == PCI_CLASS_SYSTEM_PIC) { 55 u16 command; 56 pci_read_config_word(dev, PCI_COMMAND, &command); 57 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) 58 continue; 59 } 60 61 pdev_sort_resources(dev, &head); 62 } 63 64 for (list = head.next; list;) { 65 res = list->res; 66 idx = res - &list->dev->resource[0]; 67 if (pci_assign_resource(list->dev, idx)) { 68 res->start = 0; 69 res->end = 0; 70 res->flags = 0; 71 } 72 tmp = list; 73 list = list->next; 74 kfree(tmp); 75 } 76 } 77 78 void pci_setup_cardbus(struct pci_bus *bus) 79 { 80 struct pci_dev *bridge = bus->self; 81 struct pci_bus_region region; 82 83 printk("PCI: Bus %d, cardbus bridge: %s\n", 84 bus->number, pci_name(bridge)); 85 86 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); 87 if (bus->resource[0]->flags & IORESOURCE_IO) { 88 /* 89 * The IO resource is allocated a range twice as large as it 90 * would normally need. This allows us to set both IO regs. 91 */ 92 printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n", 93 (unsigned long)region.start, 94 (unsigned long)region.end); 95 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 96 region.start); 97 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 98 region.end); 99 } 100 101 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); 102 if (bus->resource[1]->flags & IORESOURCE_IO) { 103 printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n", 104 (unsigned long)region.start, 105 (unsigned long)region.end); 106 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 107 region.start); 108 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 109 region.end); 110 } 111 112 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); 113 if (bus->resource[2]->flags & IORESOURCE_MEM) { 114 printk(KERN_INFO " PREFETCH window: 0x%08lx-0x%08lx\n", 115 (unsigned long)region.start, 116 (unsigned long)region.end); 117 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 118 region.start); 119 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 120 region.end); 121 } 122 123 pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); 124 if (bus->resource[3]->flags & IORESOURCE_MEM) { 125 printk(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n", 126 (unsigned long)region.start, 127 (unsigned long)region.end); 128 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 129 region.start); 130 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 131 region.end); 132 } 133 } 134 EXPORT_SYMBOL(pci_setup_cardbus); 135 136 /* Initialize bridges with base/limit values we have collected. 137 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) 138 requires that if there is no I/O ports or memory behind the 139 bridge, corresponding range must be turned off by writing base 140 value greater than limit to the bridge's base/limit registers. 141 142 Note: care must be taken when updating I/O base/limit registers 143 of bridges which support 32-bit I/O. This update requires two 144 config space writes, so it's quite possible that an I/O window of 145 the bridge will have some undesirable address (e.g. 0) after the 146 first write. Ditto 64-bit prefetchable MMIO. */ 147 static void __devinit 148 pci_setup_bridge(struct pci_bus *bus) 149 { 150 struct pci_dev *bridge = bus->self; 151 struct pci_bus_region region; 152 u32 l, bu, lu, io_upper16; 153 154 DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge)); 155 156 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 157 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); 158 if (bus->resource[0]->flags & IORESOURCE_IO) { 159 pci_read_config_dword(bridge, PCI_IO_BASE, &l); 160 l &= 0xffff0000; 161 l |= (region.start >> 8) & 0x00f0; 162 l |= region.end & 0xf000; 163 /* Set up upper 16 bits of I/O base/limit. */ 164 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 165 DBG(KERN_INFO " IO window: %04lx-%04lx\n", 166 (unsigned long)region.start, 167 (unsigned long)region.end); 168 } 169 else { 170 /* Clear upper 16 bits of I/O base/limit. */ 171 io_upper16 = 0; 172 l = 0x00f0; 173 DBG(KERN_INFO " IO window: disabled.\n"); 174 } 175 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ 176 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 177 /* Update lower 16 bits of I/O base/limit. */ 178 pci_write_config_dword(bridge, PCI_IO_BASE, l); 179 /* Update upper 16 bits of I/O base/limit. */ 180 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 181 182 /* Set up the top and bottom of the PCI Memory segment 183 for this bus. */ 184 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); 185 if (bus->resource[1]->flags & IORESOURCE_MEM) { 186 l = (region.start >> 16) & 0xfff0; 187 l |= region.end & 0xfff00000; 188 DBG(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n", 189 (unsigned long)region.start, 190 (unsigned long)region.end); 191 } 192 else { 193 l = 0x0000fff0; 194 DBG(KERN_INFO " MEM window: disabled.\n"); 195 } 196 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 197 198 /* Clear out the upper 32 bits of PREF limit. 199 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily 200 disables PREF range, which is ok. */ 201 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 202 203 /* Set up PREF base/limit. */ 204 bu = lu = 0; 205 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); 206 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { 207 l = (region.start >> 16) & 0xfff0; 208 l |= region.end & 0xfff00000; 209 #ifdef CONFIG_RESOURCES_64BIT 210 bu = region.start >> 32; 211 lu = region.end >> 32; 212 #endif 213 DBG(KERN_INFO " PREFETCH window: 0x%016llx-0x%016llx\n", 214 (unsigned long long)region.start, 215 (unsigned long long)region.end); 216 } 217 else { 218 l = 0x0000fff0; 219 DBG(KERN_INFO " PREFETCH window: disabled.\n"); 220 } 221 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 222 223 /* Set the upper 32 bits of PREF base & limit. */ 224 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); 225 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); 226 227 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 228 } 229 230 /* Check whether the bridge supports optional I/O and 231 prefetchable memory ranges. If not, the respective 232 base/limit registers must be read-only and read as 0. */ 233 static void pci_bridge_check_ranges(struct pci_bus *bus) 234 { 235 u16 io; 236 u32 pmem; 237 struct pci_dev *bridge = bus->self; 238 struct resource *b_res; 239 240 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 241 b_res[1].flags |= IORESOURCE_MEM; 242 243 pci_read_config_word(bridge, PCI_IO_BASE, &io); 244 if (!io) { 245 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); 246 pci_read_config_word(bridge, PCI_IO_BASE, &io); 247 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 248 } 249 if (io) 250 b_res[0].flags |= IORESOURCE_IO; 251 /* DECchip 21050 pass 2 errata: the bridge may miss an address 252 disconnect boundary by one PCI data phase. 253 Workaround: do not use prefetching on this device. */ 254 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 255 return; 256 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 257 if (!pmem) { 258 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 259 0xfff0fff0); 260 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 261 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 262 } 263 if (pmem) 264 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 265 } 266 267 /* Helper function for sizing routines: find first available 268 bus resource of a given type. Note: we intentionally skip 269 the bus resources which have already been assigned (that is, 270 have non-NULL parent resource). */ 271 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) 272 { 273 int i; 274 struct resource *r; 275 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 276 IORESOURCE_PREFETCH; 277 278 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 279 r = bus->resource[i]; 280 if (r == &ioport_resource || r == &iomem_resource) 281 continue; 282 if (r && (r->flags & type_mask) == type && !r->parent) 283 return r; 284 } 285 return NULL; 286 } 287 288 /* Sizing the IO windows of the PCI-PCI bridge is trivial, 289 since these windows have 4K granularity and the IO ranges 290 of non-bridge PCI devices are limited to 256 bytes. 291 We must be careful with the ISA aliasing though. */ 292 static void pbus_size_io(struct pci_bus *bus) 293 { 294 struct pci_dev *dev; 295 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 296 unsigned long size = 0, size1 = 0; 297 298 if (!b_res) 299 return; 300 301 list_for_each_entry(dev, &bus->devices, bus_list) { 302 int i; 303 304 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 305 struct resource *r = &dev->resource[i]; 306 unsigned long r_size; 307 308 if (r->parent || !(r->flags & IORESOURCE_IO)) 309 continue; 310 r_size = r->end - r->start + 1; 311 312 if (r_size < 0x400) 313 /* Might be re-aligned for ISA */ 314 size += r_size; 315 else 316 size1 += r_size; 317 } 318 } 319 /* To be fixed in 2.5: we should have sort of HAVE_ISA 320 flag in the struct pci_bus. */ 321 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 322 size = (size & 0xff) + ((size & ~0xffUL) << 2); 323 #endif 324 size = ALIGN(size + size1, 4096); 325 if (!size) { 326 b_res->flags = 0; 327 return; 328 } 329 /* Alignment of the IO window is always 4K */ 330 b_res->start = 4096; 331 b_res->end = b_res->start + size - 1; 332 } 333 334 /* Calculate the size of the bus and minimal alignment which 335 guarantees that all child resources fit in this size. */ 336 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) 337 { 338 struct pci_dev *dev; 339 resource_size_t min_align, align, size; 340 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ 341 int order, max_order; 342 struct resource *b_res = find_free_bus_resource(bus, type); 343 344 if (!b_res) 345 return 0; 346 347 memset(aligns, 0, sizeof(aligns)); 348 max_order = 0; 349 size = 0; 350 351 list_for_each_entry(dev, &bus->devices, bus_list) { 352 int i; 353 354 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 355 struct resource *r = &dev->resource[i]; 356 resource_size_t r_size; 357 358 if (r->parent || (r->flags & mask) != type) 359 continue; 360 r_size = r->end - r->start + 1; 361 /* For bridges size != alignment */ 362 align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start; 363 order = __ffs(align) - 20; 364 if (order > 11) { 365 printk(KERN_WARNING "PCI: region %s/%d " 366 "too large: 0x%016llx-0x%016llx\n", 367 pci_name(dev), i, 368 (unsigned long long)r->start, 369 (unsigned long long)r->end); 370 r->flags = 0; 371 continue; 372 } 373 size += r_size; 374 if (order < 0) 375 order = 0; 376 /* Exclude ranges with size > align from 377 calculation of the alignment. */ 378 if (r_size == align) 379 aligns[order] += align; 380 if (order > max_order) 381 max_order = order; 382 } 383 } 384 385 align = 0; 386 min_align = 0; 387 for (order = 0; order <= max_order; order++) { 388 #ifdef CONFIG_RESOURCES_64BIT 389 resource_size_t align1 = 1ULL << (order + 20); 390 #else 391 resource_size_t align1 = 1U << (order + 20); 392 #endif 393 if (!align) 394 min_align = align1; 395 else if (ALIGN(align + min_align, min_align) < align1) 396 min_align = align1 >> 1; 397 align += aligns[order]; 398 } 399 size = ALIGN(size, min_align); 400 if (!size) { 401 b_res->flags = 0; 402 return 1; 403 } 404 b_res->start = min_align; 405 b_res->end = size + min_align - 1; 406 return 1; 407 } 408 409 static void __devinit 410 pci_bus_size_cardbus(struct pci_bus *bus) 411 { 412 struct pci_dev *bridge = bus->self; 413 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 414 u16 ctrl; 415 416 /* 417 * Reserve some resources for CardBus. We reserve 418 * a fixed amount of bus space for CardBus bridges. 419 */ 420 b_res[0].start = pci_cardbus_io_size; 421 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; 422 b_res[0].flags |= IORESOURCE_IO; 423 424 b_res[1].start = pci_cardbus_io_size; 425 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; 426 b_res[1].flags |= IORESOURCE_IO; 427 428 /* 429 * Check whether prefetchable memory is supported 430 * by this bridge. 431 */ 432 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 433 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 434 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 435 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 436 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 437 } 438 439 /* 440 * If we have prefetchable memory support, allocate 441 * two regions. Otherwise, allocate one region of 442 * twice the size. 443 */ 444 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 445 b_res[2].start = pci_cardbus_mem_size; 446 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; 447 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 448 449 b_res[3].start = pci_cardbus_mem_size; 450 b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1; 451 b_res[3].flags |= IORESOURCE_MEM; 452 } else { 453 b_res[3].start = pci_cardbus_mem_size * 2; 454 b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1; 455 b_res[3].flags |= IORESOURCE_MEM; 456 } 457 } 458 459 void __ref pci_bus_size_bridges(struct pci_bus *bus) 460 { 461 struct pci_dev *dev; 462 unsigned long mask, prefmask; 463 464 list_for_each_entry(dev, &bus->devices, bus_list) { 465 struct pci_bus *b = dev->subordinate; 466 if (!b) 467 continue; 468 469 switch (dev->class >> 8) { 470 case PCI_CLASS_BRIDGE_CARDBUS: 471 pci_bus_size_cardbus(b); 472 break; 473 474 case PCI_CLASS_BRIDGE_PCI: 475 default: 476 pci_bus_size_bridges(b); 477 break; 478 } 479 } 480 481 /* The root bus? */ 482 if (!bus->self) 483 return; 484 485 switch (bus->self->class >> 8) { 486 case PCI_CLASS_BRIDGE_CARDBUS: 487 /* don't size cardbuses yet. */ 488 break; 489 490 case PCI_CLASS_BRIDGE_PCI: 491 /* don't size subtractive decoding (transparent) 492 * PCI-to-PCI bridges */ 493 if (bus->self->transparent) 494 break; 495 pci_bridge_check_ranges(bus); 496 /* fall through */ 497 default: 498 pbus_size_io(bus); 499 /* If the bridge supports prefetchable range, size it 500 separately. If it doesn't, or its prefetchable window 501 has already been allocated by arch code, try 502 non-prefetchable range for both types of PCI memory 503 resources. */ 504 mask = IORESOURCE_MEM; 505 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 506 if (pbus_size_mem(bus, prefmask, prefmask)) 507 mask = prefmask; /* Success, size non-prefetch only. */ 508 pbus_size_mem(bus, mask, IORESOURCE_MEM); 509 break; 510 } 511 } 512 EXPORT_SYMBOL(pci_bus_size_bridges); 513 514 void __ref pci_bus_assign_resources(struct pci_bus *bus) 515 { 516 struct pci_bus *b; 517 struct pci_dev *dev; 518 519 pbus_assign_resources_sorted(bus); 520 521 list_for_each_entry(dev, &bus->devices, bus_list) { 522 b = dev->subordinate; 523 if (!b) 524 continue; 525 526 pci_bus_assign_resources(b); 527 528 switch (dev->class >> 8) { 529 case PCI_CLASS_BRIDGE_PCI: 530 pci_setup_bridge(b); 531 break; 532 533 case PCI_CLASS_BRIDGE_CARDBUS: 534 pci_setup_cardbus(b); 535 break; 536 537 default: 538 printk(KERN_INFO "PCI: not setting up bridge %s " 539 "for bus %d\n", pci_name(dev), b->number); 540 break; 541 } 542 } 543 } 544 EXPORT_SYMBOL(pci_bus_assign_resources); 545 546 void __init 547 pci_assign_unassigned_resources(void) 548 { 549 struct pci_bus *bus; 550 551 /* Depth first, calculate sizes and alignments of all 552 subordinate buses. */ 553 list_for_each_entry(bus, &pci_root_buses, node) { 554 pci_bus_size_bridges(bus); 555 } 556 /* Depth last, allocate resources and update the hardware. */ 557 list_for_each_entry(bus, &pci_root_buses, node) { 558 pci_bus_assign_resources(bus); 559 pci_enable_bridges(bus); 560 } 561 } 562