1 /* 2 * drivers/pci/setup-bus.c 3 * 4 * Extruded from code written by 5 * Dave Rusling (david.rusling@reo.mts.dec.com) 6 * David Mosberger (davidm@cs.arizona.edu) 7 * David Miller (davem@redhat.com) 8 * 9 * Support routines for initializing a PCI subsystem. 10 */ 11 12 /* 13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 14 * PCI-PCI bridges cleanup, sorted resource allocation. 15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 16 * Converted to allocation in 3 passes, which gives 17 * tighter packing. Prefetchable range support. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/pci.h> 24 #include <linux/errno.h> 25 #include <linux/ioport.h> 26 #include <linux/cache.h> 27 #include <linux/slab.h> 28 29 30 #define DEBUG_CONFIG 1 31 #if DEBUG_CONFIG 32 #define DBG(x...) printk(x) 33 #else 34 #define DBG(x...) 35 #endif 36 37 #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1)) 38 39 static void pbus_assign_resources_sorted(struct pci_bus *bus) 40 { 41 struct pci_dev *dev; 42 struct resource *res; 43 struct resource_list head, *list, *tmp; 44 int idx; 45 46 head.next = NULL; 47 list_for_each_entry(dev, &bus->devices, bus_list) { 48 u16 class = dev->class >> 8; 49 50 /* Don't touch classless devices or host bridges or ioapics. */ 51 if (class == PCI_CLASS_NOT_DEFINED || 52 class == PCI_CLASS_BRIDGE_HOST) 53 continue; 54 55 /* Don't touch ioapic devices already enabled by firmware */ 56 if (class == PCI_CLASS_SYSTEM_PIC) { 57 u16 command; 58 pci_read_config_word(dev, PCI_COMMAND, &command); 59 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) 60 continue; 61 } 62 63 pdev_sort_resources(dev, &head); 64 } 65 66 for (list = head.next; list;) { 67 res = list->res; 68 idx = res - &list->dev->resource[0]; 69 if (pci_assign_resource(list->dev, idx)) { 70 res->start = 0; 71 res->end = 0; 72 res->flags = 0; 73 } 74 tmp = list; 75 list = list->next; 76 kfree(tmp); 77 } 78 } 79 80 void pci_setup_cardbus(struct pci_bus *bus) 81 { 82 struct pci_dev *bridge = bus->self; 83 struct pci_bus_region region; 84 85 printk("PCI: Bus %d, cardbus bridge: %s\n", 86 bus->number, pci_name(bridge)); 87 88 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); 89 if (bus->resource[0]->flags & IORESOURCE_IO) { 90 /* 91 * The IO resource is allocated a range twice as large as it 92 * would normally need. This allows us to set both IO regs. 93 */ 94 printk(" IO window: %08lx-%08lx\n", 95 region.start, region.end); 96 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 97 region.start); 98 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 99 region.end); 100 } 101 102 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); 103 if (bus->resource[1]->flags & IORESOURCE_IO) { 104 printk(" IO window: %08lx-%08lx\n", 105 region.start, region.end); 106 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 107 region.start); 108 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 109 region.end); 110 } 111 112 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); 113 if (bus->resource[2]->flags & IORESOURCE_MEM) { 114 printk(" PREFETCH window: %08lx-%08lx\n", 115 region.start, region.end); 116 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 117 region.start); 118 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 119 region.end); 120 } 121 122 pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); 123 if (bus->resource[3]->flags & IORESOURCE_MEM) { 124 printk(" MEM window: %08lx-%08lx\n", 125 region.start, region.end); 126 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 127 region.start); 128 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 129 region.end); 130 } 131 } 132 EXPORT_SYMBOL(pci_setup_cardbus); 133 134 /* Initialize bridges with base/limit values we have collected. 135 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) 136 requires that if there is no I/O ports or memory behind the 137 bridge, corresponding range must be turned off by writing base 138 value greater than limit to the bridge's base/limit registers. 139 140 Note: care must be taken when updating I/O base/limit registers 141 of bridges which support 32-bit I/O. This update requires two 142 config space writes, so it's quite possible that an I/O window of 143 the bridge will have some undesirable address (e.g. 0) after the 144 first write. Ditto 64-bit prefetchable MMIO. */ 145 static void __devinit 146 pci_setup_bridge(struct pci_bus *bus) 147 { 148 struct pci_dev *bridge = bus->self; 149 struct pci_bus_region region; 150 u32 l, io_upper16; 151 152 DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge)); 153 154 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 155 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); 156 if (bus->resource[0]->flags & IORESOURCE_IO) { 157 pci_read_config_dword(bridge, PCI_IO_BASE, &l); 158 l &= 0xffff0000; 159 l |= (region.start >> 8) & 0x00f0; 160 l |= region.end & 0xf000; 161 /* Set up upper 16 bits of I/O base/limit. */ 162 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 163 DBG(KERN_INFO " IO window: %04lx-%04lx\n", 164 region.start, region.end); 165 } 166 else { 167 /* Clear upper 16 bits of I/O base/limit. */ 168 io_upper16 = 0; 169 l = 0x00f0; 170 DBG(KERN_INFO " IO window: disabled.\n"); 171 } 172 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ 173 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 174 /* Update lower 16 bits of I/O base/limit. */ 175 pci_write_config_dword(bridge, PCI_IO_BASE, l); 176 /* Update upper 16 bits of I/O base/limit. */ 177 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 178 179 /* Set up the top and bottom of the PCI Memory segment 180 for this bus. */ 181 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); 182 if (bus->resource[1]->flags & IORESOURCE_MEM) { 183 l = (region.start >> 16) & 0xfff0; 184 l |= region.end & 0xfff00000; 185 DBG(KERN_INFO " MEM window: %08lx-%08lx\n", 186 region.start, region.end); 187 } 188 else { 189 l = 0x0000fff0; 190 DBG(KERN_INFO " MEM window: disabled.\n"); 191 } 192 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 193 194 /* Clear out the upper 32 bits of PREF limit. 195 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily 196 disables PREF range, which is ok. */ 197 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 198 199 /* Set up PREF base/limit. */ 200 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); 201 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { 202 l = (region.start >> 16) & 0xfff0; 203 l |= region.end & 0xfff00000; 204 DBG(KERN_INFO " PREFETCH window: %08lx-%08lx\n", 205 region.start, region.end); 206 } 207 else { 208 l = 0x0000fff0; 209 DBG(KERN_INFO " PREFETCH window: disabled.\n"); 210 } 211 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 212 213 /* Clear out the upper 32 bits of PREF base. */ 214 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0); 215 216 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 217 } 218 219 /* Check whether the bridge supports optional I/O and 220 prefetchable memory ranges. If not, the respective 221 base/limit registers must be read-only and read as 0. */ 222 static void pci_bridge_check_ranges(struct pci_bus *bus) 223 { 224 u16 io; 225 u32 pmem; 226 struct pci_dev *bridge = bus->self; 227 struct resource *b_res; 228 229 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 230 b_res[1].flags |= IORESOURCE_MEM; 231 232 pci_read_config_word(bridge, PCI_IO_BASE, &io); 233 if (!io) { 234 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); 235 pci_read_config_word(bridge, PCI_IO_BASE, &io); 236 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 237 } 238 if (io) 239 b_res[0].flags |= IORESOURCE_IO; 240 /* DECchip 21050 pass 2 errata: the bridge may miss an address 241 disconnect boundary by one PCI data phase. 242 Workaround: do not use prefetching on this device. */ 243 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 244 return; 245 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 246 if (!pmem) { 247 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 248 0xfff0fff0); 249 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 250 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 251 } 252 if (pmem) 253 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 254 } 255 256 /* Helper function for sizing routines: find first available 257 bus resource of a given type. Note: we intentionally skip 258 the bus resources which have already been assigned (that is, 259 have non-NULL parent resource). */ 260 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) 261 { 262 int i; 263 struct resource *r; 264 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 265 IORESOURCE_PREFETCH; 266 267 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 268 r = bus->resource[i]; 269 if (r == &ioport_resource || r == &iomem_resource) 270 continue; 271 if (r && (r->flags & type_mask) == type && !r->parent) 272 return r; 273 } 274 return NULL; 275 } 276 277 /* Sizing the IO windows of the PCI-PCI bridge is trivial, 278 since these windows have 4K granularity and the IO ranges 279 of non-bridge PCI devices are limited to 256 bytes. 280 We must be careful with the ISA aliasing though. */ 281 static void pbus_size_io(struct pci_bus *bus) 282 { 283 struct pci_dev *dev; 284 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 285 unsigned long size = 0, size1 = 0; 286 287 if (!b_res) 288 return; 289 290 list_for_each_entry(dev, &bus->devices, bus_list) { 291 int i; 292 293 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 294 struct resource *r = &dev->resource[i]; 295 unsigned long r_size; 296 297 if (r->parent || !(r->flags & IORESOURCE_IO)) 298 continue; 299 r_size = r->end - r->start + 1; 300 301 if (r_size < 0x400) 302 /* Might be re-aligned for ISA */ 303 size += r_size; 304 else 305 size1 += r_size; 306 } 307 } 308 /* To be fixed in 2.5: we should have sort of HAVE_ISA 309 flag in the struct pci_bus. */ 310 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 311 size = (size & 0xff) + ((size & ~0xffUL) << 2); 312 #endif 313 size = ROUND_UP(size + size1, 4096); 314 if (!size) { 315 b_res->flags = 0; 316 return; 317 } 318 /* Alignment of the IO window is always 4K */ 319 b_res->start = 4096; 320 b_res->end = b_res->start + size - 1; 321 } 322 323 /* Calculate the size of the bus and minimal alignment which 324 guarantees that all child resources fit in this size. */ 325 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) 326 { 327 struct pci_dev *dev; 328 unsigned long min_align, align, size; 329 unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */ 330 int order, max_order; 331 struct resource *b_res = find_free_bus_resource(bus, type); 332 333 if (!b_res) 334 return 0; 335 336 memset(aligns, 0, sizeof(aligns)); 337 max_order = 0; 338 size = 0; 339 340 list_for_each_entry(dev, &bus->devices, bus_list) { 341 int i; 342 343 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 344 struct resource *r = &dev->resource[i]; 345 unsigned long r_size; 346 347 if (r->parent || (r->flags & mask) != type) 348 continue; 349 r_size = r->end - r->start + 1; 350 /* For bridges size != alignment */ 351 align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start; 352 order = __ffs(align) - 20; 353 if (order > 11) { 354 printk(KERN_WARNING "PCI: region %s/%d " 355 "too large: %llx-%llx\n", 356 pci_name(dev), i, 357 (unsigned long long)r->start, 358 (unsigned long long)r->end); 359 r->flags = 0; 360 continue; 361 } 362 size += r_size; 363 if (order < 0) 364 order = 0; 365 /* Exclude ranges with size > align from 366 calculation of the alignment. */ 367 if (r_size == align) 368 aligns[order] += align; 369 if (order > max_order) 370 max_order = order; 371 } 372 } 373 374 align = 0; 375 min_align = 0; 376 for (order = 0; order <= max_order; order++) { 377 unsigned long align1 = 1UL << (order + 20); 378 379 if (!align) 380 min_align = align1; 381 else if (ROUND_UP(align + min_align, min_align) < align1) 382 min_align = align1 >> 1; 383 align += aligns[order]; 384 } 385 size = ROUND_UP(size, min_align); 386 if (!size) { 387 b_res->flags = 0; 388 return 1; 389 } 390 b_res->start = min_align; 391 b_res->end = size + min_align - 1; 392 return 1; 393 } 394 395 static void __devinit 396 pci_bus_size_cardbus(struct pci_bus *bus) 397 { 398 struct pci_dev *bridge = bus->self; 399 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 400 u16 ctrl; 401 402 /* 403 * Reserve some resources for CardBus. We reserve 404 * a fixed amount of bus space for CardBus bridges. 405 */ 406 b_res[0].start = pci_cardbus_io_size; 407 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; 408 b_res[0].flags |= IORESOURCE_IO; 409 410 b_res[1].start = pci_cardbus_io_size; 411 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; 412 b_res[1].flags |= IORESOURCE_IO; 413 414 /* 415 * Check whether prefetchable memory is supported 416 * by this bridge. 417 */ 418 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 419 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 420 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 421 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 422 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 423 } 424 425 /* 426 * If we have prefetchable memory support, allocate 427 * two regions. Otherwise, allocate one region of 428 * twice the size. 429 */ 430 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 431 b_res[2].start = pci_cardbus_mem_size; 432 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; 433 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 434 435 b_res[3].start = pci_cardbus_mem_size; 436 b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1; 437 b_res[3].flags |= IORESOURCE_MEM; 438 } else { 439 b_res[3].start = pci_cardbus_mem_size * 2; 440 b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1; 441 b_res[3].flags |= IORESOURCE_MEM; 442 } 443 } 444 445 void pci_bus_size_bridges(struct pci_bus *bus) 446 { 447 struct pci_dev *dev; 448 unsigned long mask, prefmask; 449 450 list_for_each_entry(dev, &bus->devices, bus_list) { 451 struct pci_bus *b = dev->subordinate; 452 if (!b) 453 continue; 454 455 switch (dev->class >> 8) { 456 case PCI_CLASS_BRIDGE_CARDBUS: 457 pci_bus_size_cardbus(b); 458 break; 459 460 case PCI_CLASS_BRIDGE_PCI: 461 default: 462 pci_bus_size_bridges(b); 463 break; 464 } 465 } 466 467 /* The root bus? */ 468 if (!bus->self) 469 return; 470 471 switch (bus->self->class >> 8) { 472 case PCI_CLASS_BRIDGE_CARDBUS: 473 /* don't size cardbuses yet. */ 474 break; 475 476 case PCI_CLASS_BRIDGE_PCI: 477 pci_bridge_check_ranges(bus); 478 default: 479 pbus_size_io(bus); 480 /* If the bridge supports prefetchable range, size it 481 separately. If it doesn't, or its prefetchable window 482 has already been allocated by arch code, try 483 non-prefetchable range for both types of PCI memory 484 resources. */ 485 mask = IORESOURCE_MEM; 486 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 487 if (pbus_size_mem(bus, prefmask, prefmask)) 488 mask = prefmask; /* Success, size non-prefetch only. */ 489 pbus_size_mem(bus, mask, IORESOURCE_MEM); 490 break; 491 } 492 } 493 EXPORT_SYMBOL(pci_bus_size_bridges); 494 495 void pci_bus_assign_resources(struct pci_bus *bus) 496 { 497 struct pci_bus *b; 498 struct pci_dev *dev; 499 500 pbus_assign_resources_sorted(bus); 501 502 list_for_each_entry(dev, &bus->devices, bus_list) { 503 b = dev->subordinate; 504 if (!b) 505 continue; 506 507 pci_bus_assign_resources(b); 508 509 switch (dev->class >> 8) { 510 case PCI_CLASS_BRIDGE_PCI: 511 pci_setup_bridge(b); 512 break; 513 514 case PCI_CLASS_BRIDGE_CARDBUS: 515 pci_setup_cardbus(b); 516 break; 517 518 default: 519 printk(KERN_INFO "PCI: not setting up bridge %s " 520 "for bus %d\n", pci_name(dev), b->number); 521 break; 522 } 523 } 524 } 525 EXPORT_SYMBOL(pci_bus_assign_resources); 526 527 void __init 528 pci_assign_unassigned_resources(void) 529 { 530 struct pci_bus *bus; 531 532 /* Depth first, calculate sizes and alignments of all 533 subordinate buses. */ 534 list_for_each_entry(bus, &pci_root_buses, node) { 535 pci_bus_size_bridges(bus); 536 } 537 /* Depth last, allocate resources and update the hardware. */ 538 list_for_each_entry(bus, &pci_root_buses, node) { 539 pci_bus_assign_resources(bus); 540 pci_enable_bridges(bus); 541 } 542 } 543