1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support routines for initializing a PCI subsystem 4 * 5 * Extruded from code written by 6 * Dave Rusling (david.rusling@reo.mts.dec.com) 7 * David Mosberger (davidm@cs.arizona.edu) 8 * David Miller (davem@redhat.com) 9 * 10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 11 * PCI-PCI bridges cleanup, sorted resource allocation. 12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 13 * Converted to allocation in 3 passes, which gives 14 * tighter packing. Prefetchable range support. 15 */ 16 17 #include <linux/bitops.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/errno.h> 23 #include <linux/ioport.h> 24 #include <linux/cache.h> 25 #include <linux/limits.h> 26 #include <linux/sizes.h> 27 #include <linux/slab.h> 28 #include <linux/acpi.h> 29 #include "pci.h" 30 31 #define PCI_RES_TYPE_MASK \ 32 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\ 33 IORESOURCE_MEM_64) 34 35 unsigned int pci_flags; 36 EXPORT_SYMBOL_GPL(pci_flags); 37 38 struct pci_dev_resource { 39 struct list_head list; 40 struct resource *res; 41 struct pci_dev *dev; 42 resource_size_t start; 43 resource_size_t end; 44 resource_size_t add_size; 45 resource_size_t min_align; 46 unsigned long flags; 47 }; 48 49 static void free_list(struct list_head *head) 50 { 51 struct pci_dev_resource *dev_res, *tmp; 52 53 list_for_each_entry_safe(dev_res, tmp, head, list) { 54 list_del(&dev_res->list); 55 kfree(dev_res); 56 } 57 } 58 59 /** 60 * add_to_list() - Add a new resource tracker to the list 61 * @head: Head of the list 62 * @dev: Device to which the resource belongs 63 * @res: Resource to be tracked 64 * @add_size: Additional size to be optionally added to the resource 65 * @min_align: Minimum memory window alignment 66 */ 67 static int add_to_list(struct list_head *head, struct pci_dev *dev, 68 struct resource *res, resource_size_t add_size, 69 resource_size_t min_align) 70 { 71 struct pci_dev_resource *tmp; 72 73 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 74 if (!tmp) 75 return -ENOMEM; 76 77 tmp->res = res; 78 tmp->dev = dev; 79 tmp->start = res->start; 80 tmp->end = res->end; 81 tmp->flags = res->flags; 82 tmp->add_size = add_size; 83 tmp->min_align = min_align; 84 85 list_add(&tmp->list, head); 86 87 return 0; 88 } 89 90 static void remove_from_list(struct list_head *head, struct resource *res) 91 { 92 struct pci_dev_resource *dev_res, *tmp; 93 94 list_for_each_entry_safe(dev_res, tmp, head, list) { 95 if (dev_res->res == res) { 96 list_del(&dev_res->list); 97 kfree(dev_res); 98 break; 99 } 100 } 101 } 102 103 static struct pci_dev_resource *res_to_dev_res(struct list_head *head, 104 struct resource *res) 105 { 106 struct pci_dev_resource *dev_res; 107 108 list_for_each_entry(dev_res, head, list) { 109 if (dev_res->res == res) 110 return dev_res; 111 } 112 113 return NULL; 114 } 115 116 static resource_size_t get_res_add_size(struct list_head *head, 117 struct resource *res) 118 { 119 struct pci_dev_resource *dev_res; 120 121 dev_res = res_to_dev_res(head, res); 122 return dev_res ? dev_res->add_size : 0; 123 } 124 125 static resource_size_t get_res_add_align(struct list_head *head, 126 struct resource *res) 127 { 128 struct pci_dev_resource *dev_res; 129 130 dev_res = res_to_dev_res(head, res); 131 return dev_res ? dev_res->min_align : 0; 132 } 133 134 static void restore_dev_resource(struct pci_dev_resource *dev_res) 135 { 136 struct resource *res = dev_res->res; 137 138 res->start = dev_res->start; 139 res->end = dev_res->end; 140 res->flags = dev_res->flags; 141 } 142 143 /* 144 * Helper function for sizing routines. Assigned resources have non-NULL 145 * parent resource. 146 * 147 * Return first unassigned resource of the correct type. If there is none, 148 * return first assigned resource of the correct type. If none of the 149 * above, return NULL. 150 * 151 * Returning an assigned resource of the correct type allows the caller to 152 * distinguish between already assigned and no resource of the correct type. 153 */ 154 static struct resource *find_bus_resource_of_type(struct pci_bus *bus, 155 unsigned long type_mask, 156 unsigned long type) 157 { 158 struct resource *r, *r_assigned = NULL; 159 160 pci_bus_for_each_resource(bus, r) { 161 if (!r || r == &ioport_resource || r == &iomem_resource) 162 continue; 163 164 if ((r->flags & type_mask) != type) 165 continue; 166 167 if (!r->parent) 168 return r; 169 if (!r_assigned) 170 r_assigned = r; 171 } 172 return r_assigned; 173 } 174 175 /** 176 * pbus_select_window_for_type - Select bridge window for a resource type 177 * @bus: PCI bus 178 * @type: Resource type (resource flags can be passed as is) 179 * 180 * Select the bridge window based on a resource @type. 181 * 182 * For memory resources, the selection is done as follows: 183 * 184 * Any non-prefetchable resource is put into the non-prefetchable window. 185 * 186 * If there is no prefetchable MMIO window, put all memory resources into the 187 * non-prefetchable window. 188 * 189 * If there's a 64-bit prefetchable MMIO window, put all 64-bit prefetchable 190 * resources into it and place 32-bit prefetchable memory into the 191 * non-prefetchable window. 192 * 193 * Otherwise, put all prefetchable resources into the prefetchable window. 194 * 195 * Return: the bridge window resource or NULL if no bridge window is found. 196 */ 197 static struct resource *pbus_select_window_for_type(struct pci_bus *bus, 198 unsigned long type) 199 { 200 int iores_type = type & IORESOURCE_TYPE_BITS; /* w/o 64bit & pref */ 201 struct resource *mmio, *mmio_pref, *win; 202 203 type &= PCI_RES_TYPE_MASK; /* with 64bit & pref */ 204 205 if ((iores_type != IORESOURCE_IO) && (iores_type != IORESOURCE_MEM)) 206 return NULL; 207 208 if (pci_is_root_bus(bus)) { 209 win = find_bus_resource_of_type(bus, type, type); 210 if (win) 211 return win; 212 213 type &= ~IORESOURCE_MEM_64; 214 win = find_bus_resource_of_type(bus, type, type); 215 if (win) 216 return win; 217 218 type &= ~IORESOURCE_PREFETCH; 219 return find_bus_resource_of_type(bus, type, type); 220 } 221 222 switch (iores_type) { 223 case IORESOURCE_IO: 224 return pci_bus_resource_n(bus, PCI_BUS_BRIDGE_IO_WINDOW); 225 226 case IORESOURCE_MEM: 227 mmio = pci_bus_resource_n(bus, PCI_BUS_BRIDGE_MEM_WINDOW); 228 mmio_pref = pci_bus_resource_n(bus, PCI_BUS_BRIDGE_PREF_MEM_WINDOW); 229 230 if (!(type & IORESOURCE_PREFETCH) || 231 !(mmio_pref->flags & IORESOURCE_MEM)) 232 return mmio; 233 234 if ((type & IORESOURCE_MEM_64) || 235 !(mmio_pref->flags & IORESOURCE_MEM_64)) 236 return mmio_pref; 237 238 return mmio; 239 default: 240 return NULL; 241 } 242 } 243 244 /** 245 * pbus_select_window - Select bridge window for a resource 246 * @bus: PCI bus 247 * @res: Resource 248 * 249 * Select the bridge window for @res. If the resource is already assigned, 250 * return the current bridge window. 251 * 252 * For memory resources, the selection is done as follows: 253 * 254 * Any non-prefetchable resource is put into the non-prefetchable window. 255 * 256 * If there is no prefetchable MMIO window, put all memory resources into the 257 * non-prefetchable window. 258 * 259 * If there's a 64-bit prefetchable MMIO window, put all 64-bit prefetchable 260 * resources into it and place 32-bit prefetchable memory into the 261 * non-prefetchable window. 262 * 263 * Otherwise, put all prefetchable resources into the prefetchable window. 264 * 265 * Return: the bridge window resource or NULL if no bridge window is found. 266 */ 267 struct resource *pbus_select_window(struct pci_bus *bus, 268 const struct resource *res) 269 { 270 if (res->parent) 271 return res->parent; 272 273 return pbus_select_window_for_type(bus, res->flags); 274 } 275 276 static bool pdev_resources_assignable(struct pci_dev *dev) 277 { 278 u16 class = dev->class >> 8, command; 279 280 /* Don't touch classless devices or host bridges or IOAPICs */ 281 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) 282 return false; 283 284 /* Don't touch IOAPIC devices already enabled by firmware */ 285 if (class == PCI_CLASS_SYSTEM_PIC) { 286 pci_read_config_word(dev, PCI_COMMAND, &command); 287 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) 288 return false; 289 } 290 291 return true; 292 } 293 294 static bool pdev_resource_assignable(struct pci_dev *dev, struct resource *res) 295 { 296 int idx = pci_resource_num(dev, res); 297 298 if (!res->flags) 299 return false; 300 301 if (idx >= PCI_BRIDGE_RESOURCES && idx <= PCI_BRIDGE_RESOURCE_END && 302 res->flags & IORESOURCE_DISABLED) 303 return false; 304 305 return true; 306 } 307 308 static bool pdev_resource_should_fit(struct pci_dev *dev, struct resource *res) 309 { 310 if (res->parent) 311 return false; 312 313 if (res->flags & IORESOURCE_PCI_FIXED) 314 return false; 315 316 return pdev_resource_assignable(dev, res); 317 } 318 319 /* Sort resources by alignment */ 320 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) 321 { 322 struct resource *r; 323 int i; 324 325 if (!pdev_resources_assignable(dev)) 326 return; 327 328 pci_dev_for_each_resource(dev, r, i) { 329 const char *r_name = pci_resource_name(dev, i); 330 struct pci_dev_resource *dev_res, *tmp; 331 resource_size_t r_align; 332 struct list_head *n; 333 334 if (!pdev_resource_should_fit(dev, r)) 335 continue; 336 337 r_align = pci_resource_alignment(dev, r); 338 if (!r_align) { 339 pci_warn(dev, "%s %pR: alignment must not be zero\n", 340 r_name, r); 341 continue; 342 } 343 344 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 345 if (!tmp) 346 panic("%s: kzalloc() failed!\n", __func__); 347 tmp->res = r; 348 tmp->dev = dev; 349 tmp->start = r->start; 350 tmp->end = r->end; 351 tmp->flags = r->flags; 352 353 /* Fallback is smallest one or list is empty */ 354 n = head; 355 list_for_each_entry(dev_res, head, list) { 356 resource_size_t align; 357 358 align = pci_resource_alignment(dev_res->dev, 359 dev_res->res); 360 361 if (r_align > align) { 362 n = &dev_res->list; 363 break; 364 } 365 } 366 /* Insert it just before n */ 367 list_add_tail(&tmp->list, n); 368 } 369 } 370 371 bool pci_resource_is_optional(const struct pci_dev *dev, int resno) 372 { 373 const struct resource *res = pci_resource_n(dev, resno); 374 375 if (pci_resource_is_iov(resno)) 376 return true; 377 if (resno == PCI_ROM_RESOURCE && !(res->flags & IORESOURCE_ROM_ENABLE)) 378 return true; 379 380 return false; 381 } 382 383 static inline void reset_resource(struct pci_dev *dev, struct resource *res) 384 { 385 int idx = pci_resource_num(dev, res); 386 387 if (idx >= PCI_BRIDGE_RESOURCES && idx <= PCI_BRIDGE_RESOURCE_END) { 388 res->flags |= IORESOURCE_UNSET; 389 return; 390 } 391 392 res->start = 0; 393 res->end = 0; 394 res->flags = 0; 395 } 396 397 /** 398 * reassign_resources_sorted() - Satisfy any additional resource requests 399 * 400 * @realloc_head: Head of the list tracking requests requiring 401 * additional resources 402 * @head: Head of the list tracking requests with allocated 403 * resources 404 * 405 * Walk through each element of the realloc_head and try to procure additional 406 * resources for the element, provided the element is in the head list. 407 */ 408 static void reassign_resources_sorted(struct list_head *realloc_head, 409 struct list_head *head) 410 { 411 struct pci_dev_resource *add_res, *tmp; 412 struct pci_dev_resource *dev_res; 413 struct pci_dev *dev; 414 struct resource *res; 415 const char *res_name; 416 resource_size_t add_size, align; 417 int idx; 418 419 list_for_each_entry_safe(add_res, tmp, realloc_head, list) { 420 bool found_match = false; 421 422 res = add_res->res; 423 dev = add_res->dev; 424 idx = pci_resource_num(dev, res); 425 426 /* 427 * Skip resource that failed the earlier assignment and is 428 * not optional as it would just fail again. 429 */ 430 if (!res->parent && resource_size(res) && 431 !pci_resource_is_optional(dev, idx)) 432 goto out; 433 434 /* Skip this resource if not found in head list */ 435 list_for_each_entry(dev_res, head, list) { 436 if (dev_res->res == res) { 437 found_match = true; 438 break; 439 } 440 } 441 if (!found_match) /* Just skip */ 442 continue; 443 444 res_name = pci_resource_name(dev, idx); 445 add_size = add_res->add_size; 446 align = add_res->min_align; 447 if (!res->parent) { 448 resource_set_range(res, align, 449 resource_size(res) + add_size); 450 if (pci_assign_resource(dev, idx)) { 451 pci_dbg(dev, 452 "%s %pR: ignoring failure in optional allocation\n", 453 res_name, res); 454 } 455 } else if (add_size > 0) { 456 res->flags |= add_res->flags & 457 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); 458 if (pci_reassign_resource(dev, idx, add_size, align)) 459 pci_info(dev, "%s %pR: failed to add optional %llx\n", 460 res_name, res, 461 (unsigned long long) add_size); 462 } 463 out: 464 list_del(&add_res->list); 465 kfree(add_res); 466 } 467 } 468 469 /** 470 * assign_requested_resources_sorted() - Satisfy resource requests 471 * 472 * @head: Head of the list tracking requests for resources 473 * @fail_head: Head of the list tracking requests that could not be 474 * allocated 475 * @optional: Assign also optional resources 476 * 477 * Satisfy resource requests of each element in the list. Add requests that 478 * could not be satisfied to the failed_list. 479 */ 480 static void assign_requested_resources_sorted(struct list_head *head, 481 struct list_head *fail_head, 482 bool optional) 483 { 484 struct pci_dev_resource *dev_res; 485 struct resource *res; 486 struct pci_dev *dev; 487 bool optional_res; 488 int idx; 489 490 list_for_each_entry(dev_res, head, list) { 491 res = dev_res->res; 492 dev = dev_res->dev; 493 idx = pci_resource_num(dev, res); 494 optional_res = pci_resource_is_optional(dev, idx); 495 496 if (!resource_size(res)) 497 continue; 498 499 if (!optional && optional_res) 500 continue; 501 502 if (pci_assign_resource(dev, idx)) { 503 if (fail_head) { 504 add_to_list(fail_head, dev, res, 505 0 /* don't care */, 506 0 /* don't care */); 507 } 508 } 509 } 510 } 511 512 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) 513 { 514 struct pci_dev_resource *fail_res; 515 unsigned long mask = 0; 516 517 /* Check failed type */ 518 list_for_each_entry(fail_res, fail_head, list) 519 mask |= fail_res->flags; 520 521 /* 522 * One pref failed resource will set IORESOURCE_MEM, as we can 523 * allocate pref in non-pref range. Will release all assigned 524 * non-pref sibling resources according to that bit. 525 */ 526 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); 527 } 528 529 static bool pci_need_to_release(unsigned long mask, struct resource *res) 530 { 531 if (res->flags & IORESOURCE_IO) 532 return !!(mask & IORESOURCE_IO); 533 534 /* Check pref at first */ 535 if (res->flags & IORESOURCE_PREFETCH) { 536 if (mask & IORESOURCE_PREFETCH) 537 return true; 538 /* Count pref if its parent is non-pref */ 539 else if ((mask & IORESOURCE_MEM) && 540 !(res->parent->flags & IORESOURCE_PREFETCH)) 541 return true; 542 else 543 return false; 544 } 545 546 if (res->flags & IORESOURCE_MEM) 547 return !!(mask & IORESOURCE_MEM); 548 549 return false; /* Should not get here */ 550 } 551 552 /* Return: @true if assignment of a required resource failed. */ 553 static bool pci_required_resource_failed(struct list_head *fail_head, 554 unsigned long type) 555 { 556 struct pci_dev_resource *fail_res; 557 558 type &= PCI_RES_TYPE_MASK; 559 560 list_for_each_entry(fail_res, fail_head, list) { 561 int idx = pci_resource_num(fail_res->dev, fail_res->res); 562 563 if (type && (fail_res->flags & PCI_RES_TYPE_MASK) != type) 564 continue; 565 566 if (!pci_resource_is_optional(fail_res->dev, idx)) 567 return true; 568 } 569 return false; 570 } 571 572 static void __assign_resources_sorted(struct list_head *head, 573 struct list_head *realloc_head, 574 struct list_head *fail_head) 575 { 576 /* 577 * Should not assign requested resources at first. They could be 578 * adjacent, so later reassign can not reallocate them one by one in 579 * parent resource window. 580 * 581 * Try to assign required and any optional resources at beginning 582 * (add_size included). If all required resources were successfully 583 * assigned, get out early. If could not do that, we still try to 584 * assign required at first, then try to reassign some optional 585 * resources. 586 * 587 * Separate three resource type checking if we need to release 588 * assigned resource after requested + add_size try. 589 * 590 * 1. If IO port assignment fails, will release assigned IO 591 * port. 592 * 2. If pref MMIO assignment fails, release assigned pref 593 * MMIO. If assigned pref MMIO's parent is non-pref MMIO 594 * and non-pref MMIO assignment fails, will release that 595 * assigned pref MMIO. 596 * 3. If non-pref MMIO assignment fails or pref MMIO 597 * assignment fails, will release assigned non-pref MMIO. 598 */ 599 LIST_HEAD(save_head); 600 LIST_HEAD(local_fail_head); 601 LIST_HEAD(dummy_head); 602 struct pci_dev_resource *save_res; 603 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; 604 struct resource *res; 605 struct pci_dev *dev; 606 unsigned long fail_type; 607 resource_size_t add_align, align; 608 609 if (!realloc_head) 610 realloc_head = &dummy_head; 611 612 /* Check if optional add_size is there */ 613 if (list_empty(realloc_head)) 614 goto assign; 615 616 /* Save original start, end, flags etc at first */ 617 list_for_each_entry(dev_res, head, list) { 618 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { 619 free_list(&save_head); 620 goto assign; 621 } 622 } 623 624 /* Update res in head list with add_size in realloc_head list */ 625 list_for_each_entry_safe(dev_res, tmp_res, head, list) { 626 res = dev_res->res; 627 628 res->end += get_res_add_size(realloc_head, res); 629 630 /* 631 * There are two kinds of additional resources in the list: 632 * 1. bridge resource -- IORESOURCE_STARTALIGN 633 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN 634 * Here just fix the additional alignment for bridge 635 */ 636 if (!(res->flags & IORESOURCE_STARTALIGN)) 637 continue; 638 639 add_align = get_res_add_align(realloc_head, res); 640 641 /* 642 * The "head" list is sorted by alignment so resources with 643 * bigger alignment will be assigned first. After we 644 * change the alignment of a dev_res in "head" list, we 645 * need to reorder the list by alignment to make it 646 * consistent. 647 */ 648 if (add_align > res->start) { 649 resource_set_range(res, add_align, resource_size(res)); 650 651 list_for_each_entry(dev_res2, head, list) { 652 align = pci_resource_alignment(dev_res2->dev, 653 dev_res2->res); 654 if (add_align > align) { 655 list_move_tail(&dev_res->list, 656 &dev_res2->list); 657 break; 658 } 659 } 660 } 661 662 } 663 664 assign: 665 assign_requested_resources_sorted(head, &local_fail_head, true); 666 667 /* All non-optional resources assigned? */ 668 if (list_empty(&local_fail_head)) { 669 /* Remove head list from realloc_head list */ 670 list_for_each_entry(dev_res, head, list) 671 remove_from_list(realloc_head, dev_res->res); 672 free_list(&save_head); 673 goto out; 674 } 675 676 /* Without realloc_head and only optional fails, nothing more to do. */ 677 if (!pci_required_resource_failed(&local_fail_head, 0) && 678 list_empty(realloc_head)) { 679 list_for_each_entry(save_res, &save_head, list) { 680 struct resource *res = save_res->res; 681 682 if (res->parent) 683 continue; 684 685 restore_dev_resource(save_res); 686 } 687 free_list(&local_fail_head); 688 free_list(&save_head); 689 goto out; 690 } 691 692 /* Check failed type */ 693 fail_type = pci_fail_res_type_mask(&local_fail_head); 694 /* Remove not need to be released assigned res from head list etc */ 695 list_for_each_entry_safe(dev_res, tmp_res, head, list) { 696 res = dev_res->res; 697 698 if (res->parent && !pci_need_to_release(fail_type, res)) { 699 /* Remove it from realloc_head list */ 700 remove_from_list(realloc_head, res); 701 remove_from_list(&save_head, res); 702 list_del(&dev_res->list); 703 kfree(dev_res); 704 } 705 } 706 707 free_list(&local_fail_head); 708 /* Release assigned resource */ 709 list_for_each_entry(dev_res, head, list) { 710 res = dev_res->res; 711 dev = dev_res->dev; 712 713 pci_release_resource(dev, pci_resource_num(dev, res)); 714 restore_dev_resource(dev_res); 715 } 716 /* Restore start/end/flags from saved list */ 717 list_for_each_entry(save_res, &save_head, list) 718 restore_dev_resource(save_res); 719 free_list(&save_head); 720 721 /* Satisfy the must-have resource requests */ 722 assign_requested_resources_sorted(head, NULL, false); 723 724 /* Try to satisfy any additional optional resource requests */ 725 if (!list_empty(realloc_head)) 726 reassign_resources_sorted(realloc_head, head); 727 728 out: 729 /* Reset any failed resource, cannot use fail_head as it can be NULL. */ 730 list_for_each_entry(dev_res, head, list) { 731 res = dev_res->res; 732 dev = dev_res->dev; 733 734 if (res->parent) 735 continue; 736 737 if (fail_head) { 738 add_to_list(fail_head, dev, res, 739 0 /* don't care */, 740 0 /* don't care */); 741 } 742 743 reset_resource(dev, res); 744 } 745 746 free_list(head); 747 } 748 749 static void pdev_assign_resources_sorted(struct pci_dev *dev, 750 struct list_head *add_head, 751 struct list_head *fail_head) 752 { 753 LIST_HEAD(head); 754 755 pdev_sort_resources(dev, &head); 756 __assign_resources_sorted(&head, add_head, fail_head); 757 758 } 759 760 static void pbus_assign_resources_sorted(const struct pci_bus *bus, 761 struct list_head *realloc_head, 762 struct list_head *fail_head) 763 { 764 struct pci_dev *dev; 765 LIST_HEAD(head); 766 767 list_for_each_entry(dev, &bus->devices, bus_list) 768 pdev_sort_resources(dev, &head); 769 770 __assign_resources_sorted(&head, realloc_head, fail_head); 771 } 772 773 void pci_setup_cardbus(struct pci_bus *bus) 774 { 775 struct pci_dev *bridge = bus->self; 776 struct resource *res; 777 struct pci_bus_region region; 778 779 pci_info(bridge, "CardBus bridge to %pR\n", 780 &bus->busn_res); 781 782 res = bus->resource[0]; 783 pcibios_resource_to_bus(bridge->bus, ®ion, res); 784 if (res->parent && res->flags & IORESOURCE_IO) { 785 /* 786 * The IO resource is allocated a range twice as large as it 787 * would normally need. This allows us to set both IO regs. 788 */ 789 pci_info(bridge, " bridge window %pR\n", res); 790 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 791 region.start); 792 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 793 region.end); 794 } 795 796 res = bus->resource[1]; 797 pcibios_resource_to_bus(bridge->bus, ®ion, res); 798 if (res->parent && res->flags & IORESOURCE_IO) { 799 pci_info(bridge, " bridge window %pR\n", res); 800 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 801 region.start); 802 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 803 region.end); 804 } 805 806 res = bus->resource[2]; 807 pcibios_resource_to_bus(bridge->bus, ®ion, res); 808 if (res->parent && res->flags & IORESOURCE_MEM) { 809 pci_info(bridge, " bridge window %pR\n", res); 810 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 811 region.start); 812 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 813 region.end); 814 } 815 816 res = bus->resource[3]; 817 pcibios_resource_to_bus(bridge->bus, ®ion, res); 818 if (res->parent && res->flags & IORESOURCE_MEM) { 819 pci_info(bridge, " bridge window %pR\n", res); 820 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 821 region.start); 822 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 823 region.end); 824 } 825 } 826 EXPORT_SYMBOL(pci_setup_cardbus); 827 828 /* 829 * Initialize bridges with base/limit values we have collected. PCI-to-PCI 830 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there 831 * are no I/O ports or memory behind the bridge, the corresponding range 832 * must be turned off by writing base value greater than limit to the 833 * bridge's base/limit registers. 834 * 835 * Note: care must be taken when updating I/O base/limit registers of 836 * bridges which support 32-bit I/O. This update requires two config space 837 * writes, so it's quite possible that an I/O window of the bridge will 838 * have some undesirable address (e.g. 0) after the first write. Ditto 839 * 64-bit prefetchable MMIO. 840 */ 841 static void pci_setup_bridge_io(struct pci_dev *bridge) 842 { 843 struct resource *res; 844 const char *res_name; 845 struct pci_bus_region region; 846 unsigned long io_mask; 847 u8 io_base_lo, io_limit_lo; 848 u16 l; 849 u32 io_upper16; 850 851 io_mask = PCI_IO_RANGE_MASK; 852 if (bridge->io_window_1k) 853 io_mask = PCI_IO_1K_RANGE_MASK; 854 855 /* Set up the top and bottom of the PCI I/O segment for this bus */ 856 res = &bridge->resource[PCI_BRIDGE_IO_WINDOW]; 857 res_name = pci_resource_name(bridge, PCI_BRIDGE_IO_WINDOW); 858 pcibios_resource_to_bus(bridge->bus, ®ion, res); 859 if (res->parent && res->flags & IORESOURCE_IO) { 860 pci_read_config_word(bridge, PCI_IO_BASE, &l); 861 io_base_lo = (region.start >> 8) & io_mask; 862 io_limit_lo = (region.end >> 8) & io_mask; 863 l = ((u16) io_limit_lo << 8) | io_base_lo; 864 /* Set up upper 16 bits of I/O base/limit */ 865 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 866 pci_info(bridge, " %s %pR\n", res_name, res); 867 } else { 868 /* Clear upper 16 bits of I/O base/limit */ 869 io_upper16 = 0; 870 l = 0x00f0; 871 } 872 /* Temporarily disable the I/O range before updating PCI_IO_BASE */ 873 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 874 /* Update lower 16 bits of I/O base/limit */ 875 pci_write_config_word(bridge, PCI_IO_BASE, l); 876 /* Update upper 16 bits of I/O base/limit */ 877 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 878 } 879 880 static void pci_setup_bridge_mmio(struct pci_dev *bridge) 881 { 882 struct resource *res; 883 const char *res_name; 884 struct pci_bus_region region; 885 u32 l; 886 887 /* Set up the top and bottom of the PCI Memory segment for this bus */ 888 res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 889 res_name = pci_resource_name(bridge, PCI_BRIDGE_MEM_WINDOW); 890 pcibios_resource_to_bus(bridge->bus, ®ion, res); 891 if (res->parent && res->flags & IORESOURCE_MEM) { 892 l = (region.start >> 16) & 0xfff0; 893 l |= region.end & 0xfff00000; 894 pci_info(bridge, " %s %pR\n", res_name, res); 895 } else { 896 l = 0x0000fff0; 897 } 898 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 899 } 900 901 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) 902 { 903 struct resource *res; 904 const char *res_name; 905 struct pci_bus_region region; 906 u32 l, bu, lu; 907 908 /* 909 * Clear out the upper 32 bits of PREF limit. If 910 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables 911 * PREF range, which is ok. 912 */ 913 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 914 915 /* Set up PREF base/limit */ 916 bu = lu = 0; 917 res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 918 res_name = pci_resource_name(bridge, PCI_BRIDGE_PREF_MEM_WINDOW); 919 pcibios_resource_to_bus(bridge->bus, ®ion, res); 920 if (res->parent && res->flags & IORESOURCE_PREFETCH) { 921 l = (region.start >> 16) & 0xfff0; 922 l |= region.end & 0xfff00000; 923 if (res->flags & IORESOURCE_MEM_64) { 924 bu = upper_32_bits(region.start); 925 lu = upper_32_bits(region.end); 926 } 927 pci_info(bridge, " %s %pR\n", res_name, res); 928 } else { 929 l = 0x0000fff0; 930 } 931 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 932 933 /* Set the upper 32 bits of PREF base & limit */ 934 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); 935 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); 936 } 937 938 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) 939 { 940 struct pci_dev *bridge = bus->self; 941 942 pci_info(bridge, "PCI bridge to %pR\n", &bus->busn_res); 943 944 if (type & IORESOURCE_IO) 945 pci_setup_bridge_io(bridge); 946 947 if (type & IORESOURCE_MEM) 948 pci_setup_bridge_mmio(bridge); 949 950 if (type & IORESOURCE_PREFETCH) 951 pci_setup_bridge_mmio_pref(bridge); 952 953 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 954 } 955 956 static void pci_setup_one_bridge_window(struct pci_dev *bridge, int resno) 957 { 958 switch (resno) { 959 case PCI_BRIDGE_IO_WINDOW: 960 pci_setup_bridge_io(bridge); 961 break; 962 case PCI_BRIDGE_MEM_WINDOW: 963 pci_setup_bridge_mmio(bridge); 964 break; 965 case PCI_BRIDGE_PREF_MEM_WINDOW: 966 pci_setup_bridge_mmio_pref(bridge); 967 break; 968 default: 969 return; 970 } 971 } 972 973 void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) 974 { 975 } 976 977 static void pci_setup_bridge(struct pci_bus *bus) 978 { 979 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | 980 IORESOURCE_PREFETCH; 981 982 pcibios_setup_bridge(bus, type); 983 __pci_setup_bridge(bus, type); 984 } 985 986 987 int pci_claim_bridge_resource(struct pci_dev *bridge, int i) 988 { 989 int ret = -EINVAL; 990 991 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) 992 return 0; 993 994 if (pci_claim_resource(bridge, i) == 0) 995 return 0; /* Claimed the window */ 996 997 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) 998 return 0; 999 1000 if (i > PCI_BRIDGE_PREF_MEM_WINDOW) 1001 return -EINVAL; 1002 1003 /* Try to clip the resource and claim the smaller window */ 1004 if (pci_bus_clip_resource(bridge, i)) 1005 ret = pci_claim_resource(bridge, i); 1006 1007 pci_setup_one_bridge_window(bridge, i); 1008 1009 return ret; 1010 } 1011 1012 /* 1013 * Check whether the bridge supports optional I/O and prefetchable memory 1014 * ranges. If not, the respective base/limit registers must be read-only 1015 * and read as 0. 1016 */ 1017 static void pci_bridge_check_ranges(struct pci_bus *bus) 1018 { 1019 struct pci_dev *bridge = bus->self; 1020 struct resource *b_res; 1021 1022 b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 1023 b_res->flags |= IORESOURCE_MEM; 1024 1025 if (bridge->io_window) { 1026 b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW]; 1027 b_res->flags |= IORESOURCE_IO; 1028 } 1029 1030 if (bridge->pref_window) { 1031 b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1032 b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 1033 if (bridge->pref_64_window) { 1034 b_res->flags |= IORESOURCE_MEM_64 | 1035 PCI_PREF_RANGE_TYPE_64; 1036 } 1037 } 1038 } 1039 1040 static resource_size_t calculate_iosize(resource_size_t size, 1041 resource_size_t min_size, 1042 resource_size_t size1, 1043 resource_size_t add_size, 1044 resource_size_t children_add_size, 1045 resource_size_t old_size, 1046 resource_size_t align) 1047 { 1048 if (size < min_size) 1049 size = min_size; 1050 if (old_size == 1) 1051 old_size = 0; 1052 /* 1053 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the 1054 * struct pci_bus. 1055 */ 1056 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 1057 size = (size & 0xff) + ((size & ~0xffUL) << 2); 1058 #endif 1059 size = size + size1; 1060 1061 size = max(size, add_size) + children_add_size; 1062 return ALIGN(max(size, old_size), align); 1063 } 1064 1065 static resource_size_t calculate_memsize(resource_size_t size, 1066 resource_size_t min_size, 1067 resource_size_t add_size, 1068 resource_size_t children_add_size, 1069 resource_size_t old_size, 1070 resource_size_t align) 1071 { 1072 if (size < min_size) 1073 size = min_size; 1074 if (old_size == 1) 1075 old_size = 0; 1076 1077 size = max(size, add_size) + children_add_size; 1078 return ALIGN(max(size, old_size), align); 1079 } 1080 1081 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, 1082 unsigned long type) 1083 { 1084 return 1; 1085 } 1086 1087 #define PCI_P2P_DEFAULT_MEM_ALIGN SZ_1M 1088 #define PCI_P2P_DEFAULT_IO_ALIGN SZ_4K 1089 #define PCI_P2P_DEFAULT_IO_ALIGN_1K SZ_1K 1090 1091 static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type) 1092 { 1093 resource_size_t align = 1, arch_align; 1094 1095 if (type & IORESOURCE_MEM) 1096 align = PCI_P2P_DEFAULT_MEM_ALIGN; 1097 else if (type & IORESOURCE_IO) { 1098 /* 1099 * Per spec, I/O windows are 4K-aligned, but some bridges have 1100 * an extension to support 1K alignment. 1101 */ 1102 if (bus->self && bus->self->io_window_1k) 1103 align = PCI_P2P_DEFAULT_IO_ALIGN_1K; 1104 else 1105 align = PCI_P2P_DEFAULT_IO_ALIGN; 1106 } 1107 1108 arch_align = pcibios_window_alignment(bus, type); 1109 return max(align, arch_align); 1110 } 1111 1112 /** 1113 * pbus_size_io() - Size the I/O window of a given bus 1114 * 1115 * @bus: The bus 1116 * @min_size: The minimum I/O window that must be allocated 1117 * @add_size: Additional optional I/O window 1118 * @realloc_head: Track the additional I/O window on this list 1119 * 1120 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these 1121 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI 1122 * devices are limited to 256 bytes. We must be careful with the ISA 1123 * aliasing though. 1124 */ 1125 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, 1126 resource_size_t add_size, 1127 struct list_head *realloc_head) 1128 { 1129 struct pci_dev *dev; 1130 struct resource *b_res = pbus_select_window_for_type(bus, IORESOURCE_IO); 1131 resource_size_t size = 0, size0 = 0, size1 = 0; 1132 resource_size_t children_add_size = 0; 1133 resource_size_t min_align, align; 1134 1135 if (!b_res) 1136 return; 1137 1138 /* If resource is already assigned, nothing more to do */ 1139 if (b_res->parent) 1140 return; 1141 1142 min_align = window_alignment(bus, IORESOURCE_IO); 1143 list_for_each_entry(dev, &bus->devices, bus_list) { 1144 struct resource *r; 1145 1146 pci_dev_for_each_resource(dev, r) { 1147 unsigned long r_size; 1148 1149 if (r->parent || !(r->flags & IORESOURCE_IO)) 1150 continue; 1151 1152 if (!pdev_resource_assignable(dev, r)) 1153 continue; 1154 1155 r_size = resource_size(r); 1156 if (r_size < SZ_1K) 1157 /* Might be re-aligned for ISA */ 1158 size += r_size; 1159 else 1160 size1 += r_size; 1161 1162 align = pci_resource_alignment(dev, r); 1163 if (align > min_align) 1164 min_align = align; 1165 1166 if (realloc_head) 1167 children_add_size += get_res_add_size(realloc_head, r); 1168 } 1169 } 1170 1171 size0 = calculate_iosize(size, min_size, size1, 0, 0, 1172 resource_size(b_res), min_align); 1173 1174 if (size0) 1175 b_res->flags &= ~IORESOURCE_DISABLED; 1176 1177 size1 = size0; 1178 if (realloc_head && (add_size > 0 || children_add_size > 0)) { 1179 size1 = calculate_iosize(size, min_size, size1, add_size, 1180 children_add_size, resource_size(b_res), 1181 min_align); 1182 } 1183 1184 if (!size0 && !size1) { 1185 if (bus->self && (b_res->start || b_res->end)) 1186 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", 1187 b_res, &bus->busn_res); 1188 b_res->flags |= IORESOURCE_DISABLED; 1189 return; 1190 } 1191 1192 resource_set_range(b_res, min_align, size0); 1193 b_res->flags |= IORESOURCE_STARTALIGN; 1194 if (bus->self && size1 > size0 && realloc_head) { 1195 b_res->flags &= ~IORESOURCE_DISABLED; 1196 add_to_list(realloc_head, bus->self, b_res, size1-size0, 1197 min_align); 1198 pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n", 1199 b_res, &bus->busn_res, 1200 (unsigned long long) size1 - size0); 1201 } 1202 } 1203 1204 static inline resource_size_t calculate_mem_align(resource_size_t *aligns, 1205 int max_order) 1206 { 1207 resource_size_t align = 0; 1208 resource_size_t min_align = 0; 1209 int order; 1210 1211 for (order = 0; order <= max_order; order++) { 1212 resource_size_t align1 = 1; 1213 1214 align1 <<= order + __ffs(SZ_1M); 1215 1216 if (!align) 1217 min_align = align1; 1218 else if (ALIGN(align + min_align, min_align) < align1) 1219 min_align = align1 >> 1; 1220 align += aligns[order]; 1221 } 1222 1223 return min_align; 1224 } 1225 1226 /** 1227 * pbus_upstream_space_available - Check no upstream resource limits allocation 1228 * @bus: The bus 1229 * @res: The resource to help select the correct bridge window 1230 * @size: The size required from the bridge window 1231 * @align: Required alignment for the resource 1232 * 1233 * Check that @size can fit inside the upstream bridge resources that are 1234 * already assigned. Select the upstream bridge window based on the type of 1235 * @res. 1236 * 1237 * Return: %true if enough space is available on all assigned upstream 1238 * resources. 1239 */ 1240 static bool pbus_upstream_space_available(struct pci_bus *bus, 1241 struct resource *res, 1242 resource_size_t size, 1243 resource_size_t align) 1244 { 1245 struct resource_constraint constraint = { 1246 .max = RESOURCE_SIZE_MAX, 1247 .align = align, 1248 }; 1249 struct pci_bus *downstream = bus; 1250 1251 while ((bus = bus->parent)) { 1252 if (pci_is_root_bus(bus)) 1253 break; 1254 1255 res = pbus_select_window(bus, res); 1256 if (!res) 1257 return false; 1258 if (!res->parent) 1259 continue; 1260 1261 if (resource_size(res) >= size) { 1262 struct resource gap = {}; 1263 1264 if (find_resource_space(res, &gap, size, &constraint) == 0) { 1265 gap.flags = res->flags; 1266 pci_dbg(bus->self, 1267 "Assigned bridge window %pR to %pR free space at %pR\n", 1268 res, &bus->busn_res, &gap); 1269 return true; 1270 } 1271 } 1272 1273 if (bus->self) { 1274 pci_info(bus->self, 1275 "Assigned bridge window %pR to %pR cannot fit 0x%llx required for %s bridging to %pR\n", 1276 res, &bus->busn_res, 1277 (unsigned long long)size, 1278 pci_name(downstream->self), 1279 &downstream->busn_res); 1280 } 1281 1282 return false; 1283 } 1284 1285 return true; 1286 } 1287 1288 /** 1289 * pbus_size_mem() - Size the memory window of a given bus 1290 * 1291 * @bus: The bus 1292 * @type: The type of bridge resource 1293 * @min_size: The minimum memory window that must be allocated 1294 * @add_size: Additional optional memory window 1295 * @realloc_head: Track the additional memory window on this list 1296 * 1297 * Calculate the size of the bus resource for @type and minimal alignment 1298 * which guarantees that all child resources fit in this size. 1299 * 1300 * Set the bus resource start/end to indicate the required size if there an 1301 * available unassigned bus resource of the desired @type. 1302 * 1303 * Add optional resource requests to the @realloc_head list if it is 1304 * supplied. 1305 */ 1306 static void pbus_size_mem(struct pci_bus *bus, unsigned long type, 1307 resource_size_t min_size, 1308 resource_size_t add_size, 1309 struct list_head *realloc_head) 1310 { 1311 struct pci_dev *dev; 1312 resource_size_t min_align, win_align, align, size, size0, size1 = 0; 1313 resource_size_t aligns[28]; /* Alignments from 1MB to 128TB */ 1314 int order, max_order; 1315 struct resource *b_res = pbus_select_window_for_type(bus, type); 1316 resource_size_t children_add_size = 0; 1317 resource_size_t children_add_align = 0; 1318 resource_size_t add_align = 0; 1319 resource_size_t relaxed_align; 1320 resource_size_t old_size; 1321 1322 if (!b_res) 1323 return; 1324 1325 /* If resource is already assigned, nothing more to do */ 1326 if (b_res->parent) 1327 return; 1328 1329 memset(aligns, 0, sizeof(aligns)); 1330 max_order = 0; 1331 size = 0; 1332 1333 list_for_each_entry(dev, &bus->devices, bus_list) { 1334 struct resource *r; 1335 int i; 1336 1337 pci_dev_for_each_resource(dev, r, i) { 1338 const char *r_name = pci_resource_name(dev, i); 1339 resource_size_t r_size; 1340 1341 if (!pdev_resources_assignable(dev) || 1342 !pdev_resource_should_fit(dev, r)) 1343 continue; 1344 if (b_res != pbus_select_window(bus, r)) 1345 continue; 1346 1347 r_size = resource_size(r); 1348 1349 /* Put SRIOV requested res to the optional list */ 1350 if (realloc_head && pci_resource_is_optional(dev, i)) { 1351 add_align = max(pci_resource_alignment(dev, r), add_align); 1352 add_to_list(realloc_head, dev, r, 0, 0 /* Don't care */); 1353 children_add_size += r_size; 1354 continue; 1355 } 1356 1357 /* 1358 * aligns[0] is for 1MB (since bridge memory 1359 * windows are always at least 1MB aligned), so 1360 * keep "order" from being negative for smaller 1361 * resources. 1362 */ 1363 align = pci_resource_alignment(dev, r); 1364 order = __ffs(align) - __ffs(SZ_1M); 1365 if (order < 0) 1366 order = 0; 1367 if (order >= ARRAY_SIZE(aligns)) { 1368 pci_warn(dev, "%s %pR: disabling; bad alignment %#llx\n", 1369 r_name, r, (unsigned long long) align); 1370 r->flags = 0; 1371 continue; 1372 } 1373 size += max(r_size, align); 1374 /* 1375 * Exclude ranges with size > align from calculation of 1376 * the alignment. 1377 */ 1378 if (r_size <= align) 1379 aligns[order] += align; 1380 if (order > max_order) 1381 max_order = order; 1382 1383 if (realloc_head) { 1384 children_add_size += get_res_add_size(realloc_head, r); 1385 children_add_align = get_res_add_align(realloc_head, r); 1386 add_align = max(add_align, children_add_align); 1387 } 1388 } 1389 } 1390 1391 old_size = resource_size(b_res); 1392 win_align = window_alignment(bus, b_res->flags); 1393 min_align = calculate_mem_align(aligns, max_order); 1394 min_align = max(min_align, win_align); 1395 size0 = calculate_memsize(size, min_size, 0, 0, old_size, min_align); 1396 1397 if (size0) { 1398 resource_set_range(b_res, min_align, size0); 1399 b_res->flags &= ~IORESOURCE_DISABLED; 1400 } 1401 1402 if (bus->self && size0 && 1403 !pbus_upstream_space_available(bus, b_res, size0, min_align)) { 1404 relaxed_align = 1ULL << (max_order + __ffs(SZ_1M)); 1405 relaxed_align = max(relaxed_align, win_align); 1406 min_align = min(min_align, relaxed_align); 1407 size0 = calculate_memsize(size, min_size, 0, 0, old_size, win_align); 1408 resource_set_range(b_res, min_align, size0); 1409 pci_info(bus->self, "bridge window %pR to %pR requires relaxed alignment rules\n", 1410 b_res, &bus->busn_res); 1411 } 1412 1413 if (realloc_head && (add_size > 0 || children_add_size > 0)) { 1414 add_align = max(min_align, add_align); 1415 size1 = calculate_memsize(size, min_size, add_size, children_add_size, 1416 old_size, add_align); 1417 1418 if (bus->self && size1 && 1419 !pbus_upstream_space_available(bus, b_res, size1, add_align)) { 1420 relaxed_align = 1ULL << (max_order + __ffs(SZ_1M)); 1421 relaxed_align = max(relaxed_align, win_align); 1422 min_align = min(min_align, relaxed_align); 1423 size1 = calculate_memsize(size, min_size, add_size, children_add_size, 1424 old_size, win_align); 1425 pci_info(bus->self, 1426 "bridge window %pR to %pR requires relaxed alignment rules\n", 1427 b_res, &bus->busn_res); 1428 } 1429 } 1430 1431 if (!size0 && !size1) { 1432 if (bus->self && (b_res->start || b_res->end)) 1433 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", 1434 b_res, &bus->busn_res); 1435 b_res->flags |= IORESOURCE_DISABLED; 1436 return; 1437 } 1438 1439 resource_set_range(b_res, min_align, size0); 1440 b_res->flags |= IORESOURCE_STARTALIGN; 1441 if (bus->self && size1 > size0 && realloc_head) { 1442 b_res->flags &= ~IORESOURCE_DISABLED; 1443 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); 1444 pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n", 1445 b_res, &bus->busn_res, 1446 (unsigned long long) (size1 - size0), 1447 (unsigned long long) add_align); 1448 } 1449 } 1450 1451 unsigned long pci_cardbus_resource_alignment(struct resource *res) 1452 { 1453 if (res->flags & IORESOURCE_IO) 1454 return pci_cardbus_io_size; 1455 if (res->flags & IORESOURCE_MEM) 1456 return pci_cardbus_mem_size; 1457 return 0; 1458 } 1459 1460 static void pci_bus_size_cardbus(struct pci_bus *bus, 1461 struct list_head *realloc_head) 1462 { 1463 struct pci_dev *bridge = bus->self; 1464 struct resource *b_res; 1465 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; 1466 u16 ctrl; 1467 1468 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; 1469 if (b_res->parent) 1470 goto handle_b_res_1; 1471 /* 1472 * Reserve some resources for CardBus. We reserve a fixed amount 1473 * of bus space for CardBus bridges. 1474 */ 1475 resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 1476 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1477 if (realloc_head) { 1478 b_res->end -= pci_cardbus_io_size; 1479 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 1480 pci_cardbus_io_size); 1481 } 1482 1483 handle_b_res_1: 1484 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; 1485 if (b_res->parent) 1486 goto handle_b_res_2; 1487 resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 1488 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1489 if (realloc_head) { 1490 b_res->end -= pci_cardbus_io_size; 1491 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 1492 pci_cardbus_io_size); 1493 } 1494 1495 handle_b_res_2: 1496 /* MEM1 must not be pref MMIO */ 1497 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1498 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 1499 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 1500 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1501 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1502 } 1503 1504 /* Check whether prefetchable memory is supported by this bridge. */ 1505 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1506 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 1507 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 1508 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1509 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1510 } 1511 1512 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; 1513 if (b_res->parent) 1514 goto handle_b_res_3; 1515 /* 1516 * If we have prefetchable memory support, allocate two regions. 1517 * Otherwise, allocate one region of twice the size. 1518 */ 1519 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 1520 resource_set_range(b_res, pci_cardbus_mem_size, 1521 pci_cardbus_mem_size); 1522 b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | 1523 IORESOURCE_STARTALIGN; 1524 if (realloc_head) { 1525 b_res->end -= pci_cardbus_mem_size; 1526 add_to_list(realloc_head, bridge, b_res, 1527 pci_cardbus_mem_size, pci_cardbus_mem_size); 1528 } 1529 1530 /* Reduce that to half */ 1531 b_res_3_size = pci_cardbus_mem_size; 1532 } 1533 1534 handle_b_res_3: 1535 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; 1536 if (b_res->parent) 1537 goto handle_done; 1538 resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); 1539 b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; 1540 if (realloc_head) { 1541 b_res->end -= b_res_3_size; 1542 add_to_list(realloc_head, bridge, b_res, b_res_3_size, 1543 pci_cardbus_mem_size); 1544 } 1545 1546 handle_done: 1547 ; 1548 } 1549 1550 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) 1551 { 1552 struct pci_dev *dev; 1553 resource_size_t additional_io_size = 0, additional_mmio_size = 0, 1554 additional_mmio_pref_size = 0; 1555 struct resource *pref; 1556 struct pci_host_bridge *host; 1557 int hdr_type; 1558 1559 list_for_each_entry(dev, &bus->devices, bus_list) { 1560 struct pci_bus *b = dev->subordinate; 1561 if (!b) 1562 continue; 1563 1564 switch (dev->hdr_type) { 1565 case PCI_HEADER_TYPE_CARDBUS: 1566 pci_bus_size_cardbus(b, realloc_head); 1567 break; 1568 1569 case PCI_HEADER_TYPE_BRIDGE: 1570 default: 1571 __pci_bus_size_bridges(b, realloc_head); 1572 break; 1573 } 1574 } 1575 1576 /* The root bus? */ 1577 if (pci_is_root_bus(bus)) { 1578 host = to_pci_host_bridge(bus->bridge); 1579 if (!host->size_windows) 1580 return; 1581 pci_bus_for_each_resource(bus, pref) 1582 if (pref && (pref->flags & IORESOURCE_PREFETCH)) 1583 break; 1584 hdr_type = -1; /* Intentionally invalid - not a PCI device. */ 1585 } else { 1586 pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1587 hdr_type = bus->self->hdr_type; 1588 } 1589 1590 switch (hdr_type) { 1591 case PCI_HEADER_TYPE_CARDBUS: 1592 /* Don't size CardBuses yet */ 1593 break; 1594 1595 case PCI_HEADER_TYPE_BRIDGE: 1596 pci_bridge_check_ranges(bus); 1597 if (bus->self->is_hotplug_bridge) { 1598 additional_io_size = pci_hotplug_io_size; 1599 additional_mmio_size = pci_hotplug_mmio_size; 1600 additional_mmio_pref_size = pci_hotplug_mmio_pref_size; 1601 } 1602 fallthrough; 1603 default: 1604 pbus_size_io(bus, realloc_head ? 0 : additional_io_size, 1605 additional_io_size, realloc_head); 1606 1607 if (pref) { 1608 pbus_size_mem(bus, 1609 IORESOURCE_MEM | IORESOURCE_PREFETCH | 1610 (pref->flags & IORESOURCE_MEM_64), 1611 realloc_head ? 0 : additional_mmio_pref_size, 1612 additional_mmio_pref_size, realloc_head); 1613 } 1614 1615 pbus_size_mem(bus, IORESOURCE_MEM, 1616 realloc_head ? 0 : additional_mmio_size, 1617 additional_mmio_size, realloc_head); 1618 break; 1619 } 1620 } 1621 1622 void pci_bus_size_bridges(struct pci_bus *bus) 1623 { 1624 __pci_bus_size_bridges(bus, NULL); 1625 } 1626 EXPORT_SYMBOL(pci_bus_size_bridges); 1627 1628 static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r) 1629 { 1630 struct resource *parent_r; 1631 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM | 1632 IORESOURCE_PREFETCH; 1633 1634 pci_bus_for_each_resource(b, parent_r) { 1635 if (!parent_r) 1636 continue; 1637 1638 if ((r->flags & mask) == (parent_r->flags & mask) && 1639 resource_contains(parent_r, r)) 1640 request_resource(parent_r, r); 1641 } 1642 } 1643 1644 /* 1645 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are 1646 * skipped by pbus_assign_resources_sorted(). 1647 */ 1648 static void pdev_assign_fixed_resources(struct pci_dev *dev) 1649 { 1650 struct resource *r; 1651 1652 pci_dev_for_each_resource(dev, r) { 1653 struct pci_bus *b; 1654 1655 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) || 1656 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 1657 continue; 1658 1659 b = dev->bus; 1660 while (b && !r->parent) { 1661 assign_fixed_resource_on_bus(b, r); 1662 b = b->parent; 1663 } 1664 } 1665 } 1666 1667 void __pci_bus_assign_resources(const struct pci_bus *bus, 1668 struct list_head *realloc_head, 1669 struct list_head *fail_head) 1670 { 1671 struct pci_bus *b; 1672 struct pci_dev *dev; 1673 1674 pbus_assign_resources_sorted(bus, realloc_head, fail_head); 1675 1676 list_for_each_entry(dev, &bus->devices, bus_list) { 1677 pdev_assign_fixed_resources(dev); 1678 1679 b = dev->subordinate; 1680 if (!b) 1681 continue; 1682 1683 __pci_bus_assign_resources(b, realloc_head, fail_head); 1684 1685 switch (dev->hdr_type) { 1686 case PCI_HEADER_TYPE_BRIDGE: 1687 if (!pci_is_enabled(dev)) 1688 pci_setup_bridge(b); 1689 break; 1690 1691 case PCI_HEADER_TYPE_CARDBUS: 1692 pci_setup_cardbus(b); 1693 break; 1694 1695 default: 1696 pci_info(dev, "not setting up bridge for bus %04x:%02x\n", 1697 pci_domain_nr(b), b->number); 1698 break; 1699 } 1700 } 1701 } 1702 1703 void pci_bus_assign_resources(const struct pci_bus *bus) 1704 { 1705 __pci_bus_assign_resources(bus, NULL, NULL); 1706 } 1707 EXPORT_SYMBOL(pci_bus_assign_resources); 1708 1709 static void pci_claim_device_resources(struct pci_dev *dev) 1710 { 1711 int i; 1712 1713 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 1714 struct resource *r = &dev->resource[i]; 1715 1716 if (!r->flags || r->parent) 1717 continue; 1718 1719 pci_claim_resource(dev, i); 1720 } 1721 } 1722 1723 static void pci_claim_bridge_resources(struct pci_dev *dev) 1724 { 1725 int i; 1726 1727 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 1728 struct resource *r = &dev->resource[i]; 1729 1730 if (!r->flags || r->parent) 1731 continue; 1732 1733 pci_claim_bridge_resource(dev, i); 1734 } 1735 } 1736 1737 static void pci_bus_allocate_dev_resources(struct pci_bus *b) 1738 { 1739 struct pci_dev *dev; 1740 struct pci_bus *child; 1741 1742 list_for_each_entry(dev, &b->devices, bus_list) { 1743 pci_claim_device_resources(dev); 1744 1745 child = dev->subordinate; 1746 if (child) 1747 pci_bus_allocate_dev_resources(child); 1748 } 1749 } 1750 1751 static void pci_bus_allocate_resources(struct pci_bus *b) 1752 { 1753 struct pci_bus *child; 1754 1755 /* 1756 * Carry out a depth-first search on the PCI bus tree to allocate 1757 * bridge apertures. Read the programmed bridge bases and 1758 * recursively claim the respective bridge resources. 1759 */ 1760 if (b->self) { 1761 pci_read_bridge_bases(b); 1762 pci_claim_bridge_resources(b->self); 1763 } 1764 1765 list_for_each_entry(child, &b->children, node) 1766 pci_bus_allocate_resources(child); 1767 } 1768 1769 void pci_bus_claim_resources(struct pci_bus *b) 1770 { 1771 pci_bus_allocate_resources(b); 1772 pci_bus_allocate_dev_resources(b); 1773 } 1774 EXPORT_SYMBOL(pci_bus_claim_resources); 1775 1776 static void __pci_bridge_assign_resources(const struct pci_dev *bridge, 1777 struct list_head *add_head, 1778 struct list_head *fail_head) 1779 { 1780 struct pci_bus *b; 1781 1782 pdev_assign_resources_sorted((struct pci_dev *)bridge, 1783 add_head, fail_head); 1784 1785 b = bridge->subordinate; 1786 if (!b) 1787 return; 1788 1789 __pci_bus_assign_resources(b, add_head, fail_head); 1790 1791 switch (bridge->class >> 8) { 1792 case PCI_CLASS_BRIDGE_PCI: 1793 pci_setup_bridge(b); 1794 break; 1795 1796 case PCI_CLASS_BRIDGE_CARDBUS: 1797 pci_setup_cardbus(b); 1798 break; 1799 1800 default: 1801 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n", 1802 pci_domain_nr(b), b->number); 1803 break; 1804 } 1805 } 1806 1807 static void pci_bridge_release_resources(struct pci_bus *bus, 1808 struct resource *b_win) 1809 { 1810 struct pci_dev *dev = bus->self; 1811 int idx, ret; 1812 1813 if (!b_win->parent) 1814 return; 1815 1816 idx = pci_resource_num(dev, b_win); 1817 1818 /* If there are children, release them all */ 1819 release_child_resources(b_win); 1820 1821 ret = pci_release_resource(dev, idx); 1822 if (ret) 1823 return; 1824 1825 pci_setup_one_bridge_window(dev, idx); 1826 } 1827 1828 enum release_type { 1829 leaf_only, 1830 whole_subtree, 1831 }; 1832 1833 /* 1834 * Try to release PCI bridge resources from leaf bridge, so we can allocate 1835 * a larger window later. 1836 */ 1837 static void pci_bus_release_bridge_resources(struct pci_bus *bus, 1838 struct resource *b_win, 1839 enum release_type rel_type) 1840 { 1841 struct pci_dev *dev; 1842 bool is_leaf_bridge = true; 1843 1844 list_for_each_entry(dev, &bus->devices, bus_list) { 1845 struct pci_bus *b = dev->subordinate; 1846 struct resource *res; 1847 1848 if (!b) 1849 continue; 1850 1851 is_leaf_bridge = false; 1852 1853 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 1854 continue; 1855 1856 if (rel_type != whole_subtree) 1857 continue; 1858 1859 pci_bus_for_each_resource(b, res) { 1860 if (res->parent != b_win) 1861 continue; 1862 1863 pci_bus_release_bridge_resources(b, res, rel_type); 1864 } 1865 } 1866 1867 if (pci_is_root_bus(bus)) 1868 return; 1869 1870 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) 1871 return; 1872 1873 if ((rel_type == whole_subtree) || is_leaf_bridge) 1874 pci_bridge_release_resources(bus, b_win); 1875 } 1876 1877 static void pci_bus_dump_res(struct pci_bus *bus) 1878 { 1879 struct resource *res; 1880 int i; 1881 1882 pci_bus_for_each_resource(bus, res, i) { 1883 if (!res || !res->end || !res->flags) 1884 continue; 1885 1886 dev_info(&bus->dev, "resource %d %pR\n", i, res); 1887 } 1888 } 1889 1890 static void pci_bus_dump_resources(struct pci_bus *bus) 1891 { 1892 struct pci_bus *b; 1893 struct pci_dev *dev; 1894 1895 1896 pci_bus_dump_res(bus); 1897 1898 list_for_each_entry(dev, &bus->devices, bus_list) { 1899 b = dev->subordinate; 1900 if (!b) 1901 continue; 1902 1903 pci_bus_dump_resources(b); 1904 } 1905 } 1906 1907 static int pci_bus_get_depth(struct pci_bus *bus) 1908 { 1909 int depth = 0; 1910 struct pci_bus *child_bus; 1911 1912 list_for_each_entry(child_bus, &bus->children, node) { 1913 int ret; 1914 1915 ret = pci_bus_get_depth(child_bus); 1916 if (ret + 1 > depth) 1917 depth = ret + 1; 1918 } 1919 1920 return depth; 1921 } 1922 1923 /* 1924 * -1: undefined, will auto detect later 1925 * 0: disabled by user 1926 * 1: disabled by auto detect 1927 * 2: enabled by user 1928 * 3: enabled by auto detect 1929 */ 1930 enum enable_type { 1931 undefined = -1, 1932 user_disabled, 1933 auto_disabled, 1934 user_enabled, 1935 auto_enabled, 1936 }; 1937 1938 static enum enable_type pci_realloc_enable = undefined; 1939 void __init pci_realloc_get_opt(char *str) 1940 { 1941 if (!strncmp(str, "off", 3)) 1942 pci_realloc_enable = user_disabled; 1943 else if (!strncmp(str, "on", 2)) 1944 pci_realloc_enable = user_enabled; 1945 } 1946 static bool pci_realloc_enabled(enum enable_type enable) 1947 { 1948 return enable >= user_enabled; 1949 } 1950 1951 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) 1952 static int iov_resources_unassigned(struct pci_dev *dev, void *data) 1953 { 1954 int i; 1955 bool *unassigned = data; 1956 1957 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1958 int idx = pci_resource_num_from_vf_bar(i); 1959 struct resource *r = &dev->resource[idx]; 1960 struct pci_bus_region region; 1961 1962 /* Not assigned or rejected by kernel? */ 1963 if (!r->flags) 1964 continue; 1965 1966 pcibios_resource_to_bus(dev->bus, ®ion, r); 1967 if (!region.start) { 1968 *unassigned = true; 1969 return 1; /* Return early from pci_walk_bus() */ 1970 } 1971 } 1972 1973 return 0; 1974 } 1975 1976 static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1977 enum enable_type enable_local) 1978 { 1979 bool unassigned = false; 1980 struct pci_host_bridge *host; 1981 1982 if (enable_local != undefined) 1983 return enable_local; 1984 1985 host = pci_find_host_bridge(bus); 1986 if (host->preserve_config) 1987 return auto_disabled; 1988 1989 pci_walk_bus(bus, iov_resources_unassigned, &unassigned); 1990 if (unassigned) 1991 return auto_enabled; 1992 1993 return enable_local; 1994 } 1995 #else 1996 static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1997 enum enable_type enable_local) 1998 { 1999 return enable_local; 2000 } 2001 #endif 2002 2003 static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res, 2004 struct list_head *add_list, 2005 resource_size_t new_size) 2006 { 2007 resource_size_t add_size, size = resource_size(res); 2008 2009 if (res->parent) 2010 return; 2011 2012 if (!new_size) 2013 return; 2014 2015 if (new_size > size) { 2016 add_size = new_size - size; 2017 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res, 2018 &add_size); 2019 } else if (new_size < size) { 2020 add_size = size - new_size; 2021 pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res, 2022 &add_size); 2023 } else { 2024 return; 2025 } 2026 2027 resource_set_size(res, new_size); 2028 2029 /* If the resource is part of the add_list, remove it now */ 2030 if (add_list) 2031 remove_from_list(add_list, res); 2032 } 2033 2034 static void remove_dev_resource(struct resource *avail, struct pci_dev *dev, 2035 struct resource *res) 2036 { 2037 resource_size_t size, align, tmp; 2038 2039 size = resource_size(res); 2040 if (!size) 2041 return; 2042 2043 align = pci_resource_alignment(dev, res); 2044 align = align ? ALIGN(avail->start, align) - avail->start : 0; 2045 tmp = align + size; 2046 avail->start = min(avail->start + tmp, avail->end + 1); 2047 } 2048 2049 static void remove_dev_resources(struct pci_dev *dev, 2050 struct resource available[PCI_P2P_BRIDGE_RESOURCE_NUM]) 2051 { 2052 struct resource *res, *b_win; 2053 int idx; 2054 2055 pci_dev_for_each_resource(dev, res) { 2056 b_win = pbus_select_window(dev->bus, res); 2057 if (!b_win) 2058 continue; 2059 2060 idx = pci_resource_num(dev->bus->self, b_win); 2061 idx -= PCI_BRIDGE_RESOURCES; 2062 2063 remove_dev_resource(&available[idx], dev, res); 2064 } 2065 } 2066 2067 #define ALIGN_DOWN_IF_NONZERO(addr, align) \ 2068 ((align) ? ALIGN_DOWN((addr), (align)) : (addr)) 2069 2070 /* 2071 * io, mmio and mmio_pref contain the total amount of bridge window space 2072 * available. This includes the minimal space needed to cover all the 2073 * existing devices on the bus and the possible extra space that can be 2074 * shared with the bridges. 2075 */ 2076 static void pci_bus_distribute_available_resources(struct pci_bus *bus, 2077 struct list_head *add_list, 2078 struct resource available_in[PCI_P2P_BRIDGE_RESOURCE_NUM]) 2079 { 2080 struct resource available[PCI_P2P_BRIDGE_RESOURCE_NUM]; 2081 unsigned int normal_bridges = 0, hotplug_bridges = 0; 2082 struct pci_dev *dev, *bridge = bus->self; 2083 resource_size_t per_bridge[PCI_P2P_BRIDGE_RESOURCE_NUM]; 2084 resource_size_t align; 2085 int i; 2086 2087 for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) { 2088 struct resource *res = 2089 pci_resource_n(bridge, PCI_BRIDGE_RESOURCES + i); 2090 2091 available[i] = available_in[i]; 2092 2093 /* 2094 * The alignment of this bridge is yet to be considered, 2095 * hence it must be done now before extending its bridge 2096 * window. 2097 */ 2098 align = pci_resource_alignment(bridge, res); 2099 if (!res->parent && align) 2100 available[i].start = min(ALIGN(available[i].start, align), 2101 available[i].end + 1); 2102 2103 /* 2104 * Now that we have adjusted for alignment, update the 2105 * bridge window resources to fill as much remaining 2106 * resource space as possible. 2107 */ 2108 adjust_bridge_window(bridge, res, add_list, 2109 resource_size(&available[i])); 2110 } 2111 2112 /* 2113 * Calculate how many hotplug bridges and normal bridges there 2114 * are on this bus. We will distribute the additional available 2115 * resources between hotplug bridges. 2116 */ 2117 for_each_pci_bridge(dev, bus) { 2118 if (dev->is_hotplug_bridge) 2119 hotplug_bridges++; 2120 else 2121 normal_bridges++; 2122 } 2123 2124 if (!(hotplug_bridges + normal_bridges)) 2125 return; 2126 2127 /* 2128 * Calculate the amount of space we can forward from "bus" to any 2129 * downstream buses, i.e., the space left over after assigning the 2130 * BARs and windows on "bus". 2131 */ 2132 list_for_each_entry(dev, &bus->devices, bus_list) { 2133 if (!dev->is_virtfn) 2134 remove_dev_resources(dev, available); 2135 } 2136 2137 /* 2138 * If there is at least one hotplug bridge on this bus it gets all 2139 * the extra resource space that was left after the reductions 2140 * above. 2141 * 2142 * If there are no hotplug bridges the extra resource space is 2143 * split between non-hotplug bridges. This is to allow possible 2144 * hotplug bridges below them to get the extra space as well. 2145 */ 2146 for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) { 2147 per_bridge[i] = div64_ul(resource_size(&available[i]), 2148 hotplug_bridges ?: normal_bridges); 2149 } 2150 2151 for_each_pci_bridge(dev, bus) { 2152 struct resource *res; 2153 struct pci_bus *b; 2154 2155 b = dev->subordinate; 2156 if (!b) 2157 continue; 2158 if (hotplug_bridges && !dev->is_hotplug_bridge) 2159 continue; 2160 2161 for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) { 2162 res = pci_resource_n(dev, PCI_BRIDGE_RESOURCES + i); 2163 2164 /* 2165 * Make sure the split resource space is properly 2166 * aligned for bridge windows (align it down to 2167 * avoid going above what is available). 2168 */ 2169 align = pci_resource_alignment(dev, res); 2170 resource_set_size(&available[i], 2171 ALIGN_DOWN_IF_NONZERO(per_bridge[i], 2172 align)); 2173 2174 /* 2175 * The per_bridge holds the extra resource space 2176 * that can be added for each bridge but there is 2177 * the minimal already reserved as well so adjust 2178 * x.start down accordingly to cover the whole 2179 * space. 2180 */ 2181 available[i].start -= resource_size(res); 2182 } 2183 2184 pci_bus_distribute_available_resources(b, add_list, available); 2185 2186 for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) 2187 available[i].start += available[i].end + 1; 2188 } 2189 } 2190 2191 static void pci_bridge_distribute_available_resources(struct pci_dev *bridge, 2192 struct list_head *add_list) 2193 { 2194 struct resource *res, available[PCI_P2P_BRIDGE_RESOURCE_NUM]; 2195 unsigned int i; 2196 2197 if (!bridge->is_hotplug_bridge) 2198 return; 2199 2200 pci_dbg(bridge, "distributing available resources\n"); 2201 2202 /* Take the initial extra resources from the hotplug port */ 2203 for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) { 2204 res = pci_resource_n(bridge, PCI_BRIDGE_RESOURCES + i); 2205 available[i] = *res; 2206 } 2207 2208 pci_bus_distribute_available_resources(bridge->subordinate, 2209 add_list, available); 2210 } 2211 2212 static bool pci_bridge_resources_not_assigned(struct pci_dev *dev) 2213 { 2214 const struct resource *r; 2215 2216 /* 2217 * If the child device's resources are not yet assigned it means we 2218 * are configuring them (not the boot firmware), so we should be 2219 * able to extend the upstream bridge resources in the same way we 2220 * do with the normal hotplug case. 2221 */ 2222 r = &dev->resource[PCI_BRIDGE_IO_WINDOW]; 2223 if (r->flags && !(r->flags & IORESOURCE_STARTALIGN)) 2224 return false; 2225 r = &dev->resource[PCI_BRIDGE_MEM_WINDOW]; 2226 if (r->flags && !(r->flags & IORESOURCE_STARTALIGN)) 2227 return false; 2228 r = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 2229 if (r->flags && !(r->flags & IORESOURCE_STARTALIGN)) 2230 return false; 2231 2232 return true; 2233 } 2234 2235 static void 2236 pci_root_bus_distribute_available_resources(struct pci_bus *bus, 2237 struct list_head *add_list) 2238 { 2239 struct pci_dev *dev, *bridge = bus->self; 2240 2241 for_each_pci_bridge(dev, bus) { 2242 struct pci_bus *b; 2243 2244 b = dev->subordinate; 2245 if (!b) 2246 continue; 2247 2248 /* 2249 * Need to check "bridge" here too because it is NULL 2250 * in case of root bus. 2251 */ 2252 if (bridge && pci_bridge_resources_not_assigned(dev)) 2253 pci_bridge_distribute_available_resources(dev, add_list); 2254 else 2255 pci_root_bus_distribute_available_resources(b, add_list); 2256 } 2257 } 2258 2259 static void pci_prepare_next_assign_round(struct list_head *fail_head, 2260 int tried_times, 2261 enum release_type rel_type) 2262 { 2263 struct pci_dev_resource *fail_res; 2264 2265 pr_info("PCI: No. %d try to assign unassigned res\n", tried_times + 1); 2266 2267 /* 2268 * Try to release leaf bridge's resources that aren't big 2269 * enough to contain child device resources. 2270 */ 2271 list_for_each_entry(fail_res, fail_head, list) { 2272 struct pci_bus *bus = fail_res->dev->bus; 2273 struct resource *b_win; 2274 2275 b_win = pbus_select_window_for_type(bus, fail_res->flags); 2276 if (!b_win) 2277 continue; 2278 pci_bus_release_bridge_resources(bus, b_win, rel_type); 2279 } 2280 2281 /* Restore size and flags */ 2282 list_for_each_entry(fail_res, fail_head, list) 2283 restore_dev_resource(fail_res); 2284 2285 free_list(fail_head); 2286 } 2287 2288 /* 2289 * First try will not touch PCI bridge res. 2290 * Second and later try will clear small leaf bridge res. 2291 * Will stop till to the max depth if can not find good one. 2292 */ 2293 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) 2294 { 2295 LIST_HEAD(realloc_head); 2296 /* List of resources that want additional resources */ 2297 struct list_head *add_list = NULL; 2298 int tried_times = 0; 2299 enum release_type rel_type = leaf_only; 2300 LIST_HEAD(fail_head); 2301 int pci_try_num = 1; 2302 enum enable_type enable_local; 2303 2304 /* Don't realloc if asked to do so */ 2305 enable_local = pci_realloc_detect(bus, pci_realloc_enable); 2306 if (pci_realloc_enabled(enable_local)) { 2307 int max_depth = pci_bus_get_depth(bus); 2308 2309 pci_try_num = max_depth + 1; 2310 dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n", 2311 max_depth, pci_try_num); 2312 } 2313 2314 while (1) { 2315 /* 2316 * Last try will use add_list, otherwise will try good to 2317 * have as must have, so can realloc parent bridge resource 2318 */ 2319 if (tried_times + 1 == pci_try_num) 2320 add_list = &realloc_head; 2321 /* 2322 * Depth first, calculate sizes and alignments of all 2323 * subordinate buses. 2324 */ 2325 __pci_bus_size_bridges(bus, add_list); 2326 2327 pci_root_bus_distribute_available_resources(bus, add_list); 2328 2329 /* Depth last, allocate resources and update the hardware. */ 2330 __pci_bus_assign_resources(bus, add_list, &fail_head); 2331 if (WARN_ON_ONCE(add_list && !list_empty(add_list))) 2332 free_list(add_list); 2333 tried_times++; 2334 2335 /* Any device complain? */ 2336 if (list_empty(&fail_head)) 2337 break; 2338 2339 if (tried_times >= pci_try_num) { 2340 if (enable_local == undefined) { 2341 dev_info(&bus->dev, 2342 "Some PCI device resources are unassigned, try booting with pci=realloc\n"); 2343 } else if (enable_local == auto_enabled) { 2344 dev_info(&bus->dev, 2345 "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); 2346 } 2347 free_list(&fail_head); 2348 break; 2349 } 2350 2351 /* Third times and later will not check if it is leaf */ 2352 if (tried_times + 1 > 2) 2353 rel_type = whole_subtree; 2354 2355 pci_prepare_next_assign_round(&fail_head, tried_times, rel_type); 2356 } 2357 2358 pci_bus_dump_resources(bus); 2359 } 2360 2361 void pci_assign_unassigned_resources(void) 2362 { 2363 struct pci_bus *root_bus; 2364 2365 list_for_each_entry(root_bus, &pci_root_buses, node) { 2366 pci_assign_unassigned_root_bus_resources(root_bus); 2367 2368 /* Make sure the root bridge has a companion ACPI device */ 2369 if (ACPI_HANDLE(root_bus->bridge)) 2370 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge)); 2371 } 2372 } 2373 2374 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) 2375 { 2376 struct pci_bus *parent = bridge->subordinate; 2377 /* List of resources that want additional resources */ 2378 LIST_HEAD(add_list); 2379 int tried_times = 0; 2380 LIST_HEAD(fail_head); 2381 int ret; 2382 2383 while (1) { 2384 __pci_bus_size_bridges(parent, &add_list); 2385 2386 /* 2387 * Distribute remaining resources (if any) equally between 2388 * hotplug bridges below. This makes it possible to extend 2389 * the hierarchy later without running out of resources. 2390 */ 2391 pci_bridge_distribute_available_resources(bridge, &add_list); 2392 2393 __pci_bridge_assign_resources(bridge, &add_list, &fail_head); 2394 if (WARN_ON_ONCE(!list_empty(&add_list))) 2395 free_list(&add_list); 2396 tried_times++; 2397 2398 if (list_empty(&fail_head)) 2399 break; 2400 2401 if (tried_times >= 2) { 2402 /* Still fail, don't need to try more */ 2403 free_list(&fail_head); 2404 break; 2405 } 2406 2407 pci_prepare_next_assign_round(&fail_head, tried_times, 2408 whole_subtree); 2409 } 2410 2411 ret = pci_reenable_device(bridge); 2412 if (ret) 2413 pci_err(bridge, "Error reenabling bridge (%d)\n", ret); 2414 pci_set_master(bridge); 2415 } 2416 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); 2417 2418 /* 2419 * Walk to the root bus, find the bridge window relevant for @res and 2420 * release it when possible. If the bridge window contains assigned 2421 * resources, it cannot be released. 2422 */ 2423 int pbus_reassign_bridge_resources(struct pci_bus *bus, struct resource *res) 2424 { 2425 unsigned long type = res->flags; 2426 struct pci_dev_resource *dev_res; 2427 struct pci_dev *bridge; 2428 LIST_HEAD(saved); 2429 LIST_HEAD(added); 2430 LIST_HEAD(failed); 2431 unsigned int i; 2432 int ret; 2433 2434 down_read(&pci_bus_sem); 2435 2436 while (!pci_is_root_bus(bus)) { 2437 bridge = bus->self; 2438 res = pbus_select_window(bus, res); 2439 if (!res) 2440 break; 2441 2442 i = pci_resource_num(bridge, res); 2443 2444 /* Ignore BARs which are still in use */ 2445 if (!res->child) { 2446 ret = add_to_list(&saved, bridge, res, 0, 0); 2447 if (ret) 2448 goto cleanup; 2449 2450 pci_release_resource(bridge, i); 2451 } else { 2452 const char *res_name = pci_resource_name(bridge, i); 2453 2454 pci_warn(bridge, 2455 "%s %pR: was not released (still contains assigned resources)\n", 2456 res_name, res); 2457 } 2458 2459 bus = bus->parent; 2460 } 2461 2462 if (list_empty(&saved)) { 2463 up_read(&pci_bus_sem); 2464 return -ENOENT; 2465 } 2466 2467 __pci_bus_size_bridges(bridge->subordinate, &added); 2468 __pci_bridge_assign_resources(bridge, &added, &failed); 2469 if (WARN_ON_ONCE(!list_empty(&added))) 2470 free_list(&added); 2471 2472 if (!list_empty(&failed)) { 2473 if (pci_required_resource_failed(&failed, type)) { 2474 ret = -ENOSPC; 2475 goto cleanup; 2476 } 2477 /* Only resources with unrelated types failed (again) */ 2478 free_list(&failed); 2479 } 2480 2481 list_for_each_entry(dev_res, &saved, list) { 2482 /* Skip the bridge we just assigned resources for */ 2483 if (bridge == dev_res->dev) 2484 continue; 2485 2486 bridge = dev_res->dev; 2487 pci_setup_bridge(bridge->subordinate); 2488 } 2489 2490 free_list(&saved); 2491 up_read(&pci_bus_sem); 2492 return 0; 2493 2494 cleanup: 2495 /* Restore size and flags */ 2496 list_for_each_entry(dev_res, &failed, list) 2497 restore_dev_resource(dev_res); 2498 free_list(&failed); 2499 2500 /* Revert to the old configuration */ 2501 list_for_each_entry(dev_res, &saved, list) { 2502 struct resource *res = dev_res->res; 2503 2504 bridge = dev_res->dev; 2505 i = pci_resource_num(bridge, res); 2506 2507 restore_dev_resource(dev_res); 2508 2509 pci_claim_resource(bridge, i); 2510 pci_setup_bridge(bridge->subordinate); 2511 } 2512 free_list(&saved); 2513 up_read(&pci_bus_sem); 2514 2515 return ret; 2516 } 2517 2518 void pci_assign_unassigned_bus_resources(struct pci_bus *bus) 2519 { 2520 struct pci_dev *dev; 2521 /* List of resources that want additional resources */ 2522 LIST_HEAD(add_list); 2523 2524 down_read(&pci_bus_sem); 2525 for_each_pci_bridge(dev, bus) 2526 if (pci_has_subordinate(dev)) 2527 __pci_bus_size_bridges(dev->subordinate, &add_list); 2528 up_read(&pci_bus_sem); 2529 __pci_bus_assign_resources(bus, &add_list, NULL); 2530 if (WARN_ON_ONCE(!list_empty(&add_list))) 2531 free_list(&add_list); 2532 } 2533 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); 2534