1 /* 2 * drivers/pci/setup-bus.c 3 * 4 * Extruded from code written by 5 * Dave Rusling (david.rusling@reo.mts.dec.com) 6 * David Mosberger (davidm@cs.arizona.edu) 7 * David Miller (davem@redhat.com) 8 * 9 * Support routines for initializing a PCI subsystem. 10 */ 11 12 /* 13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 14 * PCI-PCI bridges cleanup, sorted resource allocation. 15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 16 * Converted to allocation in 3 passes, which gives 17 * tighter packing. Prefetchable range support. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/pci.h> 24 #include <linux/errno.h> 25 #include <linux/ioport.h> 26 #include <linux/cache.h> 27 #include <linux/slab.h> 28 29 30 static void pbus_assign_resources_sorted(struct pci_bus *bus) 31 { 32 struct pci_dev *dev; 33 struct resource *res; 34 struct resource_list head, *list, *tmp; 35 int idx; 36 37 head.next = NULL; 38 list_for_each_entry(dev, &bus->devices, bus_list) { 39 u16 class = dev->class >> 8; 40 41 /* Don't touch classless devices or host bridges or ioapics. */ 42 if (class == PCI_CLASS_NOT_DEFINED || 43 class == PCI_CLASS_BRIDGE_HOST) 44 continue; 45 46 /* Don't touch ioapic devices already enabled by firmware */ 47 if (class == PCI_CLASS_SYSTEM_PIC) { 48 u16 command; 49 pci_read_config_word(dev, PCI_COMMAND, &command); 50 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) 51 continue; 52 } 53 54 pdev_sort_resources(dev, &head); 55 } 56 57 for (list = head.next; list;) { 58 res = list->res; 59 idx = res - &list->dev->resource[0]; 60 if (pci_assign_resource(list->dev, idx)) { 61 /* FIXME: get rid of this */ 62 res->start = 0; 63 res->end = 0; 64 res->flags = 0; 65 } 66 tmp = list; 67 list = list->next; 68 kfree(tmp); 69 } 70 } 71 72 void pci_setup_cardbus(struct pci_bus *bus) 73 { 74 struct pci_dev *bridge = bus->self; 75 struct pci_bus_region region; 76 77 dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n", 78 pci_domain_nr(bus), bus->number); 79 80 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); 81 if (bus->resource[0]->flags & IORESOURCE_IO) { 82 /* 83 * The IO resource is allocated a range twice as large as it 84 * would normally need. This allows us to set both IO regs. 85 */ 86 dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n", 87 (unsigned long)region.start, 88 (unsigned long)region.end); 89 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 90 region.start); 91 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 92 region.end); 93 } 94 95 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); 96 if (bus->resource[1]->flags & IORESOURCE_IO) { 97 dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n", 98 (unsigned long)region.start, 99 (unsigned long)region.end); 100 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 101 region.start); 102 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 103 region.end); 104 } 105 106 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); 107 if (bus->resource[2]->flags & IORESOURCE_MEM) { 108 dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n", 109 (unsigned long)region.start, 110 (unsigned long)region.end); 111 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 112 region.start); 113 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 114 region.end); 115 } 116 117 pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); 118 if (bus->resource[3]->flags & IORESOURCE_MEM) { 119 dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n", 120 (unsigned long)region.start, 121 (unsigned long)region.end); 122 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 123 region.start); 124 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 125 region.end); 126 } 127 } 128 EXPORT_SYMBOL(pci_setup_cardbus); 129 130 /* Initialize bridges with base/limit values we have collected. 131 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) 132 requires that if there is no I/O ports or memory behind the 133 bridge, corresponding range must be turned off by writing base 134 value greater than limit to the bridge's base/limit registers. 135 136 Note: care must be taken when updating I/O base/limit registers 137 of bridges which support 32-bit I/O. This update requires two 138 config space writes, so it's quite possible that an I/O window of 139 the bridge will have some undesirable address (e.g. 0) after the 140 first write. Ditto 64-bit prefetchable MMIO. */ 141 static void pci_setup_bridge(struct pci_bus *bus) 142 { 143 struct pci_dev *bridge = bus->self; 144 struct pci_bus_region region; 145 u32 l, bu, lu, io_upper16; 146 147 dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n", 148 pci_domain_nr(bus), bus->number); 149 150 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 151 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); 152 if (bus->resource[0]->flags & IORESOURCE_IO) { 153 pci_read_config_dword(bridge, PCI_IO_BASE, &l); 154 l &= 0xffff0000; 155 l |= (region.start >> 8) & 0x00f0; 156 l |= region.end & 0xf000; 157 /* Set up upper 16 bits of I/O base/limit. */ 158 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 159 dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n", 160 (unsigned long)region.start, 161 (unsigned long)region.end); 162 } 163 else { 164 /* Clear upper 16 bits of I/O base/limit. */ 165 io_upper16 = 0; 166 l = 0x00f0; 167 dev_info(&bridge->dev, " IO window: disabled\n"); 168 } 169 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ 170 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 171 /* Update lower 16 bits of I/O base/limit. */ 172 pci_write_config_dword(bridge, PCI_IO_BASE, l); 173 /* Update upper 16 bits of I/O base/limit. */ 174 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 175 176 /* Set up the top and bottom of the PCI Memory segment 177 for this bus. */ 178 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); 179 if (bus->resource[1]->flags & IORESOURCE_MEM) { 180 l = (region.start >> 16) & 0xfff0; 181 l |= region.end & 0xfff00000; 182 dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n", 183 (unsigned long)region.start, 184 (unsigned long)region.end); 185 } 186 else { 187 l = 0x0000fff0; 188 dev_info(&bridge->dev, " MEM window: disabled\n"); 189 } 190 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 191 192 /* Clear out the upper 32 bits of PREF limit. 193 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily 194 disables PREF range, which is ok. */ 195 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 196 197 /* Set up PREF base/limit. */ 198 bu = lu = 0; 199 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); 200 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { 201 l = (region.start >> 16) & 0xfff0; 202 l |= region.end & 0xfff00000; 203 bu = upper_32_bits(region.start); 204 lu = upper_32_bits(region.end); 205 dev_info(&bridge->dev, " PREFETCH window: %#016llx-%#016llx\n", 206 (unsigned long long)region.start, 207 (unsigned long long)region.end); 208 } 209 else { 210 l = 0x0000fff0; 211 dev_info(&bridge->dev, " PREFETCH window: disabled\n"); 212 } 213 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 214 215 /* Set the upper 32 bits of PREF base & limit. */ 216 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); 217 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); 218 219 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 220 } 221 222 /* Check whether the bridge supports optional I/O and 223 prefetchable memory ranges. If not, the respective 224 base/limit registers must be read-only and read as 0. */ 225 static void pci_bridge_check_ranges(struct pci_bus *bus) 226 { 227 u16 io; 228 u32 pmem; 229 struct pci_dev *bridge = bus->self; 230 struct resource *b_res; 231 232 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 233 b_res[1].flags |= IORESOURCE_MEM; 234 235 pci_read_config_word(bridge, PCI_IO_BASE, &io); 236 if (!io) { 237 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); 238 pci_read_config_word(bridge, PCI_IO_BASE, &io); 239 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 240 } 241 if (io) 242 b_res[0].flags |= IORESOURCE_IO; 243 /* DECchip 21050 pass 2 errata: the bridge may miss an address 244 disconnect boundary by one PCI data phase. 245 Workaround: do not use prefetching on this device. */ 246 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 247 return; 248 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 249 if (!pmem) { 250 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 251 0xfff0fff0); 252 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 253 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 254 } 255 if (pmem) 256 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 257 } 258 259 /* Helper function for sizing routines: find first available 260 bus resource of a given type. Note: we intentionally skip 261 the bus resources which have already been assigned (that is, 262 have non-NULL parent resource). */ 263 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) 264 { 265 int i; 266 struct resource *r; 267 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 268 IORESOURCE_PREFETCH; 269 270 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 271 r = bus->resource[i]; 272 if (r == &ioport_resource || r == &iomem_resource) 273 continue; 274 if (r && (r->flags & type_mask) == type && !r->parent) 275 return r; 276 } 277 return NULL; 278 } 279 280 /* Sizing the IO windows of the PCI-PCI bridge is trivial, 281 since these windows have 4K granularity and the IO ranges 282 of non-bridge PCI devices are limited to 256 bytes. 283 We must be careful with the ISA aliasing though. */ 284 static void pbus_size_io(struct pci_bus *bus) 285 { 286 struct pci_dev *dev; 287 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 288 unsigned long size = 0, size1 = 0; 289 290 if (!b_res) 291 return; 292 293 list_for_each_entry(dev, &bus->devices, bus_list) { 294 int i; 295 296 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 297 struct resource *r = &dev->resource[i]; 298 unsigned long r_size; 299 300 if (r->parent || !(r->flags & IORESOURCE_IO)) 301 continue; 302 r_size = resource_size(r); 303 304 if (r_size < 0x400) 305 /* Might be re-aligned for ISA */ 306 size += r_size; 307 else 308 size1 += r_size; 309 } 310 } 311 /* To be fixed in 2.5: we should have sort of HAVE_ISA 312 flag in the struct pci_bus. */ 313 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 314 size = (size & 0xff) + ((size & ~0xffUL) << 2); 315 #endif 316 size = ALIGN(size + size1, 4096); 317 if (!size) { 318 b_res->flags = 0; 319 return; 320 } 321 /* Alignment of the IO window is always 4K */ 322 b_res->start = 4096; 323 b_res->end = b_res->start + size - 1; 324 b_res->flags |= IORESOURCE_STARTALIGN; 325 } 326 327 /* Calculate the size of the bus and minimal alignment which 328 guarantees that all child resources fit in this size. */ 329 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) 330 { 331 struct pci_dev *dev; 332 resource_size_t min_align, align, size; 333 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ 334 int order, max_order; 335 struct resource *b_res = find_free_bus_resource(bus, type); 336 337 if (!b_res) 338 return 0; 339 340 memset(aligns, 0, sizeof(aligns)); 341 max_order = 0; 342 size = 0; 343 344 list_for_each_entry(dev, &bus->devices, bus_list) { 345 int i; 346 347 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 348 struct resource *r = &dev->resource[i]; 349 resource_size_t r_size; 350 351 if (r->parent || (r->flags & mask) != type) 352 continue; 353 r_size = resource_size(r); 354 /* For bridges size != alignment */ 355 align = resource_alignment(r); 356 order = __ffs(align) - 20; 357 if (order > 11) { 358 dev_warn(&dev->dev, "BAR %d bad alignment %llx: " 359 "%pR\n", i, (unsigned long long)align, r); 360 r->flags = 0; 361 continue; 362 } 363 size += r_size; 364 if (order < 0) 365 order = 0; 366 /* Exclude ranges with size > align from 367 calculation of the alignment. */ 368 if (r_size == align) 369 aligns[order] += align; 370 if (order > max_order) 371 max_order = order; 372 } 373 } 374 375 align = 0; 376 min_align = 0; 377 for (order = 0; order <= max_order; order++) { 378 resource_size_t align1 = 1; 379 380 align1 <<= (order + 20); 381 382 if (!align) 383 min_align = align1; 384 else if (ALIGN(align + min_align, min_align) < align1) 385 min_align = align1 >> 1; 386 align += aligns[order]; 387 } 388 size = ALIGN(size, min_align); 389 if (!size) { 390 b_res->flags = 0; 391 return 1; 392 } 393 b_res->start = min_align; 394 b_res->end = size + min_align - 1; 395 b_res->flags |= IORESOURCE_STARTALIGN; 396 return 1; 397 } 398 399 static void pci_bus_size_cardbus(struct pci_bus *bus) 400 { 401 struct pci_dev *bridge = bus->self; 402 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 403 u16 ctrl; 404 405 /* 406 * Reserve some resources for CardBus. We reserve 407 * a fixed amount of bus space for CardBus bridges. 408 */ 409 b_res[0].start = 0; 410 b_res[0].end = pci_cardbus_io_size - 1; 411 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; 412 413 b_res[1].start = 0; 414 b_res[1].end = pci_cardbus_io_size - 1; 415 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; 416 417 /* 418 * Check whether prefetchable memory is supported 419 * by this bridge. 420 */ 421 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 422 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 423 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 424 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 425 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 426 } 427 428 /* 429 * If we have prefetchable memory support, allocate 430 * two regions. Otherwise, allocate one region of 431 * twice the size. 432 */ 433 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 434 b_res[2].start = 0; 435 b_res[2].end = pci_cardbus_mem_size - 1; 436 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; 437 438 b_res[3].start = 0; 439 b_res[3].end = pci_cardbus_mem_size - 1; 440 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; 441 } else { 442 b_res[3].start = 0; 443 b_res[3].end = pci_cardbus_mem_size * 2 - 1; 444 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; 445 } 446 } 447 448 void __ref pci_bus_size_bridges(struct pci_bus *bus) 449 { 450 struct pci_dev *dev; 451 unsigned long mask, prefmask; 452 453 list_for_each_entry(dev, &bus->devices, bus_list) { 454 struct pci_bus *b = dev->subordinate; 455 if (!b) 456 continue; 457 458 switch (dev->class >> 8) { 459 case PCI_CLASS_BRIDGE_CARDBUS: 460 pci_bus_size_cardbus(b); 461 break; 462 463 case PCI_CLASS_BRIDGE_PCI: 464 default: 465 pci_bus_size_bridges(b); 466 break; 467 } 468 } 469 470 /* The root bus? */ 471 if (!bus->self) 472 return; 473 474 switch (bus->self->class >> 8) { 475 case PCI_CLASS_BRIDGE_CARDBUS: 476 /* don't size cardbuses yet. */ 477 break; 478 479 case PCI_CLASS_BRIDGE_PCI: 480 pci_bridge_check_ranges(bus); 481 default: 482 pbus_size_io(bus); 483 /* If the bridge supports prefetchable range, size it 484 separately. If it doesn't, or its prefetchable window 485 has already been allocated by arch code, try 486 non-prefetchable range for both types of PCI memory 487 resources. */ 488 mask = IORESOURCE_MEM; 489 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 490 if (pbus_size_mem(bus, prefmask, prefmask)) 491 mask = prefmask; /* Success, size non-prefetch only. */ 492 pbus_size_mem(bus, mask, IORESOURCE_MEM); 493 break; 494 } 495 } 496 EXPORT_SYMBOL(pci_bus_size_bridges); 497 498 void __ref pci_bus_assign_resources(struct pci_bus *bus) 499 { 500 struct pci_bus *b; 501 struct pci_dev *dev; 502 503 pbus_assign_resources_sorted(bus); 504 505 list_for_each_entry(dev, &bus->devices, bus_list) { 506 b = dev->subordinate; 507 if (!b) 508 continue; 509 510 pci_bus_assign_resources(b); 511 512 switch (dev->class >> 8) { 513 case PCI_CLASS_BRIDGE_PCI: 514 pci_setup_bridge(b); 515 break; 516 517 case PCI_CLASS_BRIDGE_CARDBUS: 518 pci_setup_cardbus(b); 519 break; 520 521 default: 522 dev_info(&dev->dev, "not setting up bridge for bus " 523 "%04x:%02x\n", pci_domain_nr(b), b->number); 524 break; 525 } 526 } 527 } 528 EXPORT_SYMBOL(pci_bus_assign_resources); 529 530 static void pci_bus_dump_res(struct pci_bus *bus) 531 { 532 int i; 533 534 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 535 struct resource *res = bus->resource[i]; 536 if (!res) 537 continue; 538 539 printk(KERN_INFO "bus: %02x index %x %s: %pR\n", 540 bus->number, i, 541 (res->flags & IORESOURCE_IO) ? "io port" : "mmio", res); 542 } 543 } 544 545 static void pci_bus_dump_resources(struct pci_bus *bus) 546 { 547 struct pci_bus *b; 548 struct pci_dev *dev; 549 550 551 pci_bus_dump_res(bus); 552 553 list_for_each_entry(dev, &bus->devices, bus_list) { 554 b = dev->subordinate; 555 if (!b) 556 continue; 557 558 pci_bus_dump_resources(b); 559 } 560 } 561 562 void __init 563 pci_assign_unassigned_resources(void) 564 { 565 struct pci_bus *bus; 566 567 /* Depth first, calculate sizes and alignments of all 568 subordinate buses. */ 569 list_for_each_entry(bus, &pci_root_buses, node) { 570 pci_bus_size_bridges(bus); 571 } 572 /* Depth last, allocate resources and update the hardware. */ 573 list_for_each_entry(bus, &pci_root_buses, node) { 574 pci_bus_assign_resources(bus); 575 pci_enable_bridges(bus); 576 } 577 578 /* dump the resource on buses */ 579 list_for_each_entry(bus, &pci_root_buses, node) { 580 pci_bus_dump_resources(bus); 581 } 582 } 583