1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/acpi.h> 24 #include "pci.h" 25 26 /* The Mellanox Tavor device gives false positive parity errors 27 * Mark this device with a broken_parity_status, to allow 28 * PCI scanning code to "skip" this now blacklisted device. 29 */ 30 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 31 { 32 dev->broken_parity_status = 1; /* This device gives false positives */ 33 } 34 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 36 37 /* Deal with broken BIOS'es that neglect to enable passive release, 38 which can cause problems in combination with the 82441FX/PPro MTRRs */ 39 static void __devinit quirk_passive_release(struct pci_dev *dev) 40 { 41 struct pci_dev *d = NULL; 42 unsigned char dlc; 43 44 /* We have to make sure a particular bit is set in the PIIX3 45 ISA bridge, so we have to go out and find it. */ 46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 47 pci_read_config_byte(d, 0x82, &dlc); 48 if (!(dlc & 1<<1)) { 49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 50 dlc |= 1<<1; 51 pci_write_config_byte(d, 0x82, dlc); 52 } 53 } 54 } 55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 56 57 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 58 but VIA don't answer queries. If you happen to have good contacts at VIA 59 ask them for me please -- Alan 60 61 This appears to be BIOS not version dependent. So presumably there is a 62 chipset level fix */ 63 int isa_dma_bridge_buggy; /* Exported */ 64 65 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 66 { 67 if (!isa_dma_bridge_buggy) { 68 isa_dma_bridge_buggy=1; 69 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 70 } 71 } 72 /* 73 * Its not totally clear which chipsets are the problematic ones 74 * We know 82C586 and 82C596 variants are affected. 75 */ 76 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 77 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 78 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 83 84 int pci_pci_problems; 85 86 /* 87 * Chipsets where PCI->PCI transfers vanish or hang 88 */ 89 static void __devinit quirk_nopcipci(struct pci_dev *dev) 90 { 91 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 92 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 93 pci_pci_problems |= PCIPCI_FAIL; 94 } 95 } 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 98 99 /* 100 * Triton requires workarounds to be used by the drivers 101 */ 102 static void __devinit quirk_triton(struct pci_dev *dev) 103 { 104 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 105 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 106 pci_pci_problems |= PCIPCI_TRITON; 107 } 108 } 109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 113 114 /* 115 * VIA Apollo KT133 needs PCI latency patch 116 * Made according to a windows driver based patch by George E. Breese 117 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 118 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 119 * the info on which Mr Breese based his work. 120 * 121 * Updated based on further information from the site and also on 122 * information provided by VIA 123 */ 124 static void __devinit quirk_vialatency(struct pci_dev *dev) 125 { 126 struct pci_dev *p; 127 u8 rev; 128 u8 busarb; 129 /* Ok we have a potential problem chipset here. Now see if we have 130 a buggy southbridge */ 131 132 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 133 if (p!=NULL) { 134 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 135 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 136 /* Check for buggy part revisions */ 137 if (rev < 0x40 || rev > 0x42) 138 goto exit; 139 } else { 140 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 141 if (p==NULL) /* No problem parts */ 142 goto exit; 143 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 144 /* Check for buggy part revisions */ 145 if (rev < 0x10 || rev > 0x12) 146 goto exit; 147 } 148 149 /* 150 * Ok we have the problem. Now set the PCI master grant to 151 * occur every master grant. The apparent bug is that under high 152 * PCI load (quite common in Linux of course) you can get data 153 * loss when the CPU is held off the bus for 3 bus master requests 154 * This happens to include the IDE controllers.... 155 * 156 * VIA only apply this fix when an SB Live! is present but under 157 * both Linux and Windows this isnt enough, and we have seen 158 * corruption without SB Live! but with things like 3 UDMA IDE 159 * controllers. So we ignore that bit of the VIA recommendation.. 160 */ 161 162 pci_read_config_byte(dev, 0x76, &busarb); 163 /* Set bit 4 and bi 5 of byte 76 to 0x01 164 "Master priority rotation on every PCI master grant */ 165 busarb &= ~(1<<5); 166 busarb |= (1<<4); 167 pci_write_config_byte(dev, 0x76, busarb); 168 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 169 exit: 170 pci_dev_put(p); 171 } 172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 175 176 /* 177 * VIA Apollo VP3 needs ETBF on BT848/878 178 */ 179 static void __devinit quirk_viaetbf(struct pci_dev *dev) 180 { 181 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 182 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 183 pci_pci_problems |= PCIPCI_VIAETBF; 184 } 185 } 186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 187 188 static void __devinit quirk_vsfx(struct pci_dev *dev) 189 { 190 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 191 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 192 pci_pci_problems |= PCIPCI_VSFX; 193 } 194 } 195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 196 197 /* 198 * Ali Magik requires workarounds to be used by the drivers 199 * that DMA to AGP space. Latency must be set to 0xA and triton 200 * workaround applied too 201 * [Info kindly provided by ALi] 202 */ 203 static void __init quirk_alimagik(struct pci_dev *dev) 204 { 205 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 206 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 207 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 208 } 209 } 210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 212 213 /* 214 * Natoma has some interesting boundary conditions with Zoran stuff 215 * at least 216 */ 217 static void __devinit quirk_natoma(struct pci_dev *dev) 218 { 219 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 220 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 221 pci_pci_problems |= PCIPCI_NATOMA; 222 } 223 } 224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 230 231 /* 232 * This chip can cause PCI parity errors if config register 0xA0 is read 233 * while DMAs are occurring. 234 */ 235 static void __devinit quirk_citrine(struct pci_dev *dev) 236 { 237 dev->cfg_size = 0xA0; 238 } 239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 240 241 /* 242 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 243 * If it's needed, re-allocate the region. 244 */ 245 static void __devinit quirk_s3_64M(struct pci_dev *dev) 246 { 247 struct resource *r = &dev->resource[0]; 248 249 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 250 r->start = 0; 251 r->end = 0x3ffffff; 252 } 253 } 254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 256 257 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 258 unsigned size, int nr, const char *name) 259 { 260 region &= ~(size-1); 261 if (region) { 262 struct pci_bus_region bus_region; 263 struct resource *res = dev->resource + nr; 264 265 res->name = pci_name(dev); 266 res->start = region; 267 res->end = region + size - 1; 268 res->flags = IORESOURCE_IO; 269 270 /* Convert from PCI bus to resource space. */ 271 bus_region.start = res->start; 272 bus_region.end = res->end; 273 pcibios_bus_to_resource(dev, res, &bus_region); 274 275 pci_claim_resource(dev, nr); 276 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 277 } 278 } 279 280 /* 281 * ATI Northbridge setups MCE the processor if you even 282 * read somewhere between 0x3b0->0x3bb or read 0x3d3 283 */ 284 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 285 { 286 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 287 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 288 request_region(0x3b0, 0x0C, "RadeonIGP"); 289 request_region(0x3d3, 0x01, "RadeonIGP"); 290 } 291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 292 293 /* 294 * Let's make the southbridge information explicit instead 295 * of having to worry about people probing the ACPI areas, 296 * for example.. (Yes, it happens, and if you read the wrong 297 * ACPI register it will put the machine to sleep with no 298 * way of waking it up again. Bummer). 299 * 300 * ALI M7101: Two IO regions pointed to by words at 301 * 0xE0 (64 bytes of ACPI registers) 302 * 0xE2 (32 bytes of SMB registers) 303 */ 304 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 305 { 306 u16 region; 307 308 pci_read_config_word(dev, 0xE0, ®ion); 309 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 310 pci_read_config_word(dev, 0xE2, ®ion); 311 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 312 } 313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 314 315 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 316 { 317 u32 devres; 318 u32 mask, size, base; 319 320 pci_read_config_dword(dev, port, &devres); 321 if ((devres & enable) != enable) 322 return; 323 mask = (devres >> 16) & 15; 324 base = devres & 0xffff; 325 size = 16; 326 for (;;) { 327 unsigned bit = size >> 1; 328 if ((bit & mask) == bit) 329 break; 330 size = bit; 331 } 332 /* 333 * For now we only print it out. Eventually we'll want to 334 * reserve it (at least if it's in the 0x1000+ range), but 335 * let's get enough confirmation reports first. 336 */ 337 base &= -size; 338 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); 339 } 340 341 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 342 { 343 u32 devres; 344 u32 mask, size, base; 345 346 pci_read_config_dword(dev, port, &devres); 347 if ((devres & enable) != enable) 348 return; 349 base = devres & 0xffff0000; 350 mask = (devres & 0x3f) << 16; 351 size = 128 << 16; 352 for (;;) { 353 unsigned bit = size >> 1; 354 if ((bit & mask) == bit) 355 break; 356 size = bit; 357 } 358 /* 359 * For now we only print it out. Eventually we'll want to 360 * reserve it, but let's get enough confirmation reports first. 361 */ 362 base &= -size; 363 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); 364 } 365 366 /* 367 * PIIX4 ACPI: Two IO regions pointed to by longwords at 368 * 0x40 (64 bytes of ACPI registers) 369 * 0x90 (16 bytes of SMB registers) 370 * and a few strange programmable PIIX4 device resources. 371 */ 372 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 373 { 374 u32 region, res_a; 375 376 pci_read_config_dword(dev, 0x40, ®ion); 377 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 378 pci_read_config_dword(dev, 0x90, ®ion); 379 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 380 381 /* Device resource A has enables for some of the other ones */ 382 pci_read_config_dword(dev, 0x5c, &res_a); 383 384 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 385 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 386 387 /* Device resource D is just bitfields for static resources */ 388 389 /* Device 12 enabled? */ 390 if (res_a & (1 << 29)) { 391 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 392 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 393 } 394 /* Device 13 enabled? */ 395 if (res_a & (1 << 30)) { 396 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 397 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 398 } 399 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 400 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 401 } 402 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 403 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi ); 404 405 /* 406 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 407 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 408 * 0x58 (64 bytes of GPIO I/O space) 409 */ 410 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 411 { 412 u32 region; 413 414 pci_read_config_dword(dev, 0x40, ®ion); 415 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); 416 417 pci_read_config_dword(dev, 0x58, ®ion); 418 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 419 } 420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 428 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 429 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 430 431 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) 432 { 433 u32 region; 434 435 pci_read_config_dword(dev, 0x40, ®ion); 436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); 437 438 pci_read_config_dword(dev, 0x48, ®ion); 439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 440 } 441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi ); 442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); 443 444 /* 445 * VIA ACPI: One IO region pointed to by longword at 446 * 0x48 or 0x20 (256 bytes of ACPI registers) 447 */ 448 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 449 { 450 u8 rev; 451 u32 region; 452 453 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 454 if (rev & 0x10) { 455 pci_read_config_dword(dev, 0x48, ®ion); 456 region &= PCI_BASE_ADDRESS_IO_MASK; 457 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 458 } 459 } 460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 461 462 /* 463 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 464 * 0x48 (256 bytes of ACPI registers) 465 * 0x70 (128 bytes of hardware monitoring register) 466 * 0x90 (16 bytes of SMB registers) 467 */ 468 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 469 { 470 u16 hm; 471 u32 smb; 472 473 quirk_vt82c586_acpi(dev); 474 475 pci_read_config_word(dev, 0x70, &hm); 476 hm &= PCI_BASE_ADDRESS_IO_MASK; 477 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 478 479 pci_read_config_dword(dev, 0x90, &smb); 480 smb &= PCI_BASE_ADDRESS_IO_MASK; 481 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 482 } 483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 484 485 /* 486 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 487 * 0x88 (128 bytes of power management registers) 488 * 0xd0 (16 bytes of SMB registers) 489 */ 490 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 491 { 492 u16 pm, smb; 493 494 pci_read_config_word(dev, 0x88, &pm); 495 pm &= PCI_BASE_ADDRESS_IO_MASK; 496 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 497 498 pci_read_config_word(dev, 0xd0, &smb); 499 smb &= PCI_BASE_ADDRESS_IO_MASK; 500 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 501 } 502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 503 504 505 #ifdef CONFIG_X86_IO_APIC 506 507 #include <asm/io_apic.h> 508 509 /* 510 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 511 * devices to the external APIC. 512 * 513 * TODO: When we have device-specific interrupt routers, 514 * this code will go away from quirks. 515 */ 516 static void __devinit quirk_via_ioapic(struct pci_dev *dev) 517 { 518 u8 tmp; 519 520 if (nr_ioapics < 1) 521 tmp = 0; /* nothing routed to external APIC */ 522 else 523 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 524 525 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 526 tmp == 0 ? "Disa" : "Ena"); 527 528 /* Offset 0x58: External APIC IRQ output control */ 529 pci_write_config_byte (dev, 0x58, tmp); 530 } 531 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 532 533 /* 534 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 535 * This leads to doubled level interrupt rates. 536 * Set this bit to get rid of cycle wastage. 537 * Otherwise uncritical. 538 */ 539 static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 540 { 541 u8 misc_control2; 542 #define BYPASS_APIC_DEASSERT 8 543 544 pci_read_config_byte(dev, 0x5B, &misc_control2); 545 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 546 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); 547 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 548 } 549 } 550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 551 552 /* 553 * The AMD io apic can hang the box when an apic irq is masked. 554 * We check all revs >= B0 (yet not in the pre production!) as the bug 555 * is currently marked NoFix 556 * 557 * We have multiple reports of hangs with this chipset that went away with 558 * noapic specified. For the moment we assume its the errata. We may be wrong 559 * of course. However the advice is demonstrably good even if so.. 560 */ 561 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 562 { 563 u8 rev; 564 565 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 566 if (rev >= 0x02) { 567 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n"); 568 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 569 } 570 } 571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 572 573 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 574 { 575 if (dev->devfn == 0 && dev->bus->number == 0) 576 sis_apic_bug = 1; 577 } 578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 579 580 int pci_msi_quirk; 581 582 #define AMD8131_revA0 0x01 583 #define AMD8131_revB0 0x11 584 #define AMD8131_MISC 0x40 585 #define AMD8131_NIOAMODE_BIT 0 586 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) 587 { 588 unsigned char revid, tmp; 589 590 if (dev->subordinate) { 591 printk(KERN_WARNING "PCI: MSI quirk detected. " 592 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n"); 593 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 594 } 595 596 if (nr_ioapics == 0) 597 return; 598 599 pci_read_config_byte(dev, PCI_REVISION_ID, &revid); 600 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { 601 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 602 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 603 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 604 pci_write_config_byte( dev, AMD8131_MISC, tmp); 605 } 606 } 607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); 608 609 static void __init quirk_svw_msi(struct pci_dev *dev) 610 { 611 pci_msi_quirk = 1; 612 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 613 } 614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi ); 615 #endif /* CONFIG_X86_IO_APIC */ 616 617 618 /* 619 * FIXME: it is questionable that quirk_via_acpi 620 * is needed. It shows up as an ISA bridge, and does not 621 * support the PCI_INTERRUPT_LINE register at all. Therefore 622 * it seems like setting the pci_dev's 'irq' to the 623 * value of the ACPI SCI interrupt is only done for convenience. 624 * -jgarzik 625 */ 626 static void __devinit quirk_via_acpi(struct pci_dev *d) 627 { 628 /* 629 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 630 */ 631 u8 irq; 632 pci_read_config_byte(d, 0x42, &irq); 633 irq &= 0xf; 634 if (irq && (irq != 2)) 635 d->irq = irq; 636 } 637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 639 640 /* 641 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip 642 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: 643 * when written, it makes an internal connection to the PIC. 644 * For these devices, this register is defined to be 4 bits wide. 645 * Normally this is fine. However for IO-APIC motherboards, or 646 * non-x86 architectures (yes Via exists on PPC among other places), 647 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get 648 * interrupts delivered properly. 649 * 650 * Some of the on-chip devices are actually '586 devices' so they are 651 * listed here. 652 */ 653 static void quirk_via_irq(struct pci_dev *dev) 654 { 655 u8 irq, new_irq; 656 657 new_irq = dev->irq & 0xf; 658 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 659 if (new_irq != irq) { 660 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n", 661 pci_name(dev), irq, new_irq); 662 udelay(15); /* unknown if delay really needed */ 663 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 664 } 665 } 666 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq); 667 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq); 668 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq); 669 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq); 670 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, quirk_via_irq); 671 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq); 672 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq); 673 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq); 674 675 /* 676 * VIA VT82C598 has its device ID settable and many BIOSes 677 * set it to the ID of VT82C597 for backward compatibility. 678 * We need to switch it off to be able to recognize the real 679 * type of the chip. 680 */ 681 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 682 { 683 pci_write_config_byte(dev, 0xfc, 0); 684 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 685 } 686 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 687 688 #ifdef CONFIG_ACPI_SLEEP 689 690 /* 691 * Some VIA systems boot with the abnormal status flag set. This can cause 692 * the BIOS to re-POST the system on resume rather than passing control 693 * back to the OS. Clear the flag on boot 694 */ 695 static void __devinit quirk_via_abnormal_poweroff(struct pci_dev *dev) 696 { 697 u32 reg; 698 699 acpi_hw_register_read(ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS, 700 ®); 701 702 if (reg & 0x800) { 703 printk("Clearing abnormal poweroff flag\n"); 704 acpi_hw_register_write(ACPI_MTX_DO_NOT_LOCK, 705 ACPI_REGISTER_PM1_STATUS, 706 (u16)0x800); 707 } 708 } 709 710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_abnormal_poweroff); 711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_abnormal_poweroff); 712 713 #endif 714 715 /* 716 * CardBus controllers have a legacy base address that enables them 717 * to respond as i82365 pcmcia controllers. We don't want them to 718 * do this even if the Linux CardBus driver is not loaded, because 719 * the Linux i82365 driver does not (and should not) handle CardBus. 720 */ 721 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) 722 { 723 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 724 return; 725 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 726 } 727 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 728 729 /* 730 * Following the PCI ordering rules is optional on the AMD762. I'm not 731 * sure what the designers were smoking but let's not inhale... 732 * 733 * To be fair to AMD, it follows the spec by default, its BIOS people 734 * who turn it off! 735 */ 736 static void __devinit quirk_amd_ordering(struct pci_dev *dev) 737 { 738 u32 pcic; 739 pci_read_config_dword(dev, 0x4C, &pcic); 740 if ((pcic&6)!=6) { 741 pcic |= 6; 742 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 743 pci_write_config_dword(dev, 0x4C, pcic); 744 pci_read_config_dword(dev, 0x84, &pcic); 745 pcic |= (1<<23); /* Required in this mode */ 746 pci_write_config_dword(dev, 0x84, pcic); 747 } 748 } 749 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 750 751 /* 752 * DreamWorks provided workaround for Dunord I-3000 problem 753 * 754 * This card decodes and responds to addresses not apparently 755 * assigned to it. We force a larger allocation to ensure that 756 * nothing gets put too close to it. 757 */ 758 static void __devinit quirk_dunord ( struct pci_dev * dev ) 759 { 760 struct resource *r = &dev->resource [1]; 761 r->start = 0; 762 r->end = 0xffffff; 763 } 764 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 765 766 /* 767 * i82380FB mobile docking controller: its PCI-to-PCI bridge 768 * is subtractive decoding (transparent), and does indicate this 769 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 770 * instead of 0x01. 771 */ 772 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 773 { 774 dev->transparent = 1; 775 } 776 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 777 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 778 779 /* 780 * Common misconfiguration of the MediaGX/Geode PCI master that will 781 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 782 * datasheets found at http://www.national.com/ds/GX for info on what 783 * these bits do. <christer@weinigel.se> 784 */ 785 static void __init quirk_mediagx_master(struct pci_dev *dev) 786 { 787 u8 reg; 788 pci_read_config_byte(dev, 0x41, ®); 789 if (reg & 2) { 790 reg &= ~2; 791 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 792 pci_write_config_byte(dev, 0x41, reg); 793 } 794 } 795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 796 797 /* 798 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers 799 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and 800 * secondary channels respectively). If the device reports Compatible mode 801 * but does use BAR0-3 for address decoding, we assume that firmware has 802 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374). 803 * Exceptions (if they exist) must be handled in chip/architecture specific 804 * fixups. 805 * 806 * Note: for non x86 people. You may need an arch specific quirk to handle 807 * moving IDE devices to native mode as well. Some plug in card devices power 808 * up in compatible mode and assume the BIOS will adjust them. 809 * 810 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as 811 * we do now ? We don't want is pci_enable_device to come along 812 * and assign new resources. Both approaches work for that. 813 */ 814 static void __devinit quirk_ide_bases(struct pci_dev *dev) 815 { 816 struct resource *res; 817 int first_bar = 2, last_bar = 0; 818 819 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 820 return; 821 822 res = &dev->resource[0]; 823 824 /* primary channel: ProgIf bit 0, BAR0, BAR1 */ 825 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { 826 res[0].start = res[0].end = res[0].flags = 0; 827 res[1].start = res[1].end = res[1].flags = 0; 828 first_bar = 0; 829 last_bar = 1; 830 } 831 832 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */ 833 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { 834 res[2].start = res[2].end = res[2].flags = 0; 835 res[3].start = res[3].end = res[3].flags = 0; 836 last_bar = 3; 837 } 838 839 if (!last_bar) 840 return; 841 842 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n", 843 first_bar, last_bar, pci_name(dev)); 844 } 845 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases); 846 847 /* 848 * Ensure C0 rev restreaming is off. This is normally done by 849 * the BIOS but in the odd case it is not the results are corruption 850 * hence the presence of a Linux check 851 */ 852 static void __init quirk_disable_pxb(struct pci_dev *pdev) 853 { 854 u16 config; 855 u8 rev; 856 857 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 858 if (rev != 0x04) /* Only C0 requires this */ 859 return; 860 pci_read_config_word(pdev, 0x40, &config); 861 if (config & (1<<6)) { 862 config &= ~(1<<6); 863 pci_write_config_word(pdev, 0x40, config); 864 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 865 } 866 } 867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 868 869 870 /* 871 * Serverworks CSB5 IDE does not fully support native mode 872 */ 873 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 874 { 875 u8 prog; 876 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 877 if (prog & 5) { 878 prog &= ~5; 879 pdev->class &= ~5; 880 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 881 /* need to re-assign BARs for compat mode */ 882 quirk_ide_bases(pdev); 883 } 884 } 885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 886 887 /* 888 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 889 */ 890 static void __init quirk_ide_samemode(struct pci_dev *pdev) 891 { 892 u8 prog; 893 894 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 895 896 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 897 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 898 prog &= ~5; 899 pdev->class &= ~5; 900 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 901 /* need to re-assign BARs for compat mode */ 902 quirk_ide_bases(pdev); 903 } 904 } 905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 906 907 /* This was originally an Alpha specific thing, but it really fits here. 908 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 909 */ 910 static void __init quirk_eisa_bridge(struct pci_dev *dev) 911 { 912 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 913 } 914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 915 916 /* 917 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled 918 * when a PCI-Soundcard is added. The BIOS only gives Options 919 * "Disabled" and "AUTO". This Quirk Sets the corresponding 920 * Register-Value to enable the Soundcard. 921 * 922 * FIXME: Presently this quirk will run on anything that has an 8237 923 * which isn't correct, we need to check DMI tables or something in 924 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it 925 * runs everywhere at present we suppress the printk output in most 926 * irrelevant cases. 927 */ 928 static void __init k8t_sound_hostbridge(struct pci_dev *dev) 929 { 930 unsigned char val; 931 932 pci_read_config_byte(dev, 0x50, &val); 933 if (val == 0x88 || val == 0xc8) { 934 /* Assume it's probably a MSI-K8T-Neo2Fir */ 935 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n"); 936 pci_write_config_byte(dev, 0x50, val & (~0x40)); 937 938 /* Verify the Change for Status output */ 939 pci_read_config_byte(dev, 0x50, &val); 940 if (val & 0x40) 941 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n"); 942 else 943 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n"); 944 } 945 } 946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge); 947 948 #ifndef CONFIG_ACPI_SLEEP 949 /* 950 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 951 * is not activated. The myth is that Asus said that they do not want the 952 * users to be irritated by just another PCI Device in the Win98 device 953 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 954 * package 2.7.0 for details) 955 * 956 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 957 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 958 * becomes necessary to do this tweak in two steps -- I've chosen the Host 959 * bridge as trigger. 960 * 961 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram 962 * will cause thermal management to break down, and causing machine to 963 * overheat. 964 */ 965 static int __initdata asus_hides_smbus; 966 967 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 968 { 969 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 970 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 971 switch(dev->subsystem_device) { 972 case 0x8025: /* P4B-LX */ 973 case 0x8070: /* P4B */ 974 case 0x8088: /* P4B533 */ 975 case 0x1626: /* L3C notebook */ 976 asus_hides_smbus = 1; 977 } 978 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 979 switch(dev->subsystem_device) { 980 case 0x80b1: /* P4GE-V */ 981 case 0x80b2: /* P4PE */ 982 case 0x8093: /* P4B533-V */ 983 asus_hides_smbus = 1; 984 } 985 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 986 switch(dev->subsystem_device) { 987 case 0x8030: /* P4T533 */ 988 asus_hides_smbus = 1; 989 } 990 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 991 switch (dev->subsystem_device) { 992 case 0x8070: /* P4G8X Deluxe */ 993 asus_hides_smbus = 1; 994 } 995 if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 996 switch (dev->subsystem_device) { 997 case 0x80c9: /* PU-DLS */ 998 asus_hides_smbus = 1; 999 } 1000 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1001 switch (dev->subsystem_device) { 1002 case 0x1751: /* M2N notebook */ 1003 case 0x1821: /* M5N notebook */ 1004 asus_hides_smbus = 1; 1005 } 1006 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1007 switch (dev->subsystem_device) { 1008 case 0x184b: /* W1N notebook */ 1009 case 0x186a: /* M6Ne notebook */ 1010 asus_hides_smbus = 1; 1011 } 1012 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { 1013 switch (dev->subsystem_device) { 1014 case 0x1882: /* M6V notebook */ 1015 case 0x1977: /* A6VA notebook */ 1016 asus_hides_smbus = 1; 1017 } 1018 } 1019 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1020 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1021 switch(dev->subsystem_device) { 1022 case 0x088C: /* HP Compaq nc8000 */ 1023 case 0x0890: /* HP Compaq nc6000 */ 1024 asus_hides_smbus = 1; 1025 } 1026 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1027 switch (dev->subsystem_device) { 1028 case 0x12bc: /* HP D330L */ 1029 case 0x12bd: /* HP D530 */ 1030 asus_hides_smbus = 1; 1031 } 1032 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { 1033 switch (dev->subsystem_device) { 1034 case 0x099c: /* HP Compaq nx6110 */ 1035 asus_hides_smbus = 1; 1036 } 1037 } 1038 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { 1039 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1040 switch(dev->subsystem_device) { 1041 case 0x0001: /* Toshiba Satellite A40 */ 1042 asus_hides_smbus = 1; 1043 } 1044 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1045 switch(dev->subsystem_device) { 1046 case 0x0001: /* Toshiba Tecra M2 */ 1047 asus_hides_smbus = 1; 1048 } 1049 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1050 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1051 switch(dev->subsystem_device) { 1052 case 0xC00C: /* Samsung P35 notebook */ 1053 asus_hides_smbus = 1; 1054 } 1055 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1056 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1057 switch(dev->subsystem_device) { 1058 case 0x0058: /* Compaq Evo N620c */ 1059 asus_hides_smbus = 1; 1060 } 1061 } 1062 } 1063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 1064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 1065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 1066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 1067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 1068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge ); 1069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 1070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 1071 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); 1072 1073 static void __init asus_hides_smbus_lpc(struct pci_dev *dev) 1074 { 1075 u16 val; 1076 1077 if (likely(!asus_hides_smbus)) 1078 return; 1079 1080 pci_read_config_word(dev, 0xF2, &val); 1081 if (val & 0x8) { 1082 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1083 pci_read_config_word(dev, 0xF2, &val); 1084 if (val & 0x8) 1085 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1086 else 1087 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 1088 } 1089 } 1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); 1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1096 1097 static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1098 { 1099 u32 val, rcba; 1100 void __iomem *base; 1101 1102 if (likely(!asus_hides_smbus)) 1103 return; 1104 pci_read_config_dword(dev, 0xF0, &rcba); 1105 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ 1106 if (base == NULL) return; 1107 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ 1108 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ 1109 iounmap(base); 1110 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); 1111 } 1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1113 1114 #endif 1115 1116 /* 1117 * SiS 96x south bridge: BIOS typically hides SMBus device... 1118 */ 1119 static void __init quirk_sis_96x_smbus(struct pci_dev *dev) 1120 { 1121 u8 val = 0; 1122 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 1123 pci_read_config_byte(dev, 0x77, &val); 1124 pci_write_config_byte(dev, 0x77, val & ~0x10); 1125 pci_read_config_byte(dev, 0x77, &val); 1126 } 1127 1128 /* 1129 * ... This is further complicated by the fact that some SiS96x south 1130 * bridges pretend to be 85C503/5513 instead. In that case see if we 1131 * spotted a compatible north bridge to make sure. 1132 * (pci_find_device doesn't work yet) 1133 * 1134 * We can also enable the sis96x bit in the discovery register.. 1135 */ 1136 static int __devinitdata sis_96x_compatible = 0; 1137 1138 #define SIS_DETECT_REGISTER 0x40 1139 1140 static void __init quirk_sis_503(struct pci_dev *dev) 1141 { 1142 u8 reg; 1143 u16 devid; 1144 1145 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1146 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1147 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1148 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1149 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1150 return; 1151 } 1152 1153 /* Make people aware that we changed the config.. */ 1154 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible); 1155 1156 /* 1157 * Ok, it now shows up as a 96x.. The 96x quirks are after 1158 * the 503 quirk in the quirk table, so they'll automatically 1159 * run and enable things like the SMBus device 1160 */ 1161 dev->device = devid; 1162 } 1163 1164 static void __init quirk_sis_96x_compatible(struct pci_dev *dev) 1165 { 1166 sis_96x_compatible = 1; 1167 } 1168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible ); 1169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible ); 1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible ); 1171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible ); 1172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible ); 1173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible ); 1174 1175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1176 /* 1177 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1178 * and MC97 modem controller are disabled when a second PCI soundcard is 1179 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1180 * -- bjd 1181 */ 1182 static void __init asus_hides_ac97_lpc(struct pci_dev *dev) 1183 { 1184 u8 val; 1185 int asus_hides_ac97 = 0; 1186 1187 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1188 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1189 asus_hides_ac97 = 1; 1190 } 1191 1192 if (!asus_hides_ac97) 1193 return; 1194 1195 pci_read_config_byte(dev, 0x50, &val); 1196 if (val & 0xc0) { 1197 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1198 pci_read_config_byte(dev, 0x50, &val); 1199 if (val & 0xc0) 1200 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1201 else 1202 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); 1203 } 1204 } 1205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); 1206 1207 1208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1212 1213 #if defined(CONFIG_SCSI_SATA) || defined(CONFIG_SCSI_SATA_MODULE) 1214 1215 /* 1216 * If we are using libata we can drive this chip properly but must 1217 * do this early on to make the additional device appear during 1218 * the PCI scanning. 1219 */ 1220 1221 static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev) 1222 { 1223 u32 conf; 1224 u8 hdr; 1225 1226 /* Only poke fn 0 */ 1227 if (PCI_FUNC(pdev->devfn)) 1228 return; 1229 1230 switch(pdev->device) { 1231 case PCI_DEVICE_ID_JMICRON_JMB365: 1232 case PCI_DEVICE_ID_JMICRON_JMB366: 1233 /* Redirect IDE second PATA port to the right spot */ 1234 pci_read_config_dword(pdev, 0x80, &conf); 1235 conf |= (1 << 24); 1236 /* Fall through */ 1237 pci_write_config_dword(pdev, 0x80, conf); 1238 case PCI_DEVICE_ID_JMICRON_JMB361: 1239 case PCI_DEVICE_ID_JMICRON_JMB363: 1240 pci_read_config_dword(pdev, 0x40, &conf); 1241 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1242 /* Set the class codes correctly and then direct IDE 0 */ 1243 conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */ 1244 conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */ 1245 pci_write_config_dword(pdev, 0x40, conf); 1246 1247 /* Reconfigure so that the PCI scanner discovers the 1248 device is now multifunction */ 1249 1250 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1251 pdev->hdr_type = hdr & 0x7f; 1252 pdev->multifunction = !!(hdr & 0x80); 1253 1254 break; 1255 } 1256 } 1257 1258 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn); 1259 1260 #endif 1261 1262 #ifdef CONFIG_X86_IO_APIC 1263 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1264 { 1265 int i; 1266 1267 if ((pdev->class >> 8) != 0xff00) 1268 return; 1269 1270 /* the first BAR is the location of the IO APIC...we must 1271 * not touch this (and it's already covered by the fixmap), so 1272 * forcibly insert it into the resource tree */ 1273 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1274 insert_resource(&iomem_resource, &pdev->resource[0]); 1275 1276 /* The next five BARs all seem to be rubbish, so just clean 1277 * them out */ 1278 for (i=1; i < 6; i++) { 1279 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1280 } 1281 1282 } 1283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1284 #endif 1285 1286 enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 }; 1287 /* Defaults to combined */ 1288 static enum ide_combined_type combined_mode; 1289 1290 static int __init combined_setup(char *str) 1291 { 1292 if (!strncmp(str, "ide", 3)) 1293 combined_mode = IDE; 1294 else if (!strncmp(str, "libata", 6)) 1295 combined_mode = LIBATA; 1296 else /* "combined" or anything else defaults to old behavior */ 1297 combined_mode = COMBINED; 1298 1299 return 1; 1300 } 1301 __setup("combined_mode=", combined_setup); 1302 1303 #ifdef CONFIG_SCSI_SATA_INTEL_COMBINED 1304 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) 1305 { 1306 u8 prog, comb, tmp; 1307 int ich = 0; 1308 1309 /* 1310 * Narrow down to Intel SATA PCI devices. 1311 */ 1312 switch (pdev->device) { 1313 /* PCI ids taken from drivers/scsi/ata_piix.c */ 1314 case 0x24d1: 1315 case 0x24df: 1316 case 0x25a3: 1317 case 0x25b0: 1318 ich = 5; 1319 break; 1320 case 0x2651: 1321 case 0x2652: 1322 case 0x2653: 1323 case 0x2680: /* ESB2 */ 1324 ich = 6; 1325 break; 1326 case 0x27c0: 1327 case 0x27c4: 1328 ich = 7; 1329 break; 1330 case 0x2828: /* ICH8M */ 1331 ich = 8; 1332 break; 1333 default: 1334 /* we do not handle this PCI device */ 1335 return; 1336 } 1337 1338 /* 1339 * Read combined mode register. 1340 */ 1341 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ 1342 1343 if (ich == 5) { 1344 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ 1345 if (tmp == 0x4) /* bits 10x */ 1346 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1347 else if (tmp == 0x6) /* bits 11x */ 1348 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1349 else 1350 return; /* not in combined mode */ 1351 } else { 1352 WARN_ON((ich != 6) && (ich != 7) && (ich != 8)); 1353 tmp &= 0x3; /* interesting bits 1:0 */ 1354 if (tmp & (1 << 0)) 1355 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1356 else if (tmp & (1 << 1)) 1357 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1358 else 1359 return; /* not in combined mode */ 1360 } 1361 1362 /* 1363 * Read programming interface register. 1364 * (Tells us if it's legacy or native mode) 1365 */ 1366 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1367 1368 /* if SATA port is in native mode, we're ok. */ 1369 if (prog & comb) 1370 return; 1371 1372 /* Don't reserve any so the IDE driver can get them (but only if 1373 * combined_mode=ide). 1374 */ 1375 if (combined_mode == IDE) 1376 return; 1377 1378 /* Grab them both for libata if combined_mode=libata. */ 1379 if (combined_mode == LIBATA) { 1380 request_region(0x1f0, 8, "libata"); /* port 0 */ 1381 request_region(0x170, 8, "libata"); /* port 1 */ 1382 return; 1383 } 1384 1385 /* SATA port is in legacy mode. Reserve port so that 1386 * IDE driver does not attempt to use it. If request_region 1387 * fails, it will be obvious at boot time, so we don't bother 1388 * checking return values. 1389 */ 1390 if (comb == (1 << 0)) 1391 request_region(0x1f0, 8, "libata"); /* port 0 */ 1392 else 1393 request_region(0x170, 8, "libata"); /* port 1 */ 1394 } 1395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); 1396 #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */ 1397 1398 1399 int pcie_mch_quirk; 1400 1401 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1402 { 1403 pcie_mch_quirk = 1; 1404 } 1405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1408 1409 1410 /* 1411 * It's possible for the MSI to get corrupted if shpc and acpi 1412 * are used together on certain PXH-based systems. 1413 */ 1414 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1415 { 1416 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), 1417 PCI_CAP_ID_MSI); 1418 dev->no_msi = 1; 1419 1420 printk(KERN_WARNING "PCI: PXH quirk detected, " 1421 "disabling MSI for SHPC device\n"); 1422 } 1423 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1424 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1425 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1426 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1427 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1428 1429 /* 1430 * Some Intel PCI Express chipsets have trouble with downstream 1431 * device power management. 1432 */ 1433 static void quirk_intel_pcie_pm(struct pci_dev * dev) 1434 { 1435 pci_pm_d3_delay = 120; 1436 dev->no_d1d2 = 1; 1437 } 1438 1439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1453 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1454 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1455 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1456 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1457 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1458 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1460 1461 /* 1462 * Fixup the cardbus bridges on the IBM Dock II docking station 1463 */ 1464 static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev) 1465 { 1466 u32 val; 1467 1468 /* 1469 * tie the 2 interrupt pins to INTA, and configure the 1470 * multifunction routing register to handle this. 1471 */ 1472 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) && 1473 (dev->subsystem_device == 0x0148)) { 1474 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge " 1475 "applying quirk\n"); 1476 pci_read_config_dword(dev, 0x8c, &val); 1477 val = ((val & 0xffffff00) | 0x1002); 1478 pci_write_config_dword(dev, 0x8c, val); 1479 pci_read_config_dword(dev, 0x80, &val); 1480 val = ((val & 0x00ffff00) | 0x2864c077); 1481 pci_write_config_dword(dev, 0x80, val); 1482 } 1483 } 1484 1485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, 1486 quirk_ibm_dock2_cardbus); 1487 1488 static void __devinit quirk_netmos(struct pci_dev *dev) 1489 { 1490 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1491 unsigned int num_serial = dev->subsystem_device & 0xf; 1492 1493 /* 1494 * These Netmos parts are multiport serial devices with optional 1495 * parallel ports. Even when parallel ports are present, they 1496 * are identified as class SERIAL, which means the serial driver 1497 * will claim them. To prevent this, mark them as class OTHER. 1498 * These combo devices should be claimed by parport_serial. 1499 * 1500 * The subdevice ID is of the form 0x00PS, where <P> is the number 1501 * of parallel ports and <S> is the number of serial ports. 1502 */ 1503 switch (dev->device) { 1504 case PCI_DEVICE_ID_NETMOS_9735: 1505 case PCI_DEVICE_ID_NETMOS_9745: 1506 case PCI_DEVICE_ID_NETMOS_9835: 1507 case PCI_DEVICE_ID_NETMOS_9845: 1508 case PCI_DEVICE_ID_NETMOS_9855: 1509 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1510 num_parallel) { 1511 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1512 "%u serial); changing class SERIAL to OTHER " 1513 "(use parport_serial)\n", 1514 dev->device, num_parallel, num_serial); 1515 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1516 (dev->class & 0xff); 1517 } 1518 } 1519 } 1520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1521 1522 static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1523 { 1524 u16 command; 1525 u32 bar; 1526 u8 __iomem *csr; 1527 u8 cmd_hi; 1528 1529 switch (dev->device) { 1530 /* PCI IDs taken from drivers/net/e100.c */ 1531 case 0x1029: 1532 case 0x1030 ... 0x1034: 1533 case 0x1038 ... 0x103E: 1534 case 0x1050 ... 0x1057: 1535 case 0x1059: 1536 case 0x1064 ... 0x106B: 1537 case 0x1091 ... 0x1095: 1538 case 0x1209: 1539 case 0x1229: 1540 case 0x2449: 1541 case 0x2459: 1542 case 0x245D: 1543 case 0x27DC: 1544 break; 1545 default: 1546 return; 1547 } 1548 1549 /* 1550 * Some firmware hands off the e100 with interrupts enabled, 1551 * which can cause a flood of interrupts if packets are 1552 * received before the driver attaches to the device. So 1553 * disable all e100 interrupts here. The driver will 1554 * re-enable them when it's ready. 1555 */ 1556 pci_read_config_word(dev, PCI_COMMAND, &command); 1557 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar); 1558 1559 if (!(command & PCI_COMMAND_MEMORY) || !bar) 1560 return; 1561 1562 csr = ioremap(bar, 8); 1563 if (!csr) { 1564 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n", 1565 pci_name(dev)); 1566 return; 1567 } 1568 1569 cmd_hi = readb(csr + 3); 1570 if (cmd_hi == 0) { 1571 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts " 1572 "enabled, disabling\n", pci_name(dev)); 1573 writeb(1, csr + 3); 1574 } 1575 1576 iounmap(csr); 1577 } 1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); 1579 1580 static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1581 { 1582 /* rev 1 ncr53c810 chips don't set the class at all which means 1583 * they don't get their resources remapped. Fix that here. 1584 */ 1585 1586 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1587 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); 1588 dev->class = PCI_CLASS_STORAGE_SCSI; 1589 } 1590 } 1591 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1592 1593 1594 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1595 { 1596 while (f < end) { 1597 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1598 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1599 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1600 f->hook(dev); 1601 } 1602 f++; 1603 } 1604 } 1605 1606 extern struct pci_fixup __start_pci_fixups_early[]; 1607 extern struct pci_fixup __end_pci_fixups_early[]; 1608 extern struct pci_fixup __start_pci_fixups_header[]; 1609 extern struct pci_fixup __end_pci_fixups_header[]; 1610 extern struct pci_fixup __start_pci_fixups_final[]; 1611 extern struct pci_fixup __end_pci_fixups_final[]; 1612 extern struct pci_fixup __start_pci_fixups_enable[]; 1613 extern struct pci_fixup __end_pci_fixups_enable[]; 1614 1615 1616 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 1617 { 1618 struct pci_fixup *start, *end; 1619 1620 switch(pass) { 1621 case pci_fixup_early: 1622 start = __start_pci_fixups_early; 1623 end = __end_pci_fixups_early; 1624 break; 1625 1626 case pci_fixup_header: 1627 start = __start_pci_fixups_header; 1628 end = __end_pci_fixups_header; 1629 break; 1630 1631 case pci_fixup_final: 1632 start = __start_pci_fixups_final; 1633 end = __end_pci_fixups_final; 1634 break; 1635 1636 case pci_fixup_enable: 1637 start = __start_pci_fixups_enable; 1638 end = __end_pci_fixups_enable; 1639 break; 1640 1641 default: 1642 /* stupid compiler warning, you would think with an enum... */ 1643 return; 1644 } 1645 pci_do_fixups(dev, start, end); 1646 } 1647 1648 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1649 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1650 { 1651 u16 en1k; 1652 u8 io_base_lo, io_limit_lo; 1653 unsigned long base, limit; 1654 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1655 1656 pci_read_config_word(dev, 0x40, &en1k); 1657 1658 if (en1k & 0x200) { 1659 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); 1660 1661 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1662 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1663 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1664 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1665 1666 if (base <= limit) { 1667 res->start = base; 1668 res->end = limit + 0x3ff; 1669 } 1670 } 1671 } 1672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1673 1674 /* Under some circumstances, AER is not linked with extended capabilities. 1675 * Force it to be linked by setting the corresponding control bit in the 1676 * config space. 1677 */ 1678 static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1679 { 1680 uint8_t b; 1681 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1682 if (!(b & 0x20)) { 1683 pci_write_config_byte(dev, 0xf41, b | 0x20); 1684 printk(KERN_INFO 1685 "PCI: Linking AER extended capability on %s\n", 1686 pci_name(dev)); 1687 } 1688 } 1689 } 1690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1691 quirk_nvidia_ck804_pcie_aer_ext_cap); 1692 1693 EXPORT_SYMBOL(pcie_mch_quirk); 1694 #ifdef CONFIG_HOTPLUG 1695 EXPORT_SYMBOL(pci_fixup_device); 1696 #endif 1697