1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/acpi.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <linux/mm.h> 28 #include <linux/nvme.h> 29 #include <linux/platform_data/x86/apple.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/switchtec.h> 32 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 33 #include "pci.h" 34 35 static ktime_t fixup_debug_start(struct pci_dev *dev, 36 void (*fn)(struct pci_dev *dev)) 37 { 38 if (initcall_debug) 39 pci_info(dev, "calling %pF @ %i\n", fn, task_pid_nr(current)); 40 41 return ktime_get(); 42 } 43 44 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 45 void (*fn)(struct pci_dev *dev)) 46 { 47 ktime_t delta, rettime; 48 unsigned long long duration; 49 50 rettime = ktime_get(); 51 delta = ktime_sub(rettime, calltime); 52 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 53 if (initcall_debug || duration > 10000) 54 pci_info(dev, "%pF took %lld usecs\n", fn, duration); 55 } 56 57 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 58 struct pci_fixup *end) 59 { 60 ktime_t calltime; 61 62 for (; f < end; f++) 63 if ((f->class == (u32) (dev->class >> f->class_shift) || 64 f->class == (u32) PCI_ANY_ID) && 65 (f->vendor == dev->vendor || 66 f->vendor == (u16) PCI_ANY_ID) && 67 (f->device == dev->device || 68 f->device == (u16) PCI_ANY_ID)) { 69 void (*hook)(struct pci_dev *dev); 70 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 71 hook = offset_to_ptr(&f->hook_offset); 72 #else 73 hook = f->hook; 74 #endif 75 calltime = fixup_debug_start(dev, hook); 76 hook(dev); 77 fixup_debug_report(dev, calltime, hook); 78 } 79 } 80 81 extern struct pci_fixup __start_pci_fixups_early[]; 82 extern struct pci_fixup __end_pci_fixups_early[]; 83 extern struct pci_fixup __start_pci_fixups_header[]; 84 extern struct pci_fixup __end_pci_fixups_header[]; 85 extern struct pci_fixup __start_pci_fixups_final[]; 86 extern struct pci_fixup __end_pci_fixups_final[]; 87 extern struct pci_fixup __start_pci_fixups_enable[]; 88 extern struct pci_fixup __end_pci_fixups_enable[]; 89 extern struct pci_fixup __start_pci_fixups_resume[]; 90 extern struct pci_fixup __end_pci_fixups_resume[]; 91 extern struct pci_fixup __start_pci_fixups_resume_early[]; 92 extern struct pci_fixup __end_pci_fixups_resume_early[]; 93 extern struct pci_fixup __start_pci_fixups_suspend[]; 94 extern struct pci_fixup __end_pci_fixups_suspend[]; 95 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 96 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 97 98 static bool pci_apply_fixup_final_quirks; 99 100 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 101 { 102 struct pci_fixup *start, *end; 103 104 switch (pass) { 105 case pci_fixup_early: 106 start = __start_pci_fixups_early; 107 end = __end_pci_fixups_early; 108 break; 109 110 case pci_fixup_header: 111 start = __start_pci_fixups_header; 112 end = __end_pci_fixups_header; 113 break; 114 115 case pci_fixup_final: 116 if (!pci_apply_fixup_final_quirks) 117 return; 118 start = __start_pci_fixups_final; 119 end = __end_pci_fixups_final; 120 break; 121 122 case pci_fixup_enable: 123 start = __start_pci_fixups_enable; 124 end = __end_pci_fixups_enable; 125 break; 126 127 case pci_fixup_resume: 128 start = __start_pci_fixups_resume; 129 end = __end_pci_fixups_resume; 130 break; 131 132 case pci_fixup_resume_early: 133 start = __start_pci_fixups_resume_early; 134 end = __end_pci_fixups_resume_early; 135 break; 136 137 case pci_fixup_suspend: 138 start = __start_pci_fixups_suspend; 139 end = __end_pci_fixups_suspend; 140 break; 141 142 case pci_fixup_suspend_late: 143 start = __start_pci_fixups_suspend_late; 144 end = __end_pci_fixups_suspend_late; 145 break; 146 147 default: 148 /* stupid compiler warning, you would think with an enum... */ 149 return; 150 } 151 pci_do_fixups(dev, start, end); 152 } 153 EXPORT_SYMBOL(pci_fixup_device); 154 155 static int __init pci_apply_final_quirks(void) 156 { 157 struct pci_dev *dev = NULL; 158 u8 cls = 0; 159 u8 tmp; 160 161 if (pci_cache_line_size) 162 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 163 pci_cache_line_size << 2); 164 165 pci_apply_fixup_final_quirks = true; 166 for_each_pci_dev(dev) { 167 pci_fixup_device(pci_fixup_final, dev); 168 /* 169 * If arch hasn't set it explicitly yet, use the CLS 170 * value shared by all PCI devices. If there's a 171 * mismatch, fall back to the default value. 172 */ 173 if (!pci_cache_line_size) { 174 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 175 if (!cls) 176 cls = tmp; 177 if (!tmp || cls == tmp) 178 continue; 179 180 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 181 cls << 2, tmp << 2, 182 pci_dfl_cache_line_size << 2); 183 pci_cache_line_size = pci_dfl_cache_line_size; 184 } 185 } 186 187 if (!pci_cache_line_size) { 188 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 189 cls << 2, pci_dfl_cache_line_size << 2); 190 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 191 } 192 193 return 0; 194 } 195 fs_initcall_sync(pci_apply_final_quirks); 196 197 /* 198 * Decoding should be disabled for a PCI device during BAR sizing to avoid 199 * conflict. But doing so may cause problems on host bridge and perhaps other 200 * key system devices. For devices that need to have mmio decoding always-on, 201 * we need to set the dev->mmio_always_on bit. 202 */ 203 static void quirk_mmio_always_on(struct pci_dev *dev) 204 { 205 dev->mmio_always_on = 1; 206 } 207 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 208 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 209 210 /* 211 * The Mellanox Tavor device gives false positive parity errors. Mark this 212 * device with a broken_parity_status to allow PCI scanning code to "skip" 213 * this now blacklisted device. 214 */ 215 static void quirk_mellanox_tavor(struct pci_dev *dev) 216 { 217 dev->broken_parity_status = 1; /* This device gives false positives */ 218 } 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 221 222 /* 223 * Deal with broken BIOSes that neglect to enable passive release, 224 * which can cause problems in combination with the 82441FX/PPro MTRRs 225 */ 226 static void quirk_passive_release(struct pci_dev *dev) 227 { 228 struct pci_dev *d = NULL; 229 unsigned char dlc; 230 231 /* 232 * We have to make sure a particular bit is set in the PIIX3 233 * ISA bridge, so we have to go out and find it. 234 */ 235 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 236 pci_read_config_byte(d, 0x82, &dlc); 237 if (!(dlc & 1<<1)) { 238 pci_info(d, "PIIX3: Enabling Passive Release\n"); 239 dlc |= 1<<1; 240 pci_write_config_byte(d, 0x82, dlc); 241 } 242 } 243 } 244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 245 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 246 247 /* 248 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 249 * workaround but VIA don't answer queries. If you happen to have good 250 * contacts at VIA ask them for me please -- Alan 251 * 252 * This appears to be BIOS not version dependent. So presumably there is a 253 * chipset level fix. 254 */ 255 static void quirk_isa_dma_hangs(struct pci_dev *dev) 256 { 257 if (!isa_dma_bridge_buggy) { 258 isa_dma_bridge_buggy = 1; 259 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 260 } 261 } 262 /* 263 * It's not totally clear which chipsets are the problematic ones. We know 264 * 82C586 and 82C596 variants are affected. 265 */ 266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 273 274 /* 275 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 276 * for some HT machines to use C4 w/o hanging. 277 */ 278 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 279 { 280 u32 pmbase; 281 u16 pm1a; 282 283 pci_read_config_dword(dev, 0x40, &pmbase); 284 pmbase = pmbase & 0xff80; 285 pm1a = inw(pmbase); 286 287 if (pm1a & 0x10) { 288 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 289 outw(0x10, pmbase); 290 } 291 } 292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 293 294 /* Chipsets where PCI->PCI transfers vanish or hang */ 295 static void quirk_nopcipci(struct pci_dev *dev) 296 { 297 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 298 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 299 pci_pci_problems |= PCIPCI_FAIL; 300 } 301 } 302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 304 305 static void quirk_nopciamd(struct pci_dev *dev) 306 { 307 u8 rev; 308 pci_read_config_byte(dev, 0x08, &rev); 309 if (rev == 0x13) { 310 /* Erratum 24 */ 311 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 312 pci_pci_problems |= PCIAGP_FAIL; 313 } 314 } 315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 316 317 /* Triton requires workarounds to be used by the drivers */ 318 static void quirk_triton(struct pci_dev *dev) 319 { 320 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 321 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 322 pci_pci_problems |= PCIPCI_TRITON; 323 } 324 } 325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 329 330 /* 331 * VIA Apollo KT133 needs PCI latency patch 332 * Made according to a Windows driver-based patch by George E. Breese; 333 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 334 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 335 * which Mr Breese based his work. 336 * 337 * Updated based on further information from the site and also on 338 * information provided by VIA 339 */ 340 static void quirk_vialatency(struct pci_dev *dev) 341 { 342 struct pci_dev *p; 343 u8 busarb; 344 345 /* 346 * Ok, we have a potential problem chipset here. Now see if we have 347 * a buggy southbridge. 348 */ 349 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 350 if (p != NULL) { 351 352 /* 353 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 354 * thanks Dan Hollis. 355 * Check for buggy part revisions 356 */ 357 if (p->revision < 0x40 || p->revision > 0x42) 358 goto exit; 359 } else { 360 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 361 if (p == NULL) /* No problem parts */ 362 goto exit; 363 364 /* Check for buggy part revisions */ 365 if (p->revision < 0x10 || p->revision > 0x12) 366 goto exit; 367 } 368 369 /* 370 * Ok we have the problem. Now set the PCI master grant to occur 371 * every master grant. The apparent bug is that under high PCI load 372 * (quite common in Linux of course) you can get data loss when the 373 * CPU is held off the bus for 3 bus master requests. This happens 374 * to include the IDE controllers.... 375 * 376 * VIA only apply this fix when an SB Live! is present but under 377 * both Linux and Windows this isn't enough, and we have seen 378 * corruption without SB Live! but with things like 3 UDMA IDE 379 * controllers. So we ignore that bit of the VIA recommendation.. 380 */ 381 pci_read_config_byte(dev, 0x76, &busarb); 382 383 /* 384 * Set bit 4 and bit 5 of byte 76 to 0x01 385 * "Master priority rotation on every PCI master grant" 386 */ 387 busarb &= ~(1<<5); 388 busarb |= (1<<4); 389 pci_write_config_byte(dev, 0x76, busarb); 390 pci_info(dev, "Applying VIA southbridge workaround\n"); 391 exit: 392 pci_dev_put(p); 393 } 394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 397 /* Must restore this on a resume from RAM */ 398 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 399 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 400 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 401 402 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 403 static void quirk_viaetbf(struct pci_dev *dev) 404 { 405 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 406 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 407 pci_pci_problems |= PCIPCI_VIAETBF; 408 } 409 } 410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 411 412 static void quirk_vsfx(struct pci_dev *dev) 413 { 414 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 415 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 416 pci_pci_problems |= PCIPCI_VSFX; 417 } 418 } 419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 420 421 /* 422 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 423 * space. Latency must be set to 0xA and Triton workaround applied too. 424 * [Info kindly provided by ALi] 425 */ 426 static void quirk_alimagik(struct pci_dev *dev) 427 { 428 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 429 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 430 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 431 } 432 } 433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 435 436 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 437 static void quirk_natoma(struct pci_dev *dev) 438 { 439 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 440 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 441 pci_pci_problems |= PCIPCI_NATOMA; 442 } 443 } 444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 450 451 /* 452 * This chip can cause PCI parity errors if config register 0xA0 is read 453 * while DMAs are occurring. 454 */ 455 static void quirk_citrine(struct pci_dev *dev) 456 { 457 dev->cfg_size = 0xA0; 458 } 459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 460 461 /* 462 * This chip can cause bus lockups if config addresses above 0x600 463 * are read or written. 464 */ 465 static void quirk_nfp6000(struct pci_dev *dev) 466 { 467 dev->cfg_size = 0x600; 468 } 469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 473 474 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 475 static void quirk_extend_bar_to_page(struct pci_dev *dev) 476 { 477 int i; 478 479 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) { 480 struct resource *r = &dev->resource[i]; 481 482 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 483 r->end = PAGE_SIZE - 1; 484 r->start = 0; 485 r->flags |= IORESOURCE_UNSET; 486 pci_info(dev, "expanded BAR %d to page size: %pR\n", 487 i, r); 488 } 489 } 490 } 491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 492 493 /* 494 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 495 * If it's needed, re-allocate the region. 496 */ 497 static void quirk_s3_64M(struct pci_dev *dev) 498 { 499 struct resource *r = &dev->resource[0]; 500 501 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 502 r->flags |= IORESOURCE_UNSET; 503 r->start = 0; 504 r->end = 0x3ffffff; 505 } 506 } 507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 509 510 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 511 const char *name) 512 { 513 u32 region; 514 struct pci_bus_region bus_region; 515 struct resource *res = dev->resource + pos; 516 517 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 518 519 if (!region) 520 return; 521 522 res->name = pci_name(dev); 523 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 524 res->flags |= 525 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 526 region &= ~(size - 1); 527 528 /* Convert from PCI bus to resource space */ 529 bus_region.start = region; 530 bus_region.end = region + size - 1; 531 pcibios_bus_to_resource(dev->bus, res, &bus_region); 532 533 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 534 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 535 } 536 537 /* 538 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 539 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 540 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 541 * (which conflicts w/ BAR1's memory range). 542 * 543 * CS553x's ISA PCI BARs may also be read-only (ref: 544 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 545 */ 546 static void quirk_cs5536_vsa(struct pci_dev *dev) 547 { 548 static char *name = "CS5536 ISA bridge"; 549 550 if (pci_resource_len(dev, 0) != 8) { 551 quirk_io(dev, 0, 8, name); /* SMB */ 552 quirk_io(dev, 1, 256, name); /* GPIO */ 553 quirk_io(dev, 2, 64, name); /* MFGPT */ 554 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 555 name); 556 } 557 } 558 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 559 560 static void quirk_io_region(struct pci_dev *dev, int port, 561 unsigned size, int nr, const char *name) 562 { 563 u16 region; 564 struct pci_bus_region bus_region; 565 struct resource *res = dev->resource + nr; 566 567 pci_read_config_word(dev, port, ®ion); 568 region &= ~(size - 1); 569 570 if (!region) 571 return; 572 573 res->name = pci_name(dev); 574 res->flags = IORESOURCE_IO; 575 576 /* Convert from PCI bus to resource space */ 577 bus_region.start = region; 578 bus_region.end = region + size - 1; 579 pcibios_bus_to_resource(dev->bus, res, &bus_region); 580 581 if (!pci_claim_resource(dev, nr)) 582 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 583 } 584 585 /* 586 * ATI Northbridge setups MCE the processor if you even read somewhere 587 * between 0x3b0->0x3bb or read 0x3d3 588 */ 589 static void quirk_ati_exploding_mce(struct pci_dev *dev) 590 { 591 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 592 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 593 request_region(0x3b0, 0x0C, "RadeonIGP"); 594 request_region(0x3d3, 0x01, "RadeonIGP"); 595 } 596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 597 598 /* 599 * In the AMD NL platform, this device ([1022:7912]) has a class code of 600 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 601 * claim it. 602 * 603 * But the dwc3 driver is a more specific driver for this device, and we'd 604 * prefer to use it instead of xhci. To prevent xhci from claiming the 605 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 606 * defines as "USB device (not host controller)". The dwc3 driver can then 607 * claim it based on its Vendor and Device ID. 608 */ 609 static void quirk_amd_nl_class(struct pci_dev *pdev) 610 { 611 u32 class = pdev->class; 612 613 /* Use "USB Device (not host controller)" class */ 614 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 615 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 616 class, pdev->class); 617 } 618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 619 quirk_amd_nl_class); 620 621 /* 622 * Synopsys USB 3.x host HAPS platform has a class code of 623 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 624 * devices should use dwc3-haps driver. Change these devices' class code to 625 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 626 * them. 627 */ 628 static void quirk_synopsys_haps(struct pci_dev *pdev) 629 { 630 u32 class = pdev->class; 631 632 switch (pdev->device) { 633 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 634 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 635 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 636 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 637 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 638 class, pdev->class); 639 break; 640 } 641 } 642 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 643 PCI_CLASS_SERIAL_USB_XHCI, 0, 644 quirk_synopsys_haps); 645 646 /* 647 * Let's make the southbridge information explicit instead of having to 648 * worry about people probing the ACPI areas, for example.. (Yes, it 649 * happens, and if you read the wrong ACPI register it will put the machine 650 * to sleep with no way of waking it up again. Bummer). 651 * 652 * ALI M7101: Two IO regions pointed to by words at 653 * 0xE0 (64 bytes of ACPI registers) 654 * 0xE2 (32 bytes of SMB registers) 655 */ 656 static void quirk_ali7101_acpi(struct pci_dev *dev) 657 { 658 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 659 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 660 } 661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 662 663 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 664 { 665 u32 devres; 666 u32 mask, size, base; 667 668 pci_read_config_dword(dev, port, &devres); 669 if ((devres & enable) != enable) 670 return; 671 mask = (devres >> 16) & 15; 672 base = devres & 0xffff; 673 size = 16; 674 for (;;) { 675 unsigned bit = size >> 1; 676 if ((bit & mask) == bit) 677 break; 678 size = bit; 679 } 680 /* 681 * For now we only print it out. Eventually we'll want to 682 * reserve it (at least if it's in the 0x1000+ range), but 683 * let's get enough confirmation reports first. 684 */ 685 base &= -size; 686 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 687 } 688 689 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 690 { 691 u32 devres; 692 u32 mask, size, base; 693 694 pci_read_config_dword(dev, port, &devres); 695 if ((devres & enable) != enable) 696 return; 697 base = devres & 0xffff0000; 698 mask = (devres & 0x3f) << 16; 699 size = 128 << 16; 700 for (;;) { 701 unsigned bit = size >> 1; 702 if ((bit & mask) == bit) 703 break; 704 size = bit; 705 } 706 707 /* 708 * For now we only print it out. Eventually we'll want to 709 * reserve it, but let's get enough confirmation reports first. 710 */ 711 base &= -size; 712 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 713 } 714 715 /* 716 * PIIX4 ACPI: Two IO regions pointed to by longwords at 717 * 0x40 (64 bytes of ACPI registers) 718 * 0x90 (16 bytes of SMB registers) 719 * and a few strange programmable PIIX4 device resources. 720 */ 721 static void quirk_piix4_acpi(struct pci_dev *dev) 722 { 723 u32 res_a; 724 725 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 726 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 727 728 /* Device resource A has enables for some of the other ones */ 729 pci_read_config_dword(dev, 0x5c, &res_a); 730 731 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 732 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 733 734 /* Device resource D is just bitfields for static resources */ 735 736 /* Device 12 enabled? */ 737 if (res_a & (1 << 29)) { 738 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 739 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 740 } 741 /* Device 13 enabled? */ 742 if (res_a & (1 << 30)) { 743 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 744 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 745 } 746 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 747 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 748 } 749 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 751 752 #define ICH_PMBASE 0x40 753 #define ICH_ACPI_CNTL 0x44 754 #define ICH4_ACPI_EN 0x10 755 #define ICH6_ACPI_EN 0x80 756 #define ICH4_GPIOBASE 0x58 757 #define ICH4_GPIO_CNTL 0x5c 758 #define ICH4_GPIO_EN 0x10 759 #define ICH6_GPIOBASE 0x48 760 #define ICH6_GPIO_CNTL 0x4c 761 #define ICH6_GPIO_EN 0x10 762 763 /* 764 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 765 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 766 * 0x58 (64 bytes of GPIO I/O space) 767 */ 768 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 769 { 770 u8 enable; 771 772 /* 773 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 774 * with low legacy (and fixed) ports. We don't know the decoding 775 * priority and can't tell whether the legacy device or the one created 776 * here is really at that address. This happens on boards with broken 777 * BIOSes. 778 */ 779 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 780 if (enable & ICH4_ACPI_EN) 781 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 782 "ICH4 ACPI/GPIO/TCO"); 783 784 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 785 if (enable & ICH4_GPIO_EN) 786 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 787 "ICH4 GPIO"); 788 } 789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 795 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 797 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 798 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 799 800 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 801 { 802 u8 enable; 803 804 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 805 if (enable & ICH6_ACPI_EN) 806 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 807 "ICH6 ACPI/GPIO/TCO"); 808 809 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 810 if (enable & ICH6_GPIO_EN) 811 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 812 "ICH6 GPIO"); 813 } 814 815 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 816 const char *name, int dynsize) 817 { 818 u32 val; 819 u32 size, base; 820 821 pci_read_config_dword(dev, reg, &val); 822 823 /* Enabled? */ 824 if (!(val & 1)) 825 return; 826 base = val & 0xfffc; 827 if (dynsize) { 828 /* 829 * This is not correct. It is 16, 32 or 64 bytes depending on 830 * register D31:F0:ADh bits 5:4. 831 * 832 * But this gets us at least _part_ of it. 833 */ 834 size = 16; 835 } else { 836 size = 128; 837 } 838 base &= ~(size-1); 839 840 /* 841 * Just print it out for now. We should reserve it after more 842 * debugging. 843 */ 844 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 845 } 846 847 static void quirk_ich6_lpc(struct pci_dev *dev) 848 { 849 /* Shared ACPI/GPIO decode with all ICH6+ */ 850 ich6_lpc_acpi_gpio(dev); 851 852 /* ICH6-specific generic IO decode */ 853 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 854 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 855 } 856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 858 859 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 860 const char *name) 861 { 862 u32 val; 863 u32 mask, base; 864 865 pci_read_config_dword(dev, reg, &val); 866 867 /* Enabled? */ 868 if (!(val & 1)) 869 return; 870 871 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 872 base = val & 0xfffc; 873 mask = (val >> 16) & 0xfc; 874 mask |= 3; 875 876 /* 877 * Just print it out for now. We should reserve it after more 878 * debugging. 879 */ 880 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 881 } 882 883 /* ICH7-10 has the same common LPC generic IO decode registers */ 884 static void quirk_ich7_lpc(struct pci_dev *dev) 885 { 886 /* We share the common ACPI/GPIO decode with ICH6 */ 887 ich6_lpc_acpi_gpio(dev); 888 889 /* And have 4 ICH7+ generic decodes */ 890 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 891 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 892 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 893 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 894 } 895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 908 909 /* 910 * VIA ACPI: One IO region pointed to by longword at 911 * 0x48 or 0x20 (256 bytes of ACPI registers) 912 */ 913 static void quirk_vt82c586_acpi(struct pci_dev *dev) 914 { 915 if (dev->revision & 0x10) 916 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 917 "vt82c586 ACPI"); 918 } 919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 920 921 /* 922 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 923 * 0x48 (256 bytes of ACPI registers) 924 * 0x70 (128 bytes of hardware monitoring register) 925 * 0x90 (16 bytes of SMB registers) 926 */ 927 static void quirk_vt82c686_acpi(struct pci_dev *dev) 928 { 929 quirk_vt82c586_acpi(dev); 930 931 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 932 "vt82c686 HW-mon"); 933 934 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 935 } 936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 937 938 /* 939 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 940 * 0x88 (128 bytes of power management registers) 941 * 0xd0 (16 bytes of SMB registers) 942 */ 943 static void quirk_vt8235_acpi(struct pci_dev *dev) 944 { 945 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 946 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 947 } 948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 949 950 /* 951 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 952 * back-to-back: Disable fast back-to-back on the secondary bus segment 953 */ 954 static void quirk_xio2000a(struct pci_dev *dev) 955 { 956 struct pci_dev *pdev; 957 u16 command; 958 959 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 960 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 961 pci_read_config_word(pdev, PCI_COMMAND, &command); 962 if (command & PCI_COMMAND_FAST_BACK) 963 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 964 } 965 } 966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 967 quirk_xio2000a); 968 969 #ifdef CONFIG_X86_IO_APIC 970 971 #include <asm/io_apic.h> 972 973 /* 974 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 975 * devices to the external APIC. 976 * 977 * TODO: When we have device-specific interrupt routers, this code will go 978 * away from quirks. 979 */ 980 static void quirk_via_ioapic(struct pci_dev *dev) 981 { 982 u8 tmp; 983 984 if (nr_ioapics < 1) 985 tmp = 0; /* nothing routed to external APIC */ 986 else 987 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 988 989 pci_info(dev, "%sbling VIA external APIC routing\n", 990 tmp == 0 ? "Disa" : "Ena"); 991 992 /* Offset 0x58: External APIC IRQ output control */ 993 pci_write_config_byte(dev, 0x58, tmp); 994 } 995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 996 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 997 998 /* 999 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1000 * This leads to doubled level interrupt rates. 1001 * Set this bit to get rid of cycle wastage. 1002 * Otherwise uncritical. 1003 */ 1004 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1005 { 1006 u8 misc_control2; 1007 #define BYPASS_APIC_DEASSERT 8 1008 1009 pci_read_config_byte(dev, 0x5B, &misc_control2); 1010 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1011 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1012 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1013 } 1014 } 1015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1016 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1017 1018 /* 1019 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1020 * We check all revs >= B0 (yet not in the pre production!) as the bug 1021 * is currently marked NoFix 1022 * 1023 * We have multiple reports of hangs with this chipset that went away with 1024 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1025 * of course. However the advice is demonstrably good even if so. 1026 */ 1027 static void quirk_amd_ioapic(struct pci_dev *dev) 1028 { 1029 if (dev->revision >= 0x02) { 1030 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1031 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1032 } 1033 } 1034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1035 #endif /* CONFIG_X86_IO_APIC */ 1036 1037 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1038 1039 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1040 { 1041 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1042 if (dev->subsystem_device == 0xa118) 1043 dev->sriov->link = dev->devfn; 1044 } 1045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1046 #endif 1047 1048 /* 1049 * Some settings of MMRBC can lead to data corruption so block changes. 1050 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1051 */ 1052 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1053 { 1054 if (dev->subordinate && dev->revision <= 0x12) { 1055 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1056 dev->revision); 1057 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1058 } 1059 } 1060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1061 1062 /* 1063 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1064 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1065 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1066 * of the ACPI SCI interrupt is only done for convenience. 1067 * -jgarzik 1068 */ 1069 static void quirk_via_acpi(struct pci_dev *d) 1070 { 1071 u8 irq; 1072 1073 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1074 pci_read_config_byte(d, 0x42, &irq); 1075 irq &= 0xf; 1076 if (irq && (irq != 2)) 1077 d->irq = irq; 1078 } 1079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1081 1082 /* VIA bridges which have VLink */ 1083 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1084 1085 static void quirk_via_bridge(struct pci_dev *dev) 1086 { 1087 /* See what bridge we have and find the device ranges */ 1088 switch (dev->device) { 1089 case PCI_DEVICE_ID_VIA_82C686: 1090 /* 1091 * The VT82C686 is special; it attaches to PCI and can have 1092 * any device number. All its subdevices are functions of 1093 * that single device. 1094 */ 1095 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1096 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1097 break; 1098 case PCI_DEVICE_ID_VIA_8237: 1099 case PCI_DEVICE_ID_VIA_8237A: 1100 via_vlink_dev_lo = 15; 1101 break; 1102 case PCI_DEVICE_ID_VIA_8235: 1103 via_vlink_dev_lo = 16; 1104 break; 1105 case PCI_DEVICE_ID_VIA_8231: 1106 case PCI_DEVICE_ID_VIA_8233_0: 1107 case PCI_DEVICE_ID_VIA_8233A: 1108 case PCI_DEVICE_ID_VIA_8233C_0: 1109 via_vlink_dev_lo = 17; 1110 break; 1111 } 1112 } 1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1121 1122 /* 1123 * quirk_via_vlink - VIA VLink IRQ number update 1124 * @dev: PCI device 1125 * 1126 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1127 * the IRQ line register which usually is not relevant for PCI cards, is 1128 * actually written so that interrupts get sent to the right place. 1129 * 1130 * We only do this on systems where a VIA south bridge was detected, and 1131 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1132 */ 1133 static void quirk_via_vlink(struct pci_dev *dev) 1134 { 1135 u8 irq, new_irq; 1136 1137 /* Check if we have VLink at all */ 1138 if (via_vlink_dev_lo == -1) 1139 return; 1140 1141 new_irq = dev->irq; 1142 1143 /* Don't quirk interrupts outside the legacy IRQ range */ 1144 if (!new_irq || new_irq > 15) 1145 return; 1146 1147 /* Internal device ? */ 1148 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1149 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1150 return; 1151 1152 /* 1153 * This is an internal VLink device on a PIC interrupt. The BIOS 1154 * ought to have set this but may not have, so we redo it. 1155 */ 1156 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1157 if (new_irq != irq) { 1158 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1159 irq, new_irq); 1160 udelay(15); /* unknown if delay really needed */ 1161 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1162 } 1163 } 1164 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1165 1166 /* 1167 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1168 * of VT82C597 for backward compatibility. We need to switch it off to be 1169 * able to recognize the real type of the chip. 1170 */ 1171 static void quirk_vt82c598_id(struct pci_dev *dev) 1172 { 1173 pci_write_config_byte(dev, 0xfc, 0); 1174 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1175 } 1176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1177 1178 /* 1179 * CardBus controllers have a legacy base address that enables them to 1180 * respond as i82365 pcmcia controllers. We don't want them to do this 1181 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1182 * driver does not (and should not) handle CardBus. 1183 */ 1184 static void quirk_cardbus_legacy(struct pci_dev *dev) 1185 { 1186 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1187 } 1188 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1189 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1190 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1191 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1192 1193 /* 1194 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1195 * what the designers were smoking but let's not inhale... 1196 * 1197 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1198 * turn it off! 1199 */ 1200 static void quirk_amd_ordering(struct pci_dev *dev) 1201 { 1202 u32 pcic; 1203 pci_read_config_dword(dev, 0x4C, &pcic); 1204 if ((pcic & 6) != 6) { 1205 pcic |= 6; 1206 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1207 pci_write_config_dword(dev, 0x4C, pcic); 1208 pci_read_config_dword(dev, 0x84, &pcic); 1209 pcic |= (1 << 23); /* Required in this mode */ 1210 pci_write_config_dword(dev, 0x84, pcic); 1211 } 1212 } 1213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1214 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1215 1216 /* 1217 * DreamWorks-provided workaround for Dunord I-3000 problem 1218 * 1219 * This card decodes and responds to addresses not apparently assigned to 1220 * it. We force a larger allocation to ensure that nothing gets put too 1221 * close to it. 1222 */ 1223 static void quirk_dunord(struct pci_dev *dev) 1224 { 1225 struct resource *r = &dev->resource[1]; 1226 1227 r->flags |= IORESOURCE_UNSET; 1228 r->start = 0; 1229 r->end = 0xffffff; 1230 } 1231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1232 1233 /* 1234 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1235 * decoding (transparent), and does indicate this in the ProgIf. 1236 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1237 */ 1238 static void quirk_transparent_bridge(struct pci_dev *dev) 1239 { 1240 dev->transparent = 1; 1241 } 1242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1244 1245 /* 1246 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1247 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1248 * found at http://www.national.com/analog for info on what these bits do. 1249 * <christer@weinigel.se> 1250 */ 1251 static void quirk_mediagx_master(struct pci_dev *dev) 1252 { 1253 u8 reg; 1254 1255 pci_read_config_byte(dev, 0x41, ®); 1256 if (reg & 2) { 1257 reg &= ~2; 1258 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1259 reg); 1260 pci_write_config_byte(dev, 0x41, reg); 1261 } 1262 } 1263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1264 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1265 1266 /* 1267 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1268 * in the odd case it is not the results are corruption hence the presence 1269 * of a Linux check. 1270 */ 1271 static void quirk_disable_pxb(struct pci_dev *pdev) 1272 { 1273 u16 config; 1274 1275 if (pdev->revision != 0x04) /* Only C0 requires this */ 1276 return; 1277 pci_read_config_word(pdev, 0x40, &config); 1278 if (config & (1<<6)) { 1279 config &= ~(1<<6); 1280 pci_write_config_word(pdev, 0x40, config); 1281 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1282 } 1283 } 1284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1285 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1286 1287 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1288 { 1289 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1290 u8 tmp; 1291 1292 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1293 if (tmp == 0x01) { 1294 pci_read_config_byte(pdev, 0x40, &tmp); 1295 pci_write_config_byte(pdev, 0x40, tmp|1); 1296 pci_write_config_byte(pdev, 0x9, 1); 1297 pci_write_config_byte(pdev, 0xa, 6); 1298 pci_write_config_byte(pdev, 0x40, tmp); 1299 1300 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1301 pci_info(pdev, "set SATA to AHCI mode\n"); 1302 } 1303 } 1304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1305 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1307 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1309 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1311 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1312 1313 /* Serverworks CSB5 IDE does not fully support native mode */ 1314 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1315 { 1316 u8 prog; 1317 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1318 if (prog & 5) { 1319 prog &= ~5; 1320 pdev->class &= ~5; 1321 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1322 /* PCI layer will sort out resources */ 1323 } 1324 } 1325 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1326 1327 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1328 static void quirk_ide_samemode(struct pci_dev *pdev) 1329 { 1330 u8 prog; 1331 1332 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1333 1334 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1335 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1336 prog &= ~5; 1337 pdev->class &= ~5; 1338 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1339 } 1340 } 1341 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1342 1343 /* Some ATA devices break if put into D3 */ 1344 static void quirk_no_ata_d3(struct pci_dev *pdev) 1345 { 1346 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1347 } 1348 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1349 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1350 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1351 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1352 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1353 /* ALi loses some register settings that we cannot then restore */ 1354 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1355 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1356 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1357 occur when mode detecting */ 1358 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1359 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1360 1361 /* 1362 * This was originally an Alpha-specific thing, but it really fits here. 1363 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1364 */ 1365 static void quirk_eisa_bridge(struct pci_dev *dev) 1366 { 1367 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1368 } 1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1370 1371 /* 1372 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1373 * is not activated. The myth is that Asus said that they do not want the 1374 * users to be irritated by just another PCI Device in the Win98 device 1375 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1376 * package 2.7.0 for details) 1377 * 1378 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1379 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1380 * becomes necessary to do this tweak in two steps -- the chosen trigger 1381 * is either the Host bridge (preferred) or on-board VGA controller. 1382 * 1383 * Note that we used to unhide the SMBus that way on Toshiba laptops 1384 * (Satellite A40 and Tecra M2) but then found that the thermal management 1385 * was done by SMM code, which could cause unsynchronized concurrent 1386 * accesses to the SMBus registers, with potentially bad effects. Thus you 1387 * should be very careful when adding new entries: if SMM is accessing the 1388 * Intel SMBus, this is a very good reason to leave it hidden. 1389 * 1390 * Likewise, many recent laptops use ACPI for thermal management. If the 1391 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1392 * natively, and keeping the SMBus hidden is the right thing to do. If you 1393 * are about to add an entry in the table below, please first disassemble 1394 * the DSDT and double-check that there is no code accessing the SMBus. 1395 */ 1396 static int asus_hides_smbus; 1397 1398 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1399 { 1400 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1401 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1402 switch (dev->subsystem_device) { 1403 case 0x8025: /* P4B-LX */ 1404 case 0x8070: /* P4B */ 1405 case 0x8088: /* P4B533 */ 1406 case 0x1626: /* L3C notebook */ 1407 asus_hides_smbus = 1; 1408 } 1409 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1410 switch (dev->subsystem_device) { 1411 case 0x80b1: /* P4GE-V */ 1412 case 0x80b2: /* P4PE */ 1413 case 0x8093: /* P4B533-V */ 1414 asus_hides_smbus = 1; 1415 } 1416 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1417 switch (dev->subsystem_device) { 1418 case 0x8030: /* P4T533 */ 1419 asus_hides_smbus = 1; 1420 } 1421 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1422 switch (dev->subsystem_device) { 1423 case 0x8070: /* P4G8X Deluxe */ 1424 asus_hides_smbus = 1; 1425 } 1426 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1427 switch (dev->subsystem_device) { 1428 case 0x80c9: /* PU-DLS */ 1429 asus_hides_smbus = 1; 1430 } 1431 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1432 switch (dev->subsystem_device) { 1433 case 0x1751: /* M2N notebook */ 1434 case 0x1821: /* M5N notebook */ 1435 case 0x1897: /* A6L notebook */ 1436 asus_hides_smbus = 1; 1437 } 1438 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1439 switch (dev->subsystem_device) { 1440 case 0x184b: /* W1N notebook */ 1441 case 0x186a: /* M6Ne notebook */ 1442 asus_hides_smbus = 1; 1443 } 1444 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1445 switch (dev->subsystem_device) { 1446 case 0x80f2: /* P4P800-X */ 1447 asus_hides_smbus = 1; 1448 } 1449 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1450 switch (dev->subsystem_device) { 1451 case 0x1882: /* M6V notebook */ 1452 case 0x1977: /* A6VA notebook */ 1453 asus_hides_smbus = 1; 1454 } 1455 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1456 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1457 switch (dev->subsystem_device) { 1458 case 0x088C: /* HP Compaq nc8000 */ 1459 case 0x0890: /* HP Compaq nc6000 */ 1460 asus_hides_smbus = 1; 1461 } 1462 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1463 switch (dev->subsystem_device) { 1464 case 0x12bc: /* HP D330L */ 1465 case 0x12bd: /* HP D530 */ 1466 case 0x006a: /* HP Compaq nx9500 */ 1467 asus_hides_smbus = 1; 1468 } 1469 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1470 switch (dev->subsystem_device) { 1471 case 0x12bf: /* HP xw4100 */ 1472 asus_hides_smbus = 1; 1473 } 1474 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1475 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1476 switch (dev->subsystem_device) { 1477 case 0xC00C: /* Samsung P35 notebook */ 1478 asus_hides_smbus = 1; 1479 } 1480 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1481 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1482 switch (dev->subsystem_device) { 1483 case 0x0058: /* Compaq Evo N620c */ 1484 asus_hides_smbus = 1; 1485 } 1486 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1487 switch (dev->subsystem_device) { 1488 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1489 /* Motherboard doesn't have Host bridge 1490 * subvendor/subdevice IDs, therefore checking 1491 * its on-board VGA controller */ 1492 asus_hides_smbus = 1; 1493 } 1494 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1495 switch (dev->subsystem_device) { 1496 case 0x00b8: /* Compaq Evo D510 CMT */ 1497 case 0x00b9: /* Compaq Evo D510 SFF */ 1498 case 0x00ba: /* Compaq Evo D510 USDT */ 1499 /* Motherboard doesn't have Host bridge 1500 * subvendor/subdevice IDs and on-board VGA 1501 * controller is disabled if an AGP card is 1502 * inserted, therefore checking USB UHCI 1503 * Controller #1 */ 1504 asus_hides_smbus = 1; 1505 } 1506 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1507 switch (dev->subsystem_device) { 1508 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1509 /* Motherboard doesn't have host bridge 1510 * subvendor/subdevice IDs, therefore checking 1511 * its on-board VGA controller */ 1512 asus_hides_smbus = 1; 1513 } 1514 } 1515 } 1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1526 1527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1530 1531 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1532 { 1533 u16 val; 1534 1535 if (likely(!asus_hides_smbus)) 1536 return; 1537 1538 pci_read_config_word(dev, 0xF2, &val); 1539 if (val & 0x8) { 1540 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1541 pci_read_config_word(dev, 0xF2, &val); 1542 if (val & 0x8) 1543 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1544 val); 1545 else 1546 pci_info(dev, "Enabled i801 SMBus device\n"); 1547 } 1548 } 1549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1556 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1557 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1558 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1559 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1560 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1561 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1562 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1563 1564 /* It appears we just have one such device. If not, we have a warning */ 1565 static void __iomem *asus_rcba_base; 1566 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1567 { 1568 u32 rcba; 1569 1570 if (likely(!asus_hides_smbus)) 1571 return; 1572 WARN_ON(asus_rcba_base); 1573 1574 pci_read_config_dword(dev, 0xF0, &rcba); 1575 /* use bits 31:14, 16 kB aligned */ 1576 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1577 if (asus_rcba_base == NULL) 1578 return; 1579 } 1580 1581 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1582 { 1583 u32 val; 1584 1585 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1586 return; 1587 1588 /* read the Function Disable register, dword mode only */ 1589 val = readl(asus_rcba_base + 0x3418); 1590 1591 /* enable the SMBus device */ 1592 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1593 } 1594 1595 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1596 { 1597 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1598 return; 1599 1600 iounmap(asus_rcba_base); 1601 asus_rcba_base = NULL; 1602 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1603 } 1604 1605 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1606 { 1607 asus_hides_smbus_lpc_ich6_suspend(dev); 1608 asus_hides_smbus_lpc_ich6_resume_early(dev); 1609 asus_hides_smbus_lpc_ich6_resume(dev); 1610 } 1611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1612 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1613 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1614 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1615 1616 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1617 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1618 { 1619 u8 val = 0; 1620 pci_read_config_byte(dev, 0x77, &val); 1621 if (val & 0x10) { 1622 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1623 pci_write_config_byte(dev, 0x77, val & ~0x10); 1624 } 1625 } 1626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1630 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1631 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1632 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1633 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1634 1635 /* 1636 * ... This is further complicated by the fact that some SiS96x south 1637 * bridges pretend to be 85C503/5513 instead. In that case see if we 1638 * spotted a compatible north bridge to make sure. 1639 * (pci_find_device() doesn't work yet) 1640 * 1641 * We can also enable the sis96x bit in the discovery register.. 1642 */ 1643 #define SIS_DETECT_REGISTER 0x40 1644 1645 static void quirk_sis_503(struct pci_dev *dev) 1646 { 1647 u8 reg; 1648 u16 devid; 1649 1650 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1651 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1652 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1653 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1654 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1655 return; 1656 } 1657 1658 /* 1659 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1660 * it has already been processed. (Depends on link order, which is 1661 * apparently not guaranteed) 1662 */ 1663 dev->device = devid; 1664 quirk_sis_96x_smbus(dev); 1665 } 1666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1667 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1668 1669 /* 1670 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1671 * and MC97 modem controller are disabled when a second PCI soundcard is 1672 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1673 * -- bjd 1674 */ 1675 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1676 { 1677 u8 val; 1678 int asus_hides_ac97 = 0; 1679 1680 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1681 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1682 asus_hides_ac97 = 1; 1683 } 1684 1685 if (!asus_hides_ac97) 1686 return; 1687 1688 pci_read_config_byte(dev, 0x50, &val); 1689 if (val & 0xc0) { 1690 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1691 pci_read_config_byte(dev, 0x50, &val); 1692 if (val & 0xc0) 1693 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1694 val); 1695 else 1696 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1697 } 1698 } 1699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1700 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1701 1702 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1703 1704 /* 1705 * If we are using libata we can drive this chip properly but must do this 1706 * early on to make the additional device appear during the PCI scanning. 1707 */ 1708 static void quirk_jmicron_ata(struct pci_dev *pdev) 1709 { 1710 u32 conf1, conf5, class; 1711 u8 hdr; 1712 1713 /* Only poke fn 0 */ 1714 if (PCI_FUNC(pdev->devfn)) 1715 return; 1716 1717 pci_read_config_dword(pdev, 0x40, &conf1); 1718 pci_read_config_dword(pdev, 0x80, &conf5); 1719 1720 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1721 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1722 1723 switch (pdev->device) { 1724 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1725 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1726 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1727 /* The controller should be in single function ahci mode */ 1728 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1729 break; 1730 1731 case PCI_DEVICE_ID_JMICRON_JMB365: 1732 case PCI_DEVICE_ID_JMICRON_JMB366: 1733 /* Redirect IDE second PATA port to the right spot */ 1734 conf5 |= (1 << 24); 1735 /* Fall through */ 1736 case PCI_DEVICE_ID_JMICRON_JMB361: 1737 case PCI_DEVICE_ID_JMICRON_JMB363: 1738 case PCI_DEVICE_ID_JMICRON_JMB369: 1739 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1740 /* Set the class codes correctly and then direct IDE 0 */ 1741 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1742 break; 1743 1744 case PCI_DEVICE_ID_JMICRON_JMB368: 1745 /* The controller should be in single function IDE mode */ 1746 conf1 |= 0x00C00000; /* Set 22, 23 */ 1747 break; 1748 } 1749 1750 pci_write_config_dword(pdev, 0x40, conf1); 1751 pci_write_config_dword(pdev, 0x80, conf5); 1752 1753 /* Update pdev accordingly */ 1754 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1755 pdev->hdr_type = hdr & 0x7f; 1756 pdev->multifunction = !!(hdr & 0x80); 1757 1758 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1759 pdev->class = class >> 8; 1760 } 1761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1763 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1764 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1765 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1766 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1768 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1769 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1770 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1771 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1772 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1773 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1774 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1775 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1776 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1777 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1778 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1779 1780 #endif 1781 1782 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1783 { 1784 if (dev->multifunction) { 1785 device_disable_async_suspend(&dev->dev); 1786 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1787 } 1788 } 1789 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1790 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1792 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1793 1794 #ifdef CONFIG_X86_IO_APIC 1795 static void quirk_alder_ioapic(struct pci_dev *pdev) 1796 { 1797 int i; 1798 1799 if ((pdev->class >> 8) != 0xff00) 1800 return; 1801 1802 /* 1803 * The first BAR is the location of the IO-APIC... we must 1804 * not touch this (and it's already covered by the fixmap), so 1805 * forcibly insert it into the resource tree. 1806 */ 1807 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1808 insert_resource(&iomem_resource, &pdev->resource[0]); 1809 1810 /* 1811 * The next five BARs all seem to be rubbish, so just clean 1812 * them out. 1813 */ 1814 for (i = 1; i < 6; i++) 1815 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1816 } 1817 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1818 #endif 1819 1820 static void quirk_pcie_mch(struct pci_dev *pdev) 1821 { 1822 pdev->no_msi = 1; 1823 } 1824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1826 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1827 1828 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1829 1830 /* 1831 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1832 * together on certain PXH-based systems. 1833 */ 1834 static void quirk_pcie_pxh(struct pci_dev *dev) 1835 { 1836 dev->no_msi = 1; 1837 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1838 } 1839 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1840 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1841 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1842 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1843 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1844 1845 /* 1846 * Some Intel PCI Express chipsets have trouble with downstream device 1847 * power management. 1848 */ 1849 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1850 { 1851 pci_pm_d3_delay = 120; 1852 dev->no_d1d2 = 1; 1853 } 1854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1874 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1875 1876 static void quirk_radeon_pm(struct pci_dev *dev) 1877 { 1878 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1879 dev->subsystem_device == 0x00e2) { 1880 if (dev->d3_delay < 20) { 1881 dev->d3_delay = 20; 1882 pci_info(dev, "extending delay after power-on from D3 to %d msec\n", 1883 dev->d3_delay); 1884 } 1885 } 1886 } 1887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 1888 1889 #ifdef CONFIG_X86_IO_APIC 1890 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 1891 { 1892 noioapicreroute = 1; 1893 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 1894 1895 return 0; 1896 } 1897 1898 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 1899 /* 1900 * Systems to exclude from boot interrupt reroute quirks 1901 */ 1902 { 1903 .callback = dmi_disable_ioapicreroute, 1904 .ident = "ASUSTek Computer INC. M2N-LR", 1905 .matches = { 1906 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 1907 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 1908 }, 1909 }, 1910 {} 1911 }; 1912 1913 /* 1914 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1915 * remap the original interrupt in the Linux kernel to the boot interrupt, so 1916 * that a PCI device's interrupt handler is installed on the boot interrupt 1917 * line instead. 1918 */ 1919 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1920 { 1921 dmi_check_system(boot_interrupt_dmi_table); 1922 if (noioapicquirk || noioapicreroute) 1923 return; 1924 1925 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1926 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 1927 dev->vendor, dev->device); 1928 } 1929 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1931 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1932 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1934 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1935 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1936 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1937 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1938 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1939 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1940 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1941 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1942 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1943 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1944 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1945 1946 /* 1947 * On some chipsets we can disable the generation of legacy INTx boot 1948 * interrupts. 1949 */ 1950 1951 /* 1952 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 1953 * 300641-004US, section 5.7.3. 1954 */ 1955 #define INTEL_6300_IOAPIC_ABAR 0x40 1956 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1957 1958 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1959 { 1960 u16 pci_config_word; 1961 1962 if (noioapicquirk) 1963 return; 1964 1965 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1966 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1967 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1968 1969 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1970 dev->vendor, dev->device); 1971 } 1972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1973 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1974 1975 /* Disable boot interrupts on HT-1000 */ 1976 #define BC_HT1000_FEATURE_REG 0x64 1977 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1978 #define BC_HT1000_MAP_IDX 0xC00 1979 #define BC_HT1000_MAP_DATA 0xC01 1980 1981 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1982 { 1983 u32 pci_config_dword; 1984 u8 irq; 1985 1986 if (noioapicquirk) 1987 return; 1988 1989 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1990 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1991 BC_HT1000_PIC_REGS_ENABLE); 1992 1993 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1994 outb(irq, BC_HT1000_MAP_IDX); 1995 outb(0x00, BC_HT1000_MAP_DATA); 1996 } 1997 1998 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1999 2000 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2001 dev->vendor, dev->device); 2002 } 2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2004 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2005 2006 /* Disable boot interrupts on AMD and ATI chipsets */ 2007 2008 /* 2009 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2010 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2011 * (due to an erratum). 2012 */ 2013 #define AMD_813X_MISC 0x40 2014 #define AMD_813X_NOIOAMODE (1<<0) 2015 #define AMD_813X_REV_B1 0x12 2016 #define AMD_813X_REV_B2 0x13 2017 2018 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2019 { 2020 u32 pci_config_dword; 2021 2022 if (noioapicquirk) 2023 return; 2024 if ((dev->revision == AMD_813X_REV_B1) || 2025 (dev->revision == AMD_813X_REV_B2)) 2026 return; 2027 2028 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2029 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2030 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2031 2032 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2033 dev->vendor, dev->device); 2034 } 2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2036 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2038 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2039 2040 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2041 2042 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2043 { 2044 u16 pci_config_word; 2045 2046 if (noioapicquirk) 2047 return; 2048 2049 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2050 if (!pci_config_word) { 2051 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2052 dev->vendor, dev->device); 2053 return; 2054 } 2055 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2056 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2057 dev->vendor, dev->device); 2058 } 2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2060 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2061 #endif /* CONFIG_X86_IO_APIC */ 2062 2063 /* 2064 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2065 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2066 * Re-allocate the region if needed... 2067 */ 2068 static void quirk_tc86c001_ide(struct pci_dev *dev) 2069 { 2070 struct resource *r = &dev->resource[0]; 2071 2072 if (r->start & 0x8) { 2073 r->flags |= IORESOURCE_UNSET; 2074 r->start = 0; 2075 r->end = 0xf; 2076 } 2077 } 2078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2079 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2080 quirk_tc86c001_ide); 2081 2082 /* 2083 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2084 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2085 * being read correctly if bit 7 of the base address is set. 2086 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2087 * Re-allocate the regions to a 256-byte boundary if necessary. 2088 */ 2089 static void quirk_plx_pci9050(struct pci_dev *dev) 2090 { 2091 unsigned int bar; 2092 2093 /* Fixed in revision 2 (PCI 9052). */ 2094 if (dev->revision >= 2) 2095 return; 2096 for (bar = 0; bar <= 1; bar++) 2097 if (pci_resource_len(dev, bar) == 0x80 && 2098 (pci_resource_start(dev, bar) & 0x80)) { 2099 struct resource *r = &dev->resource[bar]; 2100 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2101 bar); 2102 r->flags |= IORESOURCE_UNSET; 2103 r->start = 0; 2104 r->end = 0xff; 2105 } 2106 } 2107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2108 quirk_plx_pci9050); 2109 /* 2110 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2111 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2112 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2113 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2114 * 2115 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2116 * driver. 2117 */ 2118 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2119 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2120 2121 static void quirk_netmos(struct pci_dev *dev) 2122 { 2123 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2124 unsigned int num_serial = dev->subsystem_device & 0xf; 2125 2126 /* 2127 * These Netmos parts are multiport serial devices with optional 2128 * parallel ports. Even when parallel ports are present, they 2129 * are identified as class SERIAL, which means the serial driver 2130 * will claim them. To prevent this, mark them as class OTHER. 2131 * These combo devices should be claimed by parport_serial. 2132 * 2133 * The subdevice ID is of the form 0x00PS, where <P> is the number 2134 * of parallel ports and <S> is the number of serial ports. 2135 */ 2136 switch (dev->device) { 2137 case PCI_DEVICE_ID_NETMOS_9835: 2138 /* Well, this rule doesn't hold for the following 9835 device */ 2139 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2140 dev->subsystem_device == 0x0299) 2141 return; 2142 /* else, fall through */ 2143 case PCI_DEVICE_ID_NETMOS_9735: 2144 case PCI_DEVICE_ID_NETMOS_9745: 2145 case PCI_DEVICE_ID_NETMOS_9845: 2146 case PCI_DEVICE_ID_NETMOS_9855: 2147 if (num_parallel) { 2148 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2149 dev->device, num_parallel, num_serial); 2150 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2151 (dev->class & 0xff); 2152 } 2153 } 2154 } 2155 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2156 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2157 2158 static void quirk_e100_interrupt(struct pci_dev *dev) 2159 { 2160 u16 command, pmcsr; 2161 u8 __iomem *csr; 2162 u8 cmd_hi; 2163 2164 switch (dev->device) { 2165 /* PCI IDs taken from drivers/net/e100.c */ 2166 case 0x1029: 2167 case 0x1030 ... 0x1034: 2168 case 0x1038 ... 0x103E: 2169 case 0x1050 ... 0x1057: 2170 case 0x1059: 2171 case 0x1064 ... 0x106B: 2172 case 0x1091 ... 0x1095: 2173 case 0x1209: 2174 case 0x1229: 2175 case 0x2449: 2176 case 0x2459: 2177 case 0x245D: 2178 case 0x27DC: 2179 break; 2180 default: 2181 return; 2182 } 2183 2184 /* 2185 * Some firmware hands off the e100 with interrupts enabled, 2186 * which can cause a flood of interrupts if packets are 2187 * received before the driver attaches to the device. So 2188 * disable all e100 interrupts here. The driver will 2189 * re-enable them when it's ready. 2190 */ 2191 pci_read_config_word(dev, PCI_COMMAND, &command); 2192 2193 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2194 return; 2195 2196 /* 2197 * Check that the device is in the D0 power state. If it's not, 2198 * there is no point to look any further. 2199 */ 2200 if (dev->pm_cap) { 2201 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2202 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2203 return; 2204 } 2205 2206 /* Convert from PCI bus to resource space. */ 2207 csr = ioremap(pci_resource_start(dev, 0), 8); 2208 if (!csr) { 2209 pci_warn(dev, "Can't map e100 registers\n"); 2210 return; 2211 } 2212 2213 cmd_hi = readb(csr + 3); 2214 if (cmd_hi == 0) { 2215 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2216 writeb(1, csr + 3); 2217 } 2218 2219 iounmap(csr); 2220 } 2221 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2222 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2223 2224 /* 2225 * The 82575 and 82598 may experience data corruption issues when transitioning 2226 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2227 */ 2228 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2229 { 2230 pci_info(dev, "Disabling L0s\n"); 2231 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2232 } 2233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2247 2248 static void fixup_rev1_53c810(struct pci_dev *dev) 2249 { 2250 u32 class = dev->class; 2251 2252 /* 2253 * rev 1 ncr53c810 chips don't set the class at all which means 2254 * they don't get their resources remapped. Fix that here. 2255 */ 2256 if (class) 2257 return; 2258 2259 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2260 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2261 class, dev->class); 2262 } 2263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2264 2265 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2266 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2267 { 2268 u16 en1k; 2269 2270 pci_read_config_word(dev, 0x40, &en1k); 2271 2272 if (en1k & 0x200) { 2273 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2274 dev->io_window_1k = 1; 2275 } 2276 } 2277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2278 2279 /* 2280 * Under some circumstances, AER is not linked with extended capabilities. 2281 * Force it to be linked by setting the corresponding control bit in the 2282 * config space. 2283 */ 2284 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2285 { 2286 uint8_t b; 2287 2288 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2289 if (!(b & 0x20)) { 2290 pci_write_config_byte(dev, 0xf41, b | 0x20); 2291 pci_info(dev, "Linking AER extended capability\n"); 2292 } 2293 } 2294 } 2295 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2296 quirk_nvidia_ck804_pcie_aer_ext_cap); 2297 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2298 quirk_nvidia_ck804_pcie_aer_ext_cap); 2299 2300 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2301 { 2302 /* 2303 * Disable PCI Bus Parking and PCI Master read caching on CX700 2304 * which causes unspecified timing errors with a VT6212L on the PCI 2305 * bus leading to USB2.0 packet loss. 2306 * 2307 * This quirk is only enabled if a second (on the external PCI bus) 2308 * VT6212L is found -- the CX700 core itself also contains a USB 2309 * host controller with the same PCI ID as the VT6212L. 2310 */ 2311 2312 /* Count VT6212L instances */ 2313 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2314 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2315 uint8_t b; 2316 2317 /* 2318 * p should contain the first (internal) VT6212L -- see if we have 2319 * an external one by searching again. 2320 */ 2321 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2322 if (!p) 2323 return; 2324 pci_dev_put(p); 2325 2326 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2327 if (b & 0x40) { 2328 /* Turn off PCI Bus Parking */ 2329 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2330 2331 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2332 } 2333 } 2334 2335 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2336 if (b != 0) { 2337 /* Turn off PCI Master read caching */ 2338 pci_write_config_byte(dev, 0x72, 0x0); 2339 2340 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2341 pci_write_config_byte(dev, 0x75, 0x1); 2342 2343 /* Disable "Read FIFO Timer" */ 2344 pci_write_config_byte(dev, 0x77, 0x0); 2345 2346 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2347 } 2348 } 2349 } 2350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2351 2352 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2353 { 2354 u32 rev; 2355 2356 pci_read_config_dword(dev, 0xf4, &rev); 2357 2358 /* Only CAP the MRRS if the device is a 5719 A0 */ 2359 if (rev == 0x05719000) { 2360 int readrq = pcie_get_readrq(dev); 2361 if (readrq > 2048) 2362 pcie_set_readrq(dev, 2048); 2363 } 2364 } 2365 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2366 PCI_DEVICE_ID_TIGON3_5719, 2367 quirk_brcm_5719_limit_mrrs); 2368 2369 #ifdef CONFIG_PCIE_IPROC_PLATFORM 2370 static void quirk_paxc_bridge(struct pci_dev *pdev) 2371 { 2372 /* 2373 * The PCI config space is shared with the PAXC root port and the first 2374 * Ethernet device. So, we need to workaround this by telling the PCI 2375 * code that the bridge is not an Ethernet device. 2376 */ 2377 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2378 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; 2379 2380 /* 2381 * MPSS is not being set properly (as it is currently 0). This is 2382 * because that area of the PCI config space is hard coded to zero, and 2383 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) 2384 * so that the MPS can be set to the real max value. 2385 */ 2386 pdev->pcie_mpss = 2; 2387 } 2388 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); 2389 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); 2390 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge); 2391 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge); 2392 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge); 2393 #endif 2394 2395 /* 2396 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2397 * hide device 6 which configures the overflow device access containing the 2398 * DRBs - this is where we expose device 6. 2399 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2400 */ 2401 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2402 { 2403 u8 reg; 2404 2405 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2406 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2407 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2408 } 2409 } 2410 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2411 quirk_unhide_mch_dev6); 2412 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2413 quirk_unhide_mch_dev6); 2414 2415 #ifdef CONFIG_PCI_MSI 2416 /* 2417 * Some chipsets do not support MSI. We cannot easily rely on setting 2418 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2419 * other buses controlled by the chipset even if Linux is not aware of it. 2420 * Instead of setting the flag on all buses in the machine, simply disable 2421 * MSI globally. 2422 */ 2423 static void quirk_disable_all_msi(struct pci_dev *dev) 2424 { 2425 pci_no_msi(); 2426 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2427 } 2428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2436 2437 /* Disable MSI on chipsets that are known to not support it */ 2438 static void quirk_disable_msi(struct pci_dev *dev) 2439 { 2440 if (dev->subordinate) { 2441 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2442 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2443 } 2444 } 2445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2448 2449 /* 2450 * The APC bridge device in AMD 780 family northbridges has some random 2451 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2452 * we use the possible vendor/device IDs of the host bridge for the 2453 * declared quirk, and search for the APC bridge by slot number. 2454 */ 2455 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2456 { 2457 struct pci_dev *apc_bridge; 2458 2459 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2460 if (apc_bridge) { 2461 if (apc_bridge->device == 0x9602) 2462 quirk_disable_msi(apc_bridge); 2463 pci_dev_put(apc_bridge); 2464 } 2465 } 2466 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2468 2469 /* 2470 * Go through the list of HyperTransport capabilities and return 1 if a HT 2471 * MSI capability is found and enabled. 2472 */ 2473 static int msi_ht_cap_enabled(struct pci_dev *dev) 2474 { 2475 int pos, ttl = PCI_FIND_CAP_TTL; 2476 2477 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2478 while (pos && ttl--) { 2479 u8 flags; 2480 2481 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2482 &flags) == 0) { 2483 pci_info(dev, "Found %s HT MSI Mapping\n", 2484 flags & HT_MSI_FLAGS_ENABLE ? 2485 "enabled" : "disabled"); 2486 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2487 } 2488 2489 pos = pci_find_next_ht_capability(dev, pos, 2490 HT_CAPTYPE_MSI_MAPPING); 2491 } 2492 return 0; 2493 } 2494 2495 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2496 static void quirk_msi_ht_cap(struct pci_dev *dev) 2497 { 2498 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2499 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2500 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2501 } 2502 } 2503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2504 quirk_msi_ht_cap); 2505 2506 /* 2507 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2508 * if the MSI capability is set in any of these mappings. 2509 */ 2510 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2511 { 2512 struct pci_dev *pdev; 2513 2514 if (!dev->subordinate) 2515 return; 2516 2517 /* 2518 * Check HT MSI cap on this chipset and the root one. A single one 2519 * having MSI is enough to be sure that MSI is supported. 2520 */ 2521 pdev = pci_get_slot(dev->bus, 0); 2522 if (!pdev) 2523 return; 2524 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2525 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2526 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2527 } 2528 pci_dev_put(pdev); 2529 } 2530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2531 quirk_nvidia_ck804_msi_ht_cap); 2532 2533 /* Force enable MSI mapping capability on HT bridges */ 2534 static void ht_enable_msi_mapping(struct pci_dev *dev) 2535 { 2536 int pos, ttl = PCI_FIND_CAP_TTL; 2537 2538 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2539 while (pos && ttl--) { 2540 u8 flags; 2541 2542 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2543 &flags) == 0) { 2544 pci_info(dev, "Enabling HT MSI Mapping\n"); 2545 2546 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2547 flags | HT_MSI_FLAGS_ENABLE); 2548 } 2549 pos = pci_find_next_ht_capability(dev, pos, 2550 HT_CAPTYPE_MSI_MAPPING); 2551 } 2552 } 2553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2554 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2555 ht_enable_msi_mapping); 2556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2557 ht_enable_msi_mapping); 2558 2559 /* 2560 * The P5N32-SLI motherboards from Asus have a problem with MSI 2561 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2562 * also affects other devices. As for now, turn off MSI for this device. 2563 */ 2564 static void nvenet_msi_disable(struct pci_dev *dev) 2565 { 2566 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2567 2568 if (board_name && 2569 (strstr(board_name, "P5N32-SLI PREMIUM") || 2570 strstr(board_name, "P5N32-E SLI"))) { 2571 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2572 dev->no_msi = 1; 2573 } 2574 } 2575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2576 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2577 nvenet_msi_disable); 2578 2579 /* 2580 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2581 * config register. This register controls the routing of legacy 2582 * interrupts from devices that route through the MCP55. If this register 2583 * is misprogrammed, interrupts are only sent to the BSP, unlike 2584 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2585 * having this register set properly prevents kdump from booting up 2586 * properly, so let's make sure that we have it set correctly. 2587 * Note that this is an undocumented register. 2588 */ 2589 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2590 { 2591 u32 cfg; 2592 2593 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2594 return; 2595 2596 pci_read_config_dword(dev, 0x74, &cfg); 2597 2598 if (cfg & ((1 << 2) | (1 << 15))) { 2599 printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n"); 2600 cfg &= ~((1 << 2) | (1 << 15)); 2601 pci_write_config_dword(dev, 0x74, cfg); 2602 } 2603 } 2604 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2605 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2606 nvbridge_check_legacy_irq_routing); 2607 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2608 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2609 nvbridge_check_legacy_irq_routing); 2610 2611 static int ht_check_msi_mapping(struct pci_dev *dev) 2612 { 2613 int pos, ttl = PCI_FIND_CAP_TTL; 2614 int found = 0; 2615 2616 /* Check if there is HT MSI cap or enabled on this device */ 2617 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2618 while (pos && ttl--) { 2619 u8 flags; 2620 2621 if (found < 1) 2622 found = 1; 2623 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2624 &flags) == 0) { 2625 if (flags & HT_MSI_FLAGS_ENABLE) { 2626 if (found < 2) { 2627 found = 2; 2628 break; 2629 } 2630 } 2631 } 2632 pos = pci_find_next_ht_capability(dev, pos, 2633 HT_CAPTYPE_MSI_MAPPING); 2634 } 2635 2636 return found; 2637 } 2638 2639 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2640 { 2641 struct pci_dev *dev; 2642 int pos; 2643 int i, dev_no; 2644 int found = 0; 2645 2646 dev_no = host_bridge->devfn >> 3; 2647 for (i = dev_no + 1; i < 0x20; i++) { 2648 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2649 if (!dev) 2650 continue; 2651 2652 /* found next host bridge? */ 2653 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2654 if (pos != 0) { 2655 pci_dev_put(dev); 2656 break; 2657 } 2658 2659 if (ht_check_msi_mapping(dev)) { 2660 found = 1; 2661 pci_dev_put(dev); 2662 break; 2663 } 2664 pci_dev_put(dev); 2665 } 2666 2667 return found; 2668 } 2669 2670 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2671 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2672 2673 static int is_end_of_ht_chain(struct pci_dev *dev) 2674 { 2675 int pos, ctrl_off; 2676 int end = 0; 2677 u16 flags, ctrl; 2678 2679 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2680 2681 if (!pos) 2682 goto out; 2683 2684 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2685 2686 ctrl_off = ((flags >> 10) & 1) ? 2687 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2688 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2689 2690 if (ctrl & (1 << 6)) 2691 end = 1; 2692 2693 out: 2694 return end; 2695 } 2696 2697 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2698 { 2699 struct pci_dev *host_bridge; 2700 int pos; 2701 int i, dev_no; 2702 int found = 0; 2703 2704 dev_no = dev->devfn >> 3; 2705 for (i = dev_no; i >= 0; i--) { 2706 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2707 if (!host_bridge) 2708 continue; 2709 2710 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2711 if (pos != 0) { 2712 found = 1; 2713 break; 2714 } 2715 pci_dev_put(host_bridge); 2716 } 2717 2718 if (!found) 2719 return; 2720 2721 /* don't enable end_device/host_bridge with leaf directly here */ 2722 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2723 host_bridge_with_leaf(host_bridge)) 2724 goto out; 2725 2726 /* root did that ! */ 2727 if (msi_ht_cap_enabled(host_bridge)) 2728 goto out; 2729 2730 ht_enable_msi_mapping(dev); 2731 2732 out: 2733 pci_dev_put(host_bridge); 2734 } 2735 2736 static void ht_disable_msi_mapping(struct pci_dev *dev) 2737 { 2738 int pos, ttl = PCI_FIND_CAP_TTL; 2739 2740 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2741 while (pos && ttl--) { 2742 u8 flags; 2743 2744 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2745 &flags) == 0) { 2746 pci_info(dev, "Disabling HT MSI Mapping\n"); 2747 2748 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2749 flags & ~HT_MSI_FLAGS_ENABLE); 2750 } 2751 pos = pci_find_next_ht_capability(dev, pos, 2752 HT_CAPTYPE_MSI_MAPPING); 2753 } 2754 } 2755 2756 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2757 { 2758 struct pci_dev *host_bridge; 2759 int pos; 2760 int found; 2761 2762 if (!pci_msi_enabled()) 2763 return; 2764 2765 /* check if there is HT MSI cap or enabled on this device */ 2766 found = ht_check_msi_mapping(dev); 2767 2768 /* no HT MSI CAP */ 2769 if (found == 0) 2770 return; 2771 2772 /* 2773 * HT MSI mapping should be disabled on devices that are below 2774 * a non-Hypertransport host bridge. Locate the host bridge... 2775 */ 2776 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 2777 PCI_DEVFN(0, 0)); 2778 if (host_bridge == NULL) { 2779 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2780 return; 2781 } 2782 2783 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2784 if (pos != 0) { 2785 /* Host bridge is to HT */ 2786 if (found == 1) { 2787 /* it is not enabled, try to enable it */ 2788 if (all) 2789 ht_enable_msi_mapping(dev); 2790 else 2791 nv_ht_enable_msi_mapping(dev); 2792 } 2793 goto out; 2794 } 2795 2796 /* HT MSI is not enabled */ 2797 if (found == 1) 2798 goto out; 2799 2800 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2801 ht_disable_msi_mapping(dev); 2802 2803 out: 2804 pci_dev_put(host_bridge); 2805 } 2806 2807 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2808 { 2809 return __nv_msi_ht_cap_quirk(dev, 1); 2810 } 2811 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2812 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2813 2814 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2815 { 2816 return __nv_msi_ht_cap_quirk(dev, 0); 2817 } 2818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2819 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2820 2821 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2822 { 2823 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2824 } 2825 2826 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2827 { 2828 struct pci_dev *p; 2829 2830 /* 2831 * SB700 MSI issue will be fixed at HW level from revision A21; 2832 * we need check PCI REVISION ID of SMBus controller to get SB700 2833 * revision. 2834 */ 2835 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2836 NULL); 2837 if (!p) 2838 return; 2839 2840 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2841 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2842 pci_dev_put(p); 2843 } 2844 2845 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2846 { 2847 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2848 if (dev->revision < 0x18) { 2849 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2850 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2851 } 2852 } 2853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2854 PCI_DEVICE_ID_TIGON3_5780, 2855 quirk_msi_intx_disable_bug); 2856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2857 PCI_DEVICE_ID_TIGON3_5780S, 2858 quirk_msi_intx_disable_bug); 2859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2860 PCI_DEVICE_ID_TIGON3_5714, 2861 quirk_msi_intx_disable_bug); 2862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2863 PCI_DEVICE_ID_TIGON3_5714S, 2864 quirk_msi_intx_disable_bug); 2865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2866 PCI_DEVICE_ID_TIGON3_5715, 2867 quirk_msi_intx_disable_bug); 2868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2869 PCI_DEVICE_ID_TIGON3_5715S, 2870 quirk_msi_intx_disable_bug); 2871 2872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2873 quirk_msi_intx_disable_ati_bug); 2874 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2875 quirk_msi_intx_disable_ati_bug); 2876 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2877 quirk_msi_intx_disable_ati_bug); 2878 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2879 quirk_msi_intx_disable_ati_bug); 2880 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2881 quirk_msi_intx_disable_ati_bug); 2882 2883 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2884 quirk_msi_intx_disable_bug); 2885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2886 quirk_msi_intx_disable_bug); 2887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2888 quirk_msi_intx_disable_bug); 2889 2890 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2891 quirk_msi_intx_disable_bug); 2892 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2893 quirk_msi_intx_disable_bug); 2894 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2895 quirk_msi_intx_disable_bug); 2896 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2897 quirk_msi_intx_disable_bug); 2898 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2899 quirk_msi_intx_disable_bug); 2900 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2901 quirk_msi_intx_disable_bug); 2902 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2903 quirk_msi_intx_disable_qca_bug); 2904 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2905 quirk_msi_intx_disable_qca_bug); 2906 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2907 quirk_msi_intx_disable_qca_bug); 2908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2909 quirk_msi_intx_disable_qca_bug); 2910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2911 quirk_msi_intx_disable_qca_bug); 2912 #endif /* CONFIG_PCI_MSI */ 2913 2914 /* 2915 * Allow manual resource allocation for PCI hotplug bridges via 2916 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 2917 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 2918 * allocate resources when hotplug device is inserted and PCI bus is 2919 * rescanned. 2920 */ 2921 static void quirk_hotplug_bridge(struct pci_dev *dev) 2922 { 2923 dev->is_hotplug_bridge = 1; 2924 } 2925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2926 2927 /* 2928 * This is a quirk for the Ricoh MMC controller found as a part of some 2929 * multifunction chips. 2930 * 2931 * This is very similar and based on the ricoh_mmc driver written by 2932 * Philip Langdale. Thank you for these magic sequences. 2933 * 2934 * These chips implement the four main memory card controllers (SD, MMC, 2935 * MS, xD) and one or both of CardBus or FireWire. 2936 * 2937 * It happens that they implement SD and MMC support as separate 2938 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 2939 * cards but the chip detects MMC cards in hardware and directs them to the 2940 * MMC controller - so the SDHCI driver never sees them. 2941 * 2942 * To get around this, we must disable the useless MMC controller. At that 2943 * point, the SDHCI controller will start seeing them. It seems to be the 2944 * case that the relevant PCI registers to deactivate the MMC controller 2945 * live on PCI function 0, which might be the CardBus controller or the 2946 * FireWire controller, depending on the particular chip in question 2947 * 2948 * This has to be done early, because as soon as we disable the MMC controller 2949 * other PCI functions shift up one level, e.g. function #2 becomes function 2950 * #1, and this will confuse the PCI core. 2951 */ 2952 #ifdef CONFIG_MMC_RICOH_MMC 2953 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2954 { 2955 u8 write_enable; 2956 u8 write_target; 2957 u8 disable; 2958 2959 /* 2960 * Disable via CardBus interface 2961 * 2962 * This must be done via function #0 2963 */ 2964 if (PCI_FUNC(dev->devfn)) 2965 return; 2966 2967 pci_read_config_byte(dev, 0xB7, &disable); 2968 if (disable & 0x02) 2969 return; 2970 2971 pci_read_config_byte(dev, 0x8E, &write_enable); 2972 pci_write_config_byte(dev, 0x8E, 0xAA); 2973 pci_read_config_byte(dev, 0x8D, &write_target); 2974 pci_write_config_byte(dev, 0x8D, 0xB7); 2975 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2976 pci_write_config_byte(dev, 0x8E, write_enable); 2977 pci_write_config_byte(dev, 0x8D, write_target); 2978 2979 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 2980 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2981 } 2982 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2983 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2984 2985 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2986 { 2987 u8 write_enable; 2988 u8 disable; 2989 2990 /* 2991 * Disable via FireWire interface 2992 * 2993 * This must be done via function #0 2994 */ 2995 if (PCI_FUNC(dev->devfn)) 2996 return; 2997 /* 2998 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2999 * certain types of SD/MMC cards. Lowering the SD base clock 3000 * frequency from 200Mhz to 50Mhz fixes this issue. 3001 * 3002 * 0x150 - SD2.0 mode enable for changing base clock 3003 * frequency to 50Mhz 3004 * 0xe1 - Base clock frequency 3005 * 0x32 - 50Mhz new clock frequency 3006 * 0xf9 - Key register for 0x150 3007 * 0xfc - key register for 0xe1 3008 */ 3009 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3010 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3011 pci_write_config_byte(dev, 0xf9, 0xfc); 3012 pci_write_config_byte(dev, 0x150, 0x10); 3013 pci_write_config_byte(dev, 0xf9, 0x00); 3014 pci_write_config_byte(dev, 0xfc, 0x01); 3015 pci_write_config_byte(dev, 0xe1, 0x32); 3016 pci_write_config_byte(dev, 0xfc, 0x00); 3017 3018 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3019 } 3020 3021 pci_read_config_byte(dev, 0xCB, &disable); 3022 3023 if (disable & 0x02) 3024 return; 3025 3026 pci_read_config_byte(dev, 0xCA, &write_enable); 3027 pci_write_config_byte(dev, 0xCA, 0x57); 3028 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3029 pci_write_config_byte(dev, 0xCA, write_enable); 3030 3031 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3032 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3033 3034 } 3035 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3036 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3037 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3038 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3039 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3040 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3041 #endif /*CONFIG_MMC_RICOH_MMC*/ 3042 3043 #ifdef CONFIG_DMAR_TABLE 3044 #define VTUNCERRMSK_REG 0x1ac 3045 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3046 /* 3047 * This is a quirk for masking VT-d spec-defined errors to platform error 3048 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3049 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3050 * on the RAS config settings of the platform) when a VT-d fault happens. 3051 * The resulting SMI caused the system to hang. 3052 * 3053 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3054 * need to report the same error through other channels. 3055 */ 3056 static void vtd_mask_spec_errors(struct pci_dev *dev) 3057 { 3058 u32 word; 3059 3060 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3061 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3062 } 3063 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3064 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3065 #endif 3066 3067 static void fixup_ti816x_class(struct pci_dev *dev) 3068 { 3069 u32 class = dev->class; 3070 3071 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3072 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3073 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3074 class, dev->class); 3075 } 3076 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3077 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3078 3079 /* 3080 * Some PCIe devices do not work reliably with the claimed maximum 3081 * payload size supported. 3082 */ 3083 static void fixup_mpss_256(struct pci_dev *dev) 3084 { 3085 dev->pcie_mpss = 1; /* 256 bytes */ 3086 } 3087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3088 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3090 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3092 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3093 3094 /* 3095 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3096 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3097 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3098 * until all of the devices are discovered and buses walked, read completion 3099 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3100 * it is possible to hotplug a device with MPS of 256B. 3101 */ 3102 static void quirk_intel_mc_errata(struct pci_dev *dev) 3103 { 3104 int err; 3105 u16 rcc; 3106 3107 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3108 pcie_bus_config == PCIE_BUS_DEFAULT) 3109 return; 3110 3111 /* 3112 * Intel erratum specifies bits to change but does not say what 3113 * they are. Keeping them magical until such time as the registers 3114 * and values can be explained. 3115 */ 3116 err = pci_read_config_word(dev, 0x48, &rcc); 3117 if (err) { 3118 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3119 return; 3120 } 3121 3122 if (!(rcc & (1 << 10))) 3123 return; 3124 3125 rcc &= ~(1 << 10); 3126 3127 err = pci_write_config_word(dev, 0x48, rcc); 3128 if (err) { 3129 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3130 return; 3131 } 3132 3133 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3134 } 3135 /* Intel 5000 series memory controllers and ports 2-7 */ 3136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3144 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3146 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3149 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3150 /* Intel 5100 series memory controllers and ports 2-7 */ 3151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3153 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3162 3163 /* 3164 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3165 * To work around this, query the size it should be configured to by the 3166 * device and modify the resource end to correspond to this new size. 3167 */ 3168 static void quirk_intel_ntb(struct pci_dev *dev) 3169 { 3170 int rc; 3171 u8 val; 3172 3173 rc = pci_read_config_byte(dev, 0x00D0, &val); 3174 if (rc) 3175 return; 3176 3177 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3178 3179 rc = pci_read_config_byte(dev, 0x00D1, &val); 3180 if (rc) 3181 return; 3182 3183 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3184 } 3185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3187 3188 /* 3189 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3190 * though no one is handling them (e.g., if the i915 driver is never 3191 * loaded). Additionally the interrupt destination is not set up properly 3192 * and the interrupt ends up -somewhere-. 3193 * 3194 * These spurious interrupts are "sticky" and the kernel disables the 3195 * (shared) interrupt line after 100,000+ generated interrupts. 3196 * 3197 * Fix it by disabling the still enabled interrupts. This resolves crashes 3198 * often seen on monitor unplug. 3199 */ 3200 #define I915_DEIER_REG 0x4400c 3201 static void disable_igfx_irq(struct pci_dev *dev) 3202 { 3203 void __iomem *regs = pci_iomap(dev, 0, 0); 3204 if (regs == NULL) { 3205 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3206 return; 3207 } 3208 3209 /* Check if any interrupt line is still enabled */ 3210 if (readl(regs + I915_DEIER_REG) != 0) { 3211 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3212 3213 writel(0, regs + I915_DEIER_REG); 3214 } 3215 3216 pci_iounmap(dev, regs); 3217 } 3218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3225 3226 /* 3227 * PCI devices which are on Intel chips can skip the 10ms delay 3228 * before entering D3 mode. 3229 */ 3230 static void quirk_remove_d3_delay(struct pci_dev *dev) 3231 { 3232 dev->d3_delay = 0; 3233 } 3234 /* C600 Series devices do not need 10ms d3_delay */ 3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3238 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */ 3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3250 /* Intel Cherrytrail devices do not need 10ms d3_delay */ 3251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); 3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); 3253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); 3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); 3255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); 3256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); 3257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); 3258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); 3259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); 3260 3261 /* 3262 * Some devices may pass our check in pci_intx_mask_supported() if 3263 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3264 * support this feature. 3265 */ 3266 static void quirk_broken_intx_masking(struct pci_dev *dev) 3267 { 3268 dev->broken_intx_masking = 1; 3269 } 3270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3271 quirk_broken_intx_masking); 3272 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3273 quirk_broken_intx_masking); 3274 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3275 quirk_broken_intx_masking); 3276 3277 /* 3278 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3279 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3280 * 3281 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3282 */ 3283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3284 quirk_broken_intx_masking); 3285 3286 /* 3287 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3288 * DisINTx can be set but the interrupt status bit is non-functional. 3289 */ 3290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3293 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3294 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3295 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3296 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3298 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3305 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3306 3307 static u16 mellanox_broken_intx_devs[] = { 3308 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3309 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3310 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3311 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3312 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3313 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3314 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3315 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3316 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3317 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3318 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3319 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3320 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3321 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3322 }; 3323 3324 #define CONNECTX_4_CURR_MAX_MINOR 99 3325 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3326 3327 /* 3328 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3329 * If so, don't mark it as broken. 3330 * FW minor > 99 means older FW version format and no INTx masking support. 3331 * FW minor < 14 means new FW version format and no INTx masking support. 3332 */ 3333 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3334 { 3335 __be32 __iomem *fw_ver; 3336 u16 fw_major; 3337 u16 fw_minor; 3338 u16 fw_subminor; 3339 u32 fw_maj_min; 3340 u32 fw_sub_min; 3341 int i; 3342 3343 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3344 if (pdev->device == mellanox_broken_intx_devs[i]) { 3345 pdev->broken_intx_masking = 1; 3346 return; 3347 } 3348 } 3349 3350 /* 3351 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3352 * support so shouldn't be checked further 3353 */ 3354 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3355 return; 3356 3357 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3358 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3359 return; 3360 3361 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3362 if (pci_enable_device_mem(pdev)) { 3363 pci_warn(pdev, "Can't enable device memory\n"); 3364 return; 3365 } 3366 3367 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3368 if (!fw_ver) { 3369 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3370 goto out; 3371 } 3372 3373 /* Reading from resource space should be 32b aligned */ 3374 fw_maj_min = ioread32be(fw_ver); 3375 fw_sub_min = ioread32be(fw_ver + 1); 3376 fw_major = fw_maj_min & 0xffff; 3377 fw_minor = fw_maj_min >> 16; 3378 fw_subminor = fw_sub_min & 0xffff; 3379 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3380 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3381 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3382 fw_major, fw_minor, fw_subminor, pdev->device == 3383 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3384 pdev->broken_intx_masking = 1; 3385 } 3386 3387 iounmap(fw_ver); 3388 3389 out: 3390 pci_disable_device(pdev); 3391 } 3392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3393 mellanox_check_broken_intx_masking); 3394 3395 static void quirk_no_bus_reset(struct pci_dev *dev) 3396 { 3397 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3398 } 3399 3400 /* 3401 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3402 * The device will throw a Link Down error on AER-capable systems and 3403 * regardless of AER, config space of the device is never accessible again 3404 * and typically causes the system to hang or reset when access is attempted. 3405 * http://www.spinics.net/lists/linux-pci/msg34797.html 3406 */ 3407 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3411 3412 /* 3413 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3414 * reset when used with certain child devices. After the reset, config 3415 * accesses to the child may fail. 3416 */ 3417 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3418 3419 static void quirk_no_pm_reset(struct pci_dev *dev) 3420 { 3421 /* 3422 * We can't do a bus reset on root bus devices, but an ineffective 3423 * PM reset may be better than nothing. 3424 */ 3425 if (!pci_is_root_bus(dev->bus)) 3426 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3427 } 3428 3429 /* 3430 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3431 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3432 * to have no effect on the device: it retains the framebuffer contents and 3433 * monitor sync. Advertising this support makes other layers, like VFIO, 3434 * assume pci_reset_function() is viable for this device. Mark it as 3435 * unavailable to skip it when testing reset methods. 3436 */ 3437 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3438 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3439 3440 /* 3441 * Thunderbolt controllers with broken MSI hotplug signaling: 3442 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3443 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3444 */ 3445 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3446 { 3447 if (pdev->is_hotplug_bridge && 3448 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3449 pdev->revision <= 1)) 3450 pdev->no_msi = 1; 3451 } 3452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3453 quirk_thunderbolt_hotplug_msi); 3454 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3455 quirk_thunderbolt_hotplug_msi); 3456 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3457 quirk_thunderbolt_hotplug_msi); 3458 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3459 quirk_thunderbolt_hotplug_msi); 3460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3461 quirk_thunderbolt_hotplug_msi); 3462 3463 #ifdef CONFIG_ACPI 3464 /* 3465 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3466 * 3467 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3468 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3469 * be present after resume if a device was plugged in before suspend. 3470 * 3471 * The Thunderbolt controller consists of a PCIe switch with downstream 3472 * bridges leading to the NHI and to the tunnel PCI bridges. 3473 * 3474 * This quirk cuts power to the whole chip. Therefore we have to apply it 3475 * during suspend_noirq of the upstream bridge. 3476 * 3477 * Power is automagically restored before resume. No action is needed. 3478 */ 3479 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3480 { 3481 acpi_handle bridge, SXIO, SXFP, SXLV; 3482 3483 if (!x86_apple_machine) 3484 return; 3485 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3486 return; 3487 bridge = ACPI_HANDLE(&dev->dev); 3488 if (!bridge) 3489 return; 3490 3491 /* 3492 * SXIO and SXLV are present only on machines requiring this quirk. 3493 * Thunderbolt bridges in external devices might have the same 3494 * device ID as those on the host, but they will not have the 3495 * associated ACPI methods. This implicitly checks that we are at 3496 * the right bridge. 3497 */ 3498 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3499 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3500 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3501 return; 3502 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3503 3504 /* magic sequence */ 3505 acpi_execute_simple_method(SXIO, NULL, 1); 3506 acpi_execute_simple_method(SXFP, NULL, 0); 3507 msleep(300); 3508 acpi_execute_simple_method(SXLV, NULL, 0); 3509 acpi_execute_simple_method(SXIO, NULL, 0); 3510 acpi_execute_simple_method(SXLV, NULL, 0); 3511 } 3512 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3513 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3514 quirk_apple_poweroff_thunderbolt); 3515 3516 /* 3517 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels 3518 * 3519 * During suspend the Thunderbolt controller is reset and all PCI 3520 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3521 * during resume. We have to manually wait for the NHI since there is 3522 * no parent child relationship between the NHI and the tunneled 3523 * bridges. 3524 */ 3525 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3526 { 3527 struct pci_dev *sibling = NULL; 3528 struct pci_dev *nhi = NULL; 3529 3530 if (!x86_apple_machine) 3531 return; 3532 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3533 return; 3534 3535 /* 3536 * Find the NHI and confirm that we are a bridge on the Thunderbolt 3537 * host controller and not on a Thunderbolt endpoint. 3538 */ 3539 sibling = pci_get_slot(dev->bus, 0x0); 3540 if (sibling == dev) 3541 goto out; /* we are the downstream bridge to the NHI */ 3542 if (!sibling || !sibling->subordinate) 3543 goto out; 3544 nhi = pci_get_slot(sibling->subordinate, 0x0); 3545 if (!nhi) 3546 goto out; 3547 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3548 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE && 3549 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C && 3550 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI && 3551 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) 3552 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) 3553 goto out; 3554 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n"); 3555 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3556 out: 3557 pci_dev_put(nhi); 3558 pci_dev_put(sibling); 3559 } 3560 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3561 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3562 quirk_apple_wait_for_thunderbolt); 3563 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3564 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3565 quirk_apple_wait_for_thunderbolt); 3566 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3567 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE, 3568 quirk_apple_wait_for_thunderbolt); 3569 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3570 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE, 3571 quirk_apple_wait_for_thunderbolt); 3572 #endif 3573 3574 /* 3575 * Following are device-specific reset methods which can be used to 3576 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3577 * not available. 3578 */ 3579 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3580 { 3581 /* 3582 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3583 * 3584 * The 82599 supports FLR on VFs, but FLR support is reported only 3585 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3586 * Thus we must call pcie_flr() directly without first checking if it is 3587 * supported. 3588 */ 3589 if (!probe) 3590 pcie_flr(dev); 3591 return 0; 3592 } 3593 3594 #define SOUTH_CHICKEN2 0xc2004 3595 #define PCH_PP_STATUS 0xc7200 3596 #define PCH_PP_CONTROL 0xc7204 3597 #define MSG_CTL 0x45010 3598 #define NSDE_PWR_STATE 0xd0100 3599 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3600 3601 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3602 { 3603 void __iomem *mmio_base; 3604 unsigned long timeout; 3605 u32 val; 3606 3607 if (probe) 3608 return 0; 3609 3610 mmio_base = pci_iomap(dev, 0, 0); 3611 if (!mmio_base) 3612 return -ENOMEM; 3613 3614 iowrite32(0x00000002, mmio_base + MSG_CTL); 3615 3616 /* 3617 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3618 * driver loaded sets the right bits. However, this's a reset and 3619 * the bits have been set by i915 previously, so we clobber 3620 * SOUTH_CHICKEN2 register directly here. 3621 */ 3622 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3623 3624 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3625 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3626 3627 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3628 do { 3629 val = ioread32(mmio_base + PCH_PP_STATUS); 3630 if ((val & 0xb0000000) == 0) 3631 goto reset_complete; 3632 msleep(10); 3633 } while (time_before(jiffies, timeout)); 3634 pci_warn(dev, "timeout during reset\n"); 3635 3636 reset_complete: 3637 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3638 3639 pci_iounmap(dev, mmio_base); 3640 return 0; 3641 } 3642 3643 /* Device-specific reset method for Chelsio T4-based adapters */ 3644 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3645 { 3646 u16 old_command; 3647 u16 msix_flags; 3648 3649 /* 3650 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3651 * that we have no device-specific reset method. 3652 */ 3653 if ((dev->device & 0xf000) != 0x4000) 3654 return -ENOTTY; 3655 3656 /* 3657 * If this is the "probe" phase, return 0 indicating that we can 3658 * reset this device. 3659 */ 3660 if (probe) 3661 return 0; 3662 3663 /* 3664 * T4 can wedge if there are DMAs in flight within the chip and Bus 3665 * Master has been disabled. We need to have it on till the Function 3666 * Level Reset completes. (BUS_MASTER is disabled in 3667 * pci_reset_function()). 3668 */ 3669 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3670 pci_write_config_word(dev, PCI_COMMAND, 3671 old_command | PCI_COMMAND_MASTER); 3672 3673 /* 3674 * Perform the actual device function reset, saving and restoring 3675 * configuration information around the reset. 3676 */ 3677 pci_save_state(dev); 3678 3679 /* 3680 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3681 * are disabled when an MSI-X interrupt message needs to be delivered. 3682 * So we briefly re-enable MSI-X interrupts for the duration of the 3683 * FLR. The pci_restore_state() below will restore the original 3684 * MSI-X state. 3685 */ 3686 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3687 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3688 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3689 msix_flags | 3690 PCI_MSIX_FLAGS_ENABLE | 3691 PCI_MSIX_FLAGS_MASKALL); 3692 3693 pcie_flr(dev); 3694 3695 /* 3696 * Restore the configuration information (BAR values, etc.) including 3697 * the original PCI Configuration Space Command word, and return 3698 * success. 3699 */ 3700 pci_restore_state(dev); 3701 pci_write_config_word(dev, PCI_COMMAND, old_command); 3702 return 0; 3703 } 3704 3705 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3706 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3707 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3708 3709 /* 3710 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 3711 * FLR where config space reads from the device return -1. We seem to be 3712 * able to avoid this condition if we disable the NVMe controller prior to 3713 * FLR. This quirk is generic for any NVMe class device requiring similar 3714 * assistance to quiesce the device prior to FLR. 3715 * 3716 * NVMe specification: https://nvmexpress.org/resources/specifications/ 3717 * Revision 1.0e: 3718 * Chapter 2: Required and optional PCI config registers 3719 * Chapter 3: NVMe control registers 3720 * Chapter 7.3: Reset behavior 3721 */ 3722 static int nvme_disable_and_flr(struct pci_dev *dev, int probe) 3723 { 3724 void __iomem *bar; 3725 u16 cmd; 3726 u32 cfg; 3727 3728 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 3729 !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) 3730 return -ENOTTY; 3731 3732 if (probe) 3733 return 0; 3734 3735 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 3736 if (!bar) 3737 return -ENOTTY; 3738 3739 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3740 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 3741 3742 cfg = readl(bar + NVME_REG_CC); 3743 3744 /* Disable controller if enabled */ 3745 if (cfg & NVME_CC_ENABLE) { 3746 u32 cap = readl(bar + NVME_REG_CAP); 3747 unsigned long timeout; 3748 3749 /* 3750 * Per nvme_disable_ctrl() skip shutdown notification as it 3751 * could complete commands to the admin queue. We only intend 3752 * to quiesce the device before reset. 3753 */ 3754 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 3755 3756 writel(cfg, bar + NVME_REG_CC); 3757 3758 /* 3759 * Some controllers require an additional delay here, see 3760 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 3761 * supported by this quirk. 3762 */ 3763 3764 /* Cap register provides max timeout in 500ms increments */ 3765 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 3766 3767 for (;;) { 3768 u32 status = readl(bar + NVME_REG_CSTS); 3769 3770 /* Ready status becomes zero on disable complete */ 3771 if (!(status & NVME_CSTS_RDY)) 3772 break; 3773 3774 msleep(100); 3775 3776 if (time_after(jiffies, timeout)) { 3777 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 3778 break; 3779 } 3780 } 3781 } 3782 3783 pci_iounmap(dev, bar); 3784 3785 pcie_flr(dev); 3786 3787 return 0; 3788 } 3789 3790 /* 3791 * Intel DC P3700 NVMe controller will timeout waiting for ready status 3792 * to change after NVMe enable if the driver starts interacting with the 3793 * device too soon after FLR. A 250ms delay after FLR has heuristically 3794 * proven to produce reliably working results for device assignment cases. 3795 */ 3796 static int delay_250ms_after_flr(struct pci_dev *dev, int probe) 3797 { 3798 if (!pcie_has_flr(dev)) 3799 return -ENOTTY; 3800 3801 if (probe) 3802 return 0; 3803 3804 pcie_flr(dev); 3805 3806 msleep(250); 3807 3808 return 0; 3809 } 3810 3811 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3812 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3813 reset_intel_82599_sfp_virtfn }, 3814 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3815 reset_ivb_igd }, 3816 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3817 reset_ivb_igd }, 3818 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 3819 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 3820 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3821 reset_chelsio_generic_dev }, 3822 { 0 } 3823 }; 3824 3825 /* 3826 * These device-specific reset methods are here rather than in a driver 3827 * because when a host assigns a device to a guest VM, the host may need 3828 * to reset the device but probably doesn't have a driver for it. 3829 */ 3830 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3831 { 3832 const struct pci_dev_reset_methods *i; 3833 3834 for (i = pci_dev_reset_methods; i->reset; i++) { 3835 if ((i->vendor == dev->vendor || 3836 i->vendor == (u16)PCI_ANY_ID) && 3837 (i->device == dev->device || 3838 i->device == (u16)PCI_ANY_ID)) 3839 return i->reset(dev, probe); 3840 } 3841 3842 return -ENOTTY; 3843 } 3844 3845 static void quirk_dma_func0_alias(struct pci_dev *dev) 3846 { 3847 if (PCI_FUNC(dev->devfn) != 0) 3848 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 3849 } 3850 3851 /* 3852 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3853 * 3854 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3855 */ 3856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3858 3859 static void quirk_dma_func1_alias(struct pci_dev *dev) 3860 { 3861 if (PCI_FUNC(dev->devfn) != 1) 3862 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1)); 3863 } 3864 3865 /* 3866 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3867 * SKUs function 1 is present and is a legacy IDE controller, in other 3868 * SKUs this function is not present, making this a ghost requester. 3869 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3870 */ 3871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 3872 quirk_dma_func1_alias); 3873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3874 quirk_dma_func1_alias); 3875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 3876 quirk_dma_func1_alias); 3877 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3879 quirk_dma_func1_alias); 3880 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3882 quirk_dma_func1_alias); 3883 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3885 quirk_dma_func1_alias); 3886 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 3887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 3888 quirk_dma_func1_alias); 3889 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 3890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 3891 quirk_dma_func1_alias); 3892 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3894 quirk_dma_func1_alias); 3895 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 3896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 3897 quirk_dma_func1_alias); 3898 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3900 quirk_dma_func1_alias); 3901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3902 quirk_dma_func1_alias); 3903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 3904 quirk_dma_func1_alias); 3905 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3907 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3908 quirk_dma_func1_alias); 3909 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 3910 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 3911 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 3912 quirk_dma_func1_alias); 3913 3914 /* 3915 * Some devices DMA with the wrong devfn, not just the wrong function. 3916 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3917 * the alias is "fixed" and independent of the device devfn. 3918 * 3919 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3920 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3921 * single device on the secondary bus. In reality, the single exposed 3922 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3923 * that provides a bridge to the internal bus of the I/O processor. The 3924 * controller supports private devices, which can be hidden from PCI config 3925 * space. In the case of the Adaptec 3405, a private device at 01.0 3926 * appears to be the DMA engine, which therefore needs to become a DMA 3927 * alias for the device. 3928 */ 3929 static const struct pci_device_id fixed_dma_alias_tbl[] = { 3930 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3931 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3932 .driver_data = PCI_DEVFN(1, 0) }, 3933 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3934 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 3935 .driver_data = PCI_DEVFN(1, 0) }, 3936 { 0 } 3937 }; 3938 3939 static void quirk_fixed_dma_alias(struct pci_dev *dev) 3940 { 3941 const struct pci_device_id *id; 3942 3943 id = pci_match_id(fixed_dma_alias_tbl, dev); 3944 if (id) 3945 pci_add_dma_alias(dev, id->driver_data); 3946 } 3947 3948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3949 3950 /* 3951 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3952 * using the wrong DMA alias for the device. Some of these devices can be 3953 * used as either forward or reverse bridges, so we need to test whether the 3954 * device is operating in the correct mode. We could probably apply this 3955 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3956 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3957 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3958 */ 3959 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3960 { 3961 if (!pci_is_root_bus(pdev->bus) && 3962 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3963 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3964 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3965 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3966 } 3967 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3968 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3969 quirk_use_pcie_bridge_dma_alias); 3970 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3971 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3972 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3973 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3974 /* ITE 8893 has the same problem as the 8892 */ 3975 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 3976 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3977 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3978 3979 /* 3980 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 3981 * be added as aliases to the DMA device in order to allow buffer access 3982 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 3983 * programmed in the EEPROM. 3984 */ 3985 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 3986 { 3987 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0)); 3988 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0)); 3989 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3)); 3990 } 3991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 3992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 3993 3994 /* 3995 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 3996 * associated not at the root bus, but at a bridge below. This quirk avoids 3997 * generating invalid DMA aliases. 3998 */ 3999 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4000 { 4001 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4002 } 4003 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4004 quirk_bridge_cavm_thrx2_pcie_root); 4005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4006 quirk_bridge_cavm_thrx2_pcie_root); 4007 4008 /* 4009 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4010 * class code. Fix it. 4011 */ 4012 static void quirk_tw686x_class(struct pci_dev *pdev) 4013 { 4014 u32 class = pdev->class; 4015 4016 /* Use "Multimedia controller" class */ 4017 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4018 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4019 class, pdev->class); 4020 } 4021 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4022 quirk_tw686x_class); 4023 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4024 quirk_tw686x_class); 4025 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4026 quirk_tw686x_class); 4027 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4028 quirk_tw686x_class); 4029 4030 /* 4031 * Some devices have problems with Transaction Layer Packets with the Relaxed 4032 * Ordering Attribute set. Such devices should mark themselves and other 4033 * device drivers should check before sending TLPs with RO set. 4034 */ 4035 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4036 { 4037 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4038 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4039 } 4040 4041 /* 4042 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4043 * Complex have a Flow Control Credit issue which can cause performance 4044 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4045 */ 4046 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4047 quirk_relaxedordering_disable); 4048 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4049 quirk_relaxedordering_disable); 4050 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4051 quirk_relaxedordering_disable); 4052 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4053 quirk_relaxedordering_disable); 4054 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4055 quirk_relaxedordering_disable); 4056 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4057 quirk_relaxedordering_disable); 4058 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4059 quirk_relaxedordering_disable); 4060 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4061 quirk_relaxedordering_disable); 4062 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4063 quirk_relaxedordering_disable); 4064 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4065 quirk_relaxedordering_disable); 4066 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4067 quirk_relaxedordering_disable); 4068 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4069 quirk_relaxedordering_disable); 4070 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4071 quirk_relaxedordering_disable); 4072 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4073 quirk_relaxedordering_disable); 4074 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4075 quirk_relaxedordering_disable); 4076 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4077 quirk_relaxedordering_disable); 4078 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4079 quirk_relaxedordering_disable); 4080 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4081 quirk_relaxedordering_disable); 4082 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4083 quirk_relaxedordering_disable); 4084 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4085 quirk_relaxedordering_disable); 4086 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4087 quirk_relaxedordering_disable); 4088 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4089 quirk_relaxedordering_disable); 4090 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4091 quirk_relaxedordering_disable); 4092 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4093 quirk_relaxedordering_disable); 4094 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4095 quirk_relaxedordering_disable); 4096 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4097 quirk_relaxedordering_disable); 4098 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4099 quirk_relaxedordering_disable); 4100 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4101 quirk_relaxedordering_disable); 4102 4103 /* 4104 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4105 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4106 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4107 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4108 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4109 * November 10, 2010). As a result, on this platform we can't use Relaxed 4110 * Ordering for Upstream TLPs. 4111 */ 4112 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4113 quirk_relaxedordering_disable); 4114 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4115 quirk_relaxedordering_disable); 4116 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4117 quirk_relaxedordering_disable); 4118 4119 /* 4120 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4121 * values for the Attribute as were supplied in the header of the 4122 * corresponding Request, except as explicitly allowed when IDO is used." 4123 * 4124 * If a non-compliant device generates a completion with a different 4125 * attribute than the request, the receiver may accept it (which itself 4126 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4127 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4128 * device access timeout. 4129 * 4130 * If the non-compliant device generates completions with zero attributes 4131 * (instead of copying the attributes from the request), we can work around 4132 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4133 * upstream devices so they always generate requests with zero attributes. 4134 * 4135 * This affects other devices under the same Root Port, but since these 4136 * attributes are performance hints, there should be no functional problem. 4137 * 4138 * Note that Configuration Space accesses are never supposed to have TLP 4139 * Attributes, so we're safe waiting till after any Configuration Space 4140 * accesses to do the Root Port fixup. 4141 */ 4142 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4143 { 4144 struct pci_dev *root_port = pci_find_pcie_root_port(pdev); 4145 4146 if (!root_port) { 4147 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4148 return; 4149 } 4150 4151 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4152 dev_name(&pdev->dev)); 4153 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4154 PCI_EXP_DEVCTL_RELAX_EN | 4155 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4156 } 4157 4158 /* 4159 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4160 * Completion it generates. 4161 */ 4162 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4163 { 4164 /* 4165 * This mask/compare operation selects for Physical Function 4 on a 4166 * T5. We only need to fix up the Root Port once for any of the 4167 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4168 * 0x54xx so we use that one. 4169 */ 4170 if ((pdev->device & 0xff00) == 0x5400) 4171 quirk_disable_root_port_attributes(pdev); 4172 } 4173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4174 quirk_chelsio_T5_disable_root_port_attributes); 4175 4176 /* 4177 * AMD has indicated that the devices below do not support peer-to-peer 4178 * in any system where they are found in the southbridge with an AMD 4179 * IOMMU in the system. Multifunction devices that do not support 4180 * peer-to-peer between functions can claim to support a subset of ACS. 4181 * Such devices effectively enable request redirect (RR) and completion 4182 * redirect (CR) since all transactions are redirected to the upstream 4183 * root complex. 4184 * 4185 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 4186 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 4187 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 4188 * 4189 * 1002:4385 SBx00 SMBus Controller 4190 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4191 * 1002:4383 SBx00 Azalia (Intel HDA) 4192 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4193 * 1002:4384 SBx00 PCI to PCI Bridge 4194 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4195 * 4196 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4197 * 4198 * 1022:780f [AMD] FCH PCI Bridge 4199 * 1022:7809 [AMD] FCH USB OHCI Controller 4200 */ 4201 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4202 { 4203 #ifdef CONFIG_ACPI 4204 struct acpi_table_header *header = NULL; 4205 acpi_status status; 4206 4207 /* Targeting multifunction devices on the SB (appears on root bus) */ 4208 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4209 return -ENODEV; 4210 4211 /* The IVRS table describes the AMD IOMMU */ 4212 status = acpi_get_table("IVRS", 0, &header); 4213 if (ACPI_FAILURE(status)) 4214 return -ENODEV; 4215 4216 /* Filter out flags not applicable to multifunction */ 4217 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4218 4219 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 4220 #else 4221 return -ENODEV; 4222 #endif 4223 } 4224 4225 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4226 { 4227 /* 4228 * Effectively selects all downstream ports for whole ThunderX 1 4229 * family by 0xf800 mask (which represents 8 SoCs), while the lower 4230 * bits of device ID are used to indicate which subdevice is used 4231 * within the SoC. 4232 */ 4233 return (pci_is_pcie(dev) && 4234 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) && 4235 ((dev->device & 0xf800) == 0xa000)); 4236 } 4237 4238 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4239 { 4240 /* 4241 * Cavium root ports don't advertise an ACS capability. However, 4242 * the RTL internally implements similar protection as if ACS had 4243 * Request Redirection, Completion Redirection, Source Validation, 4244 * and Upstream Forwarding features enabled. Assert that the 4245 * hardware implements and enables equivalent ACS functionality for 4246 * these flags. 4247 */ 4248 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF); 4249 4250 if (!pci_quirk_cavium_acs_match(dev)) 4251 return -ENOTTY; 4252 4253 return acs_flags ? 0 : 1; 4254 } 4255 4256 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4257 { 4258 /* 4259 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4260 * transactions with others, allowing masking out these bits as if they 4261 * were unimplemented in the ACS capability. 4262 */ 4263 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4264 4265 return acs_flags ? 0 : 1; 4266 } 4267 4268 /* 4269 * Many Intel PCH root ports do provide ACS-like features to disable peer 4270 * transactions and validate bus numbers in requests, but do not provide an 4271 * actual PCIe ACS capability. This is the list of device IDs known to fall 4272 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4273 */ 4274 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4275 /* Ibexpeak PCH */ 4276 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4277 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4278 /* Cougarpoint PCH */ 4279 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4280 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4281 /* Pantherpoint PCH */ 4282 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4283 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4284 /* Lynxpoint-H PCH */ 4285 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4286 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4287 /* Lynxpoint-LP PCH */ 4288 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4289 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4290 /* Wildcat PCH */ 4291 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4292 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4293 /* Patsburg (X79) PCH */ 4294 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4295 /* Wellsburg (X99) PCH */ 4296 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4297 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4298 /* Lynx Point (9 series) PCH */ 4299 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4300 }; 4301 4302 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4303 { 4304 int i; 4305 4306 /* Filter out a few obvious non-matches first */ 4307 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4308 return false; 4309 4310 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4311 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4312 return true; 4313 4314 return false; 4315 } 4316 4317 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 4318 4319 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4320 { 4321 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 4322 INTEL_PCH_ACS_FLAGS : 0; 4323 4324 if (!pci_quirk_intel_pch_acs_match(dev)) 4325 return -ENOTTY; 4326 4327 return acs_flags & ~flags ? 0 : 1; 4328 } 4329 4330 /* 4331 * These QCOM root ports do provide ACS-like features to disable peer 4332 * transactions and validate bus numbers in requests, but do not provide an 4333 * actual PCIe ACS capability. Hardware supports source validation but it 4334 * will report the issue as Completer Abort instead of ACS Violation. 4335 * Hardware doesn't support peer-to-peer and each root port is a root 4336 * complex with unique segment numbers. It is not possible for one root 4337 * port to pass traffic to another root port. All PCIe transactions are 4338 * terminated inside the root port. 4339 */ 4340 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4341 { 4342 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); 4343 int ret = acs_flags & ~flags ? 0 : 1; 4344 4345 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret); 4346 4347 return ret; 4348 } 4349 4350 /* 4351 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4352 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4353 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4354 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4355 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4356 * control register is at offset 8 instead of 6 and we should probably use 4357 * dword accesses to them. This applies to the following PCI Device IDs, as 4358 * found in volume 1 of the datasheet[2]: 4359 * 4360 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4361 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4362 * 4363 * N.B. This doesn't fix what lspci shows. 4364 * 4365 * The 100 series chipset specification update includes this as errata #23[3]. 4366 * 4367 * The 200 series chipset (Union Point) has the same bug according to the 4368 * specification update (Intel 200 Series Chipset Family Platform Controller 4369 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4370 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4371 * chipset include: 4372 * 4373 * 0xa290-0xa29f PCI Express Root port #{0-16} 4374 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4375 * 4376 * Mobile chipsets are also affected, 7th & 8th Generation 4377 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4378 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4379 * Processor Family I/O for U Quad Core Platforms Specification Update, 4380 * August 2017, Revision 002, Document#: 334660-002)[6] 4381 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4382 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4383 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4384 * 4385 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4386 * 4387 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4388 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4389 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4390 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4391 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4392 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4393 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4394 */ 4395 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4396 { 4397 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4398 return false; 4399 4400 switch (dev->device) { 4401 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4402 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4403 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4404 return true; 4405 } 4406 4407 return false; 4408 } 4409 4410 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4411 4412 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4413 { 4414 int pos; 4415 u32 cap, ctrl; 4416 4417 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4418 return -ENOTTY; 4419 4420 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4421 if (!pos) 4422 return -ENOTTY; 4423 4424 /* see pci_acs_flags_enabled() */ 4425 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4426 acs_flags &= (cap | PCI_ACS_EC); 4427 4428 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4429 4430 return acs_flags & ~ctrl ? 0 : 1; 4431 } 4432 4433 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4434 { 4435 /* 4436 * SV, TB, and UF are not relevant to multifunction endpoints. 4437 * 4438 * Multifunction devices are only required to implement RR, CR, and DT 4439 * in their ACS capability if they support peer-to-peer transactions. 4440 * Devices matching this quirk have been verified by the vendor to not 4441 * perform peer-to-peer with other functions, allowing us to mask out 4442 * these bits as if they were unimplemented in the ACS capability. 4443 */ 4444 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4445 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4446 4447 return acs_flags ? 0 : 1; 4448 } 4449 4450 static const struct pci_dev_acs_enabled { 4451 u16 vendor; 4452 u16 device; 4453 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4454 } pci_dev_acs_enabled[] = { 4455 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4456 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4457 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4458 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4459 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4460 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4461 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4462 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4463 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4464 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4465 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4466 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4467 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4468 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4469 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4470 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4471 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4472 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4473 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4474 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4475 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4476 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4477 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4478 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4479 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4480 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4481 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 4482 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 4483 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 4484 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 4485 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 4486 /* 82580 */ 4487 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 4488 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 4489 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 4490 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 4491 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 4492 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 4493 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 4494 /* 82576 */ 4495 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 4496 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 4497 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 4498 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 4499 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 4500 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 4501 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 4502 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 4503 /* 82575 */ 4504 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 4505 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 4506 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 4507 /* I350 */ 4508 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 4509 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 4510 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 4511 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 4512 /* 82571 (Quads omitted due to non-ACS switch) */ 4513 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 4514 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 4515 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 4516 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 4517 /* I219 */ 4518 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 4519 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 4520 /* QCOM QDF2xxx root ports */ 4521 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 4522 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 4523 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 4524 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 4525 /* Intel PCH root ports */ 4526 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 4527 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 4528 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 4529 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 4530 /* Cavium ThunderX */ 4531 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 4532 /* APM X-Gene */ 4533 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 4534 /* Ampere Computing */ 4535 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 4536 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 4537 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 4538 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 4539 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 4540 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 4541 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 4542 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 4543 { 0 } 4544 }; 4545 4546 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 4547 { 4548 const struct pci_dev_acs_enabled *i; 4549 int ret; 4550 4551 /* 4552 * Allow devices that do not expose standard PCIe ACS capabilities 4553 * or control to indicate their support here. Multi-function express 4554 * devices which do not allow internal peer-to-peer between functions, 4555 * but do not implement PCIe ACS may wish to return true here. 4556 */ 4557 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 4558 if ((i->vendor == dev->vendor || 4559 i->vendor == (u16)PCI_ANY_ID) && 4560 (i->device == dev->device || 4561 i->device == (u16)PCI_ANY_ID)) { 4562 ret = i->acs_enabled(dev, acs_flags); 4563 if (ret >= 0) 4564 return ret; 4565 } 4566 } 4567 4568 return -ENOTTY; 4569 } 4570 4571 /* Config space offset of Root Complex Base Address register */ 4572 #define INTEL_LPC_RCBA_REG 0xf0 4573 /* 31:14 RCBA address */ 4574 #define INTEL_LPC_RCBA_MASK 0xffffc000 4575 /* RCBA Enable */ 4576 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 4577 4578 /* Backbone Scratch Pad Register */ 4579 #define INTEL_BSPR_REG 0x1104 4580 /* Backbone Peer Non-Posted Disable */ 4581 #define INTEL_BSPR_REG_BPNPD (1 << 8) 4582 /* Backbone Peer Posted Disable */ 4583 #define INTEL_BSPR_REG_BPPD (1 << 9) 4584 4585 /* Upstream Peer Decode Configuration Register */ 4586 #define INTEL_UPDCR_REG 0x1114 4587 /* 5:0 Peer Decode Enable bits */ 4588 #define INTEL_UPDCR_REG_MASK 0x3f 4589 4590 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 4591 { 4592 u32 rcba, bspr, updcr; 4593 void __iomem *rcba_mem; 4594 4595 /* 4596 * Read the RCBA register from the LPC (D31:F0). PCH root ports 4597 * are D28:F* and therefore get probed before LPC, thus we can't 4598 * use pci_get_slot()/pci_read_config_dword() here. 4599 */ 4600 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 4601 INTEL_LPC_RCBA_REG, &rcba); 4602 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 4603 return -EINVAL; 4604 4605 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 4606 PAGE_ALIGN(INTEL_UPDCR_REG)); 4607 if (!rcba_mem) 4608 return -ENOMEM; 4609 4610 /* 4611 * The BSPR can disallow peer cycles, but it's set by soft strap and 4612 * therefore read-only. If both posted and non-posted peer cycles are 4613 * disallowed, we're ok. If either are allowed, then we need to use 4614 * the UPDCR to disable peer decodes for each port. This provides the 4615 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 4616 */ 4617 bspr = readl(rcba_mem + INTEL_BSPR_REG); 4618 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 4619 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 4620 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 4621 if (updcr & INTEL_UPDCR_REG_MASK) { 4622 pci_info(dev, "Disabling UPDCR peer decodes\n"); 4623 updcr &= ~INTEL_UPDCR_REG_MASK; 4624 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 4625 } 4626 } 4627 4628 iounmap(rcba_mem); 4629 return 0; 4630 } 4631 4632 /* Miscellaneous Port Configuration register */ 4633 #define INTEL_MPC_REG 0xd8 4634 /* MPC: Invalid Receive Bus Number Check Enable */ 4635 #define INTEL_MPC_REG_IRBNCE (1 << 26) 4636 4637 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 4638 { 4639 u32 mpc; 4640 4641 /* 4642 * When enabled, the IRBNCE bit of the MPC register enables the 4643 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 4644 * ensures that requester IDs fall within the bus number range 4645 * of the bridge. Enable if not already. 4646 */ 4647 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4648 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4649 pci_info(dev, "Enabling MPC IRBNCE\n"); 4650 mpc |= INTEL_MPC_REG_IRBNCE; 4651 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4652 } 4653 } 4654 4655 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 4656 { 4657 if (!pci_quirk_intel_pch_acs_match(dev)) 4658 return -ENOTTY; 4659 4660 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4661 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 4662 return 0; 4663 } 4664 4665 pci_quirk_enable_intel_rp_mpc_acs(dev); 4666 4667 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4668 4669 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 4670 4671 return 0; 4672 } 4673 4674 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 4675 { 4676 int pos; 4677 u32 cap, ctrl; 4678 4679 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4680 return -ENOTTY; 4681 4682 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4683 if (!pos) 4684 return -ENOTTY; 4685 4686 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4687 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4688 4689 ctrl |= (cap & PCI_ACS_SV); 4690 ctrl |= (cap & PCI_ACS_RR); 4691 ctrl |= (cap & PCI_ACS_CR); 4692 ctrl |= (cap & PCI_ACS_UF); 4693 4694 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4695 4696 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 4697 4698 return 0; 4699 } 4700 4701 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 4702 { 4703 int pos; 4704 u32 cap, ctrl; 4705 4706 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4707 return -ENOTTY; 4708 4709 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4710 if (!pos) 4711 return -ENOTTY; 4712 4713 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4714 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4715 4716 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 4717 4718 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4719 4720 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 4721 4722 return 0; 4723 } 4724 4725 static const struct pci_dev_acs_ops { 4726 u16 vendor; 4727 u16 device; 4728 int (*enable_acs)(struct pci_dev *dev); 4729 int (*disable_acs_redir)(struct pci_dev *dev); 4730 } pci_dev_acs_ops[] = { 4731 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 4732 .enable_acs = pci_quirk_enable_intel_pch_acs, 4733 }, 4734 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 4735 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 4736 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 4737 }, 4738 }; 4739 4740 int pci_dev_specific_enable_acs(struct pci_dev *dev) 4741 { 4742 const struct pci_dev_acs_ops *p; 4743 int i, ret; 4744 4745 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 4746 p = &pci_dev_acs_ops[i]; 4747 if ((p->vendor == dev->vendor || 4748 p->vendor == (u16)PCI_ANY_ID) && 4749 (p->device == dev->device || 4750 p->device == (u16)PCI_ANY_ID) && 4751 p->enable_acs) { 4752 ret = p->enable_acs(dev); 4753 if (ret >= 0) 4754 return ret; 4755 } 4756 } 4757 4758 return -ENOTTY; 4759 } 4760 4761 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 4762 { 4763 const struct pci_dev_acs_ops *p; 4764 int i, ret; 4765 4766 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 4767 p = &pci_dev_acs_ops[i]; 4768 if ((p->vendor == dev->vendor || 4769 p->vendor == (u16)PCI_ANY_ID) && 4770 (p->device == dev->device || 4771 p->device == (u16)PCI_ANY_ID) && 4772 p->disable_acs_redir) { 4773 ret = p->disable_acs_redir(dev); 4774 if (ret >= 0) 4775 return ret; 4776 } 4777 } 4778 4779 return -ENOTTY; 4780 } 4781 4782 /* 4783 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 4784 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 4785 * Next Capability pointer in the MSI Capability Structure should point to 4786 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 4787 * the list. 4788 */ 4789 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 4790 { 4791 int pos, i = 0; 4792 u8 next_cap; 4793 u16 reg16, *cap; 4794 struct pci_cap_saved_state *state; 4795 4796 /* Bail if the hardware bug is fixed */ 4797 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 4798 return; 4799 4800 /* Bail if MSI Capability Structure is not found for some reason */ 4801 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 4802 if (!pos) 4803 return; 4804 4805 /* 4806 * Bail if Next Capability pointer in the MSI Capability Structure 4807 * is not the expected incorrect 0x00. 4808 */ 4809 pci_read_config_byte(pdev, pos + 1, &next_cap); 4810 if (next_cap) 4811 return; 4812 4813 /* 4814 * PCIe Capability Structure is expected to be at 0x50 and should 4815 * terminate the list (Next Capability pointer is 0x00). Verify 4816 * Capability Id and Next Capability pointer is as expected. 4817 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 4818 * to correctly set kernel data structures which have already been 4819 * set incorrectly due to the hardware bug. 4820 */ 4821 pos = 0x50; 4822 pci_read_config_word(pdev, pos, ®16); 4823 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 4824 u32 status; 4825 #ifndef PCI_EXP_SAVE_REGS 4826 #define PCI_EXP_SAVE_REGS 7 4827 #endif 4828 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 4829 4830 pdev->pcie_cap = pos; 4831 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 4832 pdev->pcie_flags_reg = reg16; 4833 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 4834 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 4835 4836 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4837 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 4838 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 4839 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 4840 4841 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 4842 return; 4843 4844 /* Save PCIe cap */ 4845 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 4846 if (!state) 4847 return; 4848 4849 state->cap.cap_nr = PCI_CAP_ID_EXP; 4850 state->cap.cap_extended = 0; 4851 state->cap.size = size; 4852 cap = (u16 *)&state->cap.data[0]; 4853 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 4854 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 4855 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 4856 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 4857 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 4858 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 4859 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 4860 hlist_add_head(&state->next, &pdev->saved_cap_space); 4861 } 4862 } 4863 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 4864 4865 /* FLR may cause some 82579 devices to hang */ 4866 static void quirk_intel_no_flr(struct pci_dev *dev) 4867 { 4868 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 4869 } 4870 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); 4871 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); 4872 4873 static void quirk_no_ext_tags(struct pci_dev *pdev) 4874 { 4875 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 4876 4877 if (!bridge) 4878 return; 4879 4880 bridge->no_ext_tags = 1; 4881 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 4882 4883 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 4884 } 4885 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 4886 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 4887 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 4888 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 4889 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 4890 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 4891 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 4892 4893 #ifdef CONFIG_PCI_ATS 4894 /* 4895 * Some devices have a broken ATS implementation causing IOMMU stalls. 4896 * Don't use ATS for those devices. 4897 */ 4898 static void quirk_no_ats(struct pci_dev *pdev) 4899 { 4900 pci_info(pdev, "disabling ATS (broken on this device)\n"); 4901 pdev->ats_cap = 0; 4902 } 4903 4904 /* AMD Stoney platform GPU */ 4905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); 4906 #endif /* CONFIG_PCI_ATS */ 4907 4908 /* Freescale PCIe doesn't support MSI in RC mode */ 4909 static void quirk_fsl_no_msi(struct pci_dev *pdev) 4910 { 4911 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 4912 pdev->no_msi = 1; 4913 } 4914 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 4915 4916 /* 4917 * GPUs with integrated HDA controller for streaming audio to attached displays 4918 * need a device link from the HDA controller (consumer) to the GPU (supplier) 4919 * so that the GPU is powered up whenever the HDA controller is accessed. 4920 * The GPU and HDA controller are functions 0 and 1 of the same PCI device. 4921 * The device link stays in place until shutdown (or removal of the PCI device 4922 * if it's hotplugged). Runtime PM is allowed by default on the HDA controller 4923 * to prevent it from permanently keeping the GPU awake. 4924 */ 4925 static void quirk_gpu_hda(struct pci_dev *hda) 4926 { 4927 struct pci_dev *gpu; 4928 4929 if (PCI_FUNC(hda->devfn) != 1) 4930 return; 4931 4932 gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus), 4933 hda->bus->number, 4934 PCI_DEVFN(PCI_SLOT(hda->devfn), 0)); 4935 if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) { 4936 pci_dev_put(gpu); 4937 return; 4938 } 4939 4940 if (!device_link_add(&hda->dev, &gpu->dev, 4941 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 4942 pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu)); 4943 4944 pm_runtime_allow(&hda->dev); 4945 pci_dev_put(gpu); 4946 } 4947 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 4948 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4949 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 4950 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4951 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 4952 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4953 4954 /* 4955 * Some IDT switches incorrectly flag an ACS Source Validation error on 4956 * completions for config read requests even though PCIe r4.0, sec 4957 * 6.12.1.1, says that completions are never affected by ACS Source 4958 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 4959 * 4960 * Item #36 - Downstream port applies ACS Source Validation to Completions 4961 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 4962 * completions are never affected by ACS Source Validation. However, 4963 * completions received by a downstream port of the PCIe switch from a 4964 * device that has not yet captured a PCIe bus number are incorrectly 4965 * dropped by ACS Source Validation by the switch downstream port. 4966 * 4967 * The workaround suggested by IDT is to issue a config write to the 4968 * downstream device before issuing the first config read. This allows the 4969 * downstream device to capture its bus and device numbers (see PCIe r4.0, 4970 * sec 2.2.9), thus avoiding the ACS error on the completion. 4971 * 4972 * However, we don't know when the device is ready to accept the config 4973 * write, so we do config reads until we receive a non-Config Request Retry 4974 * Status, then do the config write. 4975 * 4976 * To avoid hitting the erratum when doing the config reads, we disable ACS 4977 * SV around this process. 4978 */ 4979 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 4980 { 4981 int pos; 4982 u16 ctrl = 0; 4983 bool found; 4984 struct pci_dev *bridge = bus->self; 4985 4986 pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS); 4987 4988 /* Disable ACS SV before initial config reads */ 4989 if (pos) { 4990 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 4991 if (ctrl & PCI_ACS_SV) 4992 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 4993 ctrl & ~PCI_ACS_SV); 4994 } 4995 4996 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 4997 4998 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 4999 if (found) 5000 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5001 5002 /* Re-enable ACS_SV if it was previously enabled */ 5003 if (ctrl & PCI_ACS_SV) 5004 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5005 5006 return found; 5007 } 5008 5009 /* 5010 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5011 * NT endpoints via the internal switch fabric. These IDs replace the 5012 * originating requestor ID TLPs which access host memory on peer NTB 5013 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5014 * to permit access when the IOMMU is turned on. 5015 */ 5016 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5017 { 5018 void __iomem *mmio; 5019 struct ntb_info_regs __iomem *mmio_ntb; 5020 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5021 u64 partition_map; 5022 u8 partition; 5023 int pp; 5024 5025 if (pci_enable_device(pdev)) { 5026 pci_err(pdev, "Cannot enable Switchtec device\n"); 5027 return; 5028 } 5029 5030 mmio = pci_iomap(pdev, 0, 0); 5031 if (mmio == NULL) { 5032 pci_disable_device(pdev); 5033 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5034 return; 5035 } 5036 5037 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5038 5039 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5040 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5041 5042 partition = ioread8(&mmio_ntb->partition_id); 5043 5044 partition_map = ioread32(&mmio_ntb->ep_map); 5045 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5046 partition_map &= ~(1ULL << partition); 5047 5048 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5049 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5050 u32 table_sz = 0; 5051 int te; 5052 5053 if (!(partition_map & (1ULL << pp))) 5054 continue; 5055 5056 pci_dbg(pdev, "Processing partition %d\n", pp); 5057 5058 mmio_peer_ctrl = &mmio_ctrl[pp]; 5059 5060 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5061 if (!table_sz) { 5062 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5063 continue; 5064 } 5065 5066 if (table_sz > 512) { 5067 pci_warn(pdev, 5068 "Invalid Switchtec partition %d table_sz %d\n", 5069 pp, table_sz); 5070 continue; 5071 } 5072 5073 for (te = 0; te < table_sz; te++) { 5074 u32 rid_entry; 5075 u8 devfn; 5076 5077 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5078 devfn = (rid_entry >> 1) & 0xFF; 5079 pci_dbg(pdev, 5080 "Aliasing Partition %d Proxy ID %02x.%d\n", 5081 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5082 pci_add_dma_alias(pdev, devfn); 5083 } 5084 } 5085 5086 pci_iounmap(pdev, mmio); 5087 pci_disable_device(pdev); 5088 } 5089 #define SWITCHTEC_QUIRK(vid) \ 5090 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5091 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5092 5093 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5094 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5095 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5096 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5097 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5098 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5099 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5100 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5101 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5102 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5103 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5104 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5105 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5106 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5107 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5108 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5109 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5110 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5111 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5112 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5113 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5114 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5115 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5116 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5117 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5118 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5119 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5120 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5121 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5122 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5123