1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/acpi.h> 24 #include <linux/kallsyms.h> 25 #include <linux/dmi.h> 26 #include <linux/pci-aspm.h> 27 #include <linux/ioport.h> 28 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 29 #include "pci.h" 30 31 /* 32 * This quirk function disables memory decoding and releases memory resources 33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='. 34 * It also rounds up size to specified alignment. 35 * Later on, the kernel will assign page-aligned memory resource back 36 * to the device. 37 */ 38 static void __devinit quirk_resource_alignment(struct pci_dev *dev) 39 { 40 int i; 41 struct resource *r; 42 resource_size_t align, size; 43 u16 command; 44 45 if (!pci_is_reassigndev(dev)) 46 return; 47 48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 50 dev_warn(&dev->dev, 51 "Can't reassign resources to host bridge.\n"); 52 return; 53 } 54 55 dev_info(&dev->dev, 56 "Disabling memory decoding and releasing memory resources.\n"); 57 pci_read_config_word(dev, PCI_COMMAND, &command); 58 command &= ~PCI_COMMAND_MEMORY; 59 pci_write_config_word(dev, PCI_COMMAND, command); 60 61 align = pci_specified_resource_alignment(dev); 62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) { 63 r = &dev->resource[i]; 64 if (!(r->flags & IORESOURCE_MEM)) 65 continue; 66 size = resource_size(r); 67 if (size < align) { 68 size = align; 69 dev_info(&dev->dev, 70 "Rounding up size of resource #%d to %#llx.\n", 71 i, (unsigned long long)size); 72 } 73 r->end = size - 1; 74 r->start = 0; 75 } 76 /* Need to disable bridge's resource window, 77 * to enable the kernel to reassign new resource 78 * window later on. 79 */ 80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 83 r = &dev->resource[i]; 84 if (!(r->flags & IORESOURCE_MEM)) 85 continue; 86 r->end = resource_size(r) - 1; 87 r->start = 0; 88 } 89 pci_disable_bridge_window(dev); 90 } 91 } 92 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment); 93 94 /* 95 * Decoding should be disabled for a PCI device during BAR sizing to avoid 96 * conflict. But doing so may cause problems on host bridge and perhaps other 97 * key system devices. For devices that need to have mmio decoding always-on, 98 * we need to set the dev->mmio_always_on bit. 99 */ 100 static void __devinit quirk_mmio_always_on(struct pci_dev *dev) 101 { 102 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) 103 dev->mmio_always_on = 1; 104 } 105 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on); 106 107 /* The Mellanox Tavor device gives false positive parity errors 108 * Mark this device with a broken_parity_status, to allow 109 * PCI scanning code to "skip" this now blacklisted device. 110 */ 111 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 112 { 113 dev->broken_parity_status = 1; /* This device gives false positives */ 114 } 115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 117 118 /* Deal with broken BIOS'es that neglect to enable passive release, 119 which can cause problems in combination with the 82441FX/PPro MTRRs */ 120 static void quirk_passive_release(struct pci_dev *dev) 121 { 122 struct pci_dev *d = NULL; 123 unsigned char dlc; 124 125 /* We have to make sure a particular bit is set in the PIIX3 126 ISA bridge, so we have to go out and find it. */ 127 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 128 pci_read_config_byte(d, 0x82, &dlc); 129 if (!(dlc & 1<<1)) { 130 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 131 dlc |= 1<<1; 132 pci_write_config_byte(d, 0x82, dlc); 133 } 134 } 135 } 136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 137 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 138 139 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 140 but VIA don't answer queries. If you happen to have good contacts at VIA 141 ask them for me please -- Alan 142 143 This appears to be BIOS not version dependent. So presumably there is a 144 chipset level fix */ 145 146 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 147 { 148 if (!isa_dma_bridge_buggy) { 149 isa_dma_bridge_buggy=1; 150 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 151 } 152 } 153 /* 154 * Its not totally clear which chipsets are the problematic ones 155 * We know 82C586 and 82C596 variants are affected. 156 */ 157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 164 165 /* 166 * Chipsets where PCI->PCI transfers vanish or hang 167 */ 168 static void __devinit quirk_nopcipci(struct pci_dev *dev) 169 { 170 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 171 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 172 pci_pci_problems |= PCIPCI_FAIL; 173 } 174 } 175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 177 178 static void __devinit quirk_nopciamd(struct pci_dev *dev) 179 { 180 u8 rev; 181 pci_read_config_byte(dev, 0x08, &rev); 182 if (rev == 0x13) { 183 /* Erratum 24 */ 184 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 185 pci_pci_problems |= PCIAGP_FAIL; 186 } 187 } 188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 189 190 /* 191 * Triton requires workarounds to be used by the drivers 192 */ 193 static void __devinit quirk_triton(struct pci_dev *dev) 194 { 195 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 196 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 197 pci_pci_problems |= PCIPCI_TRITON; 198 } 199 } 200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 204 205 /* 206 * VIA Apollo KT133 needs PCI latency patch 207 * Made according to a windows driver based patch by George E. Breese 208 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 209 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 210 * the info on which Mr Breese based his work. 211 * 212 * Updated based on further information from the site and also on 213 * information provided by VIA 214 */ 215 static void quirk_vialatency(struct pci_dev *dev) 216 { 217 struct pci_dev *p; 218 u8 busarb; 219 /* Ok we have a potential problem chipset here. Now see if we have 220 a buggy southbridge */ 221 222 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 223 if (p!=NULL) { 224 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 225 /* Check for buggy part revisions */ 226 if (p->revision < 0x40 || p->revision > 0x42) 227 goto exit; 228 } else { 229 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 230 if (p==NULL) /* No problem parts */ 231 goto exit; 232 /* Check for buggy part revisions */ 233 if (p->revision < 0x10 || p->revision > 0x12) 234 goto exit; 235 } 236 237 /* 238 * Ok we have the problem. Now set the PCI master grant to 239 * occur every master grant. The apparent bug is that under high 240 * PCI load (quite common in Linux of course) you can get data 241 * loss when the CPU is held off the bus for 3 bus master requests 242 * This happens to include the IDE controllers.... 243 * 244 * VIA only apply this fix when an SB Live! is present but under 245 * both Linux and Windows this isnt enough, and we have seen 246 * corruption without SB Live! but with things like 3 UDMA IDE 247 * controllers. So we ignore that bit of the VIA recommendation.. 248 */ 249 250 pci_read_config_byte(dev, 0x76, &busarb); 251 /* Set bit 4 and bi 5 of byte 76 to 0x01 252 "Master priority rotation on every PCI master grant */ 253 busarb &= ~(1<<5); 254 busarb |= (1<<4); 255 pci_write_config_byte(dev, 0x76, busarb); 256 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 257 exit: 258 pci_dev_put(p); 259 } 260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 263 /* Must restore this on a resume from RAM */ 264 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 265 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 266 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 267 268 /* 269 * VIA Apollo VP3 needs ETBF on BT848/878 270 */ 271 static void __devinit quirk_viaetbf(struct pci_dev *dev) 272 { 273 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 274 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 275 pci_pci_problems |= PCIPCI_VIAETBF; 276 } 277 } 278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 279 280 static void __devinit quirk_vsfx(struct pci_dev *dev) 281 { 282 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 283 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 284 pci_pci_problems |= PCIPCI_VSFX; 285 } 286 } 287 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 288 289 /* 290 * Ali Magik requires workarounds to be used by the drivers 291 * that DMA to AGP space. Latency must be set to 0xA and triton 292 * workaround applied too 293 * [Info kindly provided by ALi] 294 */ 295 static void __init quirk_alimagik(struct pci_dev *dev) 296 { 297 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 298 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 299 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 300 } 301 } 302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 304 305 /* 306 * Natoma has some interesting boundary conditions with Zoran stuff 307 * at least 308 */ 309 static void __devinit quirk_natoma(struct pci_dev *dev) 310 { 311 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 312 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 313 pci_pci_problems |= PCIPCI_NATOMA; 314 } 315 } 316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 322 323 /* 324 * This chip can cause PCI parity errors if config register 0xA0 is read 325 * while DMAs are occurring. 326 */ 327 static void __devinit quirk_citrine(struct pci_dev *dev) 328 { 329 dev->cfg_size = 0xA0; 330 } 331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 332 333 /* 334 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 335 * If it's needed, re-allocate the region. 336 */ 337 static void __devinit quirk_s3_64M(struct pci_dev *dev) 338 { 339 struct resource *r = &dev->resource[0]; 340 341 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 342 r->start = 0; 343 r->end = 0x3ffffff; 344 } 345 } 346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 348 349 /* 350 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 351 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 352 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 353 * (which conflicts w/ BAR1's memory range). 354 */ 355 static void __devinit quirk_cs5536_vsa(struct pci_dev *dev) 356 { 357 if (pci_resource_len(dev, 0) != 8) { 358 struct resource *res = &dev->resource[0]; 359 res->end = res->start + 8 - 1; 360 dev_info(&dev->dev, "CS5536 ISA bridge bug detected " 361 "(incorrect header); workaround applied.\n"); 362 } 363 } 364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 365 366 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 367 unsigned size, int nr, const char *name) 368 { 369 region &= ~(size-1); 370 if (region) { 371 struct pci_bus_region bus_region; 372 struct resource *res = dev->resource + nr; 373 374 res->name = pci_name(dev); 375 res->start = region; 376 res->end = region + size - 1; 377 res->flags = IORESOURCE_IO; 378 379 /* Convert from PCI bus to resource space. */ 380 bus_region.start = res->start; 381 bus_region.end = res->end; 382 pcibios_bus_to_resource(dev, res, &bus_region); 383 384 if (pci_claim_resource(dev, nr) == 0) 385 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", 386 res, name); 387 } 388 } 389 390 /* 391 * ATI Northbridge setups MCE the processor if you even 392 * read somewhere between 0x3b0->0x3bb or read 0x3d3 393 */ 394 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 395 { 396 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 397 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 398 request_region(0x3b0, 0x0C, "RadeonIGP"); 399 request_region(0x3d3, 0x01, "RadeonIGP"); 400 } 401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 402 403 /* 404 * Let's make the southbridge information explicit instead 405 * of having to worry about people probing the ACPI areas, 406 * for example.. (Yes, it happens, and if you read the wrong 407 * ACPI register it will put the machine to sleep with no 408 * way of waking it up again. Bummer). 409 * 410 * ALI M7101: Two IO regions pointed to by words at 411 * 0xE0 (64 bytes of ACPI registers) 412 * 0xE2 (32 bytes of SMB registers) 413 */ 414 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 415 { 416 u16 region; 417 418 pci_read_config_word(dev, 0xE0, ®ion); 419 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 420 pci_read_config_word(dev, 0xE2, ®ion); 421 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 422 } 423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 424 425 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 426 { 427 u32 devres; 428 u32 mask, size, base; 429 430 pci_read_config_dword(dev, port, &devres); 431 if ((devres & enable) != enable) 432 return; 433 mask = (devres >> 16) & 15; 434 base = devres & 0xffff; 435 size = 16; 436 for (;;) { 437 unsigned bit = size >> 1; 438 if ((bit & mask) == bit) 439 break; 440 size = bit; 441 } 442 /* 443 * For now we only print it out. Eventually we'll want to 444 * reserve it (at least if it's in the 0x1000+ range), but 445 * let's get enough confirmation reports first. 446 */ 447 base &= -size; 448 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 449 } 450 451 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 452 { 453 u32 devres; 454 u32 mask, size, base; 455 456 pci_read_config_dword(dev, port, &devres); 457 if ((devres & enable) != enable) 458 return; 459 base = devres & 0xffff0000; 460 mask = (devres & 0x3f) << 16; 461 size = 128 << 16; 462 for (;;) { 463 unsigned bit = size >> 1; 464 if ((bit & mask) == bit) 465 break; 466 size = bit; 467 } 468 /* 469 * For now we only print it out. Eventually we'll want to 470 * reserve it, but let's get enough confirmation reports first. 471 */ 472 base &= -size; 473 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 474 } 475 476 /* 477 * PIIX4 ACPI: Two IO regions pointed to by longwords at 478 * 0x40 (64 bytes of ACPI registers) 479 * 0x90 (16 bytes of SMB registers) 480 * and a few strange programmable PIIX4 device resources. 481 */ 482 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 483 { 484 u32 region, res_a; 485 486 pci_read_config_dword(dev, 0x40, ®ion); 487 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 488 pci_read_config_dword(dev, 0x90, ®ion); 489 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 490 491 /* Device resource A has enables for some of the other ones */ 492 pci_read_config_dword(dev, 0x5c, &res_a); 493 494 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 495 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 496 497 /* Device resource D is just bitfields for static resources */ 498 499 /* Device 12 enabled? */ 500 if (res_a & (1 << 29)) { 501 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 502 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 503 } 504 /* Device 13 enabled? */ 505 if (res_a & (1 << 30)) { 506 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 507 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 508 } 509 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 510 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 511 } 512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 514 515 /* 516 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 517 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 518 * 0x58 (64 bytes of GPIO I/O space) 519 */ 520 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 521 { 522 u32 region; 523 524 pci_read_config_dword(dev, 0x40, ®ion); 525 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); 526 527 pci_read_config_dword(dev, 0x58, ®ion); 528 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 529 } 530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 537 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 538 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 540 541 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev) 542 { 543 u32 region; 544 545 pci_read_config_dword(dev, 0x40, ®ion); 546 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); 547 548 pci_read_config_dword(dev, 0x48, ®ion); 549 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 550 } 551 552 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 553 { 554 u32 val; 555 u32 size, base; 556 557 pci_read_config_dword(dev, reg, &val); 558 559 /* Enabled? */ 560 if (!(val & 1)) 561 return; 562 base = val & 0xfffc; 563 if (dynsize) { 564 /* 565 * This is not correct. It is 16, 32 or 64 bytes depending on 566 * register D31:F0:ADh bits 5:4. 567 * 568 * But this gets us at least _part_ of it. 569 */ 570 size = 16; 571 } else { 572 size = 128; 573 } 574 base &= ~(size-1); 575 576 /* Just print it out for now. We should reserve it after more debugging */ 577 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 578 } 579 580 static void __devinit quirk_ich6_lpc(struct pci_dev *dev) 581 { 582 /* Shared ACPI/GPIO decode with all ICH6+ */ 583 ich6_lpc_acpi_gpio(dev); 584 585 /* ICH6-specific generic IO decode */ 586 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 587 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 588 } 589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 591 592 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 593 { 594 u32 val; 595 u32 mask, base; 596 597 pci_read_config_dword(dev, reg, &val); 598 599 /* Enabled? */ 600 if (!(val & 1)) 601 return; 602 603 /* 604 * IO base in bits 15:2, mask in bits 23:18, both 605 * are dword-based 606 */ 607 base = val & 0xfffc; 608 mask = (val >> 16) & 0xfc; 609 mask |= 3; 610 611 /* Just print it out for now. We should reserve it after more debugging */ 612 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 613 } 614 615 /* ICH7-10 has the same common LPC generic IO decode registers */ 616 static void __devinit quirk_ich7_lpc(struct pci_dev *dev) 617 { 618 /* We share the common ACPI/DPIO decode with ICH6 */ 619 ich6_lpc_acpi_gpio(dev); 620 621 /* And have 4 ICH7+ generic decodes */ 622 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 623 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 624 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 625 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 626 } 627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 630 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 640 641 /* 642 * VIA ACPI: One IO region pointed to by longword at 643 * 0x48 or 0x20 (256 bytes of ACPI registers) 644 */ 645 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 646 { 647 u32 region; 648 649 if (dev->revision & 0x10) { 650 pci_read_config_dword(dev, 0x48, ®ion); 651 region &= PCI_BASE_ADDRESS_IO_MASK; 652 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 653 } 654 } 655 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 656 657 /* 658 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 659 * 0x48 (256 bytes of ACPI registers) 660 * 0x70 (128 bytes of hardware monitoring register) 661 * 0x90 (16 bytes of SMB registers) 662 */ 663 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 664 { 665 u16 hm; 666 u32 smb; 667 668 quirk_vt82c586_acpi(dev); 669 670 pci_read_config_word(dev, 0x70, &hm); 671 hm &= PCI_BASE_ADDRESS_IO_MASK; 672 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 673 674 pci_read_config_dword(dev, 0x90, &smb); 675 smb &= PCI_BASE_ADDRESS_IO_MASK; 676 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 677 } 678 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 679 680 /* 681 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 682 * 0x88 (128 bytes of power management registers) 683 * 0xd0 (16 bytes of SMB registers) 684 */ 685 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 686 { 687 u16 pm, smb; 688 689 pci_read_config_word(dev, 0x88, &pm); 690 pm &= PCI_BASE_ADDRESS_IO_MASK; 691 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 692 693 pci_read_config_word(dev, 0xd0, &smb); 694 smb &= PCI_BASE_ADDRESS_IO_MASK; 695 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 696 } 697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 698 699 /* 700 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 701 * Disable fast back-to-back on the secondary bus segment 702 */ 703 static void __devinit quirk_xio2000a(struct pci_dev *dev) 704 { 705 struct pci_dev *pdev; 706 u16 command; 707 708 dev_warn(&dev->dev, "TI XIO2000a quirk detected; " 709 "secondary bus fast back-to-back transfers disabled\n"); 710 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 711 pci_read_config_word(pdev, PCI_COMMAND, &command); 712 if (command & PCI_COMMAND_FAST_BACK) 713 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 714 } 715 } 716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 717 quirk_xio2000a); 718 719 #ifdef CONFIG_X86_IO_APIC 720 721 #include <asm/io_apic.h> 722 723 /* 724 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 725 * devices to the external APIC. 726 * 727 * TODO: When we have device-specific interrupt routers, 728 * this code will go away from quirks. 729 */ 730 static void quirk_via_ioapic(struct pci_dev *dev) 731 { 732 u8 tmp; 733 734 if (nr_ioapics < 1) 735 tmp = 0; /* nothing routed to external APIC */ 736 else 737 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 738 739 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 740 tmp == 0 ? "Disa" : "Ena"); 741 742 /* Offset 0x58: External APIC IRQ output control */ 743 pci_write_config_byte (dev, 0x58, tmp); 744 } 745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 746 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 747 748 /* 749 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 750 * This leads to doubled level interrupt rates. 751 * Set this bit to get rid of cycle wastage. 752 * Otherwise uncritical. 753 */ 754 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 755 { 756 u8 misc_control2; 757 #define BYPASS_APIC_DEASSERT 8 758 759 pci_read_config_byte(dev, 0x5B, &misc_control2); 760 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 761 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 762 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 763 } 764 } 765 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 766 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 767 768 /* 769 * The AMD io apic can hang the box when an apic irq is masked. 770 * We check all revs >= B0 (yet not in the pre production!) as the bug 771 * is currently marked NoFix 772 * 773 * We have multiple reports of hangs with this chipset that went away with 774 * noapic specified. For the moment we assume it's the erratum. We may be wrong 775 * of course. However the advice is demonstrably good even if so.. 776 */ 777 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 778 { 779 if (dev->revision >= 0x02) { 780 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 781 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 782 } 783 } 784 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 785 786 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 787 { 788 if (dev->devfn == 0 && dev->bus->number == 0) 789 sis_apic_bug = 1; 790 } 791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); 792 #endif /* CONFIG_X86_IO_APIC */ 793 794 /* 795 * Some settings of MMRBC can lead to data corruption so block changes. 796 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 797 */ 798 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 799 { 800 if (dev->subordinate && dev->revision <= 0x12) { 801 dev_info(&dev->dev, "AMD8131 rev %x detected; " 802 "disabling PCI-X MMRBC\n", dev->revision); 803 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 804 } 805 } 806 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 807 808 /* 809 * FIXME: it is questionable that quirk_via_acpi 810 * is needed. It shows up as an ISA bridge, and does not 811 * support the PCI_INTERRUPT_LINE register at all. Therefore 812 * it seems like setting the pci_dev's 'irq' to the 813 * value of the ACPI SCI interrupt is only done for convenience. 814 * -jgarzik 815 */ 816 static void __devinit quirk_via_acpi(struct pci_dev *d) 817 { 818 /* 819 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 820 */ 821 u8 irq; 822 pci_read_config_byte(d, 0x42, &irq); 823 irq &= 0xf; 824 if (irq && (irq != 2)) 825 d->irq = irq; 826 } 827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 829 830 831 /* 832 * VIA bridges which have VLink 833 */ 834 835 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 836 837 static void quirk_via_bridge(struct pci_dev *dev) 838 { 839 /* See what bridge we have and find the device ranges */ 840 switch (dev->device) { 841 case PCI_DEVICE_ID_VIA_82C686: 842 /* The VT82C686 is special, it attaches to PCI and can have 843 any device number. All its subdevices are functions of 844 that single device. */ 845 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 846 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 847 break; 848 case PCI_DEVICE_ID_VIA_8237: 849 case PCI_DEVICE_ID_VIA_8237A: 850 via_vlink_dev_lo = 15; 851 break; 852 case PCI_DEVICE_ID_VIA_8235: 853 via_vlink_dev_lo = 16; 854 break; 855 case PCI_DEVICE_ID_VIA_8231: 856 case PCI_DEVICE_ID_VIA_8233_0: 857 case PCI_DEVICE_ID_VIA_8233A: 858 case PCI_DEVICE_ID_VIA_8233C_0: 859 via_vlink_dev_lo = 17; 860 break; 861 } 862 } 863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 871 872 /** 873 * quirk_via_vlink - VIA VLink IRQ number update 874 * @dev: PCI device 875 * 876 * If the device we are dealing with is on a PIC IRQ we need to 877 * ensure that the IRQ line register which usually is not relevant 878 * for PCI cards, is actually written so that interrupts get sent 879 * to the right place. 880 * We only do this on systems where a VIA south bridge was detected, 881 * and only for VIA devices on the motherboard (see quirk_via_bridge 882 * above). 883 */ 884 885 static void quirk_via_vlink(struct pci_dev *dev) 886 { 887 u8 irq, new_irq; 888 889 /* Check if we have VLink at all */ 890 if (via_vlink_dev_lo == -1) 891 return; 892 893 new_irq = dev->irq; 894 895 /* Don't quirk interrupts outside the legacy IRQ range */ 896 if (!new_irq || new_irq > 15) 897 return; 898 899 /* Internal device ? */ 900 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 901 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 902 return; 903 904 /* This is an internal VLink device on a PIC interrupt. The BIOS 905 ought to have set this but may not have, so we redo it */ 906 907 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 908 if (new_irq != irq) { 909 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 910 irq, new_irq); 911 udelay(15); /* unknown if delay really needed */ 912 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 913 } 914 } 915 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 916 917 /* 918 * VIA VT82C598 has its device ID settable and many BIOSes 919 * set it to the ID of VT82C597 for backward compatibility. 920 * We need to switch it off to be able to recognize the real 921 * type of the chip. 922 */ 923 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 924 { 925 pci_write_config_byte(dev, 0xfc, 0); 926 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 927 } 928 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 929 930 /* 931 * CardBus controllers have a legacy base address that enables them 932 * to respond as i82365 pcmcia controllers. We don't want them to 933 * do this even if the Linux CardBus driver is not loaded, because 934 * the Linux i82365 driver does not (and should not) handle CardBus. 935 */ 936 static void quirk_cardbus_legacy(struct pci_dev *dev) 937 { 938 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 939 return; 940 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 941 } 942 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 943 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 944 945 /* 946 * Following the PCI ordering rules is optional on the AMD762. I'm not 947 * sure what the designers were smoking but let's not inhale... 948 * 949 * To be fair to AMD, it follows the spec by default, its BIOS people 950 * who turn it off! 951 */ 952 static void quirk_amd_ordering(struct pci_dev *dev) 953 { 954 u32 pcic; 955 pci_read_config_dword(dev, 0x4C, &pcic); 956 if ((pcic&6)!=6) { 957 pcic |= 6; 958 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 959 pci_write_config_dword(dev, 0x4C, pcic); 960 pci_read_config_dword(dev, 0x84, &pcic); 961 pcic |= (1<<23); /* Required in this mode */ 962 pci_write_config_dword(dev, 0x84, pcic); 963 } 964 } 965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 966 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 967 968 /* 969 * DreamWorks provided workaround for Dunord I-3000 problem 970 * 971 * This card decodes and responds to addresses not apparently 972 * assigned to it. We force a larger allocation to ensure that 973 * nothing gets put too close to it. 974 */ 975 static void __devinit quirk_dunord ( struct pci_dev * dev ) 976 { 977 struct resource *r = &dev->resource [1]; 978 r->start = 0; 979 r->end = 0xffffff; 980 } 981 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 982 983 /* 984 * i82380FB mobile docking controller: its PCI-to-PCI bridge 985 * is subtractive decoding (transparent), and does indicate this 986 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 987 * instead of 0x01. 988 */ 989 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 990 { 991 dev->transparent = 1; 992 } 993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 995 996 /* 997 * Common misconfiguration of the MediaGX/Geode PCI master that will 998 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 999 * datasheets found at http://www.national.com/ds/GX for info on what 1000 * these bits do. <christer@weinigel.se> 1001 */ 1002 static void quirk_mediagx_master(struct pci_dev *dev) 1003 { 1004 u8 reg; 1005 pci_read_config_byte(dev, 0x41, ®); 1006 if (reg & 2) { 1007 reg &= ~2; 1008 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 1009 pci_write_config_byte(dev, 0x41, reg); 1010 } 1011 } 1012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1013 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1014 1015 /* 1016 * Ensure C0 rev restreaming is off. This is normally done by 1017 * the BIOS but in the odd case it is not the results are corruption 1018 * hence the presence of a Linux check 1019 */ 1020 static void quirk_disable_pxb(struct pci_dev *pdev) 1021 { 1022 u16 config; 1023 1024 if (pdev->revision != 0x04) /* Only C0 requires this */ 1025 return; 1026 pci_read_config_word(pdev, 0x40, &config); 1027 if (config & (1<<6)) { 1028 config &= ~(1<<6); 1029 pci_write_config_word(pdev, 0x40, config); 1030 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1031 } 1032 } 1033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1034 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1035 1036 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) 1037 { 1038 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1039 u8 tmp; 1040 1041 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1042 if (tmp == 0x01) { 1043 pci_read_config_byte(pdev, 0x40, &tmp); 1044 pci_write_config_byte(pdev, 0x40, tmp|1); 1045 pci_write_config_byte(pdev, 0x9, 1); 1046 pci_write_config_byte(pdev, 0xa, 6); 1047 pci_write_config_byte(pdev, 0x40, tmp); 1048 1049 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1050 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1051 } 1052 } 1053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1054 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1056 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1058 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1059 1060 /* 1061 * Serverworks CSB5 IDE does not fully support native mode 1062 */ 1063 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 1064 { 1065 u8 prog; 1066 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1067 if (prog & 5) { 1068 prog &= ~5; 1069 pdev->class &= ~5; 1070 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1071 /* PCI layer will sort out resources */ 1072 } 1073 } 1074 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1075 1076 /* 1077 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1078 */ 1079 static void __init quirk_ide_samemode(struct pci_dev *pdev) 1080 { 1081 u8 prog; 1082 1083 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1084 1085 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1086 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1087 prog &= ~5; 1088 pdev->class &= ~5; 1089 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1090 } 1091 } 1092 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1093 1094 /* 1095 * Some ATA devices break if put into D3 1096 */ 1097 1098 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) 1099 { 1100 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1101 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) 1102 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1103 } 1104 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3); 1105 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3); 1106 /* ALi loses some register settings that we cannot then restore */ 1107 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3); 1108 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1109 occur when mode detecting */ 1110 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3); 1111 1112 /* This was originally an Alpha specific thing, but it really fits here. 1113 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1114 */ 1115 static void __init quirk_eisa_bridge(struct pci_dev *dev) 1116 { 1117 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1118 } 1119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1120 1121 1122 /* 1123 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1124 * is not activated. The myth is that Asus said that they do not want the 1125 * users to be irritated by just another PCI Device in the Win98 device 1126 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1127 * package 2.7.0 for details) 1128 * 1129 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1130 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1131 * becomes necessary to do this tweak in two steps -- the chosen trigger 1132 * is either the Host bridge (preferred) or on-board VGA controller. 1133 * 1134 * Note that we used to unhide the SMBus that way on Toshiba laptops 1135 * (Satellite A40 and Tecra M2) but then found that the thermal management 1136 * was done by SMM code, which could cause unsynchronized concurrent 1137 * accesses to the SMBus registers, with potentially bad effects. Thus you 1138 * should be very careful when adding new entries: if SMM is accessing the 1139 * Intel SMBus, this is a very good reason to leave it hidden. 1140 * 1141 * Likewise, many recent laptops use ACPI for thermal management. If the 1142 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1143 * natively, and keeping the SMBus hidden is the right thing to do. If you 1144 * are about to add an entry in the table below, please first disassemble 1145 * the DSDT and double-check that there is no code accessing the SMBus. 1146 */ 1147 static int asus_hides_smbus; 1148 1149 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 1150 { 1151 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1152 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1153 switch(dev->subsystem_device) { 1154 case 0x8025: /* P4B-LX */ 1155 case 0x8070: /* P4B */ 1156 case 0x8088: /* P4B533 */ 1157 case 0x1626: /* L3C notebook */ 1158 asus_hides_smbus = 1; 1159 } 1160 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1161 switch(dev->subsystem_device) { 1162 case 0x80b1: /* P4GE-V */ 1163 case 0x80b2: /* P4PE */ 1164 case 0x8093: /* P4B533-V */ 1165 asus_hides_smbus = 1; 1166 } 1167 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1168 switch(dev->subsystem_device) { 1169 case 0x8030: /* P4T533 */ 1170 asus_hides_smbus = 1; 1171 } 1172 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1173 switch (dev->subsystem_device) { 1174 case 0x8070: /* P4G8X Deluxe */ 1175 asus_hides_smbus = 1; 1176 } 1177 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1178 switch (dev->subsystem_device) { 1179 case 0x80c9: /* PU-DLS */ 1180 asus_hides_smbus = 1; 1181 } 1182 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1183 switch (dev->subsystem_device) { 1184 case 0x1751: /* M2N notebook */ 1185 case 0x1821: /* M5N notebook */ 1186 case 0x1897: /* A6L notebook */ 1187 asus_hides_smbus = 1; 1188 } 1189 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1190 switch (dev->subsystem_device) { 1191 case 0x184b: /* W1N notebook */ 1192 case 0x186a: /* M6Ne notebook */ 1193 asus_hides_smbus = 1; 1194 } 1195 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1196 switch (dev->subsystem_device) { 1197 case 0x80f2: /* P4P800-X */ 1198 asus_hides_smbus = 1; 1199 } 1200 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1201 switch (dev->subsystem_device) { 1202 case 0x1882: /* M6V notebook */ 1203 case 0x1977: /* A6VA notebook */ 1204 asus_hides_smbus = 1; 1205 } 1206 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1207 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1208 switch(dev->subsystem_device) { 1209 case 0x088C: /* HP Compaq nc8000 */ 1210 case 0x0890: /* HP Compaq nc6000 */ 1211 asus_hides_smbus = 1; 1212 } 1213 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1214 switch (dev->subsystem_device) { 1215 case 0x12bc: /* HP D330L */ 1216 case 0x12bd: /* HP D530 */ 1217 case 0x006a: /* HP Compaq nx9500 */ 1218 asus_hides_smbus = 1; 1219 } 1220 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1221 switch (dev->subsystem_device) { 1222 case 0x12bf: /* HP xw4100 */ 1223 asus_hides_smbus = 1; 1224 } 1225 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1226 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1227 switch(dev->subsystem_device) { 1228 case 0xC00C: /* Samsung P35 notebook */ 1229 asus_hides_smbus = 1; 1230 } 1231 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1232 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1233 switch(dev->subsystem_device) { 1234 case 0x0058: /* Compaq Evo N620c */ 1235 asus_hides_smbus = 1; 1236 } 1237 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1238 switch(dev->subsystem_device) { 1239 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1240 /* Motherboard doesn't have Host bridge 1241 * subvendor/subdevice IDs, therefore checking 1242 * its on-board VGA controller */ 1243 asus_hides_smbus = 1; 1244 } 1245 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1246 switch(dev->subsystem_device) { 1247 case 0x00b8: /* Compaq Evo D510 CMT */ 1248 case 0x00b9: /* Compaq Evo D510 SFF */ 1249 case 0x00ba: /* Compaq Evo D510 USDT */ 1250 /* Motherboard doesn't have Host bridge 1251 * subvendor/subdevice IDs and on-board VGA 1252 * controller is disabled if an AGP card is 1253 * inserted, therefore checking USB UHCI 1254 * Controller #1 */ 1255 asus_hides_smbus = 1; 1256 } 1257 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1258 switch (dev->subsystem_device) { 1259 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1260 /* Motherboard doesn't have host bridge 1261 * subvendor/subdevice IDs, therefore checking 1262 * its on-board VGA controller */ 1263 asus_hides_smbus = 1; 1264 } 1265 } 1266 } 1267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1277 1278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1281 1282 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1283 { 1284 u16 val; 1285 1286 if (likely(!asus_hides_smbus)) 1287 return; 1288 1289 pci_read_config_word(dev, 0xF2, &val); 1290 if (val & 0x8) { 1291 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1292 pci_read_config_word(dev, 0xF2, &val); 1293 if (val & 0x8) 1294 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1295 else 1296 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1297 } 1298 } 1299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1306 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1307 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1308 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1309 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1310 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1311 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1312 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1313 1314 /* It appears we just have one such device. If not, we have a warning */ 1315 static void __iomem *asus_rcba_base; 1316 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1317 { 1318 u32 rcba; 1319 1320 if (likely(!asus_hides_smbus)) 1321 return; 1322 WARN_ON(asus_rcba_base); 1323 1324 pci_read_config_dword(dev, 0xF0, &rcba); 1325 /* use bits 31:14, 16 kB aligned */ 1326 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1327 if (asus_rcba_base == NULL) 1328 return; 1329 } 1330 1331 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1332 { 1333 u32 val; 1334 1335 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1336 return; 1337 /* read the Function Disable register, dword mode only */ 1338 val = readl(asus_rcba_base + 0x3418); 1339 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1340 } 1341 1342 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1343 { 1344 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1345 return; 1346 iounmap(asus_rcba_base); 1347 asus_rcba_base = NULL; 1348 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1349 } 1350 1351 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1352 { 1353 asus_hides_smbus_lpc_ich6_suspend(dev); 1354 asus_hides_smbus_lpc_ich6_resume_early(dev); 1355 asus_hides_smbus_lpc_ich6_resume(dev); 1356 } 1357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1358 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1359 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1360 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1361 1362 /* 1363 * SiS 96x south bridge: BIOS typically hides SMBus device... 1364 */ 1365 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1366 { 1367 u8 val = 0; 1368 pci_read_config_byte(dev, 0x77, &val); 1369 if (val & 0x10) { 1370 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1371 pci_write_config_byte(dev, 0x77, val & ~0x10); 1372 } 1373 } 1374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1378 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1379 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1380 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1381 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1382 1383 /* 1384 * ... This is further complicated by the fact that some SiS96x south 1385 * bridges pretend to be 85C503/5513 instead. In that case see if we 1386 * spotted a compatible north bridge to make sure. 1387 * (pci_find_device doesn't work yet) 1388 * 1389 * We can also enable the sis96x bit in the discovery register.. 1390 */ 1391 #define SIS_DETECT_REGISTER 0x40 1392 1393 static void quirk_sis_503(struct pci_dev *dev) 1394 { 1395 u8 reg; 1396 u16 devid; 1397 1398 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1399 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1400 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1401 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1402 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1403 return; 1404 } 1405 1406 /* 1407 * Ok, it now shows up as a 96x.. run the 96x quirk by 1408 * hand in case it has already been processed. 1409 * (depends on link order, which is apparently not guaranteed) 1410 */ 1411 dev->device = devid; 1412 quirk_sis_96x_smbus(dev); 1413 } 1414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1415 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1416 1417 1418 /* 1419 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1420 * and MC97 modem controller are disabled when a second PCI soundcard is 1421 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1422 * -- bjd 1423 */ 1424 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1425 { 1426 u8 val; 1427 int asus_hides_ac97 = 0; 1428 1429 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1430 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1431 asus_hides_ac97 = 1; 1432 } 1433 1434 if (!asus_hides_ac97) 1435 return; 1436 1437 pci_read_config_byte(dev, 0x50, &val); 1438 if (val & 0xc0) { 1439 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1440 pci_read_config_byte(dev, 0x50, &val); 1441 if (val & 0xc0) 1442 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1443 else 1444 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1445 } 1446 } 1447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1448 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1449 1450 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1451 1452 /* 1453 * If we are using libata we can drive this chip properly but must 1454 * do this early on to make the additional device appear during 1455 * the PCI scanning. 1456 */ 1457 static void quirk_jmicron_ata(struct pci_dev *pdev) 1458 { 1459 u32 conf1, conf5, class; 1460 u8 hdr; 1461 1462 /* Only poke fn 0 */ 1463 if (PCI_FUNC(pdev->devfn)) 1464 return; 1465 1466 pci_read_config_dword(pdev, 0x40, &conf1); 1467 pci_read_config_dword(pdev, 0x80, &conf5); 1468 1469 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1470 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1471 1472 switch (pdev->device) { 1473 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1474 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1475 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1476 /* The controller should be in single function ahci mode */ 1477 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1478 break; 1479 1480 case PCI_DEVICE_ID_JMICRON_JMB365: 1481 case PCI_DEVICE_ID_JMICRON_JMB366: 1482 /* Redirect IDE second PATA port to the right spot */ 1483 conf5 |= (1 << 24); 1484 /* Fall through */ 1485 case PCI_DEVICE_ID_JMICRON_JMB361: 1486 case PCI_DEVICE_ID_JMICRON_JMB363: 1487 case PCI_DEVICE_ID_JMICRON_JMB369: 1488 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1489 /* Set the class codes correctly and then direct IDE 0 */ 1490 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1491 break; 1492 1493 case PCI_DEVICE_ID_JMICRON_JMB368: 1494 /* The controller should be in single function IDE mode */ 1495 conf1 |= 0x00C00000; /* Set 22, 23 */ 1496 break; 1497 } 1498 1499 pci_write_config_dword(pdev, 0x40, conf1); 1500 pci_write_config_dword(pdev, 0x80, conf5); 1501 1502 /* Update pdev accordingly */ 1503 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1504 pdev->hdr_type = hdr & 0x7f; 1505 pdev->multifunction = !!(hdr & 0x80); 1506 1507 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1508 pdev->class = class >> 8; 1509 } 1510 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1511 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1512 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1513 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1514 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1515 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1516 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1517 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1518 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1519 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1520 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1521 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1522 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1523 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1524 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1525 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1526 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1527 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1528 1529 #endif 1530 1531 #ifdef CONFIG_X86_IO_APIC 1532 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1533 { 1534 int i; 1535 1536 if ((pdev->class >> 8) != 0xff00) 1537 return; 1538 1539 /* the first BAR is the location of the IO APIC...we must 1540 * not touch this (and it's already covered by the fixmap), so 1541 * forcibly insert it into the resource tree */ 1542 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1543 insert_resource(&iomem_resource, &pdev->resource[0]); 1544 1545 /* The next five BARs all seem to be rubbish, so just clean 1546 * them out */ 1547 for (i=1; i < 6; i++) { 1548 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1549 } 1550 1551 } 1552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1553 #endif 1554 1555 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1556 { 1557 pci_msi_off(pdev); 1558 pdev->no_msi = 1; 1559 } 1560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1563 1564 1565 /* 1566 * It's possible for the MSI to get corrupted if shpc and acpi 1567 * are used together on certain PXH-based systems. 1568 */ 1569 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1570 { 1571 pci_msi_off(dev); 1572 dev->no_msi = 1; 1573 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1574 } 1575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1580 1581 /* 1582 * Some Intel PCI Express chipsets have trouble with downstream 1583 * device power management. 1584 */ 1585 static void quirk_intel_pcie_pm(struct pci_dev * dev) 1586 { 1587 pci_pm_d3_delay = 120; 1588 dev->no_d1d2 = 1; 1589 } 1590 1591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1612 1613 #ifdef CONFIG_X86_IO_APIC 1614 /* 1615 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1616 * remap the original interrupt in the linux kernel to the boot interrupt, so 1617 * that a PCI device's interrupt handler is installed on the boot interrupt 1618 * line instead. 1619 */ 1620 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1621 { 1622 if (noioapicquirk || noioapicreroute) 1623 return; 1624 1625 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1626 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1627 dev->vendor, dev->device); 1628 } 1629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1637 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1638 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1639 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1640 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1641 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1642 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1643 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1644 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1645 1646 /* 1647 * On some chipsets we can disable the generation of legacy INTx boot 1648 * interrupts. 1649 */ 1650 1651 /* 1652 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1653 * 300641-004US, section 5.7.3. 1654 */ 1655 #define INTEL_6300_IOAPIC_ABAR 0x40 1656 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1657 1658 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1659 { 1660 u16 pci_config_word; 1661 1662 if (noioapicquirk) 1663 return; 1664 1665 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1666 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1667 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1668 1669 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1670 dev->vendor, dev->device); 1671 } 1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1673 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1674 1675 /* 1676 * disable boot interrupts on HT-1000 1677 */ 1678 #define BC_HT1000_FEATURE_REG 0x64 1679 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1680 #define BC_HT1000_MAP_IDX 0xC00 1681 #define BC_HT1000_MAP_DATA 0xC01 1682 1683 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1684 { 1685 u32 pci_config_dword; 1686 u8 irq; 1687 1688 if (noioapicquirk) 1689 return; 1690 1691 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1692 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1693 BC_HT1000_PIC_REGS_ENABLE); 1694 1695 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1696 outb(irq, BC_HT1000_MAP_IDX); 1697 outb(0x00, BC_HT1000_MAP_DATA); 1698 } 1699 1700 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1701 1702 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1703 dev->vendor, dev->device); 1704 } 1705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1706 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1707 1708 /* 1709 * disable boot interrupts on AMD and ATI chipsets 1710 */ 1711 /* 1712 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1713 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1714 * (due to an erratum). 1715 */ 1716 #define AMD_813X_MISC 0x40 1717 #define AMD_813X_NOIOAMODE (1<<0) 1718 #define AMD_813X_REV_B1 0x12 1719 #define AMD_813X_REV_B2 0x13 1720 1721 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1722 { 1723 u32 pci_config_dword; 1724 1725 if (noioapicquirk) 1726 return; 1727 if ((dev->revision == AMD_813X_REV_B1) || 1728 (dev->revision == AMD_813X_REV_B2)) 1729 return; 1730 1731 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1732 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1733 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1734 1735 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1736 dev->vendor, dev->device); 1737 } 1738 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1739 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1741 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1742 1743 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1744 1745 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1746 { 1747 u16 pci_config_word; 1748 1749 if (noioapicquirk) 1750 return; 1751 1752 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1753 if (!pci_config_word) { 1754 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] " 1755 "already disabled\n", dev->vendor, dev->device); 1756 return; 1757 } 1758 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1759 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1760 dev->vendor, dev->device); 1761 } 1762 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1763 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1764 #endif /* CONFIG_X86_IO_APIC */ 1765 1766 /* 1767 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1768 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1769 * Re-allocate the region if needed... 1770 */ 1771 static void __init quirk_tc86c001_ide(struct pci_dev *dev) 1772 { 1773 struct resource *r = &dev->resource[0]; 1774 1775 if (r->start & 0x8) { 1776 r->start = 0; 1777 r->end = 0xf; 1778 } 1779 } 1780 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1781 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1782 quirk_tc86c001_ide); 1783 1784 static void __devinit quirk_netmos(struct pci_dev *dev) 1785 { 1786 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1787 unsigned int num_serial = dev->subsystem_device & 0xf; 1788 1789 /* 1790 * These Netmos parts are multiport serial devices with optional 1791 * parallel ports. Even when parallel ports are present, they 1792 * are identified as class SERIAL, which means the serial driver 1793 * will claim them. To prevent this, mark them as class OTHER. 1794 * These combo devices should be claimed by parport_serial. 1795 * 1796 * The subdevice ID is of the form 0x00PS, where <P> is the number 1797 * of parallel ports and <S> is the number of serial ports. 1798 */ 1799 switch (dev->device) { 1800 case PCI_DEVICE_ID_NETMOS_9835: 1801 /* Well, this rule doesn't hold for the following 9835 device */ 1802 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1803 dev->subsystem_device == 0x0299) 1804 return; 1805 case PCI_DEVICE_ID_NETMOS_9735: 1806 case PCI_DEVICE_ID_NETMOS_9745: 1807 case PCI_DEVICE_ID_NETMOS_9845: 1808 case PCI_DEVICE_ID_NETMOS_9855: 1809 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1810 num_parallel) { 1811 dev_info(&dev->dev, "Netmos %04x (%u parallel, " 1812 "%u serial); changing class SERIAL to OTHER " 1813 "(use parport_serial)\n", 1814 dev->device, num_parallel, num_serial); 1815 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1816 (dev->class & 0xff); 1817 } 1818 } 1819 } 1820 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1821 1822 static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1823 { 1824 u16 command, pmcsr; 1825 u8 __iomem *csr; 1826 u8 cmd_hi; 1827 int pm; 1828 1829 switch (dev->device) { 1830 /* PCI IDs taken from drivers/net/e100.c */ 1831 case 0x1029: 1832 case 0x1030 ... 0x1034: 1833 case 0x1038 ... 0x103E: 1834 case 0x1050 ... 0x1057: 1835 case 0x1059: 1836 case 0x1064 ... 0x106B: 1837 case 0x1091 ... 0x1095: 1838 case 0x1209: 1839 case 0x1229: 1840 case 0x2449: 1841 case 0x2459: 1842 case 0x245D: 1843 case 0x27DC: 1844 break; 1845 default: 1846 return; 1847 } 1848 1849 /* 1850 * Some firmware hands off the e100 with interrupts enabled, 1851 * which can cause a flood of interrupts if packets are 1852 * received before the driver attaches to the device. So 1853 * disable all e100 interrupts here. The driver will 1854 * re-enable them when it's ready. 1855 */ 1856 pci_read_config_word(dev, PCI_COMMAND, &command); 1857 1858 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1859 return; 1860 1861 /* 1862 * Check that the device is in the D0 power state. If it's not, 1863 * there is no point to look any further. 1864 */ 1865 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1866 if (pm) { 1867 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 1868 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1869 return; 1870 } 1871 1872 /* Convert from PCI bus to resource space. */ 1873 csr = ioremap(pci_resource_start(dev, 0), 8); 1874 if (!csr) { 1875 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1876 return; 1877 } 1878 1879 cmd_hi = readb(csr + 3); 1880 if (cmd_hi == 0) { 1881 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " 1882 "disabling\n"); 1883 writeb(1, csr + 3); 1884 } 1885 1886 iounmap(csr); 1887 } 1888 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); 1889 1890 /* 1891 * The 82575 and 82598 may experience data corruption issues when transitioning 1892 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1893 */ 1894 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) 1895 { 1896 dev_info(&dev->dev, "Disabling L0s\n"); 1897 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1898 } 1899 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 1900 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 1901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 1902 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 1903 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 1904 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 1906 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 1907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 1911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 1912 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 1913 1914 static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1915 { 1916 /* rev 1 ncr53c810 chips don't set the class at all which means 1917 * they don't get their resources remapped. Fix that here. 1918 */ 1919 1920 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1921 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 1922 dev->class = PCI_CLASS_STORAGE_SCSI; 1923 } 1924 } 1925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1926 1927 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1928 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1929 { 1930 u16 en1k; 1931 u8 io_base_lo, io_limit_lo; 1932 unsigned long base, limit; 1933 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1934 1935 pci_read_config_word(dev, 0x40, &en1k); 1936 1937 if (en1k & 0x200) { 1938 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 1939 1940 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1941 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1942 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1943 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1944 1945 if (base <= limit) { 1946 res->start = base; 1947 res->end = limit + 0x3ff; 1948 } 1949 } 1950 } 1951 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1952 1953 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 1954 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() 1955 * in drivers/pci/setup-bus.c 1956 */ 1957 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) 1958 { 1959 u16 en1k, iobl_adr, iobl_adr_1k; 1960 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1961 1962 pci_read_config_word(dev, 0x40, &en1k); 1963 1964 if (en1k & 0x200) { 1965 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); 1966 1967 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); 1968 1969 if (iobl_adr != iobl_adr_1k) { 1970 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n", 1971 iobl_adr,iobl_adr_1k); 1972 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); 1973 } 1974 } 1975 } 1976 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); 1977 1978 /* Under some circumstances, AER is not linked with extended capabilities. 1979 * Force it to be linked by setting the corresponding control bit in the 1980 * config space. 1981 */ 1982 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1983 { 1984 uint8_t b; 1985 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1986 if (!(b & 0x20)) { 1987 pci_write_config_byte(dev, 0xf41, b | 0x20); 1988 dev_info(&dev->dev, 1989 "Linking AER extended capability\n"); 1990 } 1991 } 1992 } 1993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1994 quirk_nvidia_ck804_pcie_aer_ext_cap); 1995 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1996 quirk_nvidia_ck804_pcie_aer_ext_cap); 1997 1998 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 1999 { 2000 /* 2001 * Disable PCI Bus Parking and PCI Master read caching on CX700 2002 * which causes unspecified timing errors with a VT6212L on the PCI 2003 * bus leading to USB2.0 packet loss. 2004 * 2005 * This quirk is only enabled if a second (on the external PCI bus) 2006 * VT6212L is found -- the CX700 core itself also contains a USB 2007 * host controller with the same PCI ID as the VT6212L. 2008 */ 2009 2010 /* Count VT6212L instances */ 2011 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2012 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2013 uint8_t b; 2014 2015 /* p should contain the first (internal) VT6212L -- see if we have 2016 an external one by searching again */ 2017 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2018 if (!p) 2019 return; 2020 pci_dev_put(p); 2021 2022 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2023 if (b & 0x40) { 2024 /* Turn off PCI Bus Parking */ 2025 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2026 2027 dev_info(&dev->dev, 2028 "Disabling VIA CX700 PCI parking\n"); 2029 } 2030 } 2031 2032 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2033 if (b != 0) { 2034 /* Turn off PCI Master read caching */ 2035 pci_write_config_byte(dev, 0x72, 0x0); 2036 2037 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2038 pci_write_config_byte(dev, 0x75, 0x1); 2039 2040 /* Disable "Read FIFO Timer" */ 2041 pci_write_config_byte(dev, 0x77, 0x0); 2042 2043 dev_info(&dev->dev, 2044 "Disabling VIA CX700 PCI caching\n"); 2045 } 2046 } 2047 } 2048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2049 2050 /* 2051 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2052 * VPD end tag will hang the device. This problem was initially 2053 * observed when a vpd entry was created in sysfs 2054 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2055 * will dump 32k of data. Reading a full 32k will cause an access 2056 * beyond the VPD end tag causing the device to hang. Once the device 2057 * is hung, the bnx2 driver will not be able to reset the device. 2058 * We believe that it is legal to read beyond the end tag and 2059 * therefore the solution is to limit the read/write length. 2060 */ 2061 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2062 { 2063 /* 2064 * Only disable the VPD capability for 5706, 5706S, 5708, 2065 * 5708S and 5709 rev. A 2066 */ 2067 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2068 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2069 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2070 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2071 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2072 (dev->revision & 0xf0) == 0x0)) { 2073 if (dev->vpd) 2074 dev->vpd->len = 0x80; 2075 } 2076 } 2077 2078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2079 PCI_DEVICE_ID_NX2_5706, 2080 quirk_brcm_570x_limit_vpd); 2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2082 PCI_DEVICE_ID_NX2_5706S, 2083 quirk_brcm_570x_limit_vpd); 2084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2085 PCI_DEVICE_ID_NX2_5708, 2086 quirk_brcm_570x_limit_vpd); 2087 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2088 PCI_DEVICE_ID_NX2_5708S, 2089 quirk_brcm_570x_limit_vpd); 2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2091 PCI_DEVICE_ID_NX2_5709, 2092 quirk_brcm_570x_limit_vpd); 2093 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2094 PCI_DEVICE_ID_NX2_5709S, 2095 quirk_brcm_570x_limit_vpd); 2096 2097 /* Originally in EDAC sources for i82875P: 2098 * Intel tells BIOS developers to hide device 6 which 2099 * configures the overflow device access containing 2100 * the DRBs - this is where we expose device 6. 2101 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2102 */ 2103 static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev) 2104 { 2105 u8 reg; 2106 2107 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2108 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2109 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2110 } 2111 } 2112 2113 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2114 quirk_unhide_mch_dev6); 2115 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2116 quirk_unhide_mch_dev6); 2117 2118 2119 #ifdef CONFIG_PCI_MSI 2120 /* Some chipsets do not support MSI. We cannot easily rely on setting 2121 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2122 * some other busses controlled by the chipset even if Linux is not 2123 * aware of it. Instead of setting the flag on all busses in the 2124 * machine, simply disable MSI globally. 2125 */ 2126 static void __init quirk_disable_all_msi(struct pci_dev *dev) 2127 { 2128 pci_no_msi(); 2129 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2130 } 2131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2138 2139 /* Disable MSI on chipsets that are known to not support it */ 2140 static void __devinit quirk_disable_msi(struct pci_dev *dev) 2141 { 2142 if (dev->subordinate) { 2143 dev_warn(&dev->dev, "MSI quirk detected; " 2144 "subordinate MSI disabled\n"); 2145 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2146 } 2147 } 2148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2151 2152 /* 2153 * The APC bridge device in AMD 780 family northbridges has some random 2154 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2155 * we use the possible vendor/device IDs of the host bridge for the 2156 * declared quirk, and search for the APC bridge by slot number. 2157 */ 2158 static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2159 { 2160 struct pci_dev *apc_bridge; 2161 2162 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2163 if (apc_bridge) { 2164 if (apc_bridge->device == 0x9602) 2165 quirk_disable_msi(apc_bridge); 2166 pci_dev_put(apc_bridge); 2167 } 2168 } 2169 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2171 2172 /* Go through the list of Hypertransport capabilities and 2173 * return 1 if a HT MSI capability is found and enabled */ 2174 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) 2175 { 2176 int pos, ttl = 48; 2177 2178 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2179 while (pos && ttl--) { 2180 u8 flags; 2181 2182 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2183 &flags) == 0) 2184 { 2185 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2186 flags & HT_MSI_FLAGS_ENABLE ? 2187 "enabled" : "disabled"); 2188 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2189 } 2190 2191 pos = pci_find_next_ht_capability(dev, pos, 2192 HT_CAPTYPE_MSI_MAPPING); 2193 } 2194 return 0; 2195 } 2196 2197 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2198 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 2199 { 2200 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2201 dev_warn(&dev->dev, "MSI quirk detected; " 2202 "subordinate MSI disabled\n"); 2203 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2204 } 2205 } 2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2207 quirk_msi_ht_cap); 2208 2209 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2210 * MSI are supported if the MSI capability set in any of these mappings. 2211 */ 2212 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2213 { 2214 struct pci_dev *pdev; 2215 2216 if (!dev->subordinate) 2217 return; 2218 2219 /* check HT MSI cap on this chipset and the root one. 2220 * a single one having MSI is enough to be sure that MSI are supported. 2221 */ 2222 pdev = pci_get_slot(dev->bus, 0); 2223 if (!pdev) 2224 return; 2225 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2226 dev_warn(&dev->dev, "MSI quirk detected; " 2227 "subordinate MSI disabled\n"); 2228 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2229 } 2230 pci_dev_put(pdev); 2231 } 2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2233 quirk_nvidia_ck804_msi_ht_cap); 2234 2235 /* Force enable MSI mapping capability on HT bridges */ 2236 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) 2237 { 2238 int pos, ttl = 48; 2239 2240 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2241 while (pos && ttl--) { 2242 u8 flags; 2243 2244 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2245 &flags) == 0) { 2246 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2247 2248 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2249 flags | HT_MSI_FLAGS_ENABLE); 2250 } 2251 pos = pci_find_next_ht_capability(dev, pos, 2252 HT_CAPTYPE_MSI_MAPPING); 2253 } 2254 } 2255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2256 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2257 ht_enable_msi_mapping); 2258 2259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2260 ht_enable_msi_mapping); 2261 2262 /* The P5N32-SLI motherboards from Asus have a problem with msi 2263 * for the MCP55 NIC. It is not yet determined whether the msi problem 2264 * also affects other devices. As for now, turn off msi for this device. 2265 */ 2266 static void __devinit nvenet_msi_disable(struct pci_dev *dev) 2267 { 2268 if (dmi_name_in_vendors("P5N32-SLI PREMIUM") || 2269 dmi_name_in_vendors("P5N32-E SLI")) { 2270 dev_info(&dev->dev, 2271 "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2272 dev->no_msi = 1; 2273 } 2274 } 2275 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2276 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2277 nvenet_msi_disable); 2278 2279 static int __devinit ht_check_msi_mapping(struct pci_dev *dev) 2280 { 2281 int pos, ttl = 48; 2282 int found = 0; 2283 2284 /* check if there is HT MSI cap or enabled on this device */ 2285 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2286 while (pos && ttl--) { 2287 u8 flags; 2288 2289 if (found < 1) 2290 found = 1; 2291 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2292 &flags) == 0) { 2293 if (flags & HT_MSI_FLAGS_ENABLE) { 2294 if (found < 2) { 2295 found = 2; 2296 break; 2297 } 2298 } 2299 } 2300 pos = pci_find_next_ht_capability(dev, pos, 2301 HT_CAPTYPE_MSI_MAPPING); 2302 } 2303 2304 return found; 2305 } 2306 2307 static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) 2308 { 2309 struct pci_dev *dev; 2310 int pos; 2311 int i, dev_no; 2312 int found = 0; 2313 2314 dev_no = host_bridge->devfn >> 3; 2315 for (i = dev_no + 1; i < 0x20; i++) { 2316 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2317 if (!dev) 2318 continue; 2319 2320 /* found next host bridge ?*/ 2321 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2322 if (pos != 0) { 2323 pci_dev_put(dev); 2324 break; 2325 } 2326 2327 if (ht_check_msi_mapping(dev)) { 2328 found = 1; 2329 pci_dev_put(dev); 2330 break; 2331 } 2332 pci_dev_put(dev); 2333 } 2334 2335 return found; 2336 } 2337 2338 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2339 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2340 2341 static int __devinit is_end_of_ht_chain(struct pci_dev *dev) 2342 { 2343 int pos, ctrl_off; 2344 int end = 0; 2345 u16 flags, ctrl; 2346 2347 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2348 2349 if (!pos) 2350 goto out; 2351 2352 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2353 2354 ctrl_off = ((flags >> 10) & 1) ? 2355 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2356 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2357 2358 if (ctrl & (1 << 6)) 2359 end = 1; 2360 2361 out: 2362 return end; 2363 } 2364 2365 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) 2366 { 2367 struct pci_dev *host_bridge; 2368 int pos; 2369 int i, dev_no; 2370 int found = 0; 2371 2372 dev_no = dev->devfn >> 3; 2373 for (i = dev_no; i >= 0; i--) { 2374 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2375 if (!host_bridge) 2376 continue; 2377 2378 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2379 if (pos != 0) { 2380 found = 1; 2381 break; 2382 } 2383 pci_dev_put(host_bridge); 2384 } 2385 2386 if (!found) 2387 return; 2388 2389 /* don't enable end_device/host_bridge with leaf directly here */ 2390 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2391 host_bridge_with_leaf(host_bridge)) 2392 goto out; 2393 2394 /* root did that ! */ 2395 if (msi_ht_cap_enabled(host_bridge)) 2396 goto out; 2397 2398 ht_enable_msi_mapping(dev); 2399 2400 out: 2401 pci_dev_put(host_bridge); 2402 } 2403 2404 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) 2405 { 2406 int pos, ttl = 48; 2407 2408 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2409 while (pos && ttl--) { 2410 u8 flags; 2411 2412 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2413 &flags) == 0) { 2414 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2415 2416 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2417 flags & ~HT_MSI_FLAGS_ENABLE); 2418 } 2419 pos = pci_find_next_ht_capability(dev, pos, 2420 HT_CAPTYPE_MSI_MAPPING); 2421 } 2422 } 2423 2424 static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2425 { 2426 struct pci_dev *host_bridge; 2427 int pos; 2428 int found; 2429 2430 if (!pci_msi_enabled()) 2431 return; 2432 2433 /* check if there is HT MSI cap or enabled on this device */ 2434 found = ht_check_msi_mapping(dev); 2435 2436 /* no HT MSI CAP */ 2437 if (found == 0) 2438 return; 2439 2440 /* 2441 * HT MSI mapping should be disabled on devices that are below 2442 * a non-Hypertransport host bridge. Locate the host bridge... 2443 */ 2444 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2445 if (host_bridge == NULL) { 2446 dev_warn(&dev->dev, 2447 "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2448 return; 2449 } 2450 2451 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2452 if (pos != 0) { 2453 /* Host bridge is to HT */ 2454 if (found == 1) { 2455 /* it is not enabled, try to enable it */ 2456 if (all) 2457 ht_enable_msi_mapping(dev); 2458 else 2459 nv_ht_enable_msi_mapping(dev); 2460 } 2461 return; 2462 } 2463 2464 /* HT MSI is not enabled */ 2465 if (found == 1) 2466 return; 2467 2468 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2469 ht_disable_msi_mapping(dev); 2470 } 2471 2472 static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2473 { 2474 return __nv_msi_ht_cap_quirk(dev, 1); 2475 } 2476 2477 static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2478 { 2479 return __nv_msi_ht_cap_quirk(dev, 0); 2480 } 2481 2482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2483 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2484 2485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2486 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2487 2488 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) 2489 { 2490 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2491 } 2492 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2493 { 2494 struct pci_dev *p; 2495 2496 /* SB700 MSI issue will be fixed at HW level from revision A21, 2497 * we need check PCI REVISION ID of SMBus controller to get SB700 2498 * revision. 2499 */ 2500 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2501 NULL); 2502 if (!p) 2503 return; 2504 2505 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2506 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2507 pci_dev_put(p); 2508 } 2509 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2510 PCI_DEVICE_ID_TIGON3_5780, 2511 quirk_msi_intx_disable_bug); 2512 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2513 PCI_DEVICE_ID_TIGON3_5780S, 2514 quirk_msi_intx_disable_bug); 2515 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2516 PCI_DEVICE_ID_TIGON3_5714, 2517 quirk_msi_intx_disable_bug); 2518 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2519 PCI_DEVICE_ID_TIGON3_5714S, 2520 quirk_msi_intx_disable_bug); 2521 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2522 PCI_DEVICE_ID_TIGON3_5715, 2523 quirk_msi_intx_disable_bug); 2524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2525 PCI_DEVICE_ID_TIGON3_5715S, 2526 quirk_msi_intx_disable_bug); 2527 2528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2529 quirk_msi_intx_disable_ati_bug); 2530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2531 quirk_msi_intx_disable_ati_bug); 2532 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2533 quirk_msi_intx_disable_ati_bug); 2534 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2535 quirk_msi_intx_disable_ati_bug); 2536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2537 quirk_msi_intx_disable_ati_bug); 2538 2539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2540 quirk_msi_intx_disable_bug); 2541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2542 quirk_msi_intx_disable_bug); 2543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2544 quirk_msi_intx_disable_bug); 2545 2546 #endif /* CONFIG_PCI_MSI */ 2547 2548 #ifdef CONFIG_PCI_IOV 2549 2550 /* 2551 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the 2552 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the 2553 * old Flash Memory Space. 2554 */ 2555 static void __devinit quirk_i82576_sriov(struct pci_dev *dev) 2556 { 2557 int pos, flags; 2558 u32 bar, start, size; 2559 2560 if (PAGE_SIZE > 0x10000) 2561 return; 2562 2563 flags = pci_resource_flags(dev, 0); 2564 if ((flags & PCI_BASE_ADDRESS_SPACE) != 2565 PCI_BASE_ADDRESS_SPACE_MEMORY || 2566 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) != 2567 PCI_BASE_ADDRESS_MEM_TYPE_32) 2568 return; 2569 2570 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); 2571 if (!pos) 2572 return; 2573 2574 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar); 2575 if (bar & PCI_BASE_ADDRESS_MEM_MASK) 2576 return; 2577 2578 start = pci_resource_start(dev, 1); 2579 size = pci_resource_len(dev, 1); 2580 if (!start || size != 0x400000 || start & (size - 1)) 2581 return; 2582 2583 pci_resource_flags(dev, 1) = 0; 2584 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); 2585 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start); 2586 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2); 2587 2588 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n"); 2589 } 2590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov); 2591 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov); 2592 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov); 2593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov); 2594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov); 2595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov); 2596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov); 2597 2598 #endif /* CONFIG_PCI_IOV */ 2599 2600 /* Allow manual resource allocation for PCI hotplug bridges 2601 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2602 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2603 * kernel fails to allocate resources when hotplug device is 2604 * inserted and PCI bus is rescanned. 2605 */ 2606 static void __devinit quirk_hotplug_bridge(struct pci_dev *dev) 2607 { 2608 dev->is_hotplug_bridge = 1; 2609 } 2610 2611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2612 2613 /* 2614 * This is a quirk for the Ricoh MMC controller found as a part of 2615 * some mulifunction chips. 2616 2617 * This is very similiar and based on the ricoh_mmc driver written by 2618 * Philip Langdale. Thank you for these magic sequences. 2619 * 2620 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2621 * and one or both of cardbus or firewire. 2622 * 2623 * It happens that they implement SD and MMC 2624 * support as separate controllers (and PCI functions). The linux SDHCI 2625 * driver supports MMC cards but the chip detects MMC cards in hardware 2626 * and directs them to the MMC controller - so the SDHCI driver never sees 2627 * them. 2628 * 2629 * To get around this, we must disable the useless MMC controller. 2630 * At that point, the SDHCI controller will start seeing them 2631 * It seems to be the case that the relevant PCI registers to deactivate the 2632 * MMC controller live on PCI function 0, which might be the cardbus controller 2633 * or the firewire controller, depending on the particular chip in question 2634 * 2635 * This has to be done early, because as soon as we disable the MMC controller 2636 * other pci functions shift up one level, e.g. function #2 becomes function 2637 * #1, and this will confuse the pci core. 2638 */ 2639 2640 #ifdef CONFIG_MMC_RICOH_MMC 2641 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2642 { 2643 /* disable via cardbus interface */ 2644 u8 write_enable; 2645 u8 write_target; 2646 u8 disable; 2647 2648 /* disable must be done via function #0 */ 2649 if (PCI_FUNC(dev->devfn)) 2650 return; 2651 2652 pci_read_config_byte(dev, 0xB7, &disable); 2653 if (disable & 0x02) 2654 return; 2655 2656 pci_read_config_byte(dev, 0x8E, &write_enable); 2657 pci_write_config_byte(dev, 0x8E, 0xAA); 2658 pci_read_config_byte(dev, 0x8D, &write_target); 2659 pci_write_config_byte(dev, 0x8D, 0xB7); 2660 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2661 pci_write_config_byte(dev, 0x8E, write_enable); 2662 pci_write_config_byte(dev, 0x8D, write_target); 2663 2664 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2665 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2666 } 2667 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2668 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2669 2670 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2671 { 2672 /* disable via firewire interface */ 2673 u8 write_enable; 2674 u8 disable; 2675 2676 /* disable must be done via function #0 */ 2677 if (PCI_FUNC(dev->devfn)) 2678 return; 2679 2680 pci_read_config_byte(dev, 0xCB, &disable); 2681 2682 if (disable & 0x02) 2683 return; 2684 2685 pci_read_config_byte(dev, 0xCA, &write_enable); 2686 pci_write_config_byte(dev, 0xCA, 0x57); 2687 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2688 pci_write_config_byte(dev, 0xCA, write_enable); 2689 2690 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2691 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2692 } 2693 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2694 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2695 #endif /*CONFIG_MMC_RICOH_MMC*/ 2696 2697 2698 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2699 struct pci_fixup *end) 2700 { 2701 while (f < end) { 2702 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 2703 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 2704 dev_dbg(&dev->dev, "calling %pF\n", f->hook); 2705 f->hook(dev); 2706 } 2707 f++; 2708 } 2709 } 2710 2711 extern struct pci_fixup __start_pci_fixups_early[]; 2712 extern struct pci_fixup __end_pci_fixups_early[]; 2713 extern struct pci_fixup __start_pci_fixups_header[]; 2714 extern struct pci_fixup __end_pci_fixups_header[]; 2715 extern struct pci_fixup __start_pci_fixups_final[]; 2716 extern struct pci_fixup __end_pci_fixups_final[]; 2717 extern struct pci_fixup __start_pci_fixups_enable[]; 2718 extern struct pci_fixup __end_pci_fixups_enable[]; 2719 extern struct pci_fixup __start_pci_fixups_resume[]; 2720 extern struct pci_fixup __end_pci_fixups_resume[]; 2721 extern struct pci_fixup __start_pci_fixups_resume_early[]; 2722 extern struct pci_fixup __end_pci_fixups_resume_early[]; 2723 extern struct pci_fixup __start_pci_fixups_suspend[]; 2724 extern struct pci_fixup __end_pci_fixups_suspend[]; 2725 2726 2727 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 2728 { 2729 struct pci_fixup *start, *end; 2730 2731 switch(pass) { 2732 case pci_fixup_early: 2733 start = __start_pci_fixups_early; 2734 end = __end_pci_fixups_early; 2735 break; 2736 2737 case pci_fixup_header: 2738 start = __start_pci_fixups_header; 2739 end = __end_pci_fixups_header; 2740 break; 2741 2742 case pci_fixup_final: 2743 start = __start_pci_fixups_final; 2744 end = __end_pci_fixups_final; 2745 break; 2746 2747 case pci_fixup_enable: 2748 start = __start_pci_fixups_enable; 2749 end = __end_pci_fixups_enable; 2750 break; 2751 2752 case pci_fixup_resume: 2753 start = __start_pci_fixups_resume; 2754 end = __end_pci_fixups_resume; 2755 break; 2756 2757 case pci_fixup_resume_early: 2758 start = __start_pci_fixups_resume_early; 2759 end = __end_pci_fixups_resume_early; 2760 break; 2761 2762 case pci_fixup_suspend: 2763 start = __start_pci_fixups_suspend; 2764 end = __end_pci_fixups_suspend; 2765 break; 2766 2767 default: 2768 /* stupid compiler warning, you would think with an enum... */ 2769 return; 2770 } 2771 pci_do_fixups(dev, start, end); 2772 } 2773 EXPORT_SYMBOL(pci_fixup_device); 2774 2775 static int __init pci_apply_final_quirks(void) 2776 { 2777 struct pci_dev *dev = NULL; 2778 u8 cls = 0; 2779 u8 tmp; 2780 2781 if (pci_cache_line_size) 2782 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 2783 pci_cache_line_size << 2); 2784 2785 for_each_pci_dev(dev) { 2786 pci_fixup_device(pci_fixup_final, dev); 2787 /* 2788 * If arch hasn't set it explicitly yet, use the CLS 2789 * value shared by all PCI devices. If there's a 2790 * mismatch, fall back to the default value. 2791 */ 2792 if (!pci_cache_line_size) { 2793 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 2794 if (!cls) 2795 cls = tmp; 2796 if (!tmp || cls == tmp) 2797 continue; 2798 2799 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), " 2800 "using %u bytes\n", cls << 2, tmp << 2, 2801 pci_dfl_cache_line_size << 2); 2802 pci_cache_line_size = pci_dfl_cache_line_size; 2803 } 2804 } 2805 if (!pci_cache_line_size) { 2806 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 2807 cls << 2, pci_dfl_cache_line_size << 2); 2808 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 2809 } 2810 2811 return 0; 2812 } 2813 2814 fs_initcall_sync(pci_apply_final_quirks); 2815 2816 /* 2817 * Followings are device-specific reset methods which can be used to 2818 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 2819 * not available. 2820 */ 2821 static int reset_intel_generic_dev(struct pci_dev *dev, int probe) 2822 { 2823 int pos; 2824 2825 /* only implement PCI_CLASS_SERIAL_USB at present */ 2826 if (dev->class == PCI_CLASS_SERIAL_USB) { 2827 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 2828 if (!pos) 2829 return -ENOTTY; 2830 2831 if (probe) 2832 return 0; 2833 2834 pci_write_config_byte(dev, pos + 0x4, 1); 2835 msleep(100); 2836 2837 return 0; 2838 } else { 2839 return -ENOTTY; 2840 } 2841 } 2842 2843 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 2844 { 2845 int pos; 2846 2847 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 2848 if (!pos) 2849 return -ENOTTY; 2850 2851 if (probe) 2852 return 0; 2853 2854 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, 2855 PCI_EXP_DEVCTL_BCR_FLR); 2856 msleep(100); 2857 2858 return 0; 2859 } 2860 2861 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 2862 2863 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 2864 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 2865 reset_intel_82599_sfp_virtfn }, 2866 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2867 reset_intel_generic_dev }, 2868 { 0 } 2869 }; 2870 2871 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 2872 { 2873 const struct pci_dev_reset_methods *i; 2874 2875 for (i = pci_dev_reset_methods; i->reset; i++) { 2876 if ((i->vendor == dev->vendor || 2877 i->vendor == (u16)PCI_ANY_ID) && 2878 (i->device == dev->device || 2879 i->device == (u16)PCI_ANY_ID)) 2880 return i->reset(dev, probe); 2881 } 2882 2883 return -ENOTTY; 2884 } 2885