1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/acpi.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <linux/mm.h> 28 #include <linux/platform_data/x86/apple.h> 29 #include <linux/pm_runtime.h> 30 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 31 #include "pci.h" 32 33 static ktime_t fixup_debug_start(struct pci_dev *dev, 34 void (*fn)(struct pci_dev *dev)) 35 { 36 if (initcall_debug) 37 pci_info(dev, "calling %pF @ %i\n", fn, task_pid_nr(current)); 38 39 return ktime_get(); 40 } 41 42 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 43 void (*fn)(struct pci_dev *dev)) 44 { 45 ktime_t delta, rettime; 46 unsigned long long duration; 47 48 rettime = ktime_get(); 49 delta = ktime_sub(rettime, calltime); 50 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 51 if (initcall_debug || duration > 10000) 52 pci_info(dev, "%pF took %lld usecs\n", fn, duration); 53 } 54 55 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 56 struct pci_fixup *end) 57 { 58 ktime_t calltime; 59 60 for (; f < end; f++) 61 if ((f->class == (u32) (dev->class >> f->class_shift) || 62 f->class == (u32) PCI_ANY_ID) && 63 (f->vendor == dev->vendor || 64 f->vendor == (u16) PCI_ANY_ID) && 65 (f->device == dev->device || 66 f->device == (u16) PCI_ANY_ID)) { 67 calltime = fixup_debug_start(dev, f->hook); 68 f->hook(dev); 69 fixup_debug_report(dev, calltime, f->hook); 70 } 71 } 72 73 extern struct pci_fixup __start_pci_fixups_early[]; 74 extern struct pci_fixup __end_pci_fixups_early[]; 75 extern struct pci_fixup __start_pci_fixups_header[]; 76 extern struct pci_fixup __end_pci_fixups_header[]; 77 extern struct pci_fixup __start_pci_fixups_final[]; 78 extern struct pci_fixup __end_pci_fixups_final[]; 79 extern struct pci_fixup __start_pci_fixups_enable[]; 80 extern struct pci_fixup __end_pci_fixups_enable[]; 81 extern struct pci_fixup __start_pci_fixups_resume[]; 82 extern struct pci_fixup __end_pci_fixups_resume[]; 83 extern struct pci_fixup __start_pci_fixups_resume_early[]; 84 extern struct pci_fixup __end_pci_fixups_resume_early[]; 85 extern struct pci_fixup __start_pci_fixups_suspend[]; 86 extern struct pci_fixup __end_pci_fixups_suspend[]; 87 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 88 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 89 90 static bool pci_apply_fixup_final_quirks; 91 92 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 93 { 94 struct pci_fixup *start, *end; 95 96 switch (pass) { 97 case pci_fixup_early: 98 start = __start_pci_fixups_early; 99 end = __end_pci_fixups_early; 100 break; 101 102 case pci_fixup_header: 103 start = __start_pci_fixups_header; 104 end = __end_pci_fixups_header; 105 break; 106 107 case pci_fixup_final: 108 if (!pci_apply_fixup_final_quirks) 109 return; 110 start = __start_pci_fixups_final; 111 end = __end_pci_fixups_final; 112 break; 113 114 case pci_fixup_enable: 115 start = __start_pci_fixups_enable; 116 end = __end_pci_fixups_enable; 117 break; 118 119 case pci_fixup_resume: 120 start = __start_pci_fixups_resume; 121 end = __end_pci_fixups_resume; 122 break; 123 124 case pci_fixup_resume_early: 125 start = __start_pci_fixups_resume_early; 126 end = __end_pci_fixups_resume_early; 127 break; 128 129 case pci_fixup_suspend: 130 start = __start_pci_fixups_suspend; 131 end = __end_pci_fixups_suspend; 132 break; 133 134 case pci_fixup_suspend_late: 135 start = __start_pci_fixups_suspend_late; 136 end = __end_pci_fixups_suspend_late; 137 break; 138 139 default: 140 /* stupid compiler warning, you would think with an enum... */ 141 return; 142 } 143 pci_do_fixups(dev, start, end); 144 } 145 EXPORT_SYMBOL(pci_fixup_device); 146 147 static int __init pci_apply_final_quirks(void) 148 { 149 struct pci_dev *dev = NULL; 150 u8 cls = 0; 151 u8 tmp; 152 153 if (pci_cache_line_size) 154 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 155 pci_cache_line_size << 2); 156 157 pci_apply_fixup_final_quirks = true; 158 for_each_pci_dev(dev) { 159 pci_fixup_device(pci_fixup_final, dev); 160 /* 161 * If arch hasn't set it explicitly yet, use the CLS 162 * value shared by all PCI devices. If there's a 163 * mismatch, fall back to the default value. 164 */ 165 if (!pci_cache_line_size) { 166 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 167 if (!cls) 168 cls = tmp; 169 if (!tmp || cls == tmp) 170 continue; 171 172 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 173 cls << 2, tmp << 2, 174 pci_dfl_cache_line_size << 2); 175 pci_cache_line_size = pci_dfl_cache_line_size; 176 } 177 } 178 179 if (!pci_cache_line_size) { 180 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 181 cls << 2, pci_dfl_cache_line_size << 2); 182 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 183 } 184 185 return 0; 186 } 187 fs_initcall_sync(pci_apply_final_quirks); 188 189 /* 190 * Decoding should be disabled for a PCI device during BAR sizing to avoid 191 * conflict. But doing so may cause problems on host bridge and perhaps other 192 * key system devices. For devices that need to have mmio decoding always-on, 193 * we need to set the dev->mmio_always_on bit. 194 */ 195 static void quirk_mmio_always_on(struct pci_dev *dev) 196 { 197 dev->mmio_always_on = 1; 198 } 199 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 200 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 201 202 /* 203 * The Mellanox Tavor device gives false positive parity errors. Mark this 204 * device with a broken_parity_status to allow PCI scanning code to "skip" 205 * this now blacklisted device. 206 */ 207 static void quirk_mellanox_tavor(struct pci_dev *dev) 208 { 209 dev->broken_parity_status = 1; /* This device gives false positives */ 210 } 211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 213 214 /* 215 * Deal with broken BIOSes that neglect to enable passive release, 216 * which can cause problems in combination with the 82441FX/PPro MTRRs 217 */ 218 static void quirk_passive_release(struct pci_dev *dev) 219 { 220 struct pci_dev *d = NULL; 221 unsigned char dlc; 222 223 /* 224 * We have to make sure a particular bit is set in the PIIX3 225 * ISA bridge, so we have to go out and find it. 226 */ 227 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 228 pci_read_config_byte(d, 0x82, &dlc); 229 if (!(dlc & 1<<1)) { 230 pci_info(d, "PIIX3: Enabling Passive Release\n"); 231 dlc |= 1<<1; 232 pci_write_config_byte(d, 0x82, dlc); 233 } 234 } 235 } 236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 237 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 238 239 /* 240 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 241 * workaround but VIA don't answer queries. If you happen to have good 242 * contacts at VIA ask them for me please -- Alan 243 * 244 * This appears to be BIOS not version dependent. So presumably there is a 245 * chipset level fix. 246 */ 247 static void quirk_isa_dma_hangs(struct pci_dev *dev) 248 { 249 if (!isa_dma_bridge_buggy) { 250 isa_dma_bridge_buggy = 1; 251 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 252 } 253 } 254 /* 255 * It's not totally clear which chipsets are the problematic ones. We know 256 * 82C586 and 82C596 variants are affected. 257 */ 258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 265 266 /* 267 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 268 * for some HT machines to use C4 w/o hanging. 269 */ 270 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 271 { 272 u32 pmbase; 273 u16 pm1a; 274 275 pci_read_config_dword(dev, 0x40, &pmbase); 276 pmbase = pmbase & 0xff80; 277 pm1a = inw(pmbase); 278 279 if (pm1a & 0x10) { 280 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 281 outw(0x10, pmbase); 282 } 283 } 284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 285 286 /* Chipsets where PCI->PCI transfers vanish or hang */ 287 static void quirk_nopcipci(struct pci_dev *dev) 288 { 289 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 290 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 291 pci_pci_problems |= PCIPCI_FAIL; 292 } 293 } 294 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 295 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 296 297 static void quirk_nopciamd(struct pci_dev *dev) 298 { 299 u8 rev; 300 pci_read_config_byte(dev, 0x08, &rev); 301 if (rev == 0x13) { 302 /* Erratum 24 */ 303 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 304 pci_pci_problems |= PCIAGP_FAIL; 305 } 306 } 307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 308 309 /* Triton requires workarounds to be used by the drivers */ 310 static void quirk_triton(struct pci_dev *dev) 311 { 312 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 313 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 314 pci_pci_problems |= PCIPCI_TRITON; 315 } 316 } 317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 321 322 /* 323 * VIA Apollo KT133 needs PCI latency patch 324 * Made according to a Windows driver-based patch by George E. Breese; 325 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 326 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 327 * which Mr Breese based his work. 328 * 329 * Updated based on further information from the site and also on 330 * information provided by VIA 331 */ 332 static void quirk_vialatency(struct pci_dev *dev) 333 { 334 struct pci_dev *p; 335 u8 busarb; 336 337 /* 338 * Ok, we have a potential problem chipset here. Now see if we have 339 * a buggy southbridge. 340 */ 341 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 342 if (p != NULL) { 343 344 /* 345 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 346 * thanks Dan Hollis. 347 * Check for buggy part revisions 348 */ 349 if (p->revision < 0x40 || p->revision > 0x42) 350 goto exit; 351 } else { 352 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 353 if (p == NULL) /* No problem parts */ 354 goto exit; 355 356 /* Check for buggy part revisions */ 357 if (p->revision < 0x10 || p->revision > 0x12) 358 goto exit; 359 } 360 361 /* 362 * Ok we have the problem. Now set the PCI master grant to occur 363 * every master grant. The apparent bug is that under high PCI load 364 * (quite common in Linux of course) you can get data loss when the 365 * CPU is held off the bus for 3 bus master requests. This happens 366 * to include the IDE controllers.... 367 * 368 * VIA only apply this fix when an SB Live! is present but under 369 * both Linux and Windows this isn't enough, and we have seen 370 * corruption without SB Live! but with things like 3 UDMA IDE 371 * controllers. So we ignore that bit of the VIA recommendation.. 372 */ 373 pci_read_config_byte(dev, 0x76, &busarb); 374 375 /* 376 * Set bit 4 and bit 5 of byte 76 to 0x01 377 * "Master priority rotation on every PCI master grant" 378 */ 379 busarb &= ~(1<<5); 380 busarb |= (1<<4); 381 pci_write_config_byte(dev, 0x76, busarb); 382 pci_info(dev, "Applying VIA southbridge workaround\n"); 383 exit: 384 pci_dev_put(p); 385 } 386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 389 /* Must restore this on a resume from RAM */ 390 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 391 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 392 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 393 394 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 395 static void quirk_viaetbf(struct pci_dev *dev) 396 { 397 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 398 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 399 pci_pci_problems |= PCIPCI_VIAETBF; 400 } 401 } 402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 403 404 static void quirk_vsfx(struct pci_dev *dev) 405 { 406 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 407 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 408 pci_pci_problems |= PCIPCI_VSFX; 409 } 410 } 411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 412 413 /* 414 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 415 * space. Latency must be set to 0xA and Triton workaround applied too. 416 * [Info kindly provided by ALi] 417 */ 418 static void quirk_alimagik(struct pci_dev *dev) 419 { 420 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 421 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 422 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 423 } 424 } 425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 427 428 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 429 static void quirk_natoma(struct pci_dev *dev) 430 { 431 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 432 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 433 pci_pci_problems |= PCIPCI_NATOMA; 434 } 435 } 436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 442 443 /* 444 * This chip can cause PCI parity errors if config register 0xA0 is read 445 * while DMAs are occurring. 446 */ 447 static void quirk_citrine(struct pci_dev *dev) 448 { 449 dev->cfg_size = 0xA0; 450 } 451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 452 453 /* 454 * This chip can cause bus lockups if config addresses above 0x600 455 * are read or written. 456 */ 457 static void quirk_nfp6000(struct pci_dev *dev) 458 { 459 dev->cfg_size = 0x600; 460 } 461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 464 465 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 466 static void quirk_extend_bar_to_page(struct pci_dev *dev) 467 { 468 int i; 469 470 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) { 471 struct resource *r = &dev->resource[i]; 472 473 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 474 r->end = PAGE_SIZE - 1; 475 r->start = 0; 476 r->flags |= IORESOURCE_UNSET; 477 pci_info(dev, "expanded BAR %d to page size: %pR\n", 478 i, r); 479 } 480 } 481 } 482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 483 484 /* 485 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 486 * If it's needed, re-allocate the region. 487 */ 488 static void quirk_s3_64M(struct pci_dev *dev) 489 { 490 struct resource *r = &dev->resource[0]; 491 492 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 493 r->flags |= IORESOURCE_UNSET; 494 r->start = 0; 495 r->end = 0x3ffffff; 496 } 497 } 498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 500 501 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 502 const char *name) 503 { 504 u32 region; 505 struct pci_bus_region bus_region; 506 struct resource *res = dev->resource + pos; 507 508 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 509 510 if (!region) 511 return; 512 513 res->name = pci_name(dev); 514 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 515 res->flags |= 516 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 517 region &= ~(size - 1); 518 519 /* Convert from PCI bus to resource space */ 520 bus_region.start = region; 521 bus_region.end = region + size - 1; 522 pcibios_bus_to_resource(dev->bus, res, &bus_region); 523 524 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 525 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 526 } 527 528 /* 529 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 530 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 531 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 532 * (which conflicts w/ BAR1's memory range). 533 * 534 * CS553x's ISA PCI BARs may also be read-only (ref: 535 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 536 */ 537 static void quirk_cs5536_vsa(struct pci_dev *dev) 538 { 539 static char *name = "CS5536 ISA bridge"; 540 541 if (pci_resource_len(dev, 0) != 8) { 542 quirk_io(dev, 0, 8, name); /* SMB */ 543 quirk_io(dev, 1, 256, name); /* GPIO */ 544 quirk_io(dev, 2, 64, name); /* MFGPT */ 545 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 546 name); 547 } 548 } 549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 550 551 static void quirk_io_region(struct pci_dev *dev, int port, 552 unsigned size, int nr, const char *name) 553 { 554 u16 region; 555 struct pci_bus_region bus_region; 556 struct resource *res = dev->resource + nr; 557 558 pci_read_config_word(dev, port, ®ion); 559 region &= ~(size - 1); 560 561 if (!region) 562 return; 563 564 res->name = pci_name(dev); 565 res->flags = IORESOURCE_IO; 566 567 /* Convert from PCI bus to resource space */ 568 bus_region.start = region; 569 bus_region.end = region + size - 1; 570 pcibios_bus_to_resource(dev->bus, res, &bus_region); 571 572 if (!pci_claim_resource(dev, nr)) 573 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 574 } 575 576 /* 577 * ATI Northbridge setups MCE the processor if you even read somewhere 578 * between 0x3b0->0x3bb or read 0x3d3 579 */ 580 static void quirk_ati_exploding_mce(struct pci_dev *dev) 581 { 582 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 583 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 584 request_region(0x3b0, 0x0C, "RadeonIGP"); 585 request_region(0x3d3, 0x01, "RadeonIGP"); 586 } 587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 588 589 /* 590 * In the AMD NL platform, this device ([1022:7912]) has a class code of 591 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 592 * claim it. 593 * 594 * But the dwc3 driver is a more specific driver for this device, and we'd 595 * prefer to use it instead of xhci. To prevent xhci from claiming the 596 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 597 * defines as "USB device (not host controller)". The dwc3 driver can then 598 * claim it based on its Vendor and Device ID. 599 */ 600 static void quirk_amd_nl_class(struct pci_dev *pdev) 601 { 602 u32 class = pdev->class; 603 604 /* Use "USB Device (not host controller)" class */ 605 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 606 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 607 class, pdev->class); 608 } 609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 610 quirk_amd_nl_class); 611 612 /* 613 * Let's make the southbridge information explicit instead of having to 614 * worry about people probing the ACPI areas, for example.. (Yes, it 615 * happens, and if you read the wrong ACPI register it will put the machine 616 * to sleep with no way of waking it up again. Bummer). 617 * 618 * ALI M7101: Two IO regions pointed to by words at 619 * 0xE0 (64 bytes of ACPI registers) 620 * 0xE2 (32 bytes of SMB registers) 621 */ 622 static void quirk_ali7101_acpi(struct pci_dev *dev) 623 { 624 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 625 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 626 } 627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 628 629 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 630 { 631 u32 devres; 632 u32 mask, size, base; 633 634 pci_read_config_dword(dev, port, &devres); 635 if ((devres & enable) != enable) 636 return; 637 mask = (devres >> 16) & 15; 638 base = devres & 0xffff; 639 size = 16; 640 for (;;) { 641 unsigned bit = size >> 1; 642 if ((bit & mask) == bit) 643 break; 644 size = bit; 645 } 646 /* 647 * For now we only print it out. Eventually we'll want to 648 * reserve it (at least if it's in the 0x1000+ range), but 649 * let's get enough confirmation reports first. 650 */ 651 base &= -size; 652 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 653 } 654 655 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 656 { 657 u32 devres; 658 u32 mask, size, base; 659 660 pci_read_config_dword(dev, port, &devres); 661 if ((devres & enable) != enable) 662 return; 663 base = devres & 0xffff0000; 664 mask = (devres & 0x3f) << 16; 665 size = 128 << 16; 666 for (;;) { 667 unsigned bit = size >> 1; 668 if ((bit & mask) == bit) 669 break; 670 size = bit; 671 } 672 673 /* 674 * For now we only print it out. Eventually we'll want to 675 * reserve it, but let's get enough confirmation reports first. 676 */ 677 base &= -size; 678 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 679 } 680 681 /* 682 * PIIX4 ACPI: Two IO regions pointed to by longwords at 683 * 0x40 (64 bytes of ACPI registers) 684 * 0x90 (16 bytes of SMB registers) 685 * and a few strange programmable PIIX4 device resources. 686 */ 687 static void quirk_piix4_acpi(struct pci_dev *dev) 688 { 689 u32 res_a; 690 691 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 692 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 693 694 /* Device resource A has enables for some of the other ones */ 695 pci_read_config_dword(dev, 0x5c, &res_a); 696 697 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 698 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 699 700 /* Device resource D is just bitfields for static resources */ 701 702 /* Device 12 enabled? */ 703 if (res_a & (1 << 29)) { 704 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 705 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 706 } 707 /* Device 13 enabled? */ 708 if (res_a & (1 << 30)) { 709 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 710 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 711 } 712 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 713 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 714 } 715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 716 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 717 718 #define ICH_PMBASE 0x40 719 #define ICH_ACPI_CNTL 0x44 720 #define ICH4_ACPI_EN 0x10 721 #define ICH6_ACPI_EN 0x80 722 #define ICH4_GPIOBASE 0x58 723 #define ICH4_GPIO_CNTL 0x5c 724 #define ICH4_GPIO_EN 0x10 725 #define ICH6_GPIOBASE 0x48 726 #define ICH6_GPIO_CNTL 0x4c 727 #define ICH6_GPIO_EN 0x10 728 729 /* 730 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 731 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 732 * 0x58 (64 bytes of GPIO I/O space) 733 */ 734 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 735 { 736 u8 enable; 737 738 /* 739 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 740 * with low legacy (and fixed) ports. We don't know the decoding 741 * priority and can't tell whether the legacy device or the one created 742 * here is really at that address. This happens on boards with broken 743 * BIOSes. 744 */ 745 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 746 if (enable & ICH4_ACPI_EN) 747 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 748 "ICH4 ACPI/GPIO/TCO"); 749 750 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 751 if (enable & ICH4_GPIO_EN) 752 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 753 "ICH4 GPIO"); 754 } 755 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 757 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 760 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 761 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 764 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 765 766 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 767 { 768 u8 enable; 769 770 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 771 if (enable & ICH6_ACPI_EN) 772 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 773 "ICH6 ACPI/GPIO/TCO"); 774 775 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 776 if (enable & ICH6_GPIO_EN) 777 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 778 "ICH6 GPIO"); 779 } 780 781 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 782 const char *name, int dynsize) 783 { 784 u32 val; 785 u32 size, base; 786 787 pci_read_config_dword(dev, reg, &val); 788 789 /* Enabled? */ 790 if (!(val & 1)) 791 return; 792 base = val & 0xfffc; 793 if (dynsize) { 794 /* 795 * This is not correct. It is 16, 32 or 64 bytes depending on 796 * register D31:F0:ADh bits 5:4. 797 * 798 * But this gets us at least _part_ of it. 799 */ 800 size = 16; 801 } else { 802 size = 128; 803 } 804 base &= ~(size-1); 805 806 /* 807 * Just print it out for now. We should reserve it after more 808 * debugging. 809 */ 810 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 811 } 812 813 static void quirk_ich6_lpc(struct pci_dev *dev) 814 { 815 /* Shared ACPI/GPIO decode with all ICH6+ */ 816 ich6_lpc_acpi_gpio(dev); 817 818 /* ICH6-specific generic IO decode */ 819 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 820 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 821 } 822 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 824 825 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 826 const char *name) 827 { 828 u32 val; 829 u32 mask, base; 830 831 pci_read_config_dword(dev, reg, &val); 832 833 /* Enabled? */ 834 if (!(val & 1)) 835 return; 836 837 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 838 base = val & 0xfffc; 839 mask = (val >> 16) & 0xfc; 840 mask |= 3; 841 842 /* 843 * Just print it out for now. We should reserve it after more 844 * debugging. 845 */ 846 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 847 } 848 849 /* ICH7-10 has the same common LPC generic IO decode registers */ 850 static void quirk_ich7_lpc(struct pci_dev *dev) 851 { 852 /* We share the common ACPI/GPIO decode with ICH6 */ 853 ich6_lpc_acpi_gpio(dev); 854 855 /* And have 4 ICH7+ generic decodes */ 856 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 857 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 858 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 859 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 860 } 861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 862 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 874 875 /* 876 * VIA ACPI: One IO region pointed to by longword at 877 * 0x48 or 0x20 (256 bytes of ACPI registers) 878 */ 879 static void quirk_vt82c586_acpi(struct pci_dev *dev) 880 { 881 if (dev->revision & 0x10) 882 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 883 "vt82c586 ACPI"); 884 } 885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 886 887 /* 888 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 889 * 0x48 (256 bytes of ACPI registers) 890 * 0x70 (128 bytes of hardware monitoring register) 891 * 0x90 (16 bytes of SMB registers) 892 */ 893 static void quirk_vt82c686_acpi(struct pci_dev *dev) 894 { 895 quirk_vt82c586_acpi(dev); 896 897 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 898 "vt82c686 HW-mon"); 899 900 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 901 } 902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 903 904 /* 905 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 906 * 0x88 (128 bytes of power management registers) 907 * 0xd0 (16 bytes of SMB registers) 908 */ 909 static void quirk_vt8235_acpi(struct pci_dev *dev) 910 { 911 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 912 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 913 } 914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 915 916 /* 917 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 918 * back-to-back: Disable fast back-to-back on the secondary bus segment 919 */ 920 static void quirk_xio2000a(struct pci_dev *dev) 921 { 922 struct pci_dev *pdev; 923 u16 command; 924 925 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 926 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 927 pci_read_config_word(pdev, PCI_COMMAND, &command); 928 if (command & PCI_COMMAND_FAST_BACK) 929 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 930 } 931 } 932 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 933 quirk_xio2000a); 934 935 #ifdef CONFIG_X86_IO_APIC 936 937 #include <asm/io_apic.h> 938 939 /* 940 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 941 * devices to the external APIC. 942 * 943 * TODO: When we have device-specific interrupt routers, this code will go 944 * away from quirks. 945 */ 946 static void quirk_via_ioapic(struct pci_dev *dev) 947 { 948 u8 tmp; 949 950 if (nr_ioapics < 1) 951 tmp = 0; /* nothing routed to external APIC */ 952 else 953 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 954 955 pci_info(dev, "%sbling VIA external APIC routing\n", 956 tmp == 0 ? "Disa" : "Ena"); 957 958 /* Offset 0x58: External APIC IRQ output control */ 959 pci_write_config_byte(dev, 0x58, tmp); 960 } 961 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 962 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 963 964 /* 965 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 966 * This leads to doubled level interrupt rates. 967 * Set this bit to get rid of cycle wastage. 968 * Otherwise uncritical. 969 */ 970 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 971 { 972 u8 misc_control2; 973 #define BYPASS_APIC_DEASSERT 8 974 975 pci_read_config_byte(dev, 0x5B, &misc_control2); 976 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 977 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 978 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 979 } 980 } 981 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 982 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 983 984 /* 985 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 986 * We check all revs >= B0 (yet not in the pre production!) as the bug 987 * is currently marked NoFix 988 * 989 * We have multiple reports of hangs with this chipset that went away with 990 * noapic specified. For the moment we assume it's the erratum. We may be wrong 991 * of course. However the advice is demonstrably good even if so. 992 */ 993 static void quirk_amd_ioapic(struct pci_dev *dev) 994 { 995 if (dev->revision >= 0x02) { 996 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 997 pci_warn(dev, " : booting with the \"noapic\" option\n"); 998 } 999 } 1000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1001 #endif /* CONFIG_X86_IO_APIC */ 1002 1003 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1004 1005 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1006 { 1007 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1008 if (dev->subsystem_device == 0xa118) 1009 dev->sriov->link = dev->devfn; 1010 } 1011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1012 #endif 1013 1014 /* 1015 * Some settings of MMRBC can lead to data corruption so block changes. 1016 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1017 */ 1018 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1019 { 1020 if (dev->subordinate && dev->revision <= 0x12) { 1021 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1022 dev->revision); 1023 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1024 } 1025 } 1026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1027 1028 /* 1029 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1030 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1031 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1032 * of the ACPI SCI interrupt is only done for convenience. 1033 * -jgarzik 1034 */ 1035 static void quirk_via_acpi(struct pci_dev *d) 1036 { 1037 u8 irq; 1038 1039 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1040 pci_read_config_byte(d, 0x42, &irq); 1041 irq &= 0xf; 1042 if (irq && (irq != 2)) 1043 d->irq = irq; 1044 } 1045 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1047 1048 /* VIA bridges which have VLink */ 1049 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1050 1051 static void quirk_via_bridge(struct pci_dev *dev) 1052 { 1053 /* See what bridge we have and find the device ranges */ 1054 switch (dev->device) { 1055 case PCI_DEVICE_ID_VIA_82C686: 1056 /* 1057 * The VT82C686 is special; it attaches to PCI and can have 1058 * any device number. All its subdevices are functions of 1059 * that single device. 1060 */ 1061 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1062 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1063 break; 1064 case PCI_DEVICE_ID_VIA_8237: 1065 case PCI_DEVICE_ID_VIA_8237A: 1066 via_vlink_dev_lo = 15; 1067 break; 1068 case PCI_DEVICE_ID_VIA_8235: 1069 via_vlink_dev_lo = 16; 1070 break; 1071 case PCI_DEVICE_ID_VIA_8231: 1072 case PCI_DEVICE_ID_VIA_8233_0: 1073 case PCI_DEVICE_ID_VIA_8233A: 1074 case PCI_DEVICE_ID_VIA_8233C_0: 1075 via_vlink_dev_lo = 17; 1076 break; 1077 } 1078 } 1079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1083 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1087 1088 /* 1089 * quirk_via_vlink - VIA VLink IRQ number update 1090 * @dev: PCI device 1091 * 1092 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1093 * the IRQ line register which usually is not relevant for PCI cards, is 1094 * actually written so that interrupts get sent to the right place. 1095 * 1096 * We only do this on systems where a VIA south bridge was detected, and 1097 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1098 */ 1099 static void quirk_via_vlink(struct pci_dev *dev) 1100 { 1101 u8 irq, new_irq; 1102 1103 /* Check if we have VLink at all */ 1104 if (via_vlink_dev_lo == -1) 1105 return; 1106 1107 new_irq = dev->irq; 1108 1109 /* Don't quirk interrupts outside the legacy IRQ range */ 1110 if (!new_irq || new_irq > 15) 1111 return; 1112 1113 /* Internal device ? */ 1114 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1115 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1116 return; 1117 1118 /* 1119 * This is an internal VLink device on a PIC interrupt. The BIOS 1120 * ought to have set this but may not have, so we redo it. 1121 */ 1122 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1123 if (new_irq != irq) { 1124 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1125 irq, new_irq); 1126 udelay(15); /* unknown if delay really needed */ 1127 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1128 } 1129 } 1130 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1131 1132 /* 1133 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1134 * of VT82C597 for backward compatibility. We need to switch it off to be 1135 * able to recognize the real type of the chip. 1136 */ 1137 static void quirk_vt82c598_id(struct pci_dev *dev) 1138 { 1139 pci_write_config_byte(dev, 0xfc, 0); 1140 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1141 } 1142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1143 1144 /* 1145 * CardBus controllers have a legacy base address that enables them to 1146 * respond as i82365 pcmcia controllers. We don't want them to do this 1147 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1148 * driver does not (and should not) handle CardBus. 1149 */ 1150 static void quirk_cardbus_legacy(struct pci_dev *dev) 1151 { 1152 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1153 } 1154 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1155 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1156 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1157 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1158 1159 /* 1160 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1161 * what the designers were smoking but let's not inhale... 1162 * 1163 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1164 * turn it off! 1165 */ 1166 static void quirk_amd_ordering(struct pci_dev *dev) 1167 { 1168 u32 pcic; 1169 pci_read_config_dword(dev, 0x4C, &pcic); 1170 if ((pcic & 6) != 6) { 1171 pcic |= 6; 1172 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1173 pci_write_config_dword(dev, 0x4C, pcic); 1174 pci_read_config_dword(dev, 0x84, &pcic); 1175 pcic |= (1 << 23); /* Required in this mode */ 1176 pci_write_config_dword(dev, 0x84, pcic); 1177 } 1178 } 1179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1180 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1181 1182 /* 1183 * DreamWorks-provided workaround for Dunord I-3000 problem 1184 * 1185 * This card decodes and responds to addresses not apparently assigned to 1186 * it. We force a larger allocation to ensure that nothing gets put too 1187 * close to it. 1188 */ 1189 static void quirk_dunord(struct pci_dev *dev) 1190 { 1191 struct resource *r = &dev->resource[1]; 1192 1193 r->flags |= IORESOURCE_UNSET; 1194 r->start = 0; 1195 r->end = 0xffffff; 1196 } 1197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1198 1199 /* 1200 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1201 * decoding (transparent), and does indicate this in the ProgIf. 1202 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1203 */ 1204 static void quirk_transparent_bridge(struct pci_dev *dev) 1205 { 1206 dev->transparent = 1; 1207 } 1208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1210 1211 /* 1212 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1213 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1214 * found at http://www.national.com/analog for info on what these bits do. 1215 * <christer@weinigel.se> 1216 */ 1217 static void quirk_mediagx_master(struct pci_dev *dev) 1218 { 1219 u8 reg; 1220 1221 pci_read_config_byte(dev, 0x41, ®); 1222 if (reg & 2) { 1223 reg &= ~2; 1224 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1225 reg); 1226 pci_write_config_byte(dev, 0x41, reg); 1227 } 1228 } 1229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1230 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1231 1232 /* 1233 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1234 * in the odd case it is not the results are corruption hence the presence 1235 * of a Linux check. 1236 */ 1237 static void quirk_disable_pxb(struct pci_dev *pdev) 1238 { 1239 u16 config; 1240 1241 if (pdev->revision != 0x04) /* Only C0 requires this */ 1242 return; 1243 pci_read_config_word(pdev, 0x40, &config); 1244 if (config & (1<<6)) { 1245 config &= ~(1<<6); 1246 pci_write_config_word(pdev, 0x40, config); 1247 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1248 } 1249 } 1250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1251 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1252 1253 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1254 { 1255 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1256 u8 tmp; 1257 1258 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1259 if (tmp == 0x01) { 1260 pci_read_config_byte(pdev, 0x40, &tmp); 1261 pci_write_config_byte(pdev, 0x40, tmp|1); 1262 pci_write_config_byte(pdev, 0x9, 1); 1263 pci_write_config_byte(pdev, 0xa, 6); 1264 pci_write_config_byte(pdev, 0x40, tmp); 1265 1266 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1267 pci_info(pdev, "set SATA to AHCI mode\n"); 1268 } 1269 } 1270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1271 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1273 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1275 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1277 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1278 1279 /* Serverworks CSB5 IDE does not fully support native mode */ 1280 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1281 { 1282 u8 prog; 1283 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1284 if (prog & 5) { 1285 prog &= ~5; 1286 pdev->class &= ~5; 1287 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1288 /* PCI layer will sort out resources */ 1289 } 1290 } 1291 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1292 1293 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1294 static void quirk_ide_samemode(struct pci_dev *pdev) 1295 { 1296 u8 prog; 1297 1298 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1299 1300 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1301 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1302 prog &= ~5; 1303 pdev->class &= ~5; 1304 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1305 } 1306 } 1307 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1308 1309 /* Some ATA devices break if put into D3 */ 1310 static void quirk_no_ata_d3(struct pci_dev *pdev) 1311 { 1312 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1313 } 1314 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1315 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1316 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1317 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1318 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1319 /* ALi loses some register settings that we cannot then restore */ 1320 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1321 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1322 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1323 occur when mode detecting */ 1324 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1325 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1326 1327 /* 1328 * This was originally an Alpha-specific thing, but it really fits here. 1329 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1330 */ 1331 static void quirk_eisa_bridge(struct pci_dev *dev) 1332 { 1333 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1334 } 1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1336 1337 /* 1338 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1339 * is not activated. The myth is that Asus said that they do not want the 1340 * users to be irritated by just another PCI Device in the Win98 device 1341 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1342 * package 2.7.0 for details) 1343 * 1344 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1345 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1346 * becomes necessary to do this tweak in two steps -- the chosen trigger 1347 * is either the Host bridge (preferred) or on-board VGA controller. 1348 * 1349 * Note that we used to unhide the SMBus that way on Toshiba laptops 1350 * (Satellite A40 and Tecra M2) but then found that the thermal management 1351 * was done by SMM code, which could cause unsynchronized concurrent 1352 * accesses to the SMBus registers, with potentially bad effects. Thus you 1353 * should be very careful when adding new entries: if SMM is accessing the 1354 * Intel SMBus, this is a very good reason to leave it hidden. 1355 * 1356 * Likewise, many recent laptops use ACPI for thermal management. If the 1357 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1358 * natively, and keeping the SMBus hidden is the right thing to do. If you 1359 * are about to add an entry in the table below, please first disassemble 1360 * the DSDT and double-check that there is no code accessing the SMBus. 1361 */ 1362 static int asus_hides_smbus; 1363 1364 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1365 { 1366 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1367 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1368 switch (dev->subsystem_device) { 1369 case 0x8025: /* P4B-LX */ 1370 case 0x8070: /* P4B */ 1371 case 0x8088: /* P4B533 */ 1372 case 0x1626: /* L3C notebook */ 1373 asus_hides_smbus = 1; 1374 } 1375 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1376 switch (dev->subsystem_device) { 1377 case 0x80b1: /* P4GE-V */ 1378 case 0x80b2: /* P4PE */ 1379 case 0x8093: /* P4B533-V */ 1380 asus_hides_smbus = 1; 1381 } 1382 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1383 switch (dev->subsystem_device) { 1384 case 0x8030: /* P4T533 */ 1385 asus_hides_smbus = 1; 1386 } 1387 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1388 switch (dev->subsystem_device) { 1389 case 0x8070: /* P4G8X Deluxe */ 1390 asus_hides_smbus = 1; 1391 } 1392 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1393 switch (dev->subsystem_device) { 1394 case 0x80c9: /* PU-DLS */ 1395 asus_hides_smbus = 1; 1396 } 1397 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1398 switch (dev->subsystem_device) { 1399 case 0x1751: /* M2N notebook */ 1400 case 0x1821: /* M5N notebook */ 1401 case 0x1897: /* A6L notebook */ 1402 asus_hides_smbus = 1; 1403 } 1404 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1405 switch (dev->subsystem_device) { 1406 case 0x184b: /* W1N notebook */ 1407 case 0x186a: /* M6Ne notebook */ 1408 asus_hides_smbus = 1; 1409 } 1410 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1411 switch (dev->subsystem_device) { 1412 case 0x80f2: /* P4P800-X */ 1413 asus_hides_smbus = 1; 1414 } 1415 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1416 switch (dev->subsystem_device) { 1417 case 0x1882: /* M6V notebook */ 1418 case 0x1977: /* A6VA notebook */ 1419 asus_hides_smbus = 1; 1420 } 1421 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1422 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1423 switch (dev->subsystem_device) { 1424 case 0x088C: /* HP Compaq nc8000 */ 1425 case 0x0890: /* HP Compaq nc6000 */ 1426 asus_hides_smbus = 1; 1427 } 1428 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1429 switch (dev->subsystem_device) { 1430 case 0x12bc: /* HP D330L */ 1431 case 0x12bd: /* HP D530 */ 1432 case 0x006a: /* HP Compaq nx9500 */ 1433 asus_hides_smbus = 1; 1434 } 1435 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1436 switch (dev->subsystem_device) { 1437 case 0x12bf: /* HP xw4100 */ 1438 asus_hides_smbus = 1; 1439 } 1440 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1441 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1442 switch (dev->subsystem_device) { 1443 case 0xC00C: /* Samsung P35 notebook */ 1444 asus_hides_smbus = 1; 1445 } 1446 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1447 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1448 switch (dev->subsystem_device) { 1449 case 0x0058: /* Compaq Evo N620c */ 1450 asus_hides_smbus = 1; 1451 } 1452 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1453 switch (dev->subsystem_device) { 1454 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1455 /* Motherboard doesn't have Host bridge 1456 * subvendor/subdevice IDs, therefore checking 1457 * its on-board VGA controller */ 1458 asus_hides_smbus = 1; 1459 } 1460 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1461 switch (dev->subsystem_device) { 1462 case 0x00b8: /* Compaq Evo D510 CMT */ 1463 case 0x00b9: /* Compaq Evo D510 SFF */ 1464 case 0x00ba: /* Compaq Evo D510 USDT */ 1465 /* Motherboard doesn't have Host bridge 1466 * subvendor/subdevice IDs and on-board VGA 1467 * controller is disabled if an AGP card is 1468 * inserted, therefore checking USB UHCI 1469 * Controller #1 */ 1470 asus_hides_smbus = 1; 1471 } 1472 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1473 switch (dev->subsystem_device) { 1474 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1475 /* Motherboard doesn't have host bridge 1476 * subvendor/subdevice IDs, therefore checking 1477 * its on-board VGA controller */ 1478 asus_hides_smbus = 1; 1479 } 1480 } 1481 } 1482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1492 1493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1496 1497 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1498 { 1499 u16 val; 1500 1501 if (likely(!asus_hides_smbus)) 1502 return; 1503 1504 pci_read_config_word(dev, 0xF2, &val); 1505 if (val & 0x8) { 1506 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1507 pci_read_config_word(dev, 0xF2, &val); 1508 if (val & 0x8) 1509 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1510 val); 1511 else 1512 pci_info(dev, "Enabled i801 SMBus device\n"); 1513 } 1514 } 1515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1522 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1523 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1524 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1525 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1526 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1527 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1528 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1529 1530 /* It appears we just have one such device. If not, we have a warning */ 1531 static void __iomem *asus_rcba_base; 1532 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1533 { 1534 u32 rcba; 1535 1536 if (likely(!asus_hides_smbus)) 1537 return; 1538 WARN_ON(asus_rcba_base); 1539 1540 pci_read_config_dword(dev, 0xF0, &rcba); 1541 /* use bits 31:14, 16 kB aligned */ 1542 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1543 if (asus_rcba_base == NULL) 1544 return; 1545 } 1546 1547 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1548 { 1549 u32 val; 1550 1551 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1552 return; 1553 1554 /* read the Function Disable register, dword mode only */ 1555 val = readl(asus_rcba_base + 0x3418); 1556 1557 /* enable the SMBus device */ 1558 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1559 } 1560 1561 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1562 { 1563 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1564 return; 1565 1566 iounmap(asus_rcba_base); 1567 asus_rcba_base = NULL; 1568 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1569 } 1570 1571 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1572 { 1573 asus_hides_smbus_lpc_ich6_suspend(dev); 1574 asus_hides_smbus_lpc_ich6_resume_early(dev); 1575 asus_hides_smbus_lpc_ich6_resume(dev); 1576 } 1577 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1578 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1579 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1580 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1581 1582 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1583 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1584 { 1585 u8 val = 0; 1586 pci_read_config_byte(dev, 0x77, &val); 1587 if (val & 0x10) { 1588 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1589 pci_write_config_byte(dev, 0x77, val & ~0x10); 1590 } 1591 } 1592 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1596 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1597 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1598 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1599 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1600 1601 /* 1602 * ... This is further complicated by the fact that some SiS96x south 1603 * bridges pretend to be 85C503/5513 instead. In that case see if we 1604 * spotted a compatible north bridge to make sure. 1605 * (pci_find_device() doesn't work yet) 1606 * 1607 * We can also enable the sis96x bit in the discovery register.. 1608 */ 1609 #define SIS_DETECT_REGISTER 0x40 1610 1611 static void quirk_sis_503(struct pci_dev *dev) 1612 { 1613 u8 reg; 1614 u16 devid; 1615 1616 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1617 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1618 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1619 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1620 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1621 return; 1622 } 1623 1624 /* 1625 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1626 * it has already been processed. (Depends on link order, which is 1627 * apparently not guaranteed) 1628 */ 1629 dev->device = devid; 1630 quirk_sis_96x_smbus(dev); 1631 } 1632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1633 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1634 1635 /* 1636 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1637 * and MC97 modem controller are disabled when a second PCI soundcard is 1638 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1639 * -- bjd 1640 */ 1641 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1642 { 1643 u8 val; 1644 int asus_hides_ac97 = 0; 1645 1646 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1647 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1648 asus_hides_ac97 = 1; 1649 } 1650 1651 if (!asus_hides_ac97) 1652 return; 1653 1654 pci_read_config_byte(dev, 0x50, &val); 1655 if (val & 0xc0) { 1656 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1657 pci_read_config_byte(dev, 0x50, &val); 1658 if (val & 0xc0) 1659 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1660 val); 1661 else 1662 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1663 } 1664 } 1665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1666 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1667 1668 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1669 1670 /* 1671 * If we are using libata we can drive this chip properly but must do this 1672 * early on to make the additional device appear during the PCI scanning. 1673 */ 1674 static void quirk_jmicron_ata(struct pci_dev *pdev) 1675 { 1676 u32 conf1, conf5, class; 1677 u8 hdr; 1678 1679 /* Only poke fn 0 */ 1680 if (PCI_FUNC(pdev->devfn)) 1681 return; 1682 1683 pci_read_config_dword(pdev, 0x40, &conf1); 1684 pci_read_config_dword(pdev, 0x80, &conf5); 1685 1686 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1687 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1688 1689 switch (pdev->device) { 1690 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1691 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1692 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1693 /* The controller should be in single function ahci mode */ 1694 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1695 break; 1696 1697 case PCI_DEVICE_ID_JMICRON_JMB365: 1698 case PCI_DEVICE_ID_JMICRON_JMB366: 1699 /* Redirect IDE second PATA port to the right spot */ 1700 conf5 |= (1 << 24); 1701 /* Fall through */ 1702 case PCI_DEVICE_ID_JMICRON_JMB361: 1703 case PCI_DEVICE_ID_JMICRON_JMB363: 1704 case PCI_DEVICE_ID_JMICRON_JMB369: 1705 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1706 /* Set the class codes correctly and then direct IDE 0 */ 1707 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1708 break; 1709 1710 case PCI_DEVICE_ID_JMICRON_JMB368: 1711 /* The controller should be in single function IDE mode */ 1712 conf1 |= 0x00C00000; /* Set 22, 23 */ 1713 break; 1714 } 1715 1716 pci_write_config_dword(pdev, 0x40, conf1); 1717 pci_write_config_dword(pdev, 0x80, conf5); 1718 1719 /* Update pdev accordingly */ 1720 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1721 pdev->hdr_type = hdr & 0x7f; 1722 pdev->multifunction = !!(hdr & 0x80); 1723 1724 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1725 pdev->class = class >> 8; 1726 } 1727 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1728 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1729 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1730 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1731 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1732 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1733 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1734 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1735 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1736 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1737 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1738 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1739 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1740 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1741 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1742 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1743 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1744 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1745 1746 #endif 1747 1748 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1749 { 1750 if (dev->multifunction) { 1751 device_disable_async_suspend(&dev->dev); 1752 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1753 } 1754 } 1755 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1756 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1757 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1758 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1759 1760 #ifdef CONFIG_X86_IO_APIC 1761 static void quirk_alder_ioapic(struct pci_dev *pdev) 1762 { 1763 int i; 1764 1765 if ((pdev->class >> 8) != 0xff00) 1766 return; 1767 1768 /* 1769 * The first BAR is the location of the IO-APIC... we must 1770 * not touch this (and it's already covered by the fixmap), so 1771 * forcibly insert it into the resource tree. 1772 */ 1773 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1774 insert_resource(&iomem_resource, &pdev->resource[0]); 1775 1776 /* 1777 * The next five BARs all seem to be rubbish, so just clean 1778 * them out. 1779 */ 1780 for (i = 1; i < 6; i++) 1781 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1782 } 1783 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1784 #endif 1785 1786 static void quirk_pcie_mch(struct pci_dev *pdev) 1787 { 1788 pdev->no_msi = 1; 1789 } 1790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1792 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1793 1794 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1795 1796 /* 1797 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1798 * together on certain PXH-based systems. 1799 */ 1800 static void quirk_pcie_pxh(struct pci_dev *dev) 1801 { 1802 dev->no_msi = 1; 1803 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1804 } 1805 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1806 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1807 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1808 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1809 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1810 1811 /* 1812 * Some Intel PCI Express chipsets have trouble with downstream device 1813 * power management. 1814 */ 1815 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1816 { 1817 pci_pm_d3_delay = 120; 1818 dev->no_d1d2 = 1; 1819 } 1820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1826 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1829 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1835 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1841 1842 static void quirk_radeon_pm(struct pci_dev *dev) 1843 { 1844 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1845 dev->subsystem_device == 0x00e2) { 1846 if (dev->d3_delay < 20) { 1847 dev->d3_delay = 20; 1848 pci_info(dev, "extending delay after power-on from D3 to %d msec\n", 1849 dev->d3_delay); 1850 } 1851 } 1852 } 1853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 1854 1855 #ifdef CONFIG_X86_IO_APIC 1856 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 1857 { 1858 noioapicreroute = 1; 1859 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 1860 1861 return 0; 1862 } 1863 1864 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 1865 /* 1866 * Systems to exclude from boot interrupt reroute quirks 1867 */ 1868 { 1869 .callback = dmi_disable_ioapicreroute, 1870 .ident = "ASUSTek Computer INC. M2N-LR", 1871 .matches = { 1872 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 1873 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 1874 }, 1875 }, 1876 {} 1877 }; 1878 1879 /* 1880 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1881 * remap the original interrupt in the Linux kernel to the boot interrupt, so 1882 * that a PCI device's interrupt handler is installed on the boot interrupt 1883 * line instead. 1884 */ 1885 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1886 { 1887 dmi_check_system(boot_interrupt_dmi_table); 1888 if (noioapicquirk || noioapicreroute) 1889 return; 1890 1891 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1892 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 1893 dev->vendor, dev->device); 1894 } 1895 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1896 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1897 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1898 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1899 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1900 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1902 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1903 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1904 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1905 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1906 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1907 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1908 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1909 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1910 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1911 1912 /* 1913 * On some chipsets we can disable the generation of legacy INTx boot 1914 * interrupts. 1915 */ 1916 1917 /* 1918 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 1919 * 300641-004US, section 5.7.3. 1920 */ 1921 #define INTEL_6300_IOAPIC_ABAR 0x40 1922 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1923 1924 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1925 { 1926 u16 pci_config_word; 1927 1928 if (noioapicquirk) 1929 return; 1930 1931 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1932 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1933 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1934 1935 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1936 dev->vendor, dev->device); 1937 } 1938 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1939 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1940 1941 /* Disable boot interrupts on HT-1000 */ 1942 #define BC_HT1000_FEATURE_REG 0x64 1943 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1944 #define BC_HT1000_MAP_IDX 0xC00 1945 #define BC_HT1000_MAP_DATA 0xC01 1946 1947 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1948 { 1949 u32 pci_config_dword; 1950 u8 irq; 1951 1952 if (noioapicquirk) 1953 return; 1954 1955 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1956 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1957 BC_HT1000_PIC_REGS_ENABLE); 1958 1959 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1960 outb(irq, BC_HT1000_MAP_IDX); 1961 outb(0x00, BC_HT1000_MAP_DATA); 1962 } 1963 1964 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1965 1966 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1967 dev->vendor, dev->device); 1968 } 1969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1970 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1971 1972 /* Disable boot interrupts on AMD and ATI chipsets */ 1973 1974 /* 1975 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1976 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1977 * (due to an erratum). 1978 */ 1979 #define AMD_813X_MISC 0x40 1980 #define AMD_813X_NOIOAMODE (1<<0) 1981 #define AMD_813X_REV_B1 0x12 1982 #define AMD_813X_REV_B2 0x13 1983 1984 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1985 { 1986 u32 pci_config_dword; 1987 1988 if (noioapicquirk) 1989 return; 1990 if ((dev->revision == AMD_813X_REV_B1) || 1991 (dev->revision == AMD_813X_REV_B2)) 1992 return; 1993 1994 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1995 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1996 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1997 1998 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1999 dev->vendor, dev->device); 2000 } 2001 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2002 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2004 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2005 2006 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2007 2008 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2009 { 2010 u16 pci_config_word; 2011 2012 if (noioapicquirk) 2013 return; 2014 2015 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2016 if (!pci_config_word) { 2017 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2018 dev->vendor, dev->device); 2019 return; 2020 } 2021 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2022 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2023 dev->vendor, dev->device); 2024 } 2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2026 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2027 #endif /* CONFIG_X86_IO_APIC */ 2028 2029 /* 2030 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2031 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2032 * Re-allocate the region if needed... 2033 */ 2034 static void quirk_tc86c001_ide(struct pci_dev *dev) 2035 { 2036 struct resource *r = &dev->resource[0]; 2037 2038 if (r->start & 0x8) { 2039 r->flags |= IORESOURCE_UNSET; 2040 r->start = 0; 2041 r->end = 0xf; 2042 } 2043 } 2044 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2045 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2046 quirk_tc86c001_ide); 2047 2048 /* 2049 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2050 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2051 * being read correctly if bit 7 of the base address is set. 2052 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2053 * Re-allocate the regions to a 256-byte boundary if necessary. 2054 */ 2055 static void quirk_plx_pci9050(struct pci_dev *dev) 2056 { 2057 unsigned int bar; 2058 2059 /* Fixed in revision 2 (PCI 9052). */ 2060 if (dev->revision >= 2) 2061 return; 2062 for (bar = 0; bar <= 1; bar++) 2063 if (pci_resource_len(dev, bar) == 0x80 && 2064 (pci_resource_start(dev, bar) & 0x80)) { 2065 struct resource *r = &dev->resource[bar]; 2066 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2067 bar); 2068 r->flags |= IORESOURCE_UNSET; 2069 r->start = 0; 2070 r->end = 0xff; 2071 } 2072 } 2073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2074 quirk_plx_pci9050); 2075 /* 2076 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2077 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2078 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2079 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2080 * 2081 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2082 * driver. 2083 */ 2084 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2085 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2086 2087 static void quirk_netmos(struct pci_dev *dev) 2088 { 2089 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2090 unsigned int num_serial = dev->subsystem_device & 0xf; 2091 2092 /* 2093 * These Netmos parts are multiport serial devices with optional 2094 * parallel ports. Even when parallel ports are present, they 2095 * are identified as class SERIAL, which means the serial driver 2096 * will claim them. To prevent this, mark them as class OTHER. 2097 * These combo devices should be claimed by parport_serial. 2098 * 2099 * The subdevice ID is of the form 0x00PS, where <P> is the number 2100 * of parallel ports and <S> is the number of serial ports. 2101 */ 2102 switch (dev->device) { 2103 case PCI_DEVICE_ID_NETMOS_9835: 2104 /* Well, this rule doesn't hold for the following 9835 device */ 2105 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2106 dev->subsystem_device == 0x0299) 2107 return; 2108 case PCI_DEVICE_ID_NETMOS_9735: 2109 case PCI_DEVICE_ID_NETMOS_9745: 2110 case PCI_DEVICE_ID_NETMOS_9845: 2111 case PCI_DEVICE_ID_NETMOS_9855: 2112 if (num_parallel) { 2113 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2114 dev->device, num_parallel, num_serial); 2115 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2116 (dev->class & 0xff); 2117 } 2118 } 2119 } 2120 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2121 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2122 2123 static void quirk_e100_interrupt(struct pci_dev *dev) 2124 { 2125 u16 command, pmcsr; 2126 u8 __iomem *csr; 2127 u8 cmd_hi; 2128 2129 switch (dev->device) { 2130 /* PCI IDs taken from drivers/net/e100.c */ 2131 case 0x1029: 2132 case 0x1030 ... 0x1034: 2133 case 0x1038 ... 0x103E: 2134 case 0x1050 ... 0x1057: 2135 case 0x1059: 2136 case 0x1064 ... 0x106B: 2137 case 0x1091 ... 0x1095: 2138 case 0x1209: 2139 case 0x1229: 2140 case 0x2449: 2141 case 0x2459: 2142 case 0x245D: 2143 case 0x27DC: 2144 break; 2145 default: 2146 return; 2147 } 2148 2149 /* 2150 * Some firmware hands off the e100 with interrupts enabled, 2151 * which can cause a flood of interrupts if packets are 2152 * received before the driver attaches to the device. So 2153 * disable all e100 interrupts here. The driver will 2154 * re-enable them when it's ready. 2155 */ 2156 pci_read_config_word(dev, PCI_COMMAND, &command); 2157 2158 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2159 return; 2160 2161 /* 2162 * Check that the device is in the D0 power state. If it's not, 2163 * there is no point to look any further. 2164 */ 2165 if (dev->pm_cap) { 2166 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2167 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2168 return; 2169 } 2170 2171 /* Convert from PCI bus to resource space. */ 2172 csr = ioremap(pci_resource_start(dev, 0), 8); 2173 if (!csr) { 2174 pci_warn(dev, "Can't map e100 registers\n"); 2175 return; 2176 } 2177 2178 cmd_hi = readb(csr + 3); 2179 if (cmd_hi == 0) { 2180 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2181 writeb(1, csr + 3); 2182 } 2183 2184 iounmap(csr); 2185 } 2186 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2187 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2188 2189 /* 2190 * The 82575 and 82598 may experience data corruption issues when transitioning 2191 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2192 */ 2193 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2194 { 2195 pci_info(dev, "Disabling L0s\n"); 2196 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2197 } 2198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2212 2213 static void fixup_rev1_53c810(struct pci_dev *dev) 2214 { 2215 u32 class = dev->class; 2216 2217 /* 2218 * rev 1 ncr53c810 chips don't set the class at all which means 2219 * they don't get their resources remapped. Fix that here. 2220 */ 2221 if (class) 2222 return; 2223 2224 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2225 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2226 class, dev->class); 2227 } 2228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2229 2230 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2231 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2232 { 2233 u16 en1k; 2234 2235 pci_read_config_word(dev, 0x40, &en1k); 2236 2237 if (en1k & 0x200) { 2238 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2239 dev->io_window_1k = 1; 2240 } 2241 } 2242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2243 2244 /* 2245 * Under some circumstances, AER is not linked with extended capabilities. 2246 * Force it to be linked by setting the corresponding control bit in the 2247 * config space. 2248 */ 2249 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2250 { 2251 uint8_t b; 2252 2253 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2254 if (!(b & 0x20)) { 2255 pci_write_config_byte(dev, 0xf41, b | 0x20); 2256 pci_info(dev, "Linking AER extended capability\n"); 2257 } 2258 } 2259 } 2260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2261 quirk_nvidia_ck804_pcie_aer_ext_cap); 2262 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2263 quirk_nvidia_ck804_pcie_aer_ext_cap); 2264 2265 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2266 { 2267 /* 2268 * Disable PCI Bus Parking and PCI Master read caching on CX700 2269 * which causes unspecified timing errors with a VT6212L on the PCI 2270 * bus leading to USB2.0 packet loss. 2271 * 2272 * This quirk is only enabled if a second (on the external PCI bus) 2273 * VT6212L is found -- the CX700 core itself also contains a USB 2274 * host controller with the same PCI ID as the VT6212L. 2275 */ 2276 2277 /* Count VT6212L instances */ 2278 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2279 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2280 uint8_t b; 2281 2282 /* 2283 * p should contain the first (internal) VT6212L -- see if we have 2284 * an external one by searching again. 2285 */ 2286 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2287 if (!p) 2288 return; 2289 pci_dev_put(p); 2290 2291 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2292 if (b & 0x40) { 2293 /* Turn off PCI Bus Parking */ 2294 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2295 2296 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2297 } 2298 } 2299 2300 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2301 if (b != 0) { 2302 /* Turn off PCI Master read caching */ 2303 pci_write_config_byte(dev, 0x72, 0x0); 2304 2305 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2306 pci_write_config_byte(dev, 0x75, 0x1); 2307 2308 /* Disable "Read FIFO Timer" */ 2309 pci_write_config_byte(dev, 0x77, 0x0); 2310 2311 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2312 } 2313 } 2314 } 2315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2316 2317 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2318 { 2319 u32 rev; 2320 2321 pci_read_config_dword(dev, 0xf4, &rev); 2322 2323 /* Only CAP the MRRS if the device is a 5719 A0 */ 2324 if (rev == 0x05719000) { 2325 int readrq = pcie_get_readrq(dev); 2326 if (readrq > 2048) 2327 pcie_set_readrq(dev, 2048); 2328 } 2329 } 2330 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2331 PCI_DEVICE_ID_TIGON3_5719, 2332 quirk_brcm_5719_limit_mrrs); 2333 2334 #ifdef CONFIG_PCIE_IPROC_PLATFORM 2335 static void quirk_paxc_bridge(struct pci_dev *pdev) 2336 { 2337 /* 2338 * The PCI config space is shared with the PAXC root port and the first 2339 * Ethernet device. So, we need to workaround this by telling the PCI 2340 * code that the bridge is not an Ethernet device. 2341 */ 2342 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2343 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; 2344 2345 /* 2346 * MPSS is not being set properly (as it is currently 0). This is 2347 * because that area of the PCI config space is hard coded to zero, and 2348 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) 2349 * so that the MPS can be set to the real max value. 2350 */ 2351 pdev->pcie_mpss = 2; 2352 } 2353 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); 2354 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); 2355 #endif 2356 2357 /* 2358 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2359 * hide device 6 which configures the overflow device access containing the 2360 * DRBs - this is where we expose device 6. 2361 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2362 */ 2363 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2364 { 2365 u8 reg; 2366 2367 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2368 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2369 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2370 } 2371 } 2372 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2373 quirk_unhide_mch_dev6); 2374 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2375 quirk_unhide_mch_dev6); 2376 2377 #ifdef CONFIG_PCI_MSI 2378 /* 2379 * Some chipsets do not support MSI. We cannot easily rely on setting 2380 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2381 * other buses controlled by the chipset even if Linux is not aware of it. 2382 * Instead of setting the flag on all buses in the machine, simply disable 2383 * MSI globally. 2384 */ 2385 static void quirk_disable_all_msi(struct pci_dev *dev) 2386 { 2387 pci_no_msi(); 2388 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2389 } 2390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2398 2399 /* Disable MSI on chipsets that are known to not support it */ 2400 static void quirk_disable_msi(struct pci_dev *dev) 2401 { 2402 if (dev->subordinate) { 2403 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2404 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2405 } 2406 } 2407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2410 2411 /* 2412 * The APC bridge device in AMD 780 family northbridges has some random 2413 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2414 * we use the possible vendor/device IDs of the host bridge for the 2415 * declared quirk, and search for the APC bridge by slot number. 2416 */ 2417 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2418 { 2419 struct pci_dev *apc_bridge; 2420 2421 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2422 if (apc_bridge) { 2423 if (apc_bridge->device == 0x9602) 2424 quirk_disable_msi(apc_bridge); 2425 pci_dev_put(apc_bridge); 2426 } 2427 } 2428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2430 2431 /* 2432 * Go through the list of HyperTransport capabilities and return 1 if a HT 2433 * MSI capability is found and enabled. 2434 */ 2435 static int msi_ht_cap_enabled(struct pci_dev *dev) 2436 { 2437 int pos, ttl = PCI_FIND_CAP_TTL; 2438 2439 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2440 while (pos && ttl--) { 2441 u8 flags; 2442 2443 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2444 &flags) == 0) { 2445 pci_info(dev, "Found %s HT MSI Mapping\n", 2446 flags & HT_MSI_FLAGS_ENABLE ? 2447 "enabled" : "disabled"); 2448 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2449 } 2450 2451 pos = pci_find_next_ht_capability(dev, pos, 2452 HT_CAPTYPE_MSI_MAPPING); 2453 } 2454 return 0; 2455 } 2456 2457 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2458 static void quirk_msi_ht_cap(struct pci_dev *dev) 2459 { 2460 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2461 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2462 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2463 } 2464 } 2465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2466 quirk_msi_ht_cap); 2467 2468 /* 2469 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2470 * if the MSI capability is set in any of these mappings. 2471 */ 2472 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2473 { 2474 struct pci_dev *pdev; 2475 2476 if (!dev->subordinate) 2477 return; 2478 2479 /* 2480 * Check HT MSI cap on this chipset and the root one. A single one 2481 * having MSI is enough to be sure that MSI is supported. 2482 */ 2483 pdev = pci_get_slot(dev->bus, 0); 2484 if (!pdev) 2485 return; 2486 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2487 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2488 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2489 } 2490 pci_dev_put(pdev); 2491 } 2492 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2493 quirk_nvidia_ck804_msi_ht_cap); 2494 2495 /* Force enable MSI mapping capability on HT bridges */ 2496 static void ht_enable_msi_mapping(struct pci_dev *dev) 2497 { 2498 int pos, ttl = PCI_FIND_CAP_TTL; 2499 2500 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2501 while (pos && ttl--) { 2502 u8 flags; 2503 2504 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2505 &flags) == 0) { 2506 pci_info(dev, "Enabling HT MSI Mapping\n"); 2507 2508 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2509 flags | HT_MSI_FLAGS_ENABLE); 2510 } 2511 pos = pci_find_next_ht_capability(dev, pos, 2512 HT_CAPTYPE_MSI_MAPPING); 2513 } 2514 } 2515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2516 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2517 ht_enable_msi_mapping); 2518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2519 ht_enable_msi_mapping); 2520 2521 /* 2522 * The P5N32-SLI motherboards from Asus have a problem with MSI 2523 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2524 * also affects other devices. As for now, turn off MSI for this device. 2525 */ 2526 static void nvenet_msi_disable(struct pci_dev *dev) 2527 { 2528 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2529 2530 if (board_name && 2531 (strstr(board_name, "P5N32-SLI PREMIUM") || 2532 strstr(board_name, "P5N32-E SLI"))) { 2533 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2534 dev->no_msi = 1; 2535 } 2536 } 2537 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2538 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2539 nvenet_msi_disable); 2540 2541 /* 2542 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2543 * config register. This register controls the routing of legacy 2544 * interrupts from devices that route through the MCP55. If this register 2545 * is misprogrammed, interrupts are only sent to the BSP, unlike 2546 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2547 * having this register set properly prevents kdump from booting up 2548 * properly, so let's make sure that we have it set correctly. 2549 * Note that this is an undocumented register. 2550 */ 2551 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2552 { 2553 u32 cfg; 2554 2555 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2556 return; 2557 2558 pci_read_config_dword(dev, 0x74, &cfg); 2559 2560 if (cfg & ((1 << 2) | (1 << 15))) { 2561 printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n"); 2562 cfg &= ~((1 << 2) | (1 << 15)); 2563 pci_write_config_dword(dev, 0x74, cfg); 2564 } 2565 } 2566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2567 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2568 nvbridge_check_legacy_irq_routing); 2569 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2570 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2571 nvbridge_check_legacy_irq_routing); 2572 2573 static int ht_check_msi_mapping(struct pci_dev *dev) 2574 { 2575 int pos, ttl = PCI_FIND_CAP_TTL; 2576 int found = 0; 2577 2578 /* Check if there is HT MSI cap or enabled on this device */ 2579 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2580 while (pos && ttl--) { 2581 u8 flags; 2582 2583 if (found < 1) 2584 found = 1; 2585 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2586 &flags) == 0) { 2587 if (flags & HT_MSI_FLAGS_ENABLE) { 2588 if (found < 2) { 2589 found = 2; 2590 break; 2591 } 2592 } 2593 } 2594 pos = pci_find_next_ht_capability(dev, pos, 2595 HT_CAPTYPE_MSI_MAPPING); 2596 } 2597 2598 return found; 2599 } 2600 2601 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2602 { 2603 struct pci_dev *dev; 2604 int pos; 2605 int i, dev_no; 2606 int found = 0; 2607 2608 dev_no = host_bridge->devfn >> 3; 2609 for (i = dev_no + 1; i < 0x20; i++) { 2610 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2611 if (!dev) 2612 continue; 2613 2614 /* found next host bridge? */ 2615 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2616 if (pos != 0) { 2617 pci_dev_put(dev); 2618 break; 2619 } 2620 2621 if (ht_check_msi_mapping(dev)) { 2622 found = 1; 2623 pci_dev_put(dev); 2624 break; 2625 } 2626 pci_dev_put(dev); 2627 } 2628 2629 return found; 2630 } 2631 2632 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2633 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2634 2635 static int is_end_of_ht_chain(struct pci_dev *dev) 2636 { 2637 int pos, ctrl_off; 2638 int end = 0; 2639 u16 flags, ctrl; 2640 2641 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2642 2643 if (!pos) 2644 goto out; 2645 2646 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2647 2648 ctrl_off = ((flags >> 10) & 1) ? 2649 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2650 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2651 2652 if (ctrl & (1 << 6)) 2653 end = 1; 2654 2655 out: 2656 return end; 2657 } 2658 2659 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2660 { 2661 struct pci_dev *host_bridge; 2662 int pos; 2663 int i, dev_no; 2664 int found = 0; 2665 2666 dev_no = dev->devfn >> 3; 2667 for (i = dev_no; i >= 0; i--) { 2668 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2669 if (!host_bridge) 2670 continue; 2671 2672 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2673 if (pos != 0) { 2674 found = 1; 2675 break; 2676 } 2677 pci_dev_put(host_bridge); 2678 } 2679 2680 if (!found) 2681 return; 2682 2683 /* don't enable end_device/host_bridge with leaf directly here */ 2684 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2685 host_bridge_with_leaf(host_bridge)) 2686 goto out; 2687 2688 /* root did that ! */ 2689 if (msi_ht_cap_enabled(host_bridge)) 2690 goto out; 2691 2692 ht_enable_msi_mapping(dev); 2693 2694 out: 2695 pci_dev_put(host_bridge); 2696 } 2697 2698 static void ht_disable_msi_mapping(struct pci_dev *dev) 2699 { 2700 int pos, ttl = PCI_FIND_CAP_TTL; 2701 2702 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2703 while (pos && ttl--) { 2704 u8 flags; 2705 2706 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2707 &flags) == 0) { 2708 pci_info(dev, "Disabling HT MSI Mapping\n"); 2709 2710 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2711 flags & ~HT_MSI_FLAGS_ENABLE); 2712 } 2713 pos = pci_find_next_ht_capability(dev, pos, 2714 HT_CAPTYPE_MSI_MAPPING); 2715 } 2716 } 2717 2718 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2719 { 2720 struct pci_dev *host_bridge; 2721 int pos; 2722 int found; 2723 2724 if (!pci_msi_enabled()) 2725 return; 2726 2727 /* check if there is HT MSI cap or enabled on this device */ 2728 found = ht_check_msi_mapping(dev); 2729 2730 /* no HT MSI CAP */ 2731 if (found == 0) 2732 return; 2733 2734 /* 2735 * HT MSI mapping should be disabled on devices that are below 2736 * a non-Hypertransport host bridge. Locate the host bridge... 2737 */ 2738 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 2739 PCI_DEVFN(0, 0)); 2740 if (host_bridge == NULL) { 2741 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2742 return; 2743 } 2744 2745 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2746 if (pos != 0) { 2747 /* Host bridge is to HT */ 2748 if (found == 1) { 2749 /* it is not enabled, try to enable it */ 2750 if (all) 2751 ht_enable_msi_mapping(dev); 2752 else 2753 nv_ht_enable_msi_mapping(dev); 2754 } 2755 goto out; 2756 } 2757 2758 /* HT MSI is not enabled */ 2759 if (found == 1) 2760 goto out; 2761 2762 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2763 ht_disable_msi_mapping(dev); 2764 2765 out: 2766 pci_dev_put(host_bridge); 2767 } 2768 2769 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2770 { 2771 return __nv_msi_ht_cap_quirk(dev, 1); 2772 } 2773 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2774 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2775 2776 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2777 { 2778 return __nv_msi_ht_cap_quirk(dev, 0); 2779 } 2780 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2781 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2782 2783 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2784 { 2785 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2786 } 2787 2788 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2789 { 2790 struct pci_dev *p; 2791 2792 /* 2793 * SB700 MSI issue will be fixed at HW level from revision A21; 2794 * we need check PCI REVISION ID of SMBus controller to get SB700 2795 * revision. 2796 */ 2797 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2798 NULL); 2799 if (!p) 2800 return; 2801 2802 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2803 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2804 pci_dev_put(p); 2805 } 2806 2807 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2808 { 2809 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2810 if (dev->revision < 0x18) { 2811 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2812 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2813 } 2814 } 2815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2816 PCI_DEVICE_ID_TIGON3_5780, 2817 quirk_msi_intx_disable_bug); 2818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2819 PCI_DEVICE_ID_TIGON3_5780S, 2820 quirk_msi_intx_disable_bug); 2821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2822 PCI_DEVICE_ID_TIGON3_5714, 2823 quirk_msi_intx_disable_bug); 2824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2825 PCI_DEVICE_ID_TIGON3_5714S, 2826 quirk_msi_intx_disable_bug); 2827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2828 PCI_DEVICE_ID_TIGON3_5715, 2829 quirk_msi_intx_disable_bug); 2830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2831 PCI_DEVICE_ID_TIGON3_5715S, 2832 quirk_msi_intx_disable_bug); 2833 2834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2835 quirk_msi_intx_disable_ati_bug); 2836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2837 quirk_msi_intx_disable_ati_bug); 2838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2839 quirk_msi_intx_disable_ati_bug); 2840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2841 quirk_msi_intx_disable_ati_bug); 2842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2843 quirk_msi_intx_disable_ati_bug); 2844 2845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2846 quirk_msi_intx_disable_bug); 2847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2848 quirk_msi_intx_disable_bug); 2849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2850 quirk_msi_intx_disable_bug); 2851 2852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2853 quirk_msi_intx_disable_bug); 2854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2855 quirk_msi_intx_disable_bug); 2856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2857 quirk_msi_intx_disable_bug); 2858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2859 quirk_msi_intx_disable_bug); 2860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2861 quirk_msi_intx_disable_bug); 2862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2863 quirk_msi_intx_disable_bug); 2864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2865 quirk_msi_intx_disable_qca_bug); 2866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2867 quirk_msi_intx_disable_qca_bug); 2868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2869 quirk_msi_intx_disable_qca_bug); 2870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2871 quirk_msi_intx_disable_qca_bug); 2872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2873 quirk_msi_intx_disable_qca_bug); 2874 #endif /* CONFIG_PCI_MSI */ 2875 2876 /* 2877 * Allow manual resource allocation for PCI hotplug bridges via 2878 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 2879 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 2880 * allocate resources when hotplug device is inserted and PCI bus is 2881 * rescanned. 2882 */ 2883 static void quirk_hotplug_bridge(struct pci_dev *dev) 2884 { 2885 dev->is_hotplug_bridge = 1; 2886 } 2887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2888 2889 /* 2890 * This is a quirk for the Ricoh MMC controller found as a part of some 2891 * multifunction chips. 2892 * 2893 * This is very similar and based on the ricoh_mmc driver written by 2894 * Philip Langdale. Thank you for these magic sequences. 2895 * 2896 * These chips implement the four main memory card controllers (SD, MMC, 2897 * MS, xD) and one or both of CardBus or FireWire. 2898 * 2899 * It happens that they implement SD and MMC support as separate 2900 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 2901 * cards but the chip detects MMC cards in hardware and directs them to the 2902 * MMC controller - so the SDHCI driver never sees them. 2903 * 2904 * To get around this, we must disable the useless MMC controller. At that 2905 * point, the SDHCI controller will start seeing them. It seems to be the 2906 * case that the relevant PCI registers to deactivate the MMC controller 2907 * live on PCI function 0, which might be the CardBus controller or the 2908 * FireWire controller, depending on the particular chip in question 2909 * 2910 * This has to be done early, because as soon as we disable the MMC controller 2911 * other PCI functions shift up one level, e.g. function #2 becomes function 2912 * #1, and this will confuse the PCI core. 2913 */ 2914 #ifdef CONFIG_MMC_RICOH_MMC 2915 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2916 { 2917 u8 write_enable; 2918 u8 write_target; 2919 u8 disable; 2920 2921 /* 2922 * Disable via CardBus interface 2923 * 2924 * This must be done via function #0 2925 */ 2926 if (PCI_FUNC(dev->devfn)) 2927 return; 2928 2929 pci_read_config_byte(dev, 0xB7, &disable); 2930 if (disable & 0x02) 2931 return; 2932 2933 pci_read_config_byte(dev, 0x8E, &write_enable); 2934 pci_write_config_byte(dev, 0x8E, 0xAA); 2935 pci_read_config_byte(dev, 0x8D, &write_target); 2936 pci_write_config_byte(dev, 0x8D, 0xB7); 2937 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2938 pci_write_config_byte(dev, 0x8E, write_enable); 2939 pci_write_config_byte(dev, 0x8D, write_target); 2940 2941 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 2942 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2943 } 2944 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2945 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2946 2947 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2948 { 2949 u8 write_enable; 2950 u8 disable; 2951 2952 /* 2953 * Disable via FireWire interface 2954 * 2955 * This must be done via function #0 2956 */ 2957 if (PCI_FUNC(dev->devfn)) 2958 return; 2959 /* 2960 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2961 * certain types of SD/MMC cards. Lowering the SD base clock 2962 * frequency from 200Mhz to 50Mhz fixes this issue. 2963 * 2964 * 0x150 - SD2.0 mode enable for changing base clock 2965 * frequency to 50Mhz 2966 * 0xe1 - Base clock frequency 2967 * 0x32 - 50Mhz new clock frequency 2968 * 0xf9 - Key register for 0x150 2969 * 0xfc - key register for 0xe1 2970 */ 2971 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2972 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2973 pci_write_config_byte(dev, 0xf9, 0xfc); 2974 pci_write_config_byte(dev, 0x150, 0x10); 2975 pci_write_config_byte(dev, 0xf9, 0x00); 2976 pci_write_config_byte(dev, 0xfc, 0x01); 2977 pci_write_config_byte(dev, 0xe1, 0x32); 2978 pci_write_config_byte(dev, 0xfc, 0x00); 2979 2980 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 2981 } 2982 2983 pci_read_config_byte(dev, 0xCB, &disable); 2984 2985 if (disable & 0x02) 2986 return; 2987 2988 pci_read_config_byte(dev, 0xCA, &write_enable); 2989 pci_write_config_byte(dev, 0xCA, 0x57); 2990 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2991 pci_write_config_byte(dev, 0xCA, write_enable); 2992 2993 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 2994 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2995 2996 } 2997 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2998 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2999 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3000 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3001 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3002 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3003 #endif /*CONFIG_MMC_RICOH_MMC*/ 3004 3005 #ifdef CONFIG_DMAR_TABLE 3006 #define VTUNCERRMSK_REG 0x1ac 3007 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3008 /* 3009 * This is a quirk for masking VT-d spec-defined errors to platform error 3010 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3011 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3012 * on the RAS config settings of the platform) when a VT-d fault happens. 3013 * The resulting SMI caused the system to hang. 3014 * 3015 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3016 * need to report the same error through other channels. 3017 */ 3018 static void vtd_mask_spec_errors(struct pci_dev *dev) 3019 { 3020 u32 word; 3021 3022 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3023 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3024 } 3025 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3026 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3027 #endif 3028 3029 static void fixup_ti816x_class(struct pci_dev *dev) 3030 { 3031 u32 class = dev->class; 3032 3033 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3034 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3035 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3036 class, dev->class); 3037 } 3038 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3039 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3040 3041 /* 3042 * Some PCIe devices do not work reliably with the claimed maximum 3043 * payload size supported. 3044 */ 3045 static void fixup_mpss_256(struct pci_dev *dev) 3046 { 3047 dev->pcie_mpss = 1; /* 256 bytes */ 3048 } 3049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3050 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3052 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3054 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3055 3056 /* 3057 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3058 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3059 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3060 * until all of the devices are discovered and buses walked, read completion 3061 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3062 * it is possible to hotplug a device with MPS of 256B. 3063 */ 3064 static void quirk_intel_mc_errata(struct pci_dev *dev) 3065 { 3066 int err; 3067 u16 rcc; 3068 3069 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3070 pcie_bus_config == PCIE_BUS_DEFAULT) 3071 return; 3072 3073 /* 3074 * Intel erratum specifies bits to change but does not say what 3075 * they are. Keeping them magical until such time as the registers 3076 * and values can be explained. 3077 */ 3078 err = pci_read_config_word(dev, 0x48, &rcc); 3079 if (err) { 3080 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3081 return; 3082 } 3083 3084 if (!(rcc & (1 << 10))) 3085 return; 3086 3087 rcc &= ~(1 << 10); 3088 3089 err = pci_write_config_word(dev, 0x48, rcc); 3090 if (err) { 3091 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3092 return; 3093 } 3094 3095 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3096 } 3097 /* Intel 5000 series memory controllers and ports 2-7 */ 3098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3099 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3112 /* Intel 5100 series memory controllers and ports 2-7 */ 3113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3124 3125 /* 3126 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3127 * To work around this, query the size it should be configured to by the 3128 * device and modify the resource end to correspond to this new size. 3129 */ 3130 static void quirk_intel_ntb(struct pci_dev *dev) 3131 { 3132 int rc; 3133 u8 val; 3134 3135 rc = pci_read_config_byte(dev, 0x00D0, &val); 3136 if (rc) 3137 return; 3138 3139 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3140 3141 rc = pci_read_config_byte(dev, 0x00D1, &val); 3142 if (rc) 3143 return; 3144 3145 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3146 } 3147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3149 3150 /* 3151 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3152 * though no one is handling them (e.g., if the i915 driver is never 3153 * loaded). Additionally the interrupt destination is not set up properly 3154 * and the interrupt ends up -somewhere-. 3155 * 3156 * These spurious interrupts are "sticky" and the kernel disables the 3157 * (shared) interrupt line after 100,000+ generated interrupts. 3158 * 3159 * Fix it by disabling the still enabled interrupts. This resolves crashes 3160 * often seen on monitor unplug. 3161 */ 3162 #define I915_DEIER_REG 0x4400c 3163 static void disable_igfx_irq(struct pci_dev *dev) 3164 { 3165 void __iomem *regs = pci_iomap(dev, 0, 0); 3166 if (regs == NULL) { 3167 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3168 return; 3169 } 3170 3171 /* Check if any interrupt line is still enabled */ 3172 if (readl(regs + I915_DEIER_REG) != 0) { 3173 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3174 3175 writel(0, regs + I915_DEIER_REG); 3176 } 3177 3178 pci_iounmap(dev, regs); 3179 } 3180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3183 3184 /* 3185 * PCI devices which are on Intel chips can skip the 10ms delay 3186 * before entering D3 mode. 3187 */ 3188 static void quirk_remove_d3_delay(struct pci_dev *dev) 3189 { 3190 dev->d3_delay = 0; 3191 } 3192 /* C600 Series devices do not need 10ms d3_delay */ 3193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3196 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */ 3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3208 /* Intel Cherrytrail devices do not need 10ms d3_delay */ 3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); 3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); 3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); 3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); 3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); 3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); 3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); 3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); 3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); 3218 3219 /* 3220 * Some devices may pass our check in pci_intx_mask_supported() if 3221 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3222 * support this feature. 3223 */ 3224 static void quirk_broken_intx_masking(struct pci_dev *dev) 3225 { 3226 dev->broken_intx_masking = 1; 3227 } 3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3229 quirk_broken_intx_masking); 3230 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3231 quirk_broken_intx_masking); 3232 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3233 quirk_broken_intx_masking); 3234 3235 /* 3236 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3237 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3238 * 3239 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3240 */ 3241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3242 quirk_broken_intx_masking); 3243 3244 /* 3245 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3246 * DisINTx can be set but the interrupt status bit is non-functional. 3247 */ 3248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3264 3265 static u16 mellanox_broken_intx_devs[] = { 3266 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3267 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3268 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3269 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3270 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3271 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3272 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3273 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3274 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3275 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3276 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3277 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3278 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3279 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3280 }; 3281 3282 #define CONNECTX_4_CURR_MAX_MINOR 99 3283 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3284 3285 /* 3286 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3287 * If so, don't mark it as broken. 3288 * FW minor > 99 means older FW version format and no INTx masking support. 3289 * FW minor < 14 means new FW version format and no INTx masking support. 3290 */ 3291 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3292 { 3293 __be32 __iomem *fw_ver; 3294 u16 fw_major; 3295 u16 fw_minor; 3296 u16 fw_subminor; 3297 u32 fw_maj_min; 3298 u32 fw_sub_min; 3299 int i; 3300 3301 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3302 if (pdev->device == mellanox_broken_intx_devs[i]) { 3303 pdev->broken_intx_masking = 1; 3304 return; 3305 } 3306 } 3307 3308 /* 3309 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3310 * support so shouldn't be checked further 3311 */ 3312 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3313 return; 3314 3315 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3316 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3317 return; 3318 3319 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3320 if (pci_enable_device_mem(pdev)) { 3321 pci_warn(pdev, "Can't enable device memory\n"); 3322 return; 3323 } 3324 3325 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3326 if (!fw_ver) { 3327 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3328 goto out; 3329 } 3330 3331 /* Reading from resource space should be 32b aligned */ 3332 fw_maj_min = ioread32be(fw_ver); 3333 fw_sub_min = ioread32be(fw_ver + 1); 3334 fw_major = fw_maj_min & 0xffff; 3335 fw_minor = fw_maj_min >> 16; 3336 fw_subminor = fw_sub_min & 0xffff; 3337 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3338 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3339 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3340 fw_major, fw_minor, fw_subminor, pdev->device == 3341 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3342 pdev->broken_intx_masking = 1; 3343 } 3344 3345 iounmap(fw_ver); 3346 3347 out: 3348 pci_disable_device(pdev); 3349 } 3350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3351 mellanox_check_broken_intx_masking); 3352 3353 static void quirk_no_bus_reset(struct pci_dev *dev) 3354 { 3355 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3356 } 3357 3358 /* 3359 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3360 * The device will throw a Link Down error on AER-capable systems and 3361 * regardless of AER, config space of the device is never accessible again 3362 * and typically causes the system to hang or reset when access is attempted. 3363 * http://www.spinics.net/lists/linux-pci/msg34797.html 3364 */ 3365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3369 3370 /* 3371 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3372 * reset when used with certain child devices. After the reset, config 3373 * accesses to the child may fail. 3374 */ 3375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3376 3377 static void quirk_no_pm_reset(struct pci_dev *dev) 3378 { 3379 /* 3380 * We can't do a bus reset on root bus devices, but an ineffective 3381 * PM reset may be better than nothing. 3382 */ 3383 if (!pci_is_root_bus(dev->bus)) 3384 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3385 } 3386 3387 /* 3388 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3389 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3390 * to have no effect on the device: it retains the framebuffer contents and 3391 * monitor sync. Advertising this support makes other layers, like VFIO, 3392 * assume pci_reset_function() is viable for this device. Mark it as 3393 * unavailable to skip it when testing reset methods. 3394 */ 3395 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3396 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3397 3398 /* 3399 * Thunderbolt controllers with broken MSI hotplug signaling: 3400 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3401 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3402 */ 3403 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3404 { 3405 if (pdev->is_hotplug_bridge && 3406 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3407 pdev->revision <= 1)) 3408 pdev->no_msi = 1; 3409 } 3410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3411 quirk_thunderbolt_hotplug_msi); 3412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3413 quirk_thunderbolt_hotplug_msi); 3414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3415 quirk_thunderbolt_hotplug_msi); 3416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3417 quirk_thunderbolt_hotplug_msi); 3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3419 quirk_thunderbolt_hotplug_msi); 3420 3421 #ifdef CONFIG_ACPI 3422 /* 3423 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3424 * 3425 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3426 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3427 * be present after resume if a device was plugged in before suspend. 3428 * 3429 * The Thunderbolt controller consists of a PCIe switch with downstream 3430 * bridges leading to the NHI and to the tunnel PCI bridges. 3431 * 3432 * This quirk cuts power to the whole chip. Therefore we have to apply it 3433 * during suspend_noirq of the upstream bridge. 3434 * 3435 * Power is automagically restored before resume. No action is needed. 3436 */ 3437 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3438 { 3439 acpi_handle bridge, SXIO, SXFP, SXLV; 3440 3441 if (!x86_apple_machine) 3442 return; 3443 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3444 return; 3445 bridge = ACPI_HANDLE(&dev->dev); 3446 if (!bridge) 3447 return; 3448 3449 /* 3450 * SXIO and SXLV are present only on machines requiring this quirk. 3451 * Thunderbolt bridges in external devices might have the same 3452 * device ID as those on the host, but they will not have the 3453 * associated ACPI methods. This implicitly checks that we are at 3454 * the right bridge. 3455 */ 3456 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3457 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3458 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3459 return; 3460 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3461 3462 /* magic sequence */ 3463 acpi_execute_simple_method(SXIO, NULL, 1); 3464 acpi_execute_simple_method(SXFP, NULL, 0); 3465 msleep(300); 3466 acpi_execute_simple_method(SXLV, NULL, 0); 3467 acpi_execute_simple_method(SXIO, NULL, 0); 3468 acpi_execute_simple_method(SXLV, NULL, 0); 3469 } 3470 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3471 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3472 quirk_apple_poweroff_thunderbolt); 3473 3474 /* 3475 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels 3476 * 3477 * During suspend the Thunderbolt controller is reset and all PCI 3478 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3479 * during resume. We have to manually wait for the NHI since there is 3480 * no parent child relationship between the NHI and the tunneled 3481 * bridges. 3482 */ 3483 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3484 { 3485 struct pci_dev *sibling = NULL; 3486 struct pci_dev *nhi = NULL; 3487 3488 if (!x86_apple_machine) 3489 return; 3490 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3491 return; 3492 3493 /* 3494 * Find the NHI and confirm that we are a bridge on the Thunderbolt 3495 * host controller and not on a Thunderbolt endpoint. 3496 */ 3497 sibling = pci_get_slot(dev->bus, 0x0); 3498 if (sibling == dev) 3499 goto out; /* we are the downstream bridge to the NHI */ 3500 if (!sibling || !sibling->subordinate) 3501 goto out; 3502 nhi = pci_get_slot(sibling->subordinate, 0x0); 3503 if (!nhi) 3504 goto out; 3505 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3506 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE && 3507 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C && 3508 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI && 3509 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) 3510 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) 3511 goto out; 3512 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n"); 3513 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3514 out: 3515 pci_dev_put(nhi); 3516 pci_dev_put(sibling); 3517 } 3518 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3519 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3520 quirk_apple_wait_for_thunderbolt); 3521 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3522 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3523 quirk_apple_wait_for_thunderbolt); 3524 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3525 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE, 3526 quirk_apple_wait_for_thunderbolt); 3527 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3528 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE, 3529 quirk_apple_wait_for_thunderbolt); 3530 #endif 3531 3532 /* 3533 * Following are device-specific reset methods which can be used to 3534 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3535 * not available. 3536 */ 3537 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3538 { 3539 /* 3540 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3541 * 3542 * The 82599 supports FLR on VFs, but FLR support is reported only 3543 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3544 * Thus we must call pcie_flr() directly without first checking if it is 3545 * supported. 3546 */ 3547 if (!probe) 3548 pcie_flr(dev); 3549 return 0; 3550 } 3551 3552 #define SOUTH_CHICKEN2 0xc2004 3553 #define PCH_PP_STATUS 0xc7200 3554 #define PCH_PP_CONTROL 0xc7204 3555 #define MSG_CTL 0x45010 3556 #define NSDE_PWR_STATE 0xd0100 3557 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3558 3559 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3560 { 3561 void __iomem *mmio_base; 3562 unsigned long timeout; 3563 u32 val; 3564 3565 if (probe) 3566 return 0; 3567 3568 mmio_base = pci_iomap(dev, 0, 0); 3569 if (!mmio_base) 3570 return -ENOMEM; 3571 3572 iowrite32(0x00000002, mmio_base + MSG_CTL); 3573 3574 /* 3575 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3576 * driver loaded sets the right bits. However, this's a reset and 3577 * the bits have been set by i915 previously, so we clobber 3578 * SOUTH_CHICKEN2 register directly here. 3579 */ 3580 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3581 3582 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3583 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3584 3585 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3586 do { 3587 val = ioread32(mmio_base + PCH_PP_STATUS); 3588 if ((val & 0xb0000000) == 0) 3589 goto reset_complete; 3590 msleep(10); 3591 } while (time_before(jiffies, timeout)); 3592 pci_warn(dev, "timeout during reset\n"); 3593 3594 reset_complete: 3595 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3596 3597 pci_iounmap(dev, mmio_base); 3598 return 0; 3599 } 3600 3601 /* Device-specific reset method for Chelsio T4-based adapters */ 3602 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3603 { 3604 u16 old_command; 3605 u16 msix_flags; 3606 3607 /* 3608 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3609 * that we have no device-specific reset method. 3610 */ 3611 if ((dev->device & 0xf000) != 0x4000) 3612 return -ENOTTY; 3613 3614 /* 3615 * If this is the "probe" phase, return 0 indicating that we can 3616 * reset this device. 3617 */ 3618 if (probe) 3619 return 0; 3620 3621 /* 3622 * T4 can wedge if there are DMAs in flight within the chip and Bus 3623 * Master has been disabled. We need to have it on till the Function 3624 * Level Reset completes. (BUS_MASTER is disabled in 3625 * pci_reset_function()). 3626 */ 3627 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3628 pci_write_config_word(dev, PCI_COMMAND, 3629 old_command | PCI_COMMAND_MASTER); 3630 3631 /* 3632 * Perform the actual device function reset, saving and restoring 3633 * configuration information around the reset. 3634 */ 3635 pci_save_state(dev); 3636 3637 /* 3638 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3639 * are disabled when an MSI-X interrupt message needs to be delivered. 3640 * So we briefly re-enable MSI-X interrupts for the duration of the 3641 * FLR. The pci_restore_state() below will restore the original 3642 * MSI-X state. 3643 */ 3644 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3645 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3646 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3647 msix_flags | 3648 PCI_MSIX_FLAGS_ENABLE | 3649 PCI_MSIX_FLAGS_MASKALL); 3650 3651 pcie_flr(dev); 3652 3653 /* 3654 * Restore the configuration information (BAR values, etc.) including 3655 * the original PCI Configuration Space Command word, and return 3656 * success. 3657 */ 3658 pci_restore_state(dev); 3659 pci_write_config_word(dev, PCI_COMMAND, old_command); 3660 return 0; 3661 } 3662 3663 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3664 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3665 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3666 3667 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3668 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3669 reset_intel_82599_sfp_virtfn }, 3670 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3671 reset_ivb_igd }, 3672 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3673 reset_ivb_igd }, 3674 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3675 reset_chelsio_generic_dev }, 3676 { 0 } 3677 }; 3678 3679 /* 3680 * These device-specific reset methods are here rather than in a driver 3681 * because when a host assigns a device to a guest VM, the host may need 3682 * to reset the device but probably doesn't have a driver for it. 3683 */ 3684 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3685 { 3686 const struct pci_dev_reset_methods *i; 3687 3688 for (i = pci_dev_reset_methods; i->reset; i++) { 3689 if ((i->vendor == dev->vendor || 3690 i->vendor == (u16)PCI_ANY_ID) && 3691 (i->device == dev->device || 3692 i->device == (u16)PCI_ANY_ID)) 3693 return i->reset(dev, probe); 3694 } 3695 3696 return -ENOTTY; 3697 } 3698 3699 static void quirk_dma_func0_alias(struct pci_dev *dev) 3700 { 3701 if (PCI_FUNC(dev->devfn) != 0) 3702 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 3703 } 3704 3705 /* 3706 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3707 * 3708 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3709 */ 3710 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3711 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3712 3713 static void quirk_dma_func1_alias(struct pci_dev *dev) 3714 { 3715 if (PCI_FUNC(dev->devfn) != 1) 3716 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1)); 3717 } 3718 3719 /* 3720 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3721 * SKUs function 1 is present and is a legacy IDE controller, in other 3722 * SKUs this function is not present, making this a ghost requester. 3723 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3724 */ 3725 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 3726 quirk_dma_func1_alias); 3727 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3728 quirk_dma_func1_alias); 3729 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 3730 quirk_dma_func1_alias); 3731 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3732 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3733 quirk_dma_func1_alias); 3734 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3736 quirk_dma_func1_alias); 3737 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3738 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3739 quirk_dma_func1_alias); 3740 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 3741 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 3742 quirk_dma_func1_alias); 3743 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3745 quirk_dma_func1_alias); 3746 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 3747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 3748 quirk_dma_func1_alias); 3749 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3751 quirk_dma_func1_alias); 3752 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3753 quirk_dma_func1_alias); 3754 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 3755 quirk_dma_func1_alias); 3756 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3757 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3758 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3759 quirk_dma_func1_alias); 3760 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 3761 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 3762 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 3763 quirk_dma_func1_alias); 3764 3765 /* 3766 * Some devices DMA with the wrong devfn, not just the wrong function. 3767 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3768 * the alias is "fixed" and independent of the device devfn. 3769 * 3770 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3771 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3772 * single device on the secondary bus. In reality, the single exposed 3773 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3774 * that provides a bridge to the internal bus of the I/O processor. The 3775 * controller supports private devices, which can be hidden from PCI config 3776 * space. In the case of the Adaptec 3405, a private device at 01.0 3777 * appears to be the DMA engine, which therefore needs to become a DMA 3778 * alias for the device. 3779 */ 3780 static const struct pci_device_id fixed_dma_alias_tbl[] = { 3781 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3782 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3783 .driver_data = PCI_DEVFN(1, 0) }, 3784 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3785 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 3786 .driver_data = PCI_DEVFN(1, 0) }, 3787 { 0 } 3788 }; 3789 3790 static void quirk_fixed_dma_alias(struct pci_dev *dev) 3791 { 3792 const struct pci_device_id *id; 3793 3794 id = pci_match_id(fixed_dma_alias_tbl, dev); 3795 if (id) 3796 pci_add_dma_alias(dev, id->driver_data); 3797 } 3798 3799 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3800 3801 /* 3802 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3803 * using the wrong DMA alias for the device. Some of these devices can be 3804 * used as either forward or reverse bridges, so we need to test whether the 3805 * device is operating in the correct mode. We could probably apply this 3806 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3807 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3808 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3809 */ 3810 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3811 { 3812 if (!pci_is_root_bus(pdev->bus) && 3813 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3814 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3815 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3816 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3817 } 3818 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3819 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3820 quirk_use_pcie_bridge_dma_alias); 3821 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3822 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3823 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3824 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3825 /* ITE 8893 has the same problem as the 8892 */ 3826 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 3827 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3828 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3829 3830 /* 3831 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 3832 * be added as aliases to the DMA device in order to allow buffer access 3833 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 3834 * programmed in the EEPROM. 3835 */ 3836 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 3837 { 3838 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0)); 3839 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0)); 3840 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3)); 3841 } 3842 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 3843 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 3844 3845 /* 3846 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 3847 * associated not at the root bus, but at a bridge below. This quirk avoids 3848 * generating invalid DMA aliases. 3849 */ 3850 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 3851 { 3852 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 3853 } 3854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 3855 quirk_bridge_cavm_thrx2_pcie_root); 3856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 3857 quirk_bridge_cavm_thrx2_pcie_root); 3858 3859 /* 3860 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 3861 * class code. Fix it. 3862 */ 3863 static void quirk_tw686x_class(struct pci_dev *pdev) 3864 { 3865 u32 class = pdev->class; 3866 3867 /* Use "Multimedia controller" class */ 3868 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 3869 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 3870 class, pdev->class); 3871 } 3872 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 3873 quirk_tw686x_class); 3874 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 3875 quirk_tw686x_class); 3876 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 3877 quirk_tw686x_class); 3878 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 3879 quirk_tw686x_class); 3880 3881 /* 3882 * Some devices have problems with Transaction Layer Packets with the Relaxed 3883 * Ordering Attribute set. Such devices should mark themselves and other 3884 * device drivers should check before sending TLPs with RO set. 3885 */ 3886 static void quirk_relaxedordering_disable(struct pci_dev *dev) 3887 { 3888 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 3889 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 3890 } 3891 3892 /* 3893 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 3894 * Complex have a Flow Control Credit issue which can cause performance 3895 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 3896 */ 3897 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 3898 quirk_relaxedordering_disable); 3899 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 3900 quirk_relaxedordering_disable); 3901 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 3902 quirk_relaxedordering_disable); 3903 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 3904 quirk_relaxedordering_disable); 3905 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 3906 quirk_relaxedordering_disable); 3907 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 3908 quirk_relaxedordering_disable); 3909 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 3910 quirk_relaxedordering_disable); 3911 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 3912 quirk_relaxedordering_disable); 3913 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 3914 quirk_relaxedordering_disable); 3915 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 3916 quirk_relaxedordering_disable); 3917 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 3918 quirk_relaxedordering_disable); 3919 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 3920 quirk_relaxedordering_disable); 3921 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 3922 quirk_relaxedordering_disable); 3923 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 3924 quirk_relaxedordering_disable); 3925 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 3926 quirk_relaxedordering_disable); 3927 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 3928 quirk_relaxedordering_disable); 3929 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 3930 quirk_relaxedordering_disable); 3931 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 3932 quirk_relaxedordering_disable); 3933 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 3934 quirk_relaxedordering_disable); 3935 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 3936 quirk_relaxedordering_disable); 3937 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 3938 quirk_relaxedordering_disable); 3939 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 3940 quirk_relaxedordering_disable); 3941 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 3942 quirk_relaxedordering_disable); 3943 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 3944 quirk_relaxedordering_disable); 3945 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 3946 quirk_relaxedordering_disable); 3947 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 3948 quirk_relaxedordering_disable); 3949 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 3950 quirk_relaxedordering_disable); 3951 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 3952 quirk_relaxedordering_disable); 3953 3954 /* 3955 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 3956 * where Upstream Transaction Layer Packets with the Relaxed Ordering 3957 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 3958 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 3959 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 3960 * November 10, 2010). As a result, on this platform we can't use Relaxed 3961 * Ordering for Upstream TLPs. 3962 */ 3963 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 3964 quirk_relaxedordering_disable); 3965 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 3966 quirk_relaxedordering_disable); 3967 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 3968 quirk_relaxedordering_disable); 3969 3970 /* 3971 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 3972 * values for the Attribute as were supplied in the header of the 3973 * corresponding Request, except as explicitly allowed when IDO is used." 3974 * 3975 * If a non-compliant device generates a completion with a different 3976 * attribute than the request, the receiver may accept it (which itself 3977 * seems non-compliant based on sec 2.3.2), or it may handle it as a 3978 * Malformed TLP or an Unexpected Completion, which will probably lead to a 3979 * device access timeout. 3980 * 3981 * If the non-compliant device generates completions with zero attributes 3982 * (instead of copying the attributes from the request), we can work around 3983 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 3984 * upstream devices so they always generate requests with zero attributes. 3985 * 3986 * This affects other devices under the same Root Port, but since these 3987 * attributes are performance hints, there should be no functional problem. 3988 * 3989 * Note that Configuration Space accesses are never supposed to have TLP 3990 * Attributes, so we're safe waiting till after any Configuration Space 3991 * accesses to do the Root Port fixup. 3992 */ 3993 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 3994 { 3995 struct pci_dev *root_port = pci_find_pcie_root_port(pdev); 3996 3997 if (!root_port) { 3998 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 3999 return; 4000 } 4001 4002 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4003 dev_name(&pdev->dev)); 4004 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4005 PCI_EXP_DEVCTL_RELAX_EN | 4006 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4007 } 4008 4009 /* 4010 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4011 * Completion it generates. 4012 */ 4013 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4014 { 4015 /* 4016 * This mask/compare operation selects for Physical Function 4 on a 4017 * T5. We only need to fix up the Root Port once for any of the 4018 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4019 * 0x54xx so we use that one. 4020 */ 4021 if ((pdev->device & 0xff00) == 0x5400) 4022 quirk_disable_root_port_attributes(pdev); 4023 } 4024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4025 quirk_chelsio_T5_disable_root_port_attributes); 4026 4027 /* 4028 * AMD has indicated that the devices below do not support peer-to-peer 4029 * in any system where they are found in the southbridge with an AMD 4030 * IOMMU in the system. Multifunction devices that do not support 4031 * peer-to-peer between functions can claim to support a subset of ACS. 4032 * Such devices effectively enable request redirect (RR) and completion 4033 * redirect (CR) since all transactions are redirected to the upstream 4034 * root complex. 4035 * 4036 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 4037 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 4038 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 4039 * 4040 * 1002:4385 SBx00 SMBus Controller 4041 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4042 * 1002:4383 SBx00 Azalia (Intel HDA) 4043 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4044 * 1002:4384 SBx00 PCI to PCI Bridge 4045 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4046 * 4047 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4048 * 4049 * 1022:780f [AMD] FCH PCI Bridge 4050 * 1022:7809 [AMD] FCH USB OHCI Controller 4051 */ 4052 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4053 { 4054 #ifdef CONFIG_ACPI 4055 struct acpi_table_header *header = NULL; 4056 acpi_status status; 4057 4058 /* Targeting multifunction devices on the SB (appears on root bus) */ 4059 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4060 return -ENODEV; 4061 4062 /* The IVRS table describes the AMD IOMMU */ 4063 status = acpi_get_table("IVRS", 0, &header); 4064 if (ACPI_FAILURE(status)) 4065 return -ENODEV; 4066 4067 /* Filter out flags not applicable to multifunction */ 4068 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4069 4070 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 4071 #else 4072 return -ENODEV; 4073 #endif 4074 } 4075 4076 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4077 { 4078 /* 4079 * Effectively selects all downstream ports for whole ThunderX 1 4080 * family by 0xf800 mask (which represents 8 SoCs), while the lower 4081 * bits of device ID are used to indicate which subdevice is used 4082 * within the SoC. 4083 */ 4084 return (pci_is_pcie(dev) && 4085 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) && 4086 ((dev->device & 0xf800) == 0xa000)); 4087 } 4088 4089 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4090 { 4091 /* 4092 * Cavium root ports don't advertise an ACS capability. However, 4093 * the RTL internally implements similar protection as if ACS had 4094 * Request Redirection, Completion Redirection, Source Validation, 4095 * and Upstream Forwarding features enabled. Assert that the 4096 * hardware implements and enables equivalent ACS functionality for 4097 * these flags. 4098 */ 4099 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF); 4100 4101 if (!pci_quirk_cavium_acs_match(dev)) 4102 return -ENOTTY; 4103 4104 return acs_flags ? 0 : 1; 4105 } 4106 4107 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4108 { 4109 /* 4110 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4111 * transactions with others, allowing masking out these bits as if they 4112 * were unimplemented in the ACS capability. 4113 */ 4114 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4115 4116 return acs_flags ? 0 : 1; 4117 } 4118 4119 /* 4120 * Many Intel PCH root ports do provide ACS-like features to disable peer 4121 * transactions and validate bus numbers in requests, but do not provide an 4122 * actual PCIe ACS capability. This is the list of device IDs known to fall 4123 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4124 */ 4125 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4126 /* Ibexpeak PCH */ 4127 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4128 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4129 /* Cougarpoint PCH */ 4130 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4131 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4132 /* Pantherpoint PCH */ 4133 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4134 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4135 /* Lynxpoint-H PCH */ 4136 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4137 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4138 /* Lynxpoint-LP PCH */ 4139 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4140 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4141 /* Wildcat PCH */ 4142 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4143 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4144 /* Patsburg (X79) PCH */ 4145 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4146 /* Wellsburg (X99) PCH */ 4147 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4148 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4149 /* Lynx Point (9 series) PCH */ 4150 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4151 }; 4152 4153 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4154 { 4155 int i; 4156 4157 /* Filter out a few obvious non-matches first */ 4158 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4159 return false; 4160 4161 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4162 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4163 return true; 4164 4165 return false; 4166 } 4167 4168 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 4169 4170 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4171 { 4172 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 4173 INTEL_PCH_ACS_FLAGS : 0; 4174 4175 if (!pci_quirk_intel_pch_acs_match(dev)) 4176 return -ENOTTY; 4177 4178 return acs_flags & ~flags ? 0 : 1; 4179 } 4180 4181 /* 4182 * These QCOM root ports do provide ACS-like features to disable peer 4183 * transactions and validate bus numbers in requests, but do not provide an 4184 * actual PCIe ACS capability. Hardware supports source validation but it 4185 * will report the issue as Completer Abort instead of ACS Violation. 4186 * Hardware doesn't support peer-to-peer and each root port is a root 4187 * complex with unique segment numbers. It is not possible for one root 4188 * port to pass traffic to another root port. All PCIe transactions are 4189 * terminated inside the root port. 4190 */ 4191 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4192 { 4193 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); 4194 int ret = acs_flags & ~flags ? 0 : 1; 4195 4196 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret); 4197 4198 return ret; 4199 } 4200 4201 /* 4202 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4203 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4204 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4205 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4206 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4207 * control register is at offset 8 instead of 6 and we should probably use 4208 * dword accesses to them. This applies to the following PCI Device IDs, as 4209 * found in volume 1 of the datasheet[2]: 4210 * 4211 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4212 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4213 * 4214 * N.B. This doesn't fix what lspci shows. 4215 * 4216 * The 100 series chipset specification update includes this as errata #23[3]. 4217 * 4218 * The 200 series chipset (Union Point) has the same bug according to the 4219 * specification update (Intel 200 Series Chipset Family Platform Controller 4220 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4221 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4222 * chipset include: 4223 * 4224 * 0xa290-0xa29f PCI Express Root port #{0-16} 4225 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4226 * 4227 * Mobile chipsets are also affected, 7th & 8th Generation 4228 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4229 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4230 * Processor Family I/O for U Quad Core Platforms Specification Update, 4231 * August 2017, Revision 002, Document#: 334660-002)[6] 4232 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4233 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4234 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4235 * 4236 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4237 * 4238 * The 300 series chipset suffers from the same bug so include those root 4239 * ports here as well. 4240 * 4241 * 0xa32c-0xa343 PCI Express Root port #{0-24} 4242 * 4243 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4244 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4245 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4246 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4247 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4248 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4249 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4250 */ 4251 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4252 { 4253 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4254 return false; 4255 4256 switch (dev->device) { 4257 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4258 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4259 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4260 case 0xa32c ... 0xa343: /* 300 series */ 4261 return true; 4262 } 4263 4264 return false; 4265 } 4266 4267 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4268 4269 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4270 { 4271 int pos; 4272 u32 cap, ctrl; 4273 4274 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4275 return -ENOTTY; 4276 4277 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4278 if (!pos) 4279 return -ENOTTY; 4280 4281 /* see pci_acs_flags_enabled() */ 4282 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4283 acs_flags &= (cap | PCI_ACS_EC); 4284 4285 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4286 4287 return acs_flags & ~ctrl ? 0 : 1; 4288 } 4289 4290 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4291 { 4292 /* 4293 * SV, TB, and UF are not relevant to multifunction endpoints. 4294 * 4295 * Multifunction devices are only required to implement RR, CR, and DT 4296 * in their ACS capability if they support peer-to-peer transactions. 4297 * Devices matching this quirk have been verified by the vendor to not 4298 * perform peer-to-peer with other functions, allowing us to mask out 4299 * these bits as if they were unimplemented in the ACS capability. 4300 */ 4301 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4302 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4303 4304 return acs_flags ? 0 : 1; 4305 } 4306 4307 static const struct pci_dev_acs_enabled { 4308 u16 vendor; 4309 u16 device; 4310 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4311 } pci_dev_acs_enabled[] = { 4312 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4313 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4314 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4315 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4316 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4317 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4318 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4319 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4320 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4321 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4322 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4323 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4324 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4325 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4326 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4327 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4328 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4329 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4330 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4331 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4332 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4333 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4334 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4335 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4336 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4337 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4338 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 4339 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 4340 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 4341 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 4342 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 4343 /* 82580 */ 4344 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 4345 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 4346 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 4347 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 4348 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 4349 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 4350 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 4351 /* 82576 */ 4352 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 4353 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 4354 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 4355 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 4356 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 4357 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 4358 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 4359 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 4360 /* 82575 */ 4361 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 4362 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 4363 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 4364 /* I350 */ 4365 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 4366 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 4367 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 4368 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 4369 /* 82571 (Quads omitted due to non-ACS switch) */ 4370 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 4371 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 4372 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 4373 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 4374 /* I219 */ 4375 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 4376 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 4377 /* QCOM QDF2xxx root ports */ 4378 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 4379 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 4380 /* Intel PCH root ports */ 4381 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 4382 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 4383 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 4384 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 4385 /* Cavium ThunderX */ 4386 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 4387 /* APM X-Gene */ 4388 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 4389 /* Ampere Computing */ 4390 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 4391 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 4392 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 4393 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 4394 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 4395 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 4396 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 4397 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 4398 { 0 } 4399 }; 4400 4401 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 4402 { 4403 const struct pci_dev_acs_enabled *i; 4404 int ret; 4405 4406 /* 4407 * Allow devices that do not expose standard PCIe ACS capabilities 4408 * or control to indicate their support here. Multi-function express 4409 * devices which do not allow internal peer-to-peer between functions, 4410 * but do not implement PCIe ACS may wish to return true here. 4411 */ 4412 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 4413 if ((i->vendor == dev->vendor || 4414 i->vendor == (u16)PCI_ANY_ID) && 4415 (i->device == dev->device || 4416 i->device == (u16)PCI_ANY_ID)) { 4417 ret = i->acs_enabled(dev, acs_flags); 4418 if (ret >= 0) 4419 return ret; 4420 } 4421 } 4422 4423 return -ENOTTY; 4424 } 4425 4426 /* Config space offset of Root Complex Base Address register */ 4427 #define INTEL_LPC_RCBA_REG 0xf0 4428 /* 31:14 RCBA address */ 4429 #define INTEL_LPC_RCBA_MASK 0xffffc000 4430 /* RCBA Enable */ 4431 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 4432 4433 /* Backbone Scratch Pad Register */ 4434 #define INTEL_BSPR_REG 0x1104 4435 /* Backbone Peer Non-Posted Disable */ 4436 #define INTEL_BSPR_REG_BPNPD (1 << 8) 4437 /* Backbone Peer Posted Disable */ 4438 #define INTEL_BSPR_REG_BPPD (1 << 9) 4439 4440 /* Upstream Peer Decode Configuration Register */ 4441 #define INTEL_UPDCR_REG 0x1114 4442 /* 5:0 Peer Decode Enable bits */ 4443 #define INTEL_UPDCR_REG_MASK 0x3f 4444 4445 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 4446 { 4447 u32 rcba, bspr, updcr; 4448 void __iomem *rcba_mem; 4449 4450 /* 4451 * Read the RCBA register from the LPC (D31:F0). PCH root ports 4452 * are D28:F* and therefore get probed before LPC, thus we can't 4453 * use pci_get_slot()/pci_read_config_dword() here. 4454 */ 4455 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 4456 INTEL_LPC_RCBA_REG, &rcba); 4457 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 4458 return -EINVAL; 4459 4460 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 4461 PAGE_ALIGN(INTEL_UPDCR_REG)); 4462 if (!rcba_mem) 4463 return -ENOMEM; 4464 4465 /* 4466 * The BSPR can disallow peer cycles, but it's set by soft strap and 4467 * therefore read-only. If both posted and non-posted peer cycles are 4468 * disallowed, we're ok. If either are allowed, then we need to use 4469 * the UPDCR to disable peer decodes for each port. This provides the 4470 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 4471 */ 4472 bspr = readl(rcba_mem + INTEL_BSPR_REG); 4473 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 4474 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 4475 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 4476 if (updcr & INTEL_UPDCR_REG_MASK) { 4477 pci_info(dev, "Disabling UPDCR peer decodes\n"); 4478 updcr &= ~INTEL_UPDCR_REG_MASK; 4479 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 4480 } 4481 } 4482 4483 iounmap(rcba_mem); 4484 return 0; 4485 } 4486 4487 /* Miscellaneous Port Configuration register */ 4488 #define INTEL_MPC_REG 0xd8 4489 /* MPC: Invalid Receive Bus Number Check Enable */ 4490 #define INTEL_MPC_REG_IRBNCE (1 << 26) 4491 4492 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 4493 { 4494 u32 mpc; 4495 4496 /* 4497 * When enabled, the IRBNCE bit of the MPC register enables the 4498 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 4499 * ensures that requester IDs fall within the bus number range 4500 * of the bridge. Enable if not already. 4501 */ 4502 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4503 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4504 pci_info(dev, "Enabling MPC IRBNCE\n"); 4505 mpc |= INTEL_MPC_REG_IRBNCE; 4506 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4507 } 4508 } 4509 4510 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 4511 { 4512 if (!pci_quirk_intel_pch_acs_match(dev)) 4513 return -ENOTTY; 4514 4515 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4516 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 4517 return 0; 4518 } 4519 4520 pci_quirk_enable_intel_rp_mpc_acs(dev); 4521 4522 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4523 4524 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 4525 4526 return 0; 4527 } 4528 4529 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 4530 { 4531 int pos; 4532 u32 cap, ctrl; 4533 4534 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4535 return -ENOTTY; 4536 4537 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4538 if (!pos) 4539 return -ENOTTY; 4540 4541 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4542 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4543 4544 ctrl |= (cap & PCI_ACS_SV); 4545 ctrl |= (cap & PCI_ACS_RR); 4546 ctrl |= (cap & PCI_ACS_CR); 4547 ctrl |= (cap & PCI_ACS_UF); 4548 4549 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4550 4551 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 4552 4553 return 0; 4554 } 4555 4556 static const struct pci_dev_enable_acs { 4557 u16 vendor; 4558 u16 device; 4559 int (*enable_acs)(struct pci_dev *dev); 4560 } pci_dev_enable_acs[] = { 4561 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, 4562 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs }, 4563 { 0 } 4564 }; 4565 4566 int pci_dev_specific_enable_acs(struct pci_dev *dev) 4567 { 4568 const struct pci_dev_enable_acs *i; 4569 int ret; 4570 4571 for (i = pci_dev_enable_acs; i->enable_acs; i++) { 4572 if ((i->vendor == dev->vendor || 4573 i->vendor == (u16)PCI_ANY_ID) && 4574 (i->device == dev->device || 4575 i->device == (u16)PCI_ANY_ID)) { 4576 ret = i->enable_acs(dev); 4577 if (ret >= 0) 4578 return ret; 4579 } 4580 } 4581 4582 return -ENOTTY; 4583 } 4584 4585 /* 4586 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 4587 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 4588 * Next Capability pointer in the MSI Capability Structure should point to 4589 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 4590 * the list. 4591 */ 4592 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 4593 { 4594 int pos, i = 0; 4595 u8 next_cap; 4596 u16 reg16, *cap; 4597 struct pci_cap_saved_state *state; 4598 4599 /* Bail if the hardware bug is fixed */ 4600 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 4601 return; 4602 4603 /* Bail if MSI Capability Structure is not found for some reason */ 4604 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 4605 if (!pos) 4606 return; 4607 4608 /* 4609 * Bail if Next Capability pointer in the MSI Capability Structure 4610 * is not the expected incorrect 0x00. 4611 */ 4612 pci_read_config_byte(pdev, pos + 1, &next_cap); 4613 if (next_cap) 4614 return; 4615 4616 /* 4617 * PCIe Capability Structure is expected to be at 0x50 and should 4618 * terminate the list (Next Capability pointer is 0x00). Verify 4619 * Capability Id and Next Capability pointer is as expected. 4620 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 4621 * to correctly set kernel data structures which have already been 4622 * set incorrectly due to the hardware bug. 4623 */ 4624 pos = 0x50; 4625 pci_read_config_word(pdev, pos, ®16); 4626 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 4627 u32 status; 4628 #ifndef PCI_EXP_SAVE_REGS 4629 #define PCI_EXP_SAVE_REGS 7 4630 #endif 4631 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 4632 4633 pdev->pcie_cap = pos; 4634 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 4635 pdev->pcie_flags_reg = reg16; 4636 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 4637 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 4638 4639 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4640 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 4641 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 4642 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 4643 4644 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 4645 return; 4646 4647 /* Save PCIe cap */ 4648 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 4649 if (!state) 4650 return; 4651 4652 state->cap.cap_nr = PCI_CAP_ID_EXP; 4653 state->cap.cap_extended = 0; 4654 state->cap.size = size; 4655 cap = (u16 *)&state->cap.data[0]; 4656 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 4657 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 4658 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 4659 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 4660 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 4661 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 4662 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 4663 hlist_add_head(&state->next, &pdev->saved_cap_space); 4664 } 4665 } 4666 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 4667 4668 /* FLR may cause some 82579 devices to hang */ 4669 static void quirk_intel_no_flr(struct pci_dev *dev) 4670 { 4671 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 4672 } 4673 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); 4674 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); 4675 4676 static void quirk_no_ext_tags(struct pci_dev *pdev) 4677 { 4678 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 4679 4680 if (!bridge) 4681 return; 4682 4683 bridge->no_ext_tags = 1; 4684 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 4685 4686 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 4687 } 4688 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 4689 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 4690 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 4691 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 4692 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 4693 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 4694 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 4695 4696 #ifdef CONFIG_PCI_ATS 4697 /* 4698 * Some devices have a broken ATS implementation causing IOMMU stalls. 4699 * Don't use ATS for those devices. 4700 */ 4701 static void quirk_no_ats(struct pci_dev *pdev) 4702 { 4703 pci_info(pdev, "disabling ATS (broken on this device)\n"); 4704 pdev->ats_cap = 0; 4705 } 4706 4707 /* AMD Stoney platform GPU */ 4708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); 4709 #endif /* CONFIG_PCI_ATS */ 4710 4711 /* Freescale PCIe doesn't support MSI in RC mode */ 4712 static void quirk_fsl_no_msi(struct pci_dev *pdev) 4713 { 4714 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 4715 pdev->no_msi = 1; 4716 } 4717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 4718 4719 /* 4720 * GPUs with integrated HDA controller for streaming audio to attached displays 4721 * need a device link from the HDA controller (consumer) to the GPU (supplier) 4722 * so that the GPU is powered up whenever the HDA controller is accessed. 4723 * The GPU and HDA controller are functions 0 and 1 of the same PCI device. 4724 * The device link stays in place until shutdown (or removal of the PCI device 4725 * if it's hotplugged). Runtime PM is allowed by default on the HDA controller 4726 * to prevent it from permanently keeping the GPU awake. 4727 */ 4728 static void quirk_gpu_hda(struct pci_dev *hda) 4729 { 4730 struct pci_dev *gpu; 4731 4732 if (PCI_FUNC(hda->devfn) != 1) 4733 return; 4734 4735 gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus), 4736 hda->bus->number, 4737 PCI_DEVFN(PCI_SLOT(hda->devfn), 0)); 4738 if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) { 4739 pci_dev_put(gpu); 4740 return; 4741 } 4742 4743 if (!device_link_add(&hda->dev, &gpu->dev, 4744 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 4745 pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu)); 4746 4747 pm_runtime_allow(&hda->dev); 4748 pci_dev_put(gpu); 4749 } 4750 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 4751 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4752 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 4753 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4754 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 4755 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4756