1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/align.h> 17 #include <linux/bitfield.h> 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/export.h> 21 #include <linux/pci.h> 22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 23 #include <linux/init.h> 24 #include <linux/iommu.h> 25 #include <linux/delay.h> 26 #include <linux/acpi.h> 27 #include <linux/dmi.h> 28 #include <linux/ioport.h> 29 #include <linux/sched.h> 30 #include <linux/ktime.h> 31 #include <linux/mm.h> 32 #include <linux/nvme.h> 33 #include <linux/platform_data/x86/apple.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/sizes.h> 36 #include <linux/suspend.h> 37 #include <linux/switchtec.h> 38 #include "pci.h" 39 40 static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta) 41 { 42 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) 43 return true; 44 45 return lnksta & PCI_EXP_LNKSTA_LBMS; 46 } 47 48 /* 49 * Retrain the link of a downstream PCIe port by hand if necessary. 50 * 51 * This is needed at least where a downstream port of the ASMedia ASM2824 52 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 53 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 54 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 55 * board. 56 * 57 * In such a configuration the switches are supposed to negotiate the link 58 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 59 * continues switching between the two speeds indefinitely and the data 60 * link layer never reaches the active state, with link training reported 61 * repeatedly active ~84% of the time. Forcing the target link speed to 62 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 63 * each other correctly however. And more interestingly retraining with a 64 * higher target link speed afterwards lets the two successfully negotiate 65 * 5.0GT/s. 66 * 67 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 68 * Link Active status bit and in the failed link training scenario it will 69 * be off along with the Link Bandwidth Management Status indicating that 70 * hardware has changed the link speed or width in an attempt to correct 71 * unreliable link operation. For a port that has been left unconnected 72 * both bits will be clear. So use this information to detect the problem 73 * rather than polling the Link Training bit and watching out for flips or 74 * at least the active status. 75 * 76 * Since the exact nature of the problem isn't known and in principle this 77 * could trigger where an ASM2824 device is downstream rather upstream, 78 * apply this erratum workaround to any downstream ports as long as they 79 * support Link Active reporting and have the Link Control 2 register. 80 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 81 * request a retrain and check the result. 82 * 83 * If this turns out successful and we know by the Vendor:Device ID it is 84 * safe to do so, then lift the restriction, letting the devices negotiate 85 * a higher speed. Also check for a similar 2.5GT/s speed restriction the 86 * firmware may have already arranged and lift it with ports that already 87 * report their data link being up. 88 * 89 * Otherwise revert the speed to the original setting and request a retrain 90 * again to remove any residual state, ignoring the result as it's supposed 91 * to fail anyway. 92 * 93 * Return 0 if the link has been successfully retrained. Return an error 94 * if retraining was not needed or we attempted a retrain and it failed. 95 */ 96 int pcie_failed_link_retrain(struct pci_dev *dev) 97 { 98 static const struct pci_device_id ids[] = { 99 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 100 {} 101 }; 102 u16 lnksta, lnkctl2; 103 int ret = -ENOTTY; 104 105 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 106 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 107 return ret; 108 109 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 110 if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) { 111 u16 oldlnkctl2; 112 113 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 114 115 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2); 116 ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false); 117 if (ret) { 118 pci_info(dev, "retraining failed\n"); 119 pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), 120 true); 121 return ret; 122 } 123 124 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 125 } 126 127 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 128 129 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && 130 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && 131 pci_match_id(ids, dev)) { 132 u32 lnkcap; 133 134 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 135 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 136 ret = pcie_set_target_speed(dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), false); 137 if (ret) { 138 pci_info(dev, "retraining failed\n"); 139 return ret; 140 } 141 } 142 143 return ret; 144 } 145 146 static ktime_t fixup_debug_start(struct pci_dev *dev, 147 void (*fn)(struct pci_dev *dev)) 148 { 149 if (initcall_debug) 150 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 151 152 return ktime_get(); 153 } 154 155 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 156 void (*fn)(struct pci_dev *dev)) 157 { 158 ktime_t delta, rettime; 159 unsigned long long duration; 160 161 rettime = ktime_get(); 162 delta = ktime_sub(rettime, calltime); 163 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 164 if (initcall_debug || duration > 10000) 165 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 166 } 167 168 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 169 struct pci_fixup *end) 170 { 171 ktime_t calltime; 172 173 for (; f < end; f++) 174 if ((f->class == (u32) (dev->class >> f->class_shift) || 175 f->class == (u32) PCI_ANY_ID) && 176 (f->vendor == dev->vendor || 177 f->vendor == (u16) PCI_ANY_ID) && 178 (f->device == dev->device || 179 f->device == (u16) PCI_ANY_ID)) { 180 void (*hook)(struct pci_dev *dev); 181 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 182 hook = offset_to_ptr(&f->hook_offset); 183 #else 184 hook = f->hook; 185 #endif 186 calltime = fixup_debug_start(dev, hook); 187 hook(dev); 188 fixup_debug_report(dev, calltime, hook); 189 } 190 } 191 192 extern struct pci_fixup __start_pci_fixups_early[]; 193 extern struct pci_fixup __end_pci_fixups_early[]; 194 extern struct pci_fixup __start_pci_fixups_header[]; 195 extern struct pci_fixup __end_pci_fixups_header[]; 196 extern struct pci_fixup __start_pci_fixups_final[]; 197 extern struct pci_fixup __end_pci_fixups_final[]; 198 extern struct pci_fixup __start_pci_fixups_enable[]; 199 extern struct pci_fixup __end_pci_fixups_enable[]; 200 extern struct pci_fixup __start_pci_fixups_resume[]; 201 extern struct pci_fixup __end_pci_fixups_resume[]; 202 extern struct pci_fixup __start_pci_fixups_resume_early[]; 203 extern struct pci_fixup __end_pci_fixups_resume_early[]; 204 extern struct pci_fixup __start_pci_fixups_suspend[]; 205 extern struct pci_fixup __end_pci_fixups_suspend[]; 206 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 207 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 208 209 static bool pci_apply_fixup_final_quirks; 210 211 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 212 { 213 struct pci_fixup *start, *end; 214 215 switch (pass) { 216 case pci_fixup_early: 217 start = __start_pci_fixups_early; 218 end = __end_pci_fixups_early; 219 break; 220 221 case pci_fixup_header: 222 start = __start_pci_fixups_header; 223 end = __end_pci_fixups_header; 224 break; 225 226 case pci_fixup_final: 227 if (!pci_apply_fixup_final_quirks) 228 return; 229 start = __start_pci_fixups_final; 230 end = __end_pci_fixups_final; 231 break; 232 233 case pci_fixup_enable: 234 start = __start_pci_fixups_enable; 235 end = __end_pci_fixups_enable; 236 break; 237 238 case pci_fixup_resume: 239 start = __start_pci_fixups_resume; 240 end = __end_pci_fixups_resume; 241 break; 242 243 case pci_fixup_resume_early: 244 start = __start_pci_fixups_resume_early; 245 end = __end_pci_fixups_resume_early; 246 break; 247 248 case pci_fixup_suspend: 249 start = __start_pci_fixups_suspend; 250 end = __end_pci_fixups_suspend; 251 break; 252 253 case pci_fixup_suspend_late: 254 start = __start_pci_fixups_suspend_late; 255 end = __end_pci_fixups_suspend_late; 256 break; 257 258 default: 259 /* stupid compiler warning, you would think with an enum... */ 260 return; 261 } 262 pci_do_fixups(dev, start, end); 263 } 264 EXPORT_SYMBOL(pci_fixup_device); 265 266 static int __init pci_apply_final_quirks(void) 267 { 268 struct pci_dev *dev = NULL; 269 u8 cls = 0; 270 u8 tmp; 271 272 if (pci_cache_line_size) 273 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 274 275 pci_apply_fixup_final_quirks = true; 276 for_each_pci_dev(dev) { 277 pci_fixup_device(pci_fixup_final, dev); 278 /* 279 * If arch hasn't set it explicitly yet, use the CLS 280 * value shared by all PCI devices. If there's a 281 * mismatch, fall back to the default value. 282 */ 283 if (!pci_cache_line_size) { 284 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 285 if (!cls) 286 cls = tmp; 287 if (!tmp || cls == tmp) 288 continue; 289 290 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 291 cls << 2, tmp << 2, 292 pci_dfl_cache_line_size << 2); 293 pci_cache_line_size = pci_dfl_cache_line_size; 294 } 295 } 296 297 if (!pci_cache_line_size) { 298 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 299 pci_dfl_cache_line_size << 2); 300 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 301 } 302 303 return 0; 304 } 305 fs_initcall_sync(pci_apply_final_quirks); 306 307 /* 308 * Decoding should be disabled for a PCI device during BAR sizing to avoid 309 * conflict. But doing so may cause problems on host bridge and perhaps other 310 * key system devices. For devices that need to have mmio decoding always-on, 311 * we need to set the dev->mmio_always_on bit. 312 */ 313 static void quirk_mmio_always_on(struct pci_dev *dev) 314 { 315 dev->mmio_always_on = 1; 316 } 317 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 318 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 319 320 /* 321 * The Mellanox Tavor device gives false positive parity errors. Disable 322 * parity error reporting. 323 */ 324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 326 327 /* 328 * Deal with broken BIOSes that neglect to enable passive release, 329 * which can cause problems in combination with the 82441FX/PPro MTRRs 330 */ 331 static void quirk_passive_release(struct pci_dev *dev) 332 { 333 struct pci_dev *d = NULL; 334 unsigned char dlc; 335 336 /* 337 * We have to make sure a particular bit is set in the PIIX3 338 * ISA bridge, so we have to go out and find it. 339 */ 340 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 341 pci_read_config_byte(d, 0x82, &dlc); 342 if (!(dlc & 1<<1)) { 343 pci_info(d, "PIIX3: Enabling Passive Release\n"); 344 dlc |= 1<<1; 345 pci_write_config_byte(d, 0x82, dlc); 346 } 347 } 348 } 349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 350 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 351 352 #ifdef CONFIG_X86_32 353 /* 354 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 355 * workaround but VIA don't answer queries. If you happen to have good 356 * contacts at VIA ask them for me please -- Alan 357 * 358 * This appears to be BIOS not version dependent. So presumably there is a 359 * chipset level fix. 360 */ 361 static void quirk_isa_dma_hangs(struct pci_dev *dev) 362 { 363 if (!isa_dma_bridge_buggy) { 364 isa_dma_bridge_buggy = 1; 365 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 366 } 367 } 368 /* 369 * It's not totally clear which chipsets are the problematic ones. We know 370 * 82C586 and 82C596 variants are affected. 371 */ 372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 379 #endif 380 381 #ifdef CONFIG_HAS_IOPORT 382 /* 383 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 384 * for some HT machines to use C4 w/o hanging. 385 */ 386 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 387 { 388 u32 pmbase; 389 u16 pm1a; 390 391 pci_read_config_dword(dev, 0x40, &pmbase); 392 pmbase = pmbase & 0xff80; 393 pm1a = inw(pmbase); 394 395 if (pm1a & 0x10) { 396 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 397 outw(0x10, pmbase); 398 } 399 } 400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 401 #endif 402 403 /* Chipsets where PCI->PCI transfers vanish or hang */ 404 static void quirk_nopcipci(struct pci_dev *dev) 405 { 406 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 407 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 408 pci_pci_problems |= PCIPCI_FAIL; 409 } 410 } 411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 413 414 static void quirk_nopciamd(struct pci_dev *dev) 415 { 416 u8 rev; 417 pci_read_config_byte(dev, 0x08, &rev); 418 if (rev == 0x13) { 419 /* Erratum 24 */ 420 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 421 pci_pci_problems |= PCIAGP_FAIL; 422 } 423 } 424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 425 426 /* Triton requires workarounds to be used by the drivers */ 427 static void quirk_triton(struct pci_dev *dev) 428 { 429 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 430 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 431 pci_pci_problems |= PCIPCI_TRITON; 432 } 433 } 434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 438 439 /* 440 * VIA Apollo KT133 needs PCI latency patch 441 * Made according to a Windows driver-based patch by George E. Breese; 442 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 443 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 444 * which Mr Breese based his work. 445 * 446 * Updated based on further information from the site and also on 447 * information provided by VIA 448 */ 449 static void quirk_vialatency(struct pci_dev *dev) 450 { 451 struct pci_dev *p; 452 u8 busarb; 453 454 /* 455 * Ok, we have a potential problem chipset here. Now see if we have 456 * a buggy southbridge. 457 */ 458 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 459 if (p != NULL) { 460 461 /* 462 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 463 * thanks Dan Hollis. 464 * Check for buggy part revisions 465 */ 466 if (p->revision < 0x40 || p->revision > 0x42) 467 goto exit; 468 } else { 469 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 470 if (p == NULL) /* No problem parts */ 471 goto exit; 472 473 /* Check for buggy part revisions */ 474 if (p->revision < 0x10 || p->revision > 0x12) 475 goto exit; 476 } 477 478 /* 479 * Ok we have the problem. Now set the PCI master grant to occur 480 * every master grant. The apparent bug is that under high PCI load 481 * (quite common in Linux of course) you can get data loss when the 482 * CPU is held off the bus for 3 bus master requests. This happens 483 * to include the IDE controllers.... 484 * 485 * VIA only apply this fix when an SB Live! is present but under 486 * both Linux and Windows this isn't enough, and we have seen 487 * corruption without SB Live! but with things like 3 UDMA IDE 488 * controllers. So we ignore that bit of the VIA recommendation.. 489 */ 490 pci_read_config_byte(dev, 0x76, &busarb); 491 492 /* 493 * Set bit 4 and bit 5 of byte 76 to 0x01 494 * "Master priority rotation on every PCI master grant" 495 */ 496 busarb &= ~(1<<5); 497 busarb |= (1<<4); 498 pci_write_config_byte(dev, 0x76, busarb); 499 pci_info(dev, "Applying VIA southbridge workaround\n"); 500 exit: 501 pci_dev_put(p); 502 } 503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 506 /* Must restore this on a resume from RAM */ 507 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 508 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 509 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 510 511 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 512 static void quirk_viaetbf(struct pci_dev *dev) 513 { 514 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 515 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 516 pci_pci_problems |= PCIPCI_VIAETBF; 517 } 518 } 519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 520 521 static void quirk_vsfx(struct pci_dev *dev) 522 { 523 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 524 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 525 pci_pci_problems |= PCIPCI_VSFX; 526 } 527 } 528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 529 530 /* 531 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 532 * space. Latency must be set to 0xA and Triton workaround applied too. 533 * [Info kindly provided by ALi] 534 */ 535 static void quirk_alimagik(struct pci_dev *dev) 536 { 537 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 538 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 539 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 540 } 541 } 542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 544 545 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 546 static void quirk_natoma(struct pci_dev *dev) 547 { 548 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 549 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 550 pci_pci_problems |= PCIPCI_NATOMA; 551 } 552 } 553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 559 560 /* 561 * This chip can cause PCI parity errors if config register 0xA0 is read 562 * while DMAs are occurring. 563 */ 564 static void quirk_citrine(struct pci_dev *dev) 565 { 566 dev->cfg_size = 0xA0; 567 } 568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 569 570 /* 571 * This chip can cause bus lockups if config addresses above 0x600 572 * are read or written. 573 */ 574 static void quirk_nfp6000(struct pci_dev *dev) 575 { 576 dev->cfg_size = 0x600; 577 } 578 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 582 583 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 584 static void quirk_extend_bar_to_page(struct pci_dev *dev) 585 { 586 int i; 587 588 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 589 struct resource *r = &dev->resource[i]; 590 const char *r_name = pci_resource_name(dev, i); 591 592 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 593 resource_set_range(r, 0, PAGE_SIZE); 594 r->flags |= IORESOURCE_UNSET; 595 pci_info(dev, "%s %pR: expanded to page size\n", 596 r_name, r); 597 } 598 } 599 } 600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 601 602 /* 603 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 604 * If it's needed, re-allocate the region. 605 */ 606 static void quirk_s3_64M(struct pci_dev *dev) 607 { 608 struct resource *r = &dev->resource[0]; 609 610 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) { 611 r->flags |= IORESOURCE_UNSET; 612 resource_set_range(r, 0, SZ_64M); 613 } 614 } 615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 617 618 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 619 const char *name) 620 { 621 u32 region; 622 struct pci_bus_region bus_region; 623 struct resource *res = pci_resource_n(dev, pos); 624 const char *res_name = pci_resource_name(dev, pos); 625 626 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 627 628 if (!region) 629 return; 630 631 res->name = pci_name(dev); 632 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 633 res->flags |= 634 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 635 region &= ~(size - 1); 636 637 /* Convert from PCI bus to resource space */ 638 bus_region.start = region; 639 bus_region.end = region + size - 1; 640 pcibios_bus_to_resource(dev->bus, res, &bus_region); 641 642 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name); 643 } 644 645 /* 646 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 647 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 648 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 649 * (which conflicts w/ BAR1's memory range). 650 * 651 * CS553x's ISA PCI BARs may also be read-only (ref: 652 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 653 */ 654 static void quirk_cs5536_vsa(struct pci_dev *dev) 655 { 656 static char *name = "CS5536 ISA bridge"; 657 658 if (pci_resource_len(dev, 0) != 8) { 659 quirk_io(dev, 0, 8, name); /* SMB */ 660 quirk_io(dev, 1, 256, name); /* GPIO */ 661 quirk_io(dev, 2, 64, name); /* MFGPT */ 662 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 663 name); 664 } 665 } 666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 667 668 static void quirk_io_region(struct pci_dev *dev, int port, 669 unsigned int size, int nr, const char *name) 670 { 671 u16 region; 672 struct pci_bus_region bus_region; 673 struct resource *res = pci_resource_n(dev, nr); 674 675 pci_read_config_word(dev, port, ®ion); 676 region &= ~(size - 1); 677 678 if (!region) 679 return; 680 681 res->name = pci_name(dev); 682 res->flags = IORESOURCE_IO; 683 684 /* Convert from PCI bus to resource space */ 685 bus_region.start = region; 686 bus_region.end = region + size - 1; 687 pcibios_bus_to_resource(dev->bus, res, &bus_region); 688 689 /* 690 * "res" is typically a bridge window resource that's not being 691 * used for a bridge window, so it's just a place to stash this 692 * non-standard resource. Printing "nr" or pci_resource_name() of 693 * it doesn't really make sense. 694 */ 695 if (!pci_claim_resource(dev, nr)) 696 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 697 } 698 699 /* 700 * ATI Northbridge setups MCE the processor if you even read somewhere 701 * between 0x3b0->0x3bb or read 0x3d3 702 */ 703 static void quirk_ati_exploding_mce(struct pci_dev *dev) 704 { 705 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 706 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 707 request_region(0x3b0, 0x0C, "RadeonIGP"); 708 request_region(0x3d3, 0x01, "RadeonIGP"); 709 } 710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 711 712 /* 713 * In the AMD NL platform, this device ([1022:7912]) has a class code of 714 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 715 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 716 * 717 * But the dwc3 driver is a more specific driver for this device, and we'd 718 * prefer to use it instead of xhci. To prevent xhci from claiming the 719 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 720 * defines as "USB device (not host controller)". The dwc3 driver can then 721 * claim it based on its Vendor and Device ID. 722 */ 723 static void quirk_amd_dwc_class(struct pci_dev *pdev) 724 { 725 u32 class = pdev->class; 726 727 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 728 /* Use "USB Device (not host controller)" class */ 729 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 730 pci_info(pdev, 731 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 732 class, pdev->class); 733 } 734 } 735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 736 quirk_amd_dwc_class); 737 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 738 quirk_amd_dwc_class); 739 740 /* 741 * Synopsys USB 3.x host HAPS platform has a class code of 742 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 743 * devices should use dwc3-haps driver. Change these devices' class code to 744 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 745 * them. 746 */ 747 static void quirk_synopsys_haps(struct pci_dev *pdev) 748 { 749 u32 class = pdev->class; 750 751 switch (pdev->device) { 752 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 753 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 754 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 755 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 756 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 757 class, pdev->class); 758 break; 759 } 760 } 761 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 762 PCI_CLASS_SERIAL_USB_XHCI, 0, 763 quirk_synopsys_haps); 764 765 /* 766 * Let's make the southbridge information explicit instead of having to 767 * worry about people probing the ACPI areas, for example.. (Yes, it 768 * happens, and if you read the wrong ACPI register it will put the machine 769 * to sleep with no way of waking it up again. Bummer). 770 * 771 * ALI M7101: Two IO regions pointed to by words at 772 * 0xE0 (64 bytes of ACPI registers) 773 * 0xE2 (32 bytes of SMB registers) 774 */ 775 static void quirk_ali7101_acpi(struct pci_dev *dev) 776 { 777 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 778 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 779 } 780 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 781 782 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 783 { 784 u32 devres; 785 u32 mask, size, base; 786 787 pci_read_config_dword(dev, port, &devres); 788 if ((devres & enable) != enable) 789 return; 790 mask = (devres >> 16) & 15; 791 base = devres & 0xffff; 792 size = 16; 793 for (;;) { 794 unsigned int bit = size >> 1; 795 if ((bit & mask) == bit) 796 break; 797 size = bit; 798 } 799 /* 800 * For now we only print it out. Eventually we'll want to 801 * reserve it (at least if it's in the 0x1000+ range), but 802 * let's get enough confirmation reports first. 803 */ 804 base &= -size; 805 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 806 } 807 808 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 809 { 810 u32 devres; 811 u32 mask, size, base; 812 813 pci_read_config_dword(dev, port, &devres); 814 if ((devres & enable) != enable) 815 return; 816 base = devres & 0xffff0000; 817 mask = (devres & 0x3f) << 16; 818 size = 128 << 16; 819 for (;;) { 820 unsigned int bit = size >> 1; 821 if ((bit & mask) == bit) 822 break; 823 size = bit; 824 } 825 826 /* 827 * For now we only print it out. Eventually we'll want to 828 * reserve it, but let's get enough confirmation reports first. 829 */ 830 base &= -size; 831 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 832 } 833 834 /* 835 * PIIX4 ACPI: Two IO regions pointed to by longwords at 836 * 0x40 (64 bytes of ACPI registers) 837 * 0x90 (16 bytes of SMB registers) 838 * and a few strange programmable PIIX4 device resources. 839 */ 840 static void quirk_piix4_acpi(struct pci_dev *dev) 841 { 842 u32 res_a; 843 844 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 845 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 846 847 /* Device resource A has enables for some of the other ones */ 848 pci_read_config_dword(dev, 0x5c, &res_a); 849 850 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 851 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 852 853 /* Device resource D is just bitfields for static resources */ 854 855 /* Device 12 enabled? */ 856 if (res_a & (1 << 29)) { 857 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 858 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 859 } 860 /* Device 13 enabled? */ 861 if (res_a & (1 << 30)) { 862 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 863 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 864 } 865 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 866 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 867 } 868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 870 871 #define ICH_PMBASE 0x40 872 #define ICH_ACPI_CNTL 0x44 873 #define ICH4_ACPI_EN 0x10 874 #define ICH6_ACPI_EN 0x80 875 #define ICH4_GPIOBASE 0x58 876 #define ICH4_GPIO_CNTL 0x5c 877 #define ICH4_GPIO_EN 0x10 878 #define ICH6_GPIOBASE 0x48 879 #define ICH6_GPIO_CNTL 0x4c 880 #define ICH6_GPIO_EN 0x10 881 882 /* 883 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 884 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 885 * 0x58 (64 bytes of GPIO I/O space) 886 */ 887 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 888 { 889 u8 enable; 890 891 /* 892 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 893 * with low legacy (and fixed) ports. We don't know the decoding 894 * priority and can't tell whether the legacy device or the one created 895 * here is really at that address. This happens on boards with broken 896 * BIOSes. 897 */ 898 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 899 if (enable & ICH4_ACPI_EN) 900 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 901 "ICH4 ACPI/GPIO/TCO"); 902 903 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 904 if (enable & ICH4_GPIO_EN) 905 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 906 "ICH4 GPIO"); 907 } 908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 918 919 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 920 { 921 u8 enable; 922 923 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 924 if (enable & ICH6_ACPI_EN) 925 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 926 "ICH6 ACPI/GPIO/TCO"); 927 928 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 929 if (enable & ICH6_GPIO_EN) 930 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 931 "ICH6 GPIO"); 932 } 933 934 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 935 const char *name, int dynsize) 936 { 937 u32 val; 938 u32 size, base; 939 940 pci_read_config_dword(dev, reg, &val); 941 942 /* Enabled? */ 943 if (!(val & 1)) 944 return; 945 base = val & 0xfffc; 946 if (dynsize) { 947 /* 948 * This is not correct. It is 16, 32 or 64 bytes depending on 949 * register D31:F0:ADh bits 5:4. 950 * 951 * But this gets us at least _part_ of it. 952 */ 953 size = 16; 954 } else { 955 size = 128; 956 } 957 base &= ~(size-1); 958 959 /* 960 * Just print it out for now. We should reserve it after more 961 * debugging. 962 */ 963 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 964 } 965 966 static void quirk_ich6_lpc(struct pci_dev *dev) 967 { 968 /* Shared ACPI/GPIO decode with all ICH6+ */ 969 ich6_lpc_acpi_gpio(dev); 970 971 /* ICH6-specific generic IO decode */ 972 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 973 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 974 } 975 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 977 978 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 979 const char *name) 980 { 981 u32 val; 982 u32 mask, base; 983 984 pci_read_config_dword(dev, reg, &val); 985 986 /* Enabled? */ 987 if (!(val & 1)) 988 return; 989 990 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 991 base = val & 0xfffc; 992 mask = (val >> 16) & 0xfc; 993 mask |= 3; 994 995 /* 996 * Just print it out for now. We should reserve it after more 997 * debugging. 998 */ 999 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 1000 } 1001 1002 /* ICH7-10 has the same common LPC generic IO decode registers */ 1003 static void quirk_ich7_lpc(struct pci_dev *dev) 1004 { 1005 /* We share the common ACPI/GPIO decode with ICH6 */ 1006 ich6_lpc_acpi_gpio(dev); 1007 1008 /* And have 4 ICH7+ generic decodes */ 1009 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 1010 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 1011 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 1012 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 1013 } 1014 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 1015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 1016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 1017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 1018 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 1019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 1020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 1021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 1022 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 1023 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 1024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1027 1028 /* 1029 * VIA ACPI: One IO region pointed to by longword at 1030 * 0x48 or 0x20 (256 bytes of ACPI registers) 1031 */ 1032 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1033 { 1034 if (dev->revision & 0x10) 1035 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1036 "vt82c586 ACPI"); 1037 } 1038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1039 1040 /* 1041 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1042 * 0x48 (256 bytes of ACPI registers) 1043 * 0x70 (128 bytes of hardware monitoring register) 1044 * 0x90 (16 bytes of SMB registers) 1045 */ 1046 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1047 { 1048 quirk_vt82c586_acpi(dev); 1049 1050 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1051 "vt82c686 HW-mon"); 1052 1053 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1054 } 1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1056 1057 /* 1058 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1059 * 0x88 (128 bytes of power management registers) 1060 * 0xd0 (16 bytes of SMB registers) 1061 */ 1062 static void quirk_vt8235_acpi(struct pci_dev *dev) 1063 { 1064 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1065 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1066 } 1067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1068 1069 /* 1070 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1071 * back-to-back: Disable fast back-to-back on the secondary bus segment 1072 */ 1073 static void quirk_xio2000a(struct pci_dev *dev) 1074 { 1075 struct pci_dev *pdev; 1076 u16 command; 1077 1078 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1079 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1080 pci_read_config_word(pdev, PCI_COMMAND, &command); 1081 if (command & PCI_COMMAND_FAST_BACK) 1082 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1083 } 1084 } 1085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1086 quirk_xio2000a); 1087 1088 #ifdef CONFIG_X86_IO_APIC 1089 1090 #include <asm/io_apic.h> 1091 1092 /* 1093 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1094 * devices to the external APIC. 1095 * 1096 * TODO: When we have device-specific interrupt routers, this code will go 1097 * away from quirks. 1098 */ 1099 static void quirk_via_ioapic(struct pci_dev *dev) 1100 { 1101 u8 tmp; 1102 1103 if (nr_ioapics < 1) 1104 tmp = 0; /* nothing routed to external APIC */ 1105 else 1106 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1107 1108 pci_info(dev, "%s VIA external APIC routing\n", 1109 tmp ? "Enabling" : "Disabling"); 1110 1111 /* Offset 0x58: External APIC IRQ output control */ 1112 pci_write_config_byte(dev, 0x58, tmp); 1113 } 1114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1115 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1116 1117 /* 1118 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1119 * This leads to doubled level interrupt rates. 1120 * Set this bit to get rid of cycle wastage. 1121 * Otherwise uncritical. 1122 */ 1123 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1124 { 1125 u8 misc_control2; 1126 #define BYPASS_APIC_DEASSERT 8 1127 1128 pci_read_config_byte(dev, 0x5B, &misc_control2); 1129 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1130 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1131 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1132 } 1133 } 1134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1135 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1136 1137 /* 1138 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1139 * We check all revs >= B0 (yet not in the pre production!) as the bug 1140 * is currently marked NoFix 1141 * 1142 * We have multiple reports of hangs with this chipset that went away with 1143 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1144 * of course. However the advice is demonstrably good even if so. 1145 */ 1146 static void quirk_amd_ioapic(struct pci_dev *dev) 1147 { 1148 if (dev->revision >= 0x02) { 1149 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1150 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1151 } 1152 } 1153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1154 #endif /* CONFIG_X86_IO_APIC */ 1155 1156 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1157 1158 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1159 { 1160 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1161 if (dev->subsystem_device == 0xa118) 1162 dev->sriov->link = dev->devfn; 1163 } 1164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1165 #endif 1166 1167 /* 1168 * Some settings of MMRBC can lead to data corruption so block changes. 1169 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1170 */ 1171 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1172 { 1173 if (dev->subordinate && dev->revision <= 0x12) { 1174 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1175 dev->revision); 1176 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1177 } 1178 } 1179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1180 1181 /* 1182 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1183 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1184 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1185 * of the ACPI SCI interrupt is only done for convenience. 1186 * -jgarzik 1187 */ 1188 static void quirk_via_acpi(struct pci_dev *d) 1189 { 1190 u8 irq; 1191 1192 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1193 pci_read_config_byte(d, 0x42, &irq); 1194 irq &= 0xf; 1195 if (irq && (irq != 2)) 1196 d->irq = irq; 1197 } 1198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1200 1201 /* VIA bridges which have VLink */ 1202 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1203 1204 static void quirk_via_bridge(struct pci_dev *dev) 1205 { 1206 /* See what bridge we have and find the device ranges */ 1207 switch (dev->device) { 1208 case PCI_DEVICE_ID_VIA_82C686: 1209 /* 1210 * The VT82C686 is special; it attaches to PCI and can have 1211 * any device number. All its subdevices are functions of 1212 * that single device. 1213 */ 1214 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1215 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1216 break; 1217 case PCI_DEVICE_ID_VIA_8237: 1218 case PCI_DEVICE_ID_VIA_8237A: 1219 via_vlink_dev_lo = 15; 1220 break; 1221 case PCI_DEVICE_ID_VIA_8235: 1222 via_vlink_dev_lo = 16; 1223 break; 1224 case PCI_DEVICE_ID_VIA_8231: 1225 case PCI_DEVICE_ID_VIA_8233_0: 1226 case PCI_DEVICE_ID_VIA_8233A: 1227 case PCI_DEVICE_ID_VIA_8233C_0: 1228 via_vlink_dev_lo = 17; 1229 break; 1230 } 1231 } 1232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1240 1241 /* 1242 * quirk_via_vlink - VIA VLink IRQ number update 1243 * @dev: PCI device 1244 * 1245 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1246 * the IRQ line register which usually is not relevant for PCI cards, is 1247 * actually written so that interrupts get sent to the right place. 1248 * 1249 * We only do this on systems where a VIA south bridge was detected, and 1250 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1251 */ 1252 static void quirk_via_vlink(struct pci_dev *dev) 1253 { 1254 u8 irq, new_irq; 1255 1256 /* Check if we have VLink at all */ 1257 if (via_vlink_dev_lo == -1) 1258 return; 1259 1260 new_irq = dev->irq; 1261 1262 /* Don't quirk interrupts outside the legacy IRQ range */ 1263 if (!new_irq || new_irq > 15) 1264 return; 1265 1266 /* Internal device ? */ 1267 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1268 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1269 return; 1270 1271 /* 1272 * This is an internal VLink device on a PIC interrupt. The BIOS 1273 * ought to have set this but may not have, so we redo it. 1274 */ 1275 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1276 if (new_irq != irq) { 1277 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1278 irq, new_irq); 1279 udelay(15); /* unknown if delay really needed */ 1280 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1281 } 1282 } 1283 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1284 1285 /* 1286 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1287 * of VT82C597 for backward compatibility. We need to switch it off to be 1288 * able to recognize the real type of the chip. 1289 */ 1290 static void quirk_vt82c598_id(struct pci_dev *dev) 1291 { 1292 pci_write_config_byte(dev, 0xfc, 0); 1293 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1294 } 1295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1296 1297 /* 1298 * CardBus controllers have a legacy base address that enables them to 1299 * respond as i82365 PCMCIA controllers. We don't want them to do this. 1300 */ 1301 static void quirk_cardbus_legacy(struct pci_dev *dev) 1302 { 1303 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1304 } 1305 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1306 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1307 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1308 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1309 1310 /* 1311 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1312 * what the designers were smoking but let's not inhale... 1313 * 1314 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1315 * turn it off! 1316 */ 1317 static void quirk_amd_ordering(struct pci_dev *dev) 1318 { 1319 u32 pcic; 1320 pci_read_config_dword(dev, 0x4C, &pcic); 1321 if ((pcic & 6) != 6) { 1322 pcic |= 6; 1323 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1324 pci_write_config_dword(dev, 0x4C, pcic); 1325 pci_read_config_dword(dev, 0x84, &pcic); 1326 pcic |= (1 << 23); /* Required in this mode */ 1327 pci_write_config_dword(dev, 0x84, pcic); 1328 } 1329 } 1330 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1331 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1332 1333 /* 1334 * DreamWorks-provided workaround for Dunord I-3000 problem 1335 * 1336 * This card decodes and responds to addresses not apparently assigned to 1337 * it. We force a larger allocation to ensure that nothing gets put too 1338 * close to it. 1339 */ 1340 static void quirk_dunord(struct pci_dev *dev) 1341 { 1342 struct resource *r = &dev->resource[1]; 1343 1344 r->flags |= IORESOURCE_UNSET; 1345 resource_set_range(r, 0, SZ_16M); 1346 } 1347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1348 1349 /* 1350 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1351 * decoding (transparent), and does indicate this in the ProgIf. 1352 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1353 */ 1354 static void quirk_transparent_bridge(struct pci_dev *dev) 1355 { 1356 dev->transparent = 1; 1357 } 1358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1359 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1360 1361 /* 1362 * Enabling Link Bandwidth Management Interrupts (BW notifications) can cause 1363 * boot hangs on P45. 1364 */ 1365 static void quirk_p45_bw_notifications(struct pci_dev *dev) 1366 { 1367 dev->no_bw_notif = 1; 1368 } 1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e21, quirk_p45_bw_notifications); 1370 1371 /* 1372 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1373 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1374 * found at http://www.national.com/analog for info on what these bits do. 1375 * <christer@weinigel.se> 1376 */ 1377 static void quirk_mediagx_master(struct pci_dev *dev) 1378 { 1379 u8 reg; 1380 1381 pci_read_config_byte(dev, 0x41, ®); 1382 if (reg & 2) { 1383 reg &= ~2; 1384 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1385 reg); 1386 pci_write_config_byte(dev, 0x41, reg); 1387 } 1388 } 1389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1390 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1391 1392 /* 1393 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1394 * in the odd case it is not the results are corruption hence the presence 1395 * of a Linux check. 1396 */ 1397 static void quirk_disable_pxb(struct pci_dev *pdev) 1398 { 1399 u16 config; 1400 1401 if (pdev->revision != 0x04) /* Only C0 requires this */ 1402 return; 1403 pci_read_config_word(pdev, 0x40, &config); 1404 if (config & (1<<6)) { 1405 config &= ~(1<<6); 1406 pci_write_config_word(pdev, 0x40, config); 1407 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1408 } 1409 } 1410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1411 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1412 1413 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1414 { 1415 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1416 u8 tmp; 1417 1418 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1419 if (tmp == 0x01) { 1420 pci_read_config_byte(pdev, 0x40, &tmp); 1421 pci_write_config_byte(pdev, 0x40, tmp|1); 1422 pci_write_config_byte(pdev, 0x9, 1); 1423 pci_write_config_byte(pdev, 0xa, 6); 1424 pci_write_config_byte(pdev, 0x40, tmp); 1425 1426 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1427 pci_info(pdev, "set SATA to AHCI mode\n"); 1428 } 1429 } 1430 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1431 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1432 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1433 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1435 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1437 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1438 1439 /* Serverworks CSB5 IDE does not fully support native mode */ 1440 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1441 { 1442 u8 prog; 1443 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1444 if (prog & 5) { 1445 prog &= ~5; 1446 pdev->class &= ~5; 1447 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1448 /* PCI layer will sort out resources */ 1449 } 1450 } 1451 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1452 1453 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1454 static void quirk_ide_samemode(struct pci_dev *pdev) 1455 { 1456 u8 prog; 1457 1458 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1459 1460 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1461 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1462 prog &= ~5; 1463 pdev->class &= ~5; 1464 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1465 } 1466 } 1467 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1468 1469 /* Some ATA devices break if put into D3 */ 1470 static void quirk_no_ata_d3(struct pci_dev *pdev) 1471 { 1472 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1473 } 1474 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1475 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1476 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1477 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1478 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1479 /* ALi loses some register settings that we cannot then restore */ 1480 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1481 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1482 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1483 occur when mode detecting */ 1484 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1485 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1486 1487 /* 1488 * This was originally an Alpha-specific thing, but it really fits here. 1489 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1490 */ 1491 static void quirk_eisa_bridge(struct pci_dev *dev) 1492 { 1493 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1494 } 1495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1496 1497 /* 1498 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1499 * is not activated. The myth is that Asus said that they do not want the 1500 * users to be irritated by just another PCI Device in the Win98 device 1501 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1502 * package 2.7.0 for details) 1503 * 1504 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1505 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1506 * becomes necessary to do this tweak in two steps -- the chosen trigger 1507 * is either the Host bridge (preferred) or on-board VGA controller. 1508 * 1509 * Note that we used to unhide the SMBus that way on Toshiba laptops 1510 * (Satellite A40 and Tecra M2) but then found that the thermal management 1511 * was done by SMM code, which could cause unsynchronized concurrent 1512 * accesses to the SMBus registers, with potentially bad effects. Thus you 1513 * should be very careful when adding new entries: if SMM is accessing the 1514 * Intel SMBus, this is a very good reason to leave it hidden. 1515 * 1516 * Likewise, many recent laptops use ACPI for thermal management. If the 1517 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1518 * natively, and keeping the SMBus hidden is the right thing to do. If you 1519 * are about to add an entry in the table below, please first disassemble 1520 * the DSDT and double-check that there is no code accessing the SMBus. 1521 */ 1522 static int asus_hides_smbus; 1523 1524 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1525 { 1526 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1527 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1528 switch (dev->subsystem_device) { 1529 case 0x8025: /* P4B-LX */ 1530 case 0x8070: /* P4B */ 1531 case 0x8088: /* P4B533 */ 1532 case 0x1626: /* L3C notebook */ 1533 asus_hides_smbus = 1; 1534 } 1535 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1536 switch (dev->subsystem_device) { 1537 case 0x80b1: /* P4GE-V */ 1538 case 0x80b2: /* P4PE */ 1539 case 0x8093: /* P4B533-V */ 1540 asus_hides_smbus = 1; 1541 } 1542 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1543 switch (dev->subsystem_device) { 1544 case 0x8030: /* P4T533 */ 1545 asus_hides_smbus = 1; 1546 } 1547 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1548 switch (dev->subsystem_device) { 1549 case 0x8070: /* P4G8X Deluxe */ 1550 asus_hides_smbus = 1; 1551 } 1552 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1553 switch (dev->subsystem_device) { 1554 case 0x80c9: /* PU-DLS */ 1555 asus_hides_smbus = 1; 1556 } 1557 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1558 switch (dev->subsystem_device) { 1559 case 0x1751: /* M2N notebook */ 1560 case 0x1821: /* M5N notebook */ 1561 case 0x1897: /* A6L notebook */ 1562 asus_hides_smbus = 1; 1563 } 1564 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1565 switch (dev->subsystem_device) { 1566 case 0x184b: /* W1N notebook */ 1567 case 0x186a: /* M6Ne notebook */ 1568 asus_hides_smbus = 1; 1569 } 1570 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1571 switch (dev->subsystem_device) { 1572 case 0x80f2: /* P4P800-X */ 1573 asus_hides_smbus = 1; 1574 } 1575 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1576 switch (dev->subsystem_device) { 1577 case 0x1882: /* M6V notebook */ 1578 case 0x1977: /* A6VA notebook */ 1579 asus_hides_smbus = 1; 1580 } 1581 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1582 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1583 switch (dev->subsystem_device) { 1584 case 0x088C: /* HP Compaq nc8000 */ 1585 case 0x0890: /* HP Compaq nc6000 */ 1586 asus_hides_smbus = 1; 1587 } 1588 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1589 switch (dev->subsystem_device) { 1590 case 0x12bc: /* HP D330L */ 1591 case 0x12bd: /* HP D530 */ 1592 case 0x006a: /* HP Compaq nx9500 */ 1593 asus_hides_smbus = 1; 1594 } 1595 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1596 switch (dev->subsystem_device) { 1597 case 0x12bf: /* HP xw4100 */ 1598 asus_hides_smbus = 1; 1599 } 1600 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1601 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1602 switch (dev->subsystem_device) { 1603 case 0xC00C: /* Samsung P35 notebook */ 1604 asus_hides_smbus = 1; 1605 } 1606 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1607 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1608 switch (dev->subsystem_device) { 1609 case 0x0058: /* Compaq Evo N620c */ 1610 asus_hides_smbus = 1; 1611 } 1612 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1613 switch (dev->subsystem_device) { 1614 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1615 /* Motherboard doesn't have Host bridge 1616 * subvendor/subdevice IDs, therefore checking 1617 * its on-board VGA controller */ 1618 asus_hides_smbus = 1; 1619 } 1620 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1621 switch (dev->subsystem_device) { 1622 case 0x00b8: /* Compaq Evo D510 CMT */ 1623 case 0x00b9: /* Compaq Evo D510 SFF */ 1624 case 0x00ba: /* Compaq Evo D510 USDT */ 1625 /* Motherboard doesn't have Host bridge 1626 * subvendor/subdevice IDs and on-board VGA 1627 * controller is disabled if an AGP card is 1628 * inserted, therefore checking USB UHCI 1629 * Controller #1 */ 1630 asus_hides_smbus = 1; 1631 } 1632 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1633 switch (dev->subsystem_device) { 1634 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1635 /* Motherboard doesn't have host bridge 1636 * subvendor/subdevice IDs, therefore checking 1637 * its on-board VGA controller */ 1638 asus_hides_smbus = 1; 1639 } 1640 } 1641 } 1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1651 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1652 1653 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1654 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1655 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1656 1657 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1658 { 1659 u16 val; 1660 1661 if (likely(!asus_hides_smbus)) 1662 return; 1663 1664 pci_read_config_word(dev, 0xF2, &val); 1665 if (val & 0x8) { 1666 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1667 pci_read_config_word(dev, 0xF2, &val); 1668 if (val & 0x8) 1669 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1670 val); 1671 else 1672 pci_info(dev, "Enabled i801 SMBus device\n"); 1673 } 1674 } 1675 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1676 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1677 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1678 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1680 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1681 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1682 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1683 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1684 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1685 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1686 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1687 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1688 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1689 1690 /* It appears we just have one such device. If not, we have a warning */ 1691 static void __iomem *asus_rcba_base; 1692 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1693 { 1694 u32 rcba; 1695 1696 if (likely(!asus_hides_smbus)) 1697 return; 1698 WARN_ON(asus_rcba_base); 1699 1700 pci_read_config_dword(dev, 0xF0, &rcba); 1701 /* use bits 31:14, 16 kB aligned */ 1702 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1703 if (asus_rcba_base == NULL) 1704 return; 1705 } 1706 1707 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1708 { 1709 u32 val; 1710 1711 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1712 return; 1713 1714 /* read the Function Disable register, dword mode only */ 1715 val = readl(asus_rcba_base + 0x3418); 1716 1717 /* enable the SMBus device */ 1718 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1719 } 1720 1721 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1722 { 1723 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1724 return; 1725 1726 iounmap(asus_rcba_base); 1727 asus_rcba_base = NULL; 1728 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1729 } 1730 1731 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1732 { 1733 asus_hides_smbus_lpc_ich6_suspend(dev); 1734 asus_hides_smbus_lpc_ich6_resume_early(dev); 1735 asus_hides_smbus_lpc_ich6_resume(dev); 1736 } 1737 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1738 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1739 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1740 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1741 1742 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1743 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1744 { 1745 u8 val = 0; 1746 pci_read_config_byte(dev, 0x77, &val); 1747 if (val & 0x10) { 1748 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1749 pci_write_config_byte(dev, 0x77, val & ~0x10); 1750 } 1751 } 1752 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1753 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1754 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1755 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1756 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1757 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1758 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1759 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1760 1761 /* 1762 * ... This is further complicated by the fact that some SiS96x south 1763 * bridges pretend to be 85C503/5513 instead. In that case see if we 1764 * spotted a compatible north bridge to make sure. 1765 * (pci_find_device() doesn't work yet) 1766 * 1767 * We can also enable the sis96x bit in the discovery register.. 1768 */ 1769 #define SIS_DETECT_REGISTER 0x40 1770 1771 static void quirk_sis_503(struct pci_dev *dev) 1772 { 1773 u8 reg; 1774 u16 devid; 1775 1776 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1777 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1778 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1779 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1780 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1781 return; 1782 } 1783 1784 /* 1785 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1786 * it has already been processed. (Depends on link order, which is 1787 * apparently not guaranteed) 1788 */ 1789 dev->device = devid; 1790 quirk_sis_96x_smbus(dev); 1791 } 1792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1793 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1794 1795 /* 1796 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1797 * and MC97 modem controller are disabled when a second PCI soundcard is 1798 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1799 * -- bjd 1800 */ 1801 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1802 { 1803 u8 val; 1804 int asus_hides_ac97 = 0; 1805 1806 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1807 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1808 asus_hides_ac97 = 1; 1809 } 1810 1811 if (!asus_hides_ac97) 1812 return; 1813 1814 pci_read_config_byte(dev, 0x50, &val); 1815 if (val & 0xc0) { 1816 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1817 pci_read_config_byte(dev, 0x50, &val); 1818 if (val & 0xc0) 1819 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1820 val); 1821 else 1822 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1823 } 1824 } 1825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1826 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1827 1828 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1829 1830 /* 1831 * If we are using libata we can drive this chip properly but must do this 1832 * early on to make the additional device appear during the PCI scanning. 1833 */ 1834 static void quirk_jmicron_ata(struct pci_dev *pdev) 1835 { 1836 u32 conf1, conf5, class; 1837 u8 hdr; 1838 1839 /* Only poke fn 0 */ 1840 if (PCI_FUNC(pdev->devfn)) 1841 return; 1842 1843 pci_read_config_dword(pdev, 0x40, &conf1); 1844 pci_read_config_dword(pdev, 0x80, &conf5); 1845 1846 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1847 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1848 1849 switch (pdev->device) { 1850 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1851 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1852 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1853 /* The controller should be in single function ahci mode */ 1854 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1855 break; 1856 1857 case PCI_DEVICE_ID_JMICRON_JMB365: 1858 case PCI_DEVICE_ID_JMICRON_JMB366: 1859 /* Redirect IDE second PATA port to the right spot */ 1860 conf5 |= (1 << 24); 1861 fallthrough; 1862 case PCI_DEVICE_ID_JMICRON_JMB361: 1863 case PCI_DEVICE_ID_JMICRON_JMB363: 1864 case PCI_DEVICE_ID_JMICRON_JMB369: 1865 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1866 /* Set the class codes correctly and then direct IDE 0 */ 1867 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1868 break; 1869 1870 case PCI_DEVICE_ID_JMICRON_JMB368: 1871 /* The controller should be in single function IDE mode */ 1872 conf1 |= 0x00C00000; /* Set 22, 23 */ 1873 break; 1874 } 1875 1876 pci_write_config_dword(pdev, 0x40, conf1); 1877 pci_write_config_dword(pdev, 0x80, conf5); 1878 1879 /* Update pdev accordingly */ 1880 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1881 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; 1882 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); 1883 1884 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1885 pdev->class = class >> 8; 1886 } 1887 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1888 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1889 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1890 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1891 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1892 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1893 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1894 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1895 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1896 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1897 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1898 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1899 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1900 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1901 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1902 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1903 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1904 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1905 1906 #endif 1907 1908 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1909 { 1910 if (dev->multifunction) { 1911 device_disable_async_suspend(&dev->dev); 1912 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1913 } 1914 } 1915 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1916 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1917 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1919 1920 #ifdef CONFIG_X86_IO_APIC 1921 static void quirk_alder_ioapic(struct pci_dev *pdev) 1922 { 1923 int i; 1924 1925 if ((pdev->class >> 8) != 0xff00) 1926 return; 1927 1928 /* 1929 * The first BAR is the location of the IO-APIC... we must 1930 * not touch this (and it's already covered by the fixmap), so 1931 * forcibly insert it into the resource tree. 1932 */ 1933 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1934 insert_resource(&iomem_resource, &pdev->resource[0]); 1935 1936 /* 1937 * The next five BARs all seem to be rubbish, so just clean 1938 * them out. 1939 */ 1940 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1941 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1942 } 1943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1944 #endif 1945 1946 static void quirk_no_msi(struct pci_dev *dev) 1947 { 1948 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1949 dev->no_msi = 1; 1950 } 1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1957 1958 static void quirk_pcie_mch(struct pci_dev *pdev) 1959 { 1960 pdev->no_msi = 1; 1961 } 1962 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1963 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1965 1966 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1967 1968 /* 1969 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1970 * actually on the AMBA bus. These fake PCI devices can support SVA via 1971 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1972 * 1973 * Normally stalling must not be enabled for PCI devices, since it would 1974 * break the PCI requirement for free-flowing writes and may lead to 1975 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1976 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1977 * even when a "PCI" device turns out to be a regular old SoC device 1978 * dressed up as a RCiEP and normal rules don't apply. 1979 */ 1980 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1981 { 1982 struct property_entry properties[] = { 1983 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1984 {}, 1985 }; 1986 1987 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1988 return; 1989 1990 pdev->pasid_no_tlp = 1; 1991 1992 /* 1993 * Set the dma-can-stall property on ACPI platforms. Device tree 1994 * can set it directly. 1995 */ 1996 if (!pdev->dev.of_node && 1997 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1998 pci_warn(pdev, "could not add stall property"); 1999 } 2000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 2001 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 2002 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 2003 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 2004 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 2005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 2006 2007 /* 2008 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 2009 * together on certain PXH-based systems. 2010 */ 2011 static void quirk_pcie_pxh(struct pci_dev *dev) 2012 { 2013 dev->no_msi = 1; 2014 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 2015 } 2016 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 2017 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 2018 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 2019 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 2020 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 2021 2022 /* 2023 * Some Intel PCI Express chipsets have trouble with downstream device 2024 * power management. 2025 */ 2026 static void quirk_intel_pcie_pm(struct pci_dev *dev) 2027 { 2028 pci_pm_d3hot_delay = 120; 2029 dev->no_d1d2 = 1; 2030 } 2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2052 2053 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2054 { 2055 if (dev->d3hot_delay >= delay) 2056 return; 2057 2058 dev->d3hot_delay = delay; 2059 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2060 dev->d3hot_delay); 2061 } 2062 2063 static void quirk_radeon_pm(struct pci_dev *dev) 2064 { 2065 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2066 dev->subsystem_device == 0x00e2) 2067 quirk_d3hot_delay(dev, 20); 2068 } 2069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2070 2071 /* 2072 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2073 * reset is performed too soon after transition to D0, extend d3hot_delay 2074 * to previous effective default for all NVIDIA HDA controllers. 2075 */ 2076 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2077 { 2078 quirk_d3hot_delay(dev, 20); 2079 } 2080 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2081 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2082 quirk_nvidia_hda_pm); 2083 2084 /* 2085 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2086 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2087 * 2088 * The kernel attempts to transition these devices to D3cold, but that seems 2089 * to be ineffective on the platforms in question; the PCI device appears to 2090 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2091 * extended delay in order to succeed. 2092 */ 2093 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2094 { 2095 quirk_d3hot_delay(dev, 20); 2096 } 2097 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2098 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2099 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2100 2101 #ifdef CONFIG_X86_IO_APIC 2102 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2103 { 2104 noioapicreroute = 1; 2105 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2106 2107 return 0; 2108 } 2109 2110 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2111 /* 2112 * Systems to exclude from boot interrupt reroute quirks 2113 */ 2114 { 2115 .callback = dmi_disable_ioapicreroute, 2116 .ident = "ASUSTek Computer INC. M2N-LR", 2117 .matches = { 2118 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2119 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2120 }, 2121 }, 2122 {} 2123 }; 2124 2125 /* 2126 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2127 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2128 * that a PCI device's interrupt handler is installed on the boot interrupt 2129 * line instead. 2130 */ 2131 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2132 { 2133 dmi_check_system(boot_interrupt_dmi_table); 2134 if (noioapicquirk || noioapicreroute) 2135 return; 2136 2137 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2138 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2139 dev->vendor, dev->device); 2140 } 2141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2143 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2149 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2150 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2151 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2152 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2153 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2154 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2155 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2156 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2157 2158 /* 2159 * On some chipsets we can disable the generation of legacy INTx boot 2160 * interrupts. 2161 */ 2162 2163 /* 2164 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2165 * 300641-004US, section 5.7.3. 2166 * 2167 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2168 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2169 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2170 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2171 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2172 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2173 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2174 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2175 * Core IO on Xeon Scalable, see Intel order no 610950. 2176 */ 2177 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2178 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2179 2180 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2181 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2182 2183 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2184 { 2185 u16 pci_config_word; 2186 u32 pci_config_dword; 2187 2188 if (noioapicquirk) 2189 return; 2190 2191 switch (dev->device) { 2192 case PCI_DEVICE_ID_INTEL_ESB_10: 2193 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2194 &pci_config_word); 2195 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2196 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2197 pci_config_word); 2198 break; 2199 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2200 case 0x0e28: /* Xeon E5/E7 V2 */ 2201 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2202 case 0x6f28: /* Xeon D-1500 */ 2203 case 0x2034: /* Xeon Scalable Family */ 2204 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2205 &pci_config_dword); 2206 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2207 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2208 pci_config_dword); 2209 break; 2210 default: 2211 return; 2212 } 2213 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2214 dev->vendor, dev->device); 2215 } 2216 /* 2217 * Device 29 Func 5 Device IDs of IO-APIC 2218 * containing ABAR—APIC1 Alternate Base Address Register 2219 */ 2220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2221 quirk_disable_intel_boot_interrupt); 2222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2223 quirk_disable_intel_boot_interrupt); 2224 2225 /* 2226 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2227 * containing Coherent Interface Protocol Interrupt Control 2228 * 2229 * Device IDs obtained from volume 2 datasheets of commented 2230 * families above. 2231 */ 2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2233 quirk_disable_intel_boot_interrupt); 2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2235 quirk_disable_intel_boot_interrupt); 2236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2237 quirk_disable_intel_boot_interrupt); 2238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2239 quirk_disable_intel_boot_interrupt); 2240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2241 quirk_disable_intel_boot_interrupt); 2242 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2243 quirk_disable_intel_boot_interrupt); 2244 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2245 quirk_disable_intel_boot_interrupt); 2246 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2247 quirk_disable_intel_boot_interrupt); 2248 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2249 quirk_disable_intel_boot_interrupt); 2250 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2251 quirk_disable_intel_boot_interrupt); 2252 2253 /* Disable boot interrupts on HT-1000 */ 2254 #define BC_HT1000_FEATURE_REG 0x64 2255 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2256 #define BC_HT1000_MAP_IDX 0xC00 2257 #define BC_HT1000_MAP_DATA 0xC01 2258 2259 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2260 { 2261 u32 pci_config_dword; 2262 u8 irq; 2263 2264 if (noioapicquirk) 2265 return; 2266 2267 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2268 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2269 BC_HT1000_PIC_REGS_ENABLE); 2270 2271 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2272 outb(irq, BC_HT1000_MAP_IDX); 2273 outb(0x00, BC_HT1000_MAP_DATA); 2274 } 2275 2276 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2277 2278 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2279 dev->vendor, dev->device); 2280 } 2281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2282 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2283 2284 /* Disable boot interrupts on AMD and ATI chipsets */ 2285 2286 /* 2287 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2288 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2289 * (due to an erratum). 2290 */ 2291 #define AMD_813X_MISC 0x40 2292 #define AMD_813X_NOIOAMODE (1<<0) 2293 #define AMD_813X_REV_B1 0x12 2294 #define AMD_813X_REV_B2 0x13 2295 2296 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2297 { 2298 u32 pci_config_dword; 2299 2300 if (noioapicquirk) 2301 return; 2302 if ((dev->revision == AMD_813X_REV_B1) || 2303 (dev->revision == AMD_813X_REV_B2)) 2304 return; 2305 2306 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2307 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2308 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2309 2310 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2311 dev->vendor, dev->device); 2312 } 2313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2314 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2316 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2317 2318 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2319 2320 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2321 { 2322 u16 pci_config_word; 2323 2324 if (noioapicquirk) 2325 return; 2326 2327 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2328 if (!pci_config_word) { 2329 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2330 dev->vendor, dev->device); 2331 return; 2332 } 2333 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2334 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2335 dev->vendor, dev->device); 2336 } 2337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2338 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2339 #endif /* CONFIG_X86_IO_APIC */ 2340 2341 /* 2342 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2343 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2344 * Re-allocate the region if needed... 2345 */ 2346 static void quirk_tc86c001_ide(struct pci_dev *dev) 2347 { 2348 struct resource *r = &dev->resource[0]; 2349 2350 if (r->start & 0x8) { 2351 r->flags |= IORESOURCE_UNSET; 2352 resource_set_range(r, 0, SZ_16); 2353 } 2354 } 2355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2356 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2357 quirk_tc86c001_ide); 2358 2359 /* 2360 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2361 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2362 * being read correctly if bit 7 of the base address is set. 2363 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2364 * Re-allocate the regions to a 256-byte boundary if necessary. 2365 */ 2366 static void quirk_plx_pci9050(struct pci_dev *dev) 2367 { 2368 unsigned int bar; 2369 2370 /* Fixed in revision 2 (PCI 9052). */ 2371 if (dev->revision >= 2) 2372 return; 2373 for (bar = 0; bar <= 1; bar++) 2374 if (pci_resource_len(dev, bar) == 0x80 && 2375 (pci_resource_start(dev, bar) & 0x80)) { 2376 struct resource *r = &dev->resource[bar]; 2377 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2378 bar); 2379 r->flags |= IORESOURCE_UNSET; 2380 resource_set_range(r, 0, SZ_256); 2381 } 2382 } 2383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2384 quirk_plx_pci9050); 2385 /* 2386 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2387 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2388 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2389 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2390 * 2391 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2392 * driver. 2393 */ 2394 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2395 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2396 2397 static void quirk_netmos(struct pci_dev *dev) 2398 { 2399 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2400 unsigned int num_serial = dev->subsystem_device & 0xf; 2401 2402 /* 2403 * These Netmos parts are multiport serial devices with optional 2404 * parallel ports. Even when parallel ports are present, they 2405 * are identified as class SERIAL, which means the serial driver 2406 * will claim them. To prevent this, mark them as class OTHER. 2407 * These combo devices should be claimed by parport_serial. 2408 * 2409 * The subdevice ID is of the form 0x00PS, where <P> is the number 2410 * of parallel ports and <S> is the number of serial ports. 2411 */ 2412 switch (dev->device) { 2413 case PCI_DEVICE_ID_NETMOS_9835: 2414 /* Well, this rule doesn't hold for the following 9835 device */ 2415 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2416 dev->subsystem_device == 0x0299) 2417 return; 2418 fallthrough; 2419 case PCI_DEVICE_ID_NETMOS_9735: 2420 case PCI_DEVICE_ID_NETMOS_9745: 2421 case PCI_DEVICE_ID_NETMOS_9845: 2422 case PCI_DEVICE_ID_NETMOS_9855: 2423 if (num_parallel) { 2424 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2425 dev->device, num_parallel, num_serial); 2426 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2427 (dev->class & 0xff); 2428 } 2429 } 2430 } 2431 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2432 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2433 2434 static void quirk_e100_interrupt(struct pci_dev *dev) 2435 { 2436 u16 command, pmcsr; 2437 u8 __iomem *csr; 2438 u8 cmd_hi; 2439 2440 switch (dev->device) { 2441 /* PCI IDs taken from drivers/net/e100.c */ 2442 case 0x1029: 2443 case 0x1030 ... 0x1034: 2444 case 0x1038 ... 0x103E: 2445 case 0x1050 ... 0x1057: 2446 case 0x1059: 2447 case 0x1064 ... 0x106B: 2448 case 0x1091 ... 0x1095: 2449 case 0x1209: 2450 case 0x1229: 2451 case 0x2449: 2452 case 0x2459: 2453 case 0x245D: 2454 case 0x27DC: 2455 break; 2456 default: 2457 return; 2458 } 2459 2460 /* 2461 * Some firmware hands off the e100 with interrupts enabled, 2462 * which can cause a flood of interrupts if packets are 2463 * received before the driver attaches to the device. So 2464 * disable all e100 interrupts here. The driver will 2465 * re-enable them when it's ready. 2466 */ 2467 pci_read_config_word(dev, PCI_COMMAND, &command); 2468 2469 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2470 return; 2471 2472 /* 2473 * Check that the device is in the D0 power state. If it's not, 2474 * there is no point to look any further. 2475 */ 2476 if (dev->pm_cap) { 2477 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2478 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2479 return; 2480 } 2481 2482 /* Convert from PCI bus to resource space. */ 2483 csr = ioremap(pci_resource_start(dev, 0), 8); 2484 if (!csr) { 2485 pci_warn(dev, "Can't map e100 registers\n"); 2486 return; 2487 } 2488 2489 cmd_hi = readb(csr + 3); 2490 if (cmd_hi == 0) { 2491 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2492 writeb(1, csr + 3); 2493 } 2494 2495 iounmap(csr); 2496 } 2497 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2498 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2499 2500 /* 2501 * The 82575 and 82598 may experience data corruption issues when transitioning 2502 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2503 */ 2504 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2505 { 2506 pcie_aspm_remove_cap(dev, PCI_EXP_LNKCAP_ASPM_L0S); 2507 } 2508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2522 2523 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2524 { 2525 pcie_aspm_remove_cap(dev, 2526 PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1); 2527 } 2528 2529 /* 2530 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2531 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2532 * disable both L0s and L1 for now to be safe. 2533 */ 2534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1); 2536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1); 2537 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1); 2538 2539 /* 2540 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2541 * Link bit cleared after starting the link retrain process to allow this 2542 * process to finish. 2543 * 2544 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2545 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2546 */ 2547 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2548 { 2549 dev->clear_retrain_link = 1; 2550 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2551 } 2552 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2553 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2554 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2555 2556 static void fixup_rev1_53c810(struct pci_dev *dev) 2557 { 2558 u32 class = dev->class; 2559 2560 /* 2561 * rev 1 ncr53c810 chips don't set the class at all which means 2562 * they don't get their resources remapped. Fix that here. 2563 */ 2564 if (class) 2565 return; 2566 2567 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2568 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2569 class, dev->class); 2570 } 2571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2572 2573 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2574 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2575 { 2576 u16 en1k; 2577 2578 pci_read_config_word(dev, 0x40, &en1k); 2579 2580 if (en1k & 0x200) { 2581 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2582 dev->io_window_1k = 1; 2583 } 2584 } 2585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2586 2587 /* 2588 * Under some circumstances, AER is not linked with extended capabilities. 2589 * Force it to be linked by setting the corresponding control bit in the 2590 * config space. 2591 */ 2592 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2593 { 2594 uint8_t b; 2595 2596 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2597 if (!(b & 0x20)) { 2598 pci_write_config_byte(dev, 0xf41, b | 0x20); 2599 pci_info(dev, "Linking AER extended capability\n"); 2600 } 2601 } 2602 } 2603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2604 quirk_nvidia_ck804_pcie_aer_ext_cap); 2605 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2606 quirk_nvidia_ck804_pcie_aer_ext_cap); 2607 2608 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2609 { 2610 /* 2611 * Disable PCI Bus Parking and PCI Master read caching on CX700 2612 * which causes unspecified timing errors with a VT6212L on the PCI 2613 * bus leading to USB2.0 packet loss. 2614 * 2615 * This quirk is only enabled if a second (on the external PCI bus) 2616 * VT6212L is found -- the CX700 core itself also contains a USB 2617 * host controller with the same PCI ID as the VT6212L. 2618 */ 2619 2620 /* Count VT6212L instances */ 2621 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2622 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2623 uint8_t b; 2624 2625 /* 2626 * p should contain the first (internal) VT6212L -- see if we have 2627 * an external one by searching again. 2628 */ 2629 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2630 if (!p) 2631 return; 2632 pci_dev_put(p); 2633 2634 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2635 if (b & 0x40) { 2636 /* Turn off PCI Bus Parking */ 2637 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2638 2639 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2640 } 2641 } 2642 2643 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2644 if (b != 0) { 2645 /* Turn off PCI Master read caching */ 2646 pci_write_config_byte(dev, 0x72, 0x0); 2647 2648 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2649 pci_write_config_byte(dev, 0x75, 0x1); 2650 2651 /* Disable "Read FIFO Timer" */ 2652 pci_write_config_byte(dev, 0x77, 0x0); 2653 2654 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2655 } 2656 } 2657 } 2658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2659 2660 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2661 { 2662 u32 rev; 2663 2664 pci_read_config_dword(dev, 0xf4, &rev); 2665 2666 /* Only CAP the MRRS if the device is a 5719 A0 */ 2667 if (rev == 0x05719000) { 2668 int readrq = pcie_get_readrq(dev); 2669 if (readrq > 2048) 2670 pcie_set_readrq(dev, 2048); 2671 } 2672 } 2673 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2674 PCI_DEVICE_ID_TIGON3_5719, 2675 quirk_brcm_5719_limit_mrrs); 2676 2677 /* 2678 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2679 * hide device 6 which configures the overflow device access containing the 2680 * DRBs - this is where we expose device 6. 2681 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2682 */ 2683 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2684 { 2685 u8 reg; 2686 2687 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2688 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2689 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2690 } 2691 } 2692 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2693 quirk_unhide_mch_dev6); 2694 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2695 quirk_unhide_mch_dev6); 2696 2697 #ifdef CONFIG_PCI_MSI 2698 /* 2699 * Some chipsets do not support MSI. We cannot easily rely on setting 2700 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2701 * other buses controlled by the chipset even if Linux is not aware of it. 2702 * Instead of setting the flag on all buses in the machine, simply disable 2703 * MSI globally. 2704 */ 2705 static void quirk_disable_all_msi(struct pci_dev *dev) 2706 { 2707 pci_no_msi(); 2708 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2709 } 2710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2712 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2715 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2719 2720 /* Disable MSI on chipsets that are known to not support it */ 2721 static void quirk_disable_msi(struct pci_dev *dev) 2722 { 2723 if (dev->subordinate) { 2724 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2725 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2726 } 2727 } 2728 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2729 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2730 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2731 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); 2732 2733 /* 2734 * The APC bridge device in AMD 780 family northbridges has some random 2735 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2736 * we use the possible vendor/device IDs of the host bridge for the 2737 * declared quirk, and search for the APC bridge by slot number. 2738 */ 2739 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2740 { 2741 struct pci_dev *apc_bridge; 2742 2743 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2744 if (apc_bridge) { 2745 if (apc_bridge->device == 0x9602) 2746 quirk_disable_msi(apc_bridge); 2747 pci_dev_put(apc_bridge); 2748 } 2749 } 2750 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2751 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2752 2753 /* 2754 * Go through the list of HyperTransport capabilities and return 1 if a HT 2755 * MSI capability is found and enabled. 2756 */ 2757 static int msi_ht_cap_enabled(struct pci_dev *dev) 2758 { 2759 int pos, ttl = PCI_FIND_CAP_TTL; 2760 2761 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2762 while (pos && ttl--) { 2763 u8 flags; 2764 2765 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2766 &flags) == 0) { 2767 pci_info(dev, "Found %s HT MSI Mapping\n", 2768 flags & HT_MSI_FLAGS_ENABLE ? 2769 "enabled" : "disabled"); 2770 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2771 } 2772 2773 pos = pci_find_next_ht_capability(dev, pos, 2774 HT_CAPTYPE_MSI_MAPPING); 2775 } 2776 return 0; 2777 } 2778 2779 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2780 static void quirk_msi_ht_cap(struct pci_dev *dev) 2781 { 2782 if (!msi_ht_cap_enabled(dev)) 2783 quirk_disable_msi(dev); 2784 } 2785 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2786 quirk_msi_ht_cap); 2787 2788 /* 2789 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2790 * if the MSI capability is set in any of these mappings. 2791 */ 2792 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2793 { 2794 struct pci_dev *pdev; 2795 2796 /* 2797 * Check HT MSI cap on this chipset and the root one. A single one 2798 * having MSI is enough to be sure that MSI is supported. 2799 */ 2800 pdev = pci_get_slot(dev->bus, 0); 2801 if (!pdev) 2802 return; 2803 if (!msi_ht_cap_enabled(pdev)) 2804 quirk_msi_ht_cap(dev); 2805 pci_dev_put(pdev); 2806 } 2807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2808 quirk_nvidia_ck804_msi_ht_cap); 2809 2810 /* Force enable MSI mapping capability on HT bridges */ 2811 static void ht_enable_msi_mapping(struct pci_dev *dev) 2812 { 2813 int pos, ttl = PCI_FIND_CAP_TTL; 2814 2815 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2816 while (pos && ttl--) { 2817 u8 flags; 2818 2819 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2820 &flags) == 0) { 2821 pci_info(dev, "Enabling HT MSI Mapping\n"); 2822 2823 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2824 flags | HT_MSI_FLAGS_ENABLE); 2825 } 2826 pos = pci_find_next_ht_capability(dev, pos, 2827 HT_CAPTYPE_MSI_MAPPING); 2828 } 2829 } 2830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2831 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2832 ht_enable_msi_mapping); 2833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2834 ht_enable_msi_mapping); 2835 2836 /* 2837 * The P5N32-SLI motherboards from Asus have a problem with MSI 2838 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2839 * also affects other devices. As for now, turn off MSI for this device. 2840 */ 2841 static void nvenet_msi_disable(struct pci_dev *dev) 2842 { 2843 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2844 2845 if (board_name && 2846 (strstr(board_name, "P5N32-SLI PREMIUM") || 2847 strstr(board_name, "P5N32-E SLI"))) { 2848 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2849 dev->no_msi = 1; 2850 } 2851 } 2852 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2853 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2854 nvenet_msi_disable); 2855 2856 /* 2857 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2858 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2859 * interrupts for PME and AER events; instead only INTx interrupts are 2860 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2861 * for other events, since PCIe specification doesn't support using a mix of 2862 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2863 * service drivers registering their respective ISRs for MSIs. 2864 */ 2865 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2866 { 2867 dev->no_msi = 1; 2868 } 2869 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2870 PCI_CLASS_BRIDGE_PCI, 8, 2871 pci_quirk_nvidia_tegra_disable_rp_msi); 2872 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2873 PCI_CLASS_BRIDGE_PCI, 8, 2874 pci_quirk_nvidia_tegra_disable_rp_msi); 2875 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2876 PCI_CLASS_BRIDGE_PCI, 8, 2877 pci_quirk_nvidia_tegra_disable_rp_msi); 2878 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2879 PCI_CLASS_BRIDGE_PCI, 8, 2880 pci_quirk_nvidia_tegra_disable_rp_msi); 2881 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2882 PCI_CLASS_BRIDGE_PCI, 8, 2883 pci_quirk_nvidia_tegra_disable_rp_msi); 2884 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2885 PCI_CLASS_BRIDGE_PCI, 8, 2886 pci_quirk_nvidia_tegra_disable_rp_msi); 2887 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2888 PCI_CLASS_BRIDGE_PCI, 8, 2889 pci_quirk_nvidia_tegra_disable_rp_msi); 2890 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2891 PCI_CLASS_BRIDGE_PCI, 8, 2892 pci_quirk_nvidia_tegra_disable_rp_msi); 2893 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2894 PCI_CLASS_BRIDGE_PCI, 8, 2895 pci_quirk_nvidia_tegra_disable_rp_msi); 2896 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2897 PCI_CLASS_BRIDGE_PCI, 8, 2898 pci_quirk_nvidia_tegra_disable_rp_msi); 2899 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2900 PCI_CLASS_BRIDGE_PCI, 8, 2901 pci_quirk_nvidia_tegra_disable_rp_msi); 2902 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2903 PCI_CLASS_BRIDGE_PCI, 8, 2904 pci_quirk_nvidia_tegra_disable_rp_msi); 2905 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2906 PCI_CLASS_BRIDGE_PCI, 8, 2907 pci_quirk_nvidia_tegra_disable_rp_msi); 2908 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2909 PCI_CLASS_BRIDGE_PCI, 8, 2910 pci_quirk_nvidia_tegra_disable_rp_msi); 2911 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2912 PCI_CLASS_BRIDGE_PCI, 8, 2913 pci_quirk_nvidia_tegra_disable_rp_msi); 2914 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2915 PCI_CLASS_BRIDGE_PCI, 8, 2916 pci_quirk_nvidia_tegra_disable_rp_msi); 2917 2918 /* 2919 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2920 * config register. This register controls the routing of legacy 2921 * interrupts from devices that route through the MCP55. If this register 2922 * is misprogrammed, interrupts are only sent to the BSP, unlike 2923 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2924 * having this register set properly prevents kdump from booting up 2925 * properly, so let's make sure that we have it set correctly. 2926 * Note that this is an undocumented register. 2927 */ 2928 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2929 { 2930 u32 cfg; 2931 2932 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2933 return; 2934 2935 pci_read_config_dword(dev, 0x74, &cfg); 2936 2937 if (cfg & ((1 << 2) | (1 << 15))) { 2938 pr_info("Rewriting IRQ routing register on MCP55\n"); 2939 cfg &= ~((1 << 2) | (1 << 15)); 2940 pci_write_config_dword(dev, 0x74, cfg); 2941 } 2942 } 2943 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2944 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2945 nvbridge_check_legacy_irq_routing); 2946 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2947 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2948 nvbridge_check_legacy_irq_routing); 2949 2950 static int ht_check_msi_mapping(struct pci_dev *dev) 2951 { 2952 int pos, ttl = PCI_FIND_CAP_TTL; 2953 int found = 0; 2954 2955 /* Check if there is HT MSI cap or enabled on this device */ 2956 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2957 while (pos && ttl--) { 2958 u8 flags; 2959 2960 if (found < 1) 2961 found = 1; 2962 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2963 &flags) == 0) { 2964 if (flags & HT_MSI_FLAGS_ENABLE) { 2965 if (found < 2) { 2966 found = 2; 2967 break; 2968 } 2969 } 2970 } 2971 pos = pci_find_next_ht_capability(dev, pos, 2972 HT_CAPTYPE_MSI_MAPPING); 2973 } 2974 2975 return found; 2976 } 2977 2978 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2979 { 2980 struct pci_dev *dev; 2981 int pos; 2982 int i, dev_no; 2983 int found = 0; 2984 2985 dev_no = host_bridge->devfn >> 3; 2986 for (i = dev_no + 1; i < 0x20; i++) { 2987 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2988 if (!dev) 2989 continue; 2990 2991 /* found next host bridge? */ 2992 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2993 if (pos != 0) { 2994 pci_dev_put(dev); 2995 break; 2996 } 2997 2998 if (ht_check_msi_mapping(dev)) { 2999 found = 1; 3000 pci_dev_put(dev); 3001 break; 3002 } 3003 pci_dev_put(dev); 3004 } 3005 3006 return found; 3007 } 3008 3009 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 3010 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 3011 3012 static int is_end_of_ht_chain(struct pci_dev *dev) 3013 { 3014 int pos, ctrl_off; 3015 int end = 0; 3016 u16 flags, ctrl; 3017 3018 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3019 3020 if (!pos) 3021 goto out; 3022 3023 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 3024 3025 ctrl_off = ((flags >> 10) & 1) ? 3026 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 3027 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 3028 3029 if (ctrl & (1 << 6)) 3030 end = 1; 3031 3032 out: 3033 return end; 3034 } 3035 3036 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3037 { 3038 struct pci_dev *host_bridge; 3039 int pos; 3040 int i, dev_no; 3041 int found = 0; 3042 3043 dev_no = dev->devfn >> 3; 3044 for (i = dev_no; i >= 0; i--) { 3045 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3046 if (!host_bridge) 3047 continue; 3048 3049 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3050 if (pos != 0) { 3051 found = 1; 3052 break; 3053 } 3054 pci_dev_put(host_bridge); 3055 } 3056 3057 if (!found) 3058 return; 3059 3060 /* don't enable end_device/host_bridge with leaf directly here */ 3061 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3062 host_bridge_with_leaf(host_bridge)) 3063 goto out; 3064 3065 /* root did that ! */ 3066 if (msi_ht_cap_enabled(host_bridge)) 3067 goto out; 3068 3069 ht_enable_msi_mapping(dev); 3070 3071 out: 3072 pci_dev_put(host_bridge); 3073 } 3074 3075 static void ht_disable_msi_mapping(struct pci_dev *dev) 3076 { 3077 int pos, ttl = PCI_FIND_CAP_TTL; 3078 3079 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3080 while (pos && ttl--) { 3081 u8 flags; 3082 3083 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3084 &flags) == 0) { 3085 pci_info(dev, "Disabling HT MSI Mapping\n"); 3086 3087 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3088 flags & ~HT_MSI_FLAGS_ENABLE); 3089 } 3090 pos = pci_find_next_ht_capability(dev, pos, 3091 HT_CAPTYPE_MSI_MAPPING); 3092 } 3093 } 3094 3095 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3096 { 3097 struct pci_dev *host_bridge; 3098 int pos; 3099 int found; 3100 3101 if (!pci_msi_enabled()) 3102 return; 3103 3104 /* check if there is HT MSI cap or enabled on this device */ 3105 found = ht_check_msi_mapping(dev); 3106 3107 /* no HT MSI CAP */ 3108 if (found == 0) 3109 return; 3110 3111 /* 3112 * HT MSI mapping should be disabled on devices that are below 3113 * a non-HyperTransport host bridge. Locate the host bridge. 3114 */ 3115 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3116 PCI_DEVFN(0, 0)); 3117 if (host_bridge == NULL) { 3118 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3119 return; 3120 } 3121 3122 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3123 if (pos != 0) { 3124 /* Host bridge is to HT */ 3125 if (found == 1) { 3126 /* it is not enabled, try to enable it */ 3127 if (all) 3128 ht_enable_msi_mapping(dev); 3129 else 3130 nv_ht_enable_msi_mapping(dev); 3131 } 3132 goto out; 3133 } 3134 3135 /* HT MSI is not enabled */ 3136 if (found == 1) 3137 goto out; 3138 3139 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3140 ht_disable_msi_mapping(dev); 3141 3142 out: 3143 pci_dev_put(host_bridge); 3144 } 3145 3146 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3147 { 3148 return __nv_msi_ht_cap_quirk(dev, 1); 3149 } 3150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3151 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3152 3153 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3154 { 3155 return __nv_msi_ht_cap_quirk(dev, 0); 3156 } 3157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3158 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3159 3160 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3161 { 3162 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3163 } 3164 3165 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3166 { 3167 struct pci_dev *p; 3168 3169 /* 3170 * SB700 MSI issue will be fixed at HW level from revision A21; 3171 * we need check PCI REVISION ID of SMBus controller to get SB700 3172 * revision. 3173 */ 3174 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3175 NULL); 3176 if (!p) 3177 return; 3178 3179 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3180 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3181 pci_dev_put(p); 3182 } 3183 3184 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3185 { 3186 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3187 if (dev->revision < 0x18) { 3188 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3189 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3190 } 3191 } 3192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3193 PCI_DEVICE_ID_TIGON3_5780, 3194 quirk_msi_intx_disable_bug); 3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3196 PCI_DEVICE_ID_TIGON3_5780S, 3197 quirk_msi_intx_disable_bug); 3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3199 PCI_DEVICE_ID_TIGON3_5714, 3200 quirk_msi_intx_disable_bug); 3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3202 PCI_DEVICE_ID_TIGON3_5714S, 3203 quirk_msi_intx_disable_bug); 3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3205 PCI_DEVICE_ID_TIGON3_5715, 3206 quirk_msi_intx_disable_bug); 3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3208 PCI_DEVICE_ID_TIGON3_5715S, 3209 quirk_msi_intx_disable_bug); 3210 3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3212 quirk_msi_intx_disable_ati_bug); 3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3214 quirk_msi_intx_disable_ati_bug); 3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3216 quirk_msi_intx_disable_ati_bug); 3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3218 quirk_msi_intx_disable_ati_bug); 3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3220 quirk_msi_intx_disable_ati_bug); 3221 3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3223 quirk_msi_intx_disable_bug); 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3225 quirk_msi_intx_disable_bug); 3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3227 quirk_msi_intx_disable_bug); 3228 3229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3230 quirk_msi_intx_disable_bug); 3231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3232 quirk_msi_intx_disable_bug); 3233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3234 quirk_msi_intx_disable_bug); 3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3236 quirk_msi_intx_disable_bug); 3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3238 quirk_msi_intx_disable_bug); 3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3240 quirk_msi_intx_disable_bug); 3241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3242 quirk_msi_intx_disable_qca_bug); 3243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3244 quirk_msi_intx_disable_qca_bug); 3245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3246 quirk_msi_intx_disable_qca_bug); 3247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3248 quirk_msi_intx_disable_qca_bug); 3249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3250 quirk_msi_intx_disable_qca_bug); 3251 3252 /* 3253 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3254 * should be disabled on platforms where the device (mistakenly) advertises it. 3255 * 3256 * Notice that this quirk also disables MSI (which may work, but hasn't been 3257 * tested), since currently there is no standard way to disable only MSI-X. 3258 * 3259 * The 0031 device id is reused for other non Root Port device types, 3260 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3261 */ 3262 static void quirk_al_msi_disable(struct pci_dev *dev) 3263 { 3264 dev->no_msi = 1; 3265 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3266 } 3267 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3268 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3269 #endif /* CONFIG_PCI_MSI */ 3270 3271 /* 3272 * Allow manual resource allocation for PCI hotplug bridges via 3273 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3274 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3275 * allocate resources when hotplug device is inserted and PCI bus is 3276 * rescanned. 3277 */ 3278 static void quirk_hotplug_bridge(struct pci_dev *dev) 3279 { 3280 dev->is_hotplug_bridge = 1; 3281 } 3282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3283 3284 /* 3285 * This is a quirk for the Ricoh MMC controller found as a part of some 3286 * multifunction chips. 3287 * 3288 * This is very similar and based on the ricoh_mmc driver written by 3289 * Philip Langdale. Thank you for these magic sequences. 3290 * 3291 * These chips implement the four main memory card controllers (SD, MMC, 3292 * MS, xD) and one or both of CardBus or FireWire. 3293 * 3294 * It happens that they implement SD and MMC support as separate 3295 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3296 * cards but the chip detects MMC cards in hardware and directs them to the 3297 * MMC controller - so the SDHCI driver never sees them. 3298 * 3299 * To get around this, we must disable the useless MMC controller. At that 3300 * point, the SDHCI controller will start seeing them. It seems to be the 3301 * case that the relevant PCI registers to deactivate the MMC controller 3302 * live on PCI function 0, which might be the CardBus controller or the 3303 * FireWire controller, depending on the particular chip in question 3304 * 3305 * This has to be done early, because as soon as we disable the MMC controller 3306 * other PCI functions shift up one level, e.g. function #2 becomes function 3307 * #1, and this will confuse the PCI core. 3308 */ 3309 #ifdef CONFIG_MMC_RICOH_MMC 3310 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3311 { 3312 u8 write_enable; 3313 u8 write_target; 3314 u8 disable; 3315 3316 /* 3317 * Disable via CardBus interface 3318 * 3319 * This must be done via function #0 3320 */ 3321 if (PCI_FUNC(dev->devfn)) 3322 return; 3323 3324 pci_read_config_byte(dev, 0xB7, &disable); 3325 if (disable & 0x02) 3326 return; 3327 3328 pci_read_config_byte(dev, 0x8E, &write_enable); 3329 pci_write_config_byte(dev, 0x8E, 0xAA); 3330 pci_read_config_byte(dev, 0x8D, &write_target); 3331 pci_write_config_byte(dev, 0x8D, 0xB7); 3332 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3333 pci_write_config_byte(dev, 0x8E, write_enable); 3334 pci_write_config_byte(dev, 0x8D, write_target); 3335 3336 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3337 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3338 } 3339 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3340 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3341 3342 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3343 { 3344 u8 write_enable; 3345 u8 disable; 3346 3347 /* 3348 * Disable via FireWire interface 3349 * 3350 * This must be done via function #0 3351 */ 3352 if (PCI_FUNC(dev->devfn)) 3353 return; 3354 /* 3355 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3356 * certain types of SD/MMC cards. Lowering the SD base clock 3357 * frequency from 200Mhz to 50Mhz fixes this issue. 3358 * 3359 * 0x150 - SD2.0 mode enable for changing base clock 3360 * frequency to 50Mhz 3361 * 0xe1 - Base clock frequency 3362 * 0x32 - 50Mhz new clock frequency 3363 * 0xf9 - Key register for 0x150 3364 * 0xfc - key register for 0xe1 3365 */ 3366 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3367 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3368 pci_write_config_byte(dev, 0xf9, 0xfc); 3369 pci_write_config_byte(dev, 0x150, 0x10); 3370 pci_write_config_byte(dev, 0xf9, 0x00); 3371 pci_write_config_byte(dev, 0xfc, 0x01); 3372 pci_write_config_byte(dev, 0xe1, 0x32); 3373 pci_write_config_byte(dev, 0xfc, 0x00); 3374 3375 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3376 } 3377 3378 pci_read_config_byte(dev, 0xCB, &disable); 3379 3380 if (disable & 0x02) 3381 return; 3382 3383 pci_read_config_byte(dev, 0xCA, &write_enable); 3384 pci_write_config_byte(dev, 0xCA, 0x57); 3385 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3386 pci_write_config_byte(dev, 0xCA, write_enable); 3387 3388 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3389 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3390 3391 } 3392 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3393 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3394 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3395 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3396 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3397 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3398 #endif /*CONFIG_MMC_RICOH_MMC*/ 3399 3400 #ifdef CONFIG_DMAR_TABLE 3401 #define VTUNCERRMSK_REG 0x1ac 3402 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3403 /* 3404 * This is a quirk for masking VT-d spec-defined errors to platform error 3405 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3406 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3407 * on the RAS config settings of the platform) when a VT-d fault happens. 3408 * The resulting SMI caused the system to hang. 3409 * 3410 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3411 * need to report the same error through other channels. 3412 */ 3413 static void vtd_mask_spec_errors(struct pci_dev *dev) 3414 { 3415 u32 word; 3416 3417 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3418 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3419 } 3420 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3421 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3422 #endif 3423 3424 static void fixup_ti816x_class(struct pci_dev *dev) 3425 { 3426 u32 class = dev->class; 3427 3428 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3429 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3430 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3431 class, dev->class); 3432 } 3433 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3434 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3435 3436 /* 3437 * Some PCIe devices do not work reliably with the claimed maximum 3438 * payload size supported. 3439 */ 3440 static void fixup_mpss_256(struct pci_dev *dev) 3441 { 3442 dev->pcie_mpss = 1; /* 256 bytes */ 3443 } 3444 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3445 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3446 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3447 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3448 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3449 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3450 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3451 3452 /* 3453 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3454 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3455 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3456 * until all of the devices are discovered and buses walked, read completion 3457 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3458 * it is possible to hotplug a device with MPS of 256B. 3459 */ 3460 static void quirk_intel_mc_errata(struct pci_dev *dev) 3461 { 3462 int err; 3463 u16 rcc; 3464 3465 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3466 pcie_bus_config == PCIE_BUS_DEFAULT) 3467 return; 3468 3469 /* 3470 * Intel erratum specifies bits to change but does not say what 3471 * they are. Keeping them magical until such time as the registers 3472 * and values can be explained. 3473 */ 3474 err = pci_read_config_word(dev, 0x48, &rcc); 3475 if (err) { 3476 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3477 return; 3478 } 3479 3480 if (!(rcc & (1 << 10))) 3481 return; 3482 3483 rcc &= ~(1 << 10); 3484 3485 err = pci_write_config_word(dev, 0x48, rcc); 3486 if (err) { 3487 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3488 return; 3489 } 3490 3491 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3492 } 3493 /* Intel 5000 series memory controllers and ports 2-7 */ 3494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3508 /* Intel 5100 series memory controllers and ports 2-7 */ 3509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3520 3521 /* 3522 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3523 * To work around this, query the size it should be configured to by the 3524 * device and modify the resource end to correspond to this new size. 3525 */ 3526 static void quirk_intel_ntb(struct pci_dev *dev) 3527 { 3528 int rc; 3529 u8 val; 3530 3531 rc = pci_read_config_byte(dev, 0x00D0, &val); 3532 if (rc) 3533 return; 3534 3535 resource_set_size(&dev->resource[2], (resource_size_t)1 << val); 3536 3537 rc = pci_read_config_byte(dev, 0x00D1, &val); 3538 if (rc) 3539 return; 3540 3541 resource_set_size(&dev->resource[4], (resource_size_t)1 << val); 3542 } 3543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3545 3546 /* 3547 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3548 * though no one is handling them (e.g., if the i915 driver is never 3549 * loaded). Additionally the interrupt destination is not set up properly 3550 * and the interrupt ends up -somewhere-. 3551 * 3552 * These spurious interrupts are "sticky" and the kernel disables the 3553 * (shared) interrupt line after 100,000+ generated interrupts. 3554 * 3555 * Fix it by disabling the still enabled interrupts. This resolves crashes 3556 * often seen on monitor unplug. 3557 */ 3558 #define I915_DEIER_REG 0x4400c 3559 static void disable_igfx_irq(struct pci_dev *dev) 3560 { 3561 void __iomem *regs = pci_iomap(dev, 0, 0); 3562 if (regs == NULL) { 3563 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3564 return; 3565 } 3566 3567 /* Check if any interrupt line is still enabled */ 3568 if (readl(regs + I915_DEIER_REG) != 0) { 3569 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3570 3571 writel(0, regs + I915_DEIER_REG); 3572 } 3573 3574 pci_iounmap(dev, regs); 3575 } 3576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3583 3584 /* 3585 * PCI devices which are on Intel chips can skip the 10ms delay 3586 * before entering D3 mode. 3587 */ 3588 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3589 { 3590 dev->d3hot_delay = 0; 3591 } 3592 /* C600 Series devices do not need 10ms d3hot_delay */ 3593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3596 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3608 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3618 3619 /* 3620 * Some devices may pass our check in pci_intx_mask_supported() if 3621 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3622 * support this feature. 3623 */ 3624 static void quirk_broken_intx_masking(struct pci_dev *dev) 3625 { 3626 dev->broken_intx_masking = 1; 3627 } 3628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3629 quirk_broken_intx_masking); 3630 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3631 quirk_broken_intx_masking); 3632 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3633 quirk_broken_intx_masking); 3634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, 3635 quirk_broken_intx_masking); 3636 3637 /* 3638 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3639 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3640 * 3641 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3642 */ 3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3644 quirk_broken_intx_masking); 3645 3646 /* 3647 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3648 * DisINTx can be set but the interrupt status bit is non-functional. 3649 */ 3650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3662 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3666 3667 static u16 mellanox_broken_intx_devs[] = { 3668 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3669 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3670 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3671 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3672 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3673 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3674 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3675 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3676 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3677 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3678 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3679 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3680 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3681 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3682 }; 3683 3684 #define CONNECTX_4_CURR_MAX_MINOR 99 3685 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3686 3687 /* 3688 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3689 * If so, don't mark it as broken. 3690 * FW minor > 99 means older FW version format and no INTx masking support. 3691 * FW minor < 14 means new FW version format and no INTx masking support. 3692 */ 3693 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3694 { 3695 __be32 __iomem *fw_ver; 3696 u16 fw_major; 3697 u16 fw_minor; 3698 u16 fw_subminor; 3699 u32 fw_maj_min; 3700 u32 fw_sub_min; 3701 int i; 3702 3703 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3704 if (pdev->device == mellanox_broken_intx_devs[i]) { 3705 pdev->broken_intx_masking = 1; 3706 return; 3707 } 3708 } 3709 3710 /* 3711 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3712 * support so shouldn't be checked further 3713 */ 3714 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3715 return; 3716 3717 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3718 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3719 return; 3720 3721 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3722 if (pci_enable_device_mem(pdev)) { 3723 pci_warn(pdev, "Can't enable device memory\n"); 3724 return; 3725 } 3726 3727 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3728 if (!fw_ver) { 3729 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3730 goto out; 3731 } 3732 3733 /* Reading from resource space should be 32b aligned */ 3734 fw_maj_min = ioread32be(fw_ver); 3735 fw_sub_min = ioread32be(fw_ver + 1); 3736 fw_major = fw_maj_min & 0xffff; 3737 fw_minor = fw_maj_min >> 16; 3738 fw_subminor = fw_sub_min & 0xffff; 3739 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3740 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3741 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3742 fw_major, fw_minor, fw_subminor, pdev->device == 3743 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3744 pdev->broken_intx_masking = 1; 3745 } 3746 3747 iounmap(fw_ver); 3748 3749 out: 3750 pci_disable_device(pdev); 3751 } 3752 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3753 mellanox_check_broken_intx_masking); 3754 3755 static void quirk_no_bus_reset(struct pci_dev *dev) 3756 { 3757 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3758 } 3759 3760 /* 3761 * After asserting Secondary Bus Reset to downstream devices via a GB10 3762 * Root Port, the link may not retrain correctly. 3763 * https://lore.kernel.org/r/20251113084441.2124737-1-Johnny-CC.Chang@mediatek.com 3764 */ 3765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22CE, quirk_no_bus_reset); 3766 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22D0, quirk_no_bus_reset); 3767 3768 /* 3769 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3770 * prevented for those affected devices. 3771 */ 3772 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3773 { 3774 if ((dev->device & 0xffc0) == 0x2340) 3775 quirk_no_bus_reset(dev); 3776 } 3777 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3778 quirk_nvidia_no_bus_reset); 3779 3780 /* 3781 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3782 * The device will throw a Link Down error on AER-capable systems and 3783 * regardless of AER, config space of the device is never accessible again 3784 * and typically causes the system to hang or reset when access is attempted. 3785 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3786 */ 3787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3793 3794 /* 3795 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3796 * reset when used with certain child devices. After the reset, config 3797 * accesses to the child may fail. 3798 */ 3799 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3800 3801 /* 3802 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3803 * automatically disables LTSSM when Secondary Bus Reset is received and 3804 * the device stops working. Prevent bus reset for these devices. With 3805 * this change, the device can be assigned to VMs with VFIO, but it will 3806 * leak state between VMs. Reference 3807 * https://e2e.ti.com/support/processors/f/791/t/954382 3808 */ 3809 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3810 3811 /* 3812 * Reports from users making use of PCI device assignment with ASM1164 3813 * controllers indicate an issue with bus reset where the device fails to 3814 * retrain. The issue appears more common in configurations with multiple 3815 * controllers. The device does indicate PM reset support (NoSoftRst-), 3816 * therefore this still leaves a viable reset method. 3817 * https://forum.proxmox.com/threads/problems-with-pcie-passthrough-with-two-identical-devices.149003/ 3818 */ 3819 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1164, quirk_no_bus_reset); 3820 3821 static void quirk_no_pm_reset(struct pci_dev *dev) 3822 { 3823 /* 3824 * We can't do a bus reset on root bus devices, but an ineffective 3825 * PM reset may be better than nothing. 3826 */ 3827 if (!pci_is_root_bus(dev->bus)) 3828 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3829 } 3830 3831 /* 3832 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3833 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3834 * to have no effect on the device: it retains the framebuffer contents and 3835 * monitor sync. Advertising this support makes other layers, like VFIO, 3836 * assume pci_reset_function() is viable for this device. Mark it as 3837 * unavailable to skip it when testing reset methods. 3838 */ 3839 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3840 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3841 3842 /* 3843 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3844 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3845 * any effect on the device: It continues to be operational and network ports 3846 * remain up. Advertising this support makes it seem as if a PM reset is viable 3847 * for these devices. Mark it as unavailable to skip it when testing reset 3848 * methods. 3849 */ 3850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3853 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3854 3855 /* 3856 * Thunderbolt controllers with broken MSI hotplug signaling: 3857 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3858 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3859 */ 3860 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3861 { 3862 if (pdev->is_pciehp && 3863 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3864 pdev->revision <= 1)) 3865 pdev->no_msi = 1; 3866 } 3867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3868 quirk_thunderbolt_hotplug_msi); 3869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3870 quirk_thunderbolt_hotplug_msi); 3871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3872 quirk_thunderbolt_hotplug_msi); 3873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3874 quirk_thunderbolt_hotplug_msi); 3875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3876 quirk_thunderbolt_hotplug_msi); 3877 3878 #ifdef CONFIG_ACPI 3879 /* 3880 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3881 * 3882 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3883 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3884 * be present after resume if a device was plugged in before suspend. 3885 * 3886 * The Thunderbolt controller consists of a PCIe switch with downstream 3887 * bridges leading to the NHI and to the tunnel PCI bridges. 3888 * 3889 * This quirk cuts power to the whole chip. Therefore we have to apply it 3890 * during suspend_noirq of the upstream bridge. 3891 * 3892 * Power is automagically restored before resume. No action is needed. 3893 */ 3894 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3895 { 3896 acpi_handle bridge, SXIO, SXFP, SXLV; 3897 3898 if (!x86_apple_machine) 3899 return; 3900 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3901 return; 3902 3903 /* 3904 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3905 * We don't know how to turn it back on again, but firmware does, 3906 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3907 * firmware. 3908 */ 3909 if (!pm_suspend_via_firmware()) 3910 return; 3911 3912 bridge = ACPI_HANDLE(&dev->dev); 3913 if (!bridge) 3914 return; 3915 3916 /* 3917 * SXIO and SXLV are present only on machines requiring this quirk. 3918 * Thunderbolt bridges in external devices might have the same 3919 * device ID as those on the host, but they will not have the 3920 * associated ACPI methods. This implicitly checks that we are at 3921 * the right bridge. 3922 */ 3923 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3924 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3925 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3926 return; 3927 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3928 3929 /* magic sequence */ 3930 acpi_execute_simple_method(SXIO, NULL, 1); 3931 acpi_execute_simple_method(SXFP, NULL, 0); 3932 msleep(300); 3933 acpi_execute_simple_method(SXLV, NULL, 0); 3934 acpi_execute_simple_method(SXIO, NULL, 0); 3935 acpi_execute_simple_method(SXLV, NULL, 0); 3936 } 3937 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3938 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3939 quirk_apple_poweroff_thunderbolt); 3940 #endif 3941 3942 /* 3943 * Following are device-specific reset methods which can be used to 3944 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3945 * not available. 3946 */ 3947 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3948 { 3949 /* 3950 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3951 * 3952 * The 82599 supports FLR on VFs, but FLR support is reported only 3953 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3954 * Thus we must call pcie_flr() directly without first checking if it is 3955 * supported. 3956 */ 3957 if (!probe) 3958 pcie_flr(dev); 3959 return 0; 3960 } 3961 3962 #define SOUTH_CHICKEN2 0xc2004 3963 #define PCH_PP_STATUS 0xc7200 3964 #define PCH_PP_CONTROL 0xc7204 3965 #define MSG_CTL 0x45010 3966 #define NSDE_PWR_STATE 0xd0100 3967 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3968 3969 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3970 { 3971 void __iomem *mmio_base; 3972 unsigned long timeout; 3973 u32 val; 3974 3975 if (probe) 3976 return 0; 3977 3978 mmio_base = pci_iomap(dev, 0, 0); 3979 if (!mmio_base) 3980 return -ENOMEM; 3981 3982 iowrite32(0x00000002, mmio_base + MSG_CTL); 3983 3984 /* 3985 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3986 * driver loaded sets the right bits. However, this's a reset and 3987 * the bits have been set by i915 previously, so we clobber 3988 * SOUTH_CHICKEN2 register directly here. 3989 */ 3990 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3991 3992 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3993 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3994 3995 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3996 do { 3997 val = ioread32(mmio_base + PCH_PP_STATUS); 3998 if ((val & 0xb0000000) == 0) 3999 goto reset_complete; 4000 msleep(10); 4001 } while (time_before(jiffies, timeout)); 4002 pci_warn(dev, "timeout during reset\n"); 4003 4004 reset_complete: 4005 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 4006 4007 pci_iounmap(dev, mmio_base); 4008 return 0; 4009 } 4010 4011 /* Device-specific reset method for Chelsio T4-based adapters */ 4012 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 4013 { 4014 u16 old_command; 4015 u16 msix_flags; 4016 4017 /* 4018 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 4019 * that we have no device-specific reset method. 4020 */ 4021 if ((dev->device & 0xf000) != 0x4000) 4022 return -ENOTTY; 4023 4024 /* 4025 * If this is the "probe" phase, return 0 indicating that we can 4026 * reset this device. 4027 */ 4028 if (probe) 4029 return 0; 4030 4031 /* 4032 * T4 can wedge if there are DMAs in flight within the chip and Bus 4033 * Master has been disabled. We need to have it on till the Function 4034 * Level Reset completes. (BUS_MASTER is disabled in 4035 * pci_reset_function()). 4036 */ 4037 pci_read_config_word(dev, PCI_COMMAND, &old_command); 4038 pci_write_config_word(dev, PCI_COMMAND, 4039 old_command | PCI_COMMAND_MASTER); 4040 4041 /* 4042 * Perform the actual device function reset, saving and restoring 4043 * configuration information around the reset. 4044 */ 4045 pci_save_state(dev); 4046 4047 /* 4048 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 4049 * are disabled when an MSI-X interrupt message needs to be delivered. 4050 * So we briefly re-enable MSI-X interrupts for the duration of the 4051 * FLR. The pci_restore_state() below will restore the original 4052 * MSI-X state. 4053 */ 4054 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 4055 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 4056 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 4057 msix_flags | 4058 PCI_MSIX_FLAGS_ENABLE | 4059 PCI_MSIX_FLAGS_MASKALL); 4060 4061 pcie_flr(dev); 4062 4063 /* 4064 * Restore the configuration information (BAR values, etc.) including 4065 * the original PCI Configuration Space Command word, and return 4066 * success. 4067 */ 4068 pci_restore_state(dev); 4069 pci_write_config_word(dev, PCI_COMMAND, old_command); 4070 return 0; 4071 } 4072 4073 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4074 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4075 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4076 4077 /* 4078 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4079 * FLR where config space reads from the device return -1. We seem to be 4080 * able to avoid this condition if we disable the NVMe controller prior to 4081 * FLR. This quirk is generic for any NVMe class device requiring similar 4082 * assistance to quiesce the device prior to FLR. 4083 * 4084 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4085 * Revision 1.0e: 4086 * Chapter 2: Required and optional PCI config registers 4087 * Chapter 3: NVMe control registers 4088 * Chapter 7.3: Reset behavior 4089 */ 4090 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4091 { 4092 void __iomem *bar; 4093 u16 cmd; 4094 u32 cfg; 4095 4096 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4097 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4098 return -ENOTTY; 4099 4100 if (probe) 4101 return 0; 4102 4103 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4104 if (!bar) 4105 return -ENOTTY; 4106 4107 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4108 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4109 4110 cfg = readl(bar + NVME_REG_CC); 4111 4112 /* Disable controller if enabled */ 4113 if (cfg & NVME_CC_ENABLE) { 4114 u32 cap = readl(bar + NVME_REG_CAP); 4115 unsigned long timeout; 4116 4117 /* 4118 * Per nvme_disable_ctrl() skip shutdown notification as it 4119 * could complete commands to the admin queue. We only intend 4120 * to quiesce the device before reset. 4121 */ 4122 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4123 4124 writel(cfg, bar + NVME_REG_CC); 4125 4126 /* 4127 * Some controllers require an additional delay here, see 4128 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4129 * supported by this quirk. 4130 */ 4131 4132 /* Cap register provides max timeout in 500ms increments */ 4133 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4134 4135 for (;;) { 4136 u32 status = readl(bar + NVME_REG_CSTS); 4137 4138 /* Ready status becomes zero on disable complete */ 4139 if (!(status & NVME_CSTS_RDY)) 4140 break; 4141 4142 msleep(100); 4143 4144 if (time_after(jiffies, timeout)) { 4145 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4146 break; 4147 } 4148 } 4149 } 4150 4151 pci_iounmap(dev, bar); 4152 4153 pcie_flr(dev); 4154 4155 return 0; 4156 } 4157 4158 /* 4159 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4160 * timeout waiting for ready status to change after NVMe enable if the driver 4161 * starts interacting with the device too soon after FLR. A 250ms delay after 4162 * FLR has heuristically proven to produce reliably working results for device 4163 * assignment cases. 4164 */ 4165 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4166 { 4167 if (probe) 4168 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4169 4170 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4171 4172 msleep(250); 4173 4174 return 0; 4175 } 4176 4177 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4178 #define HINIC_VF_FLR_TYPE 0x1000 4179 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4180 #define HINIC_VF_OP 0xE80 4181 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4182 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4183 4184 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4185 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4186 { 4187 unsigned long timeout; 4188 void __iomem *bar; 4189 u32 val; 4190 4191 if (probe) 4192 return 0; 4193 4194 bar = pci_iomap(pdev, 0, 0); 4195 if (!bar) 4196 return -ENOTTY; 4197 4198 /* Get and check firmware capabilities */ 4199 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4200 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4201 pci_iounmap(pdev, bar); 4202 return -ENOTTY; 4203 } 4204 4205 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4206 val = ioread32be(bar + HINIC_VF_OP); 4207 val = val | HINIC_VF_FLR_PROC_BIT; 4208 iowrite32be(val, bar + HINIC_VF_OP); 4209 4210 pcie_flr(pdev); 4211 4212 /* 4213 * The device must recapture its Bus and Device Numbers after FLR 4214 * in order generate Completions. Issue a config write to let the 4215 * device capture this information. 4216 */ 4217 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4218 4219 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4220 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4221 do { 4222 val = ioread32be(bar + HINIC_VF_OP); 4223 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4224 goto reset_complete; 4225 msleep(20); 4226 } while (time_before(jiffies, timeout)); 4227 4228 val = ioread32be(bar + HINIC_VF_OP); 4229 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4230 goto reset_complete; 4231 4232 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4233 4234 reset_complete: 4235 pci_iounmap(pdev, bar); 4236 4237 return 0; 4238 } 4239 4240 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4241 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4242 reset_intel_82599_sfp_virtfn }, 4243 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4244 reset_ivb_igd }, 4245 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4246 reset_ivb_igd }, 4247 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4248 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4249 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4250 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4251 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4252 reset_chelsio_generic_dev }, 4253 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4254 reset_hinic_vf_dev }, 4255 { 0 } 4256 }; 4257 4258 static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, 4259 const struct pci_dev_reset_methods *i) 4260 { 4261 int ret; 4262 4263 ret = pci_dev_reset_iommu_prepare(dev); 4264 if (ret) { 4265 pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); 4266 return ret; 4267 } 4268 4269 ret = i->reset(dev, probe); 4270 pci_dev_reset_iommu_done(dev); 4271 return ret; 4272 } 4273 4274 /* 4275 * These device-specific reset methods are here rather than in a driver 4276 * because when a host assigns a device to a guest VM, the host may need 4277 * to reset the device but probably doesn't have a driver for it. 4278 */ 4279 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4280 { 4281 const struct pci_dev_reset_methods *i; 4282 4283 for (i = pci_dev_reset_methods; i->reset; i++) { 4284 if ((i->vendor == dev->vendor || 4285 i->vendor == (u16)PCI_ANY_ID) && 4286 (i->device == dev->device || 4287 i->device == (u16)PCI_ANY_ID)) 4288 return __pci_dev_specific_reset(dev, probe, i); 4289 } 4290 4291 return -ENOTTY; 4292 } 4293 4294 static void quirk_dma_func0_alias(struct pci_dev *dev) 4295 { 4296 if (PCI_FUNC(dev->devfn) != 0) 4297 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4298 } 4299 4300 /* 4301 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4302 * 4303 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4304 */ 4305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4307 4308 /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ 4309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); 4310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); 4311 4312 static void quirk_dma_func1_alias(struct pci_dev *dev) 4313 { 4314 if (PCI_FUNC(dev->devfn) != 1) 4315 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4316 } 4317 4318 /* 4319 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4320 * SKUs function 1 is present and is a legacy IDE controller, in other 4321 * SKUs this function is not present, making this a ghost requester. 4322 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4323 */ 4324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4325 quirk_dma_func1_alias); 4326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4327 quirk_dma_func1_alias); 4328 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4330 quirk_dma_func1_alias); 4331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4332 quirk_dma_func1_alias); 4333 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4335 quirk_dma_func1_alias); 4336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4337 quirk_dma_func1_alias); 4338 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4340 quirk_dma_func1_alias); 4341 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4343 quirk_dma_func1_alias); 4344 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4346 quirk_dma_func1_alias); 4347 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4349 quirk_dma_func1_alias); 4350 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4352 quirk_dma_func1_alias); 4353 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4355 quirk_dma_func1_alias); 4356 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4358 quirk_dma_func1_alias); 4359 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4361 quirk_dma_func1_alias); 4362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4363 quirk_dma_func1_alias); 4364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4365 quirk_dma_func1_alias); 4366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4367 quirk_dma_func1_alias); 4368 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4370 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4371 quirk_dma_func1_alias); 4372 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4373 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4374 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4375 quirk_dma_func1_alias); 4376 4377 /* 4378 * Some devices DMA with the wrong devfn, not just the wrong function. 4379 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4380 * the alias is "fixed" and independent of the device devfn. 4381 * 4382 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4383 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4384 * single device on the secondary bus. In reality, the single exposed 4385 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4386 * that provides a bridge to the internal bus of the I/O processor. The 4387 * controller supports private devices, which can be hidden from PCI config 4388 * space. In the case of the Adaptec 3405, a private device at 01.0 4389 * appears to be the DMA engine, which therefore needs to become a DMA 4390 * alias for the device. 4391 */ 4392 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4393 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4394 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4395 .driver_data = PCI_DEVFN(1, 0) }, 4396 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4397 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4398 .driver_data = PCI_DEVFN(1, 0) }, 4399 { 0 } 4400 }; 4401 4402 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4403 { 4404 const struct pci_device_id *id; 4405 4406 id = pci_match_id(fixed_dma_alias_tbl, dev); 4407 if (id) 4408 pci_add_dma_alias(dev, id->driver_data, 1); 4409 } 4410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4411 4412 /* 4413 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4414 * using the wrong DMA alias for the device. Some of these devices can be 4415 * used as either forward or reverse bridges, so we need to test whether the 4416 * device is operating in the correct mode. We could probably apply this 4417 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4418 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4419 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4420 */ 4421 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4422 { 4423 if (!pci_is_root_bus(pdev->bus) && 4424 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4425 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4426 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4427 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4428 } 4429 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4430 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4431 quirk_use_pcie_bridge_dma_alias); 4432 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4433 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4434 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4435 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4436 /* ITE 8893 has the same problem as the 8892 */ 4437 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4438 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4439 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4440 4441 /* 4442 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4443 * be added as aliases to the DMA device in order to allow buffer access 4444 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4445 * programmed in the EEPROM. 4446 */ 4447 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4448 { 4449 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4450 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4451 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4452 } 4453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4455 4456 /* 4457 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4458 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4459 * 4460 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4461 * when IOMMU is enabled. These aliases allow computational unit access to 4462 * host memory. These aliases mark the whole VCA device as one IOMMU 4463 * group. 4464 * 4465 * All possible slot numbers (0x20) are used, since we are unable to tell 4466 * what slot is used on other side. This quirk is intended for both host 4467 * and computational unit sides. The VCA devices have up to five functions 4468 * (four for DMA channels and one additional). 4469 */ 4470 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4471 { 4472 const unsigned int num_pci_slots = 0x20; 4473 unsigned int slot; 4474 4475 for (slot = 0; slot < num_pci_slots; slot++) 4476 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4477 } 4478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4484 4485 /* 4486 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4487 * associated not at the root bus, but at a bridge below. This quirk avoids 4488 * generating invalid DMA aliases. 4489 */ 4490 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4491 { 4492 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4493 } 4494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4495 quirk_bridge_cavm_thrx2_pcie_root); 4496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4497 quirk_bridge_cavm_thrx2_pcie_root); 4498 4499 /* 4500 * AST1150 doesn't use a real PCI bus and always forwards the requester ID 4501 * from downstream devices. 4502 */ 4503 static void quirk_aspeed_pci_bridge_no_alias(struct pci_dev *pdev) 4504 { 4505 pdev->dev_flags |= PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS; 4506 } 4507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASPEED, 0x1150, quirk_aspeed_pci_bridge_no_alias); 4508 4509 /* 4510 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4511 * class code. Fix it. 4512 */ 4513 static void quirk_tw686x_class(struct pci_dev *pdev) 4514 { 4515 u32 class = pdev->class; 4516 4517 /* Use "Multimedia controller" class */ 4518 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4519 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4520 class, pdev->class); 4521 } 4522 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4523 quirk_tw686x_class); 4524 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4525 quirk_tw686x_class); 4526 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4527 quirk_tw686x_class); 4528 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4529 quirk_tw686x_class); 4530 4531 /* 4532 * Some devices have problems with Transaction Layer Packets with the Relaxed 4533 * Ordering Attribute set. Such devices should mark themselves and other 4534 * device drivers should check before sending TLPs with RO set. 4535 */ 4536 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4537 { 4538 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4539 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4540 } 4541 4542 /* 4543 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4544 * Complex have a Flow Control Credit issue which can cause performance 4545 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4546 */ 4547 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4548 quirk_relaxedordering_disable); 4549 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4550 quirk_relaxedordering_disable); 4551 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4552 quirk_relaxedordering_disable); 4553 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4554 quirk_relaxedordering_disable); 4555 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4556 quirk_relaxedordering_disable); 4557 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4558 quirk_relaxedordering_disable); 4559 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4560 quirk_relaxedordering_disable); 4561 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4562 quirk_relaxedordering_disable); 4563 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4564 quirk_relaxedordering_disable); 4565 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4566 quirk_relaxedordering_disable); 4567 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4568 quirk_relaxedordering_disable); 4569 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4570 quirk_relaxedordering_disable); 4571 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4572 quirk_relaxedordering_disable); 4573 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4574 quirk_relaxedordering_disable); 4575 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4576 quirk_relaxedordering_disable); 4577 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4578 quirk_relaxedordering_disable); 4579 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4580 quirk_relaxedordering_disable); 4581 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4582 quirk_relaxedordering_disable); 4583 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4584 quirk_relaxedordering_disable); 4585 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4586 quirk_relaxedordering_disable); 4587 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4588 quirk_relaxedordering_disable); 4589 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4590 quirk_relaxedordering_disable); 4591 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4592 quirk_relaxedordering_disable); 4593 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4594 quirk_relaxedordering_disable); 4595 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4596 quirk_relaxedordering_disable); 4597 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4598 quirk_relaxedordering_disable); 4599 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4600 quirk_relaxedordering_disable); 4601 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4602 quirk_relaxedordering_disable); 4603 4604 /* 4605 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4606 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4607 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4608 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4609 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4610 * November 10, 2010). As a result, on this platform we can't use Relaxed 4611 * Ordering for Upstream TLPs. 4612 */ 4613 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4614 quirk_relaxedordering_disable); 4615 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4616 quirk_relaxedordering_disable); 4617 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4618 quirk_relaxedordering_disable); 4619 4620 /* 4621 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4622 * values for the Attribute as were supplied in the header of the 4623 * corresponding Request, except as explicitly allowed when IDO is used." 4624 * 4625 * If a non-compliant device generates a completion with a different 4626 * attribute than the request, the receiver may accept it (which itself 4627 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4628 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4629 * device access timeout. 4630 * 4631 * If the non-compliant device generates completions with zero attributes 4632 * (instead of copying the attributes from the request), we can work around 4633 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4634 * upstream devices so they always generate requests with zero attributes. 4635 * 4636 * This affects other devices under the same Root Port, but since these 4637 * attributes are performance hints, there should be no functional problem. 4638 * 4639 * Note that Configuration Space accesses are never supposed to have TLP 4640 * Attributes, so we're safe waiting till after any Configuration Space 4641 * accesses to do the Root Port fixup. 4642 */ 4643 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4644 { 4645 struct pci_dev *root_port = pcie_find_root_port(pdev); 4646 4647 if (!root_port) { 4648 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4649 return; 4650 } 4651 4652 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4653 dev_name(&pdev->dev)); 4654 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL, 4655 PCI_EXP_DEVCTL_RELAX_EN | 4656 PCI_EXP_DEVCTL_NOSNOOP_EN); 4657 } 4658 4659 /* 4660 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4661 * Completion it generates. 4662 */ 4663 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4664 { 4665 /* 4666 * This mask/compare operation selects for Physical Function 4 on a 4667 * T5. We only need to fix up the Root Port once for any of the 4668 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4669 * 0x54xx so we use that one. 4670 */ 4671 if ((pdev->device & 0xff00) == 0x5400) 4672 quirk_disable_root_port_attributes(pdev); 4673 } 4674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4675 quirk_chelsio_T5_disable_root_port_attributes); 4676 4677 /* 4678 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4679 * by a device 4680 * @acs_ctrl_req: Bitmask of desired ACS controls 4681 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4682 * the hardware design 4683 * 4684 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4685 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4686 * caller desires. Return 0 otherwise. 4687 */ 4688 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4689 { 4690 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4691 return 1; 4692 return 0; 4693 } 4694 4695 /* 4696 * AMD has indicated that the devices below do not support peer-to-peer 4697 * in any system where they are found in the southbridge with an AMD 4698 * IOMMU in the system. Multifunction devices that do not support 4699 * peer-to-peer between functions can claim to support a subset of ACS. 4700 * Such devices effectively enable request redirect (RR) and completion 4701 * redirect (CR) since all transactions are redirected to the upstream 4702 * root complex. 4703 * 4704 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4705 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4706 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4707 * 4708 * 1002:4385 SBx00 SMBus Controller 4709 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4710 * 1002:4383 SBx00 Azalia (Intel HDA) 4711 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4712 * 1002:4384 SBx00 PCI to PCI Bridge 4713 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4714 * 4715 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4716 * 4717 * 1022:780f [AMD] FCH PCI Bridge 4718 * 1022:7809 [AMD] FCH USB OHCI Controller 4719 */ 4720 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4721 { 4722 #ifdef CONFIG_ACPI 4723 struct acpi_table_header *header = NULL; 4724 acpi_status status; 4725 4726 /* Targeting multifunction devices on the SB (appears on root bus) */ 4727 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4728 return -ENODEV; 4729 4730 /* The IVRS table describes the AMD IOMMU */ 4731 status = acpi_get_table("IVRS", 0, &header); 4732 if (ACPI_FAILURE(status)) 4733 return -ENODEV; 4734 4735 acpi_put_table(header); 4736 4737 /* Filter out flags not applicable to multifunction */ 4738 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4739 4740 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4741 #else 4742 return -ENODEV; 4743 #endif 4744 } 4745 4746 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4747 { 4748 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4749 return false; 4750 4751 switch (dev->device) { 4752 /* 4753 * Effectively selects all downstream ports for whole ThunderX1 4754 * (which represents 8 SoCs). 4755 */ 4756 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4757 case 0xaf84: /* ThunderX2 */ 4758 case 0xb884: /* ThunderX3 */ 4759 return true; 4760 default: 4761 return false; 4762 } 4763 } 4764 4765 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4766 { 4767 if (!pci_quirk_cavium_acs_match(dev)) 4768 return -ENOTTY; 4769 4770 /* 4771 * Cavium Root Ports don't advertise an ACS capability. However, 4772 * the RTL internally implements similar protection as if ACS had 4773 * Source Validation, Request Redirection, Completion Redirection, 4774 * and Upstream Forwarding features enabled. Assert that the 4775 * hardware implements and enables equivalent ACS functionality for 4776 * these flags. 4777 */ 4778 return pci_acs_ctrl_enabled(acs_flags, 4779 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4780 } 4781 4782 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4783 { 4784 /* 4785 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4786 * transactions with others, allowing masking out these bits as if they 4787 * were unimplemented in the ACS capability. 4788 */ 4789 return pci_acs_ctrl_enabled(acs_flags, 4790 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4791 } 4792 4793 /* 4794 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4795 * But the implementation could block peer-to-peer transactions between them 4796 * and provide ACS-like functionality. 4797 */ 4798 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4799 { 4800 if (!pci_is_pcie(dev) || 4801 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4802 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4803 return -ENOTTY; 4804 4805 /* 4806 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4807 * implement ACS capability in accordance with the PCIe Spec. 4808 */ 4809 switch (dev->device) { 4810 case 0x0710 ... 0x071e: 4811 case 0x0721: 4812 case 0x0723 ... 0x0752: 4813 return pci_acs_ctrl_enabled(acs_flags, 4814 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4815 } 4816 4817 return false; 4818 } 4819 4820 /* 4821 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4822 * transactions and validate bus numbers in requests, but do not provide an 4823 * actual PCIe ACS capability. This is the list of device IDs known to fall 4824 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4825 */ 4826 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4827 /* Ibexpeak PCH */ 4828 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4829 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4830 /* Cougarpoint PCH */ 4831 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4832 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4833 /* Pantherpoint PCH */ 4834 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4835 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4836 /* Lynxpoint-H PCH */ 4837 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4838 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4839 /* Lynxpoint-LP PCH */ 4840 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4841 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4842 /* Wildcat PCH */ 4843 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4844 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4845 /* Patsburg (X79) PCH */ 4846 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4847 /* Wellsburg (X99) PCH */ 4848 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4849 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4850 /* Lynx Point (9 series) PCH */ 4851 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4852 }; 4853 4854 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4855 { 4856 int i; 4857 4858 /* Filter out a few obvious non-matches first */ 4859 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4860 return false; 4861 4862 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4863 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4864 return true; 4865 4866 return false; 4867 } 4868 4869 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4870 { 4871 if (!pci_quirk_intel_pch_acs_match(dev)) 4872 return -ENOTTY; 4873 4874 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4875 return pci_acs_ctrl_enabled(acs_flags, 4876 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4877 4878 return pci_acs_ctrl_enabled(acs_flags, 0); 4879 } 4880 4881 /* 4882 * These QCOM Root Ports do provide ACS-like features to disable peer 4883 * transactions and validate bus numbers in requests, but do not provide an 4884 * actual PCIe ACS capability. Hardware supports source validation but it 4885 * will report the issue as Completer Abort instead of ACS Violation. 4886 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4887 * Complex with unique segment numbers. It is not possible for one Root 4888 * Port to pass traffic to another Root Port. All PCIe transactions are 4889 * terminated inside the Root Port. 4890 */ 4891 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4892 { 4893 return pci_acs_ctrl_enabled(acs_flags, 4894 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4895 } 4896 4897 /* 4898 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4899 * number and does provide isolation features to disable peer transactions 4900 * and validate bus numbers in requests, but does not provide an ACS 4901 * capability. 4902 */ 4903 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4904 { 4905 return pci_acs_ctrl_enabled(acs_flags, 4906 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4907 } 4908 4909 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4910 { 4911 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4912 return -ENOTTY; 4913 4914 /* 4915 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4916 * but do include ACS-like functionality. The hardware doesn't support 4917 * peer-to-peer transactions via the root port and each has a unique 4918 * segment number. 4919 * 4920 * Additionally, the root ports cannot send traffic to each other. 4921 */ 4922 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4923 4924 return acs_flags ? 0 : 1; 4925 } 4926 4927 /* 4928 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4929 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4930 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4931 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4932 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4933 * control register is at offset 8 instead of 6 and we should probably use 4934 * dword accesses to them. This applies to the following PCI Device IDs, as 4935 * found in volume 1 of the datasheet[2]: 4936 * 4937 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4938 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4939 * 4940 * N.B. This doesn't fix what lspci shows. 4941 * 4942 * The 100 series chipset specification update includes this as errata #23[3]. 4943 * 4944 * The 200 series chipset (Union Point) has the same bug according to the 4945 * specification update (Intel 200 Series Chipset Family Platform Controller 4946 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4947 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4948 * chipset include: 4949 * 4950 * 0xa290-0xa29f PCI Express Root port #{0-16} 4951 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4952 * 4953 * Mobile chipsets are also affected, 7th & 8th Generation 4954 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4955 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4956 * Processor Family I/O for U Quad Core Platforms Specification Update, 4957 * August 2017, Revision 002, Document#: 334660-002)[6] 4958 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4959 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4960 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4961 * 4962 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4963 * 4964 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4965 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4966 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4967 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4968 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4969 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4970 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4971 */ 4972 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4973 { 4974 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4975 return false; 4976 4977 switch (dev->device) { 4978 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4979 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4980 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4981 return true; 4982 } 4983 4984 return false; 4985 } 4986 4987 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4988 4989 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4990 { 4991 int pos; 4992 u32 cap, ctrl; 4993 4994 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4995 return -ENOTTY; 4996 4997 pos = dev->acs_cap; 4998 if (!pos) 4999 return -ENOTTY; 5000 5001 /* see pci_acs_flags_enabled() */ 5002 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5003 acs_flags &= (cap | PCI_ACS_EC); 5004 5005 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5006 5007 return pci_acs_ctrl_enabled(acs_flags, ctrl); 5008 } 5009 5010 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 5011 { 5012 /* 5013 * SV, TB, and UF are not relevant to multifunction endpoints. 5014 * 5015 * Multifunction devices are only required to implement RR, CR, and DT 5016 * in their ACS capability if they support peer-to-peer transactions. 5017 * Devices matching this quirk have been verified by the vendor to not 5018 * perform peer-to-peer with other functions, allowing us to mask out 5019 * these bits as if they were unimplemented in the ACS capability. 5020 */ 5021 return pci_acs_ctrl_enabled(acs_flags, 5022 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 5023 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 5024 } 5025 5026 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 5027 { 5028 /* 5029 * Intel RCiEP's are required to allow p2p only on translated 5030 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 5031 * "Root-Complex Peer to Peer Considerations". 5032 */ 5033 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 5034 return -ENOTTY; 5035 5036 return pci_acs_ctrl_enabled(acs_flags, 5037 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5038 } 5039 5040 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 5041 { 5042 /* 5043 * iProc PAXB Root Ports don't advertise an ACS capability, but 5044 * they do not allow peer-to-peer transactions between Root Ports. 5045 * Allow each Root Port to be in a separate IOMMU group by masking 5046 * SV/RR/CR/UF bits. 5047 */ 5048 return pci_acs_ctrl_enabled(acs_flags, 5049 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5050 } 5051 5052 static int pci_quirk_loongson_acs(struct pci_dev *dev, u16 acs_flags) 5053 { 5054 /* 5055 * Loongson PCIe Root Ports don't advertise an ACS capability, but 5056 * they do not allow peer-to-peer transactions between Root Ports. 5057 * Allow each Root Port to be in a separate IOMMU group by masking 5058 * SV/RR/CR/UF bits. 5059 */ 5060 return pci_acs_ctrl_enabled(acs_flags, 5061 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5062 } 5063 5064 /* 5065 * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on 5066 * multi-function devices, the hardware isolates the functions by 5067 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and 5068 * PCI_ACS_CR were set. 5069 * SFxxx 1G NICs(em). 5070 * RP1000/RP2000 10G NICs(sp). 5071 * FF5xxx 40G/25G/10G NICs(aml). 5072 */ 5073 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 5074 { 5075 switch (dev->device) { 5076 case 0x0100 ... 0x010F: /* EM */ 5077 case 0x1001: case 0x2001: /* SP */ 5078 case 0x5010: case 0x5025: case 0x5040: /* AML */ 5079 case 0x5110: case 0x5125: case 0x5140: /* AML */ 5080 return pci_acs_ctrl_enabled(acs_flags, 5081 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5082 } 5083 5084 return false; 5085 } 5086 5087 static const struct pci_dev_acs_enabled { 5088 u16 vendor; 5089 u16 device; 5090 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 5091 } pci_dev_acs_enabled[] = { 5092 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 5093 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 5094 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 5095 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 5096 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 5097 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 5098 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 5099 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 5100 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 5101 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 5102 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 5103 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 5104 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 5105 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 5106 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 5107 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 5108 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 5109 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 5110 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 5111 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 5112 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 5113 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 5114 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5115 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5116 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5117 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5118 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5119 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5120 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5121 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5122 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5123 /* 82580 */ 5124 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5125 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5126 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5127 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5128 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5129 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5130 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5131 /* 82576 */ 5132 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5133 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5134 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5135 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5136 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5137 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5138 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5139 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5140 /* 82575 */ 5141 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5142 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5143 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5144 /* I350 */ 5145 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5146 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5147 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5148 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5149 /* 82571 (Quads omitted due to non-ACS switch) */ 5150 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5151 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5152 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5153 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5154 /* I219 */ 5155 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5156 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5157 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5158 /* QCOM QDF2xxx root ports */ 5159 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5160 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5161 /* QCOM SA8775P root port */ 5162 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5163 /* QCOM Hamoa root port */ 5164 { PCI_VENDOR_ID_QCOM, 0x0111, pci_quirk_qcom_rp_acs }, 5165 /* QCOM Glymur root port */ 5166 { PCI_VENDOR_ID_QCOM, 0x0120, pci_quirk_qcom_rp_acs }, 5167 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5168 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5169 /* Intel PCH root ports */ 5170 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5171 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5172 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5173 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5174 /* Cavium ThunderX */ 5175 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5176 /* Cavium multi-function devices */ 5177 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5178 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5179 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5180 /* APM X-Gene */ 5181 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5182 /* Ampere Computing */ 5183 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5184 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5185 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5186 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5187 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5188 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5189 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5190 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5191 /* Broadcom multi-function device */ 5192 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5193 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5194 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5195 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5196 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs }, 5197 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs }, 5198 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs }, 5199 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs }, 5200 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5201 /* Loongson PCIe Root Ports */ 5202 { PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs }, 5203 { PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs }, 5204 { PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs }, 5205 { PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs }, 5206 { PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs }, 5207 { PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs }, 5208 { PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs }, 5209 { PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs }, 5210 { PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs }, 5211 { PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs }, 5212 /* Amazon Annapurna Labs */ 5213 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5214 /* Zhaoxin multi-function devices */ 5215 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5216 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5217 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5218 /* NXP root ports, xx=16, 12, or 08 cores */ 5219 /* LX2xx0A : without security features + CAN-FD */ 5220 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5221 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5222 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5223 /* LX2xx0C : security features + CAN-FD */ 5224 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5225 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5226 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5227 /* LX2xx0E : security features + CAN */ 5228 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5229 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5230 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5231 /* LX2xx0N : without security features + CAN */ 5232 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5233 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5234 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5235 /* LX2xx2A : without security features + CAN-FD */ 5236 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5237 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5238 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5239 /* LX2xx2C : security features + CAN-FD */ 5240 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5241 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5242 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5243 /* LX2xx2E : security features + CAN */ 5244 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5245 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5246 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5247 /* LX2xx2N : without security features + CAN */ 5248 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5249 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5250 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5251 /* Zhaoxin Root/Downstream Ports */ 5252 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5253 /* Wangxun nics */ 5254 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5255 { 0 } 5256 }; 5257 5258 /* 5259 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5260 * @dev: PCI device 5261 * @acs_flags: Bitmask of desired ACS controls 5262 * 5263 * Returns: 5264 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5265 * device provides the desired controls 5266 * 0: Device does not provide all the desired controls 5267 * >0: Device provides all the controls in @acs_flags 5268 */ 5269 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5270 { 5271 const struct pci_dev_acs_enabled *i; 5272 int ret; 5273 5274 /* 5275 * Allow devices that do not expose standard PCIe ACS capabilities 5276 * or control to indicate their support here. Multi-function express 5277 * devices which do not allow internal peer-to-peer between functions, 5278 * but do not implement PCIe ACS may wish to return true here. 5279 */ 5280 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5281 if ((i->vendor == dev->vendor || 5282 i->vendor == (u16)PCI_ANY_ID) && 5283 (i->device == dev->device || 5284 i->device == (u16)PCI_ANY_ID)) { 5285 ret = i->acs_enabled(dev, acs_flags); 5286 if (ret >= 0) 5287 return ret; 5288 } 5289 } 5290 5291 return -ENOTTY; 5292 } 5293 5294 /* Config space offset of Root Complex Base Address register */ 5295 #define INTEL_LPC_RCBA_REG 0xf0 5296 /* 31:14 RCBA address */ 5297 #define INTEL_LPC_RCBA_MASK 0xffffc000 5298 /* RCBA Enable */ 5299 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5300 5301 /* Backbone Scratch Pad Register */ 5302 #define INTEL_BSPR_REG 0x1104 5303 /* Backbone Peer Non-Posted Disable */ 5304 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5305 /* Backbone Peer Posted Disable */ 5306 #define INTEL_BSPR_REG_BPPD (1 << 9) 5307 5308 /* Upstream Peer Decode Configuration Register */ 5309 #define INTEL_UPDCR_REG 0x1014 5310 /* 5:0 Peer Decode Enable bits */ 5311 #define INTEL_UPDCR_REG_MASK 0x3f 5312 5313 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5314 { 5315 u32 rcba, bspr, updcr; 5316 void __iomem *rcba_mem; 5317 5318 /* 5319 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5320 * are D28:F* and therefore get probed before LPC, thus we can't 5321 * use pci_get_slot()/pci_read_config_dword() here. 5322 */ 5323 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5324 INTEL_LPC_RCBA_REG, &rcba); 5325 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5326 return -EINVAL; 5327 5328 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5329 PAGE_ALIGN(INTEL_UPDCR_REG)); 5330 if (!rcba_mem) 5331 return -ENOMEM; 5332 5333 /* 5334 * The BSPR can disallow peer cycles, but it's set by soft strap and 5335 * therefore read-only. If both posted and non-posted peer cycles are 5336 * disallowed, we're ok. If either are allowed, then we need to use 5337 * the UPDCR to disable peer decodes for each port. This provides the 5338 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5339 */ 5340 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5341 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5342 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5343 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5344 if (updcr & INTEL_UPDCR_REG_MASK) { 5345 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5346 updcr &= ~INTEL_UPDCR_REG_MASK; 5347 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5348 } 5349 } 5350 5351 iounmap(rcba_mem); 5352 return 0; 5353 } 5354 5355 /* Miscellaneous Port Configuration register */ 5356 #define INTEL_MPC_REG 0xd8 5357 /* MPC: Invalid Receive Bus Number Check Enable */ 5358 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5359 5360 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5361 { 5362 u32 mpc; 5363 5364 /* 5365 * When enabled, the IRBNCE bit of the MPC register enables the 5366 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5367 * ensures that requester IDs fall within the bus number range 5368 * of the bridge. Enable if not already. 5369 */ 5370 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5371 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5372 pci_info(dev, "Enabling MPC IRBNCE\n"); 5373 mpc |= INTEL_MPC_REG_IRBNCE; 5374 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5375 } 5376 } 5377 5378 /* 5379 * Currently this quirk does the equivalent of 5380 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5381 * 5382 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5383 * if dev->external_facing || dev->untrusted 5384 */ 5385 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5386 { 5387 if (!pci_quirk_intel_pch_acs_match(dev)) 5388 return -ENOTTY; 5389 5390 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5391 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5392 return 0; 5393 } 5394 5395 pci_quirk_enable_intel_rp_mpc_acs(dev); 5396 5397 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5398 5399 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5400 5401 return 0; 5402 } 5403 5404 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5405 { 5406 int pos; 5407 u32 cap, ctrl; 5408 5409 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5410 return -ENOTTY; 5411 5412 pos = dev->acs_cap; 5413 if (!pos) 5414 return -ENOTTY; 5415 5416 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5417 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5418 5419 ctrl |= (cap & PCI_ACS_SV); 5420 ctrl |= (cap & PCI_ACS_RR); 5421 ctrl |= (cap & PCI_ACS_CR); 5422 ctrl |= (cap & PCI_ACS_UF); 5423 5424 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5425 ctrl |= (cap & PCI_ACS_TB); 5426 5427 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5428 5429 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5430 5431 return 0; 5432 } 5433 5434 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5435 { 5436 int pos; 5437 u32 cap, ctrl; 5438 5439 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5440 return -ENOTTY; 5441 5442 pos = dev->acs_cap; 5443 if (!pos) 5444 return -ENOTTY; 5445 5446 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5447 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5448 5449 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5450 5451 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5452 5453 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5454 5455 return 0; 5456 } 5457 5458 static const struct pci_dev_acs_ops { 5459 u16 vendor; 5460 u16 device; 5461 int (*enable_acs)(struct pci_dev *dev); 5462 int (*disable_acs_redir)(struct pci_dev *dev); 5463 } pci_dev_acs_ops[] = { 5464 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5465 .enable_acs = pci_quirk_enable_intel_pch_acs, 5466 }, 5467 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5468 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5469 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5470 }, 5471 }; 5472 5473 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5474 { 5475 const struct pci_dev_acs_ops *p; 5476 int i, ret; 5477 5478 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5479 p = &pci_dev_acs_ops[i]; 5480 if ((p->vendor == dev->vendor || 5481 p->vendor == (u16)PCI_ANY_ID) && 5482 (p->device == dev->device || 5483 p->device == (u16)PCI_ANY_ID) && 5484 p->enable_acs) { 5485 ret = p->enable_acs(dev); 5486 if (ret >= 0) 5487 return ret; 5488 } 5489 } 5490 5491 return -ENOTTY; 5492 } 5493 5494 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5495 { 5496 const struct pci_dev_acs_ops *p; 5497 int i, ret; 5498 5499 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5500 p = &pci_dev_acs_ops[i]; 5501 if ((p->vendor == dev->vendor || 5502 p->vendor == (u16)PCI_ANY_ID) && 5503 (p->device == dev->device || 5504 p->device == (u16)PCI_ANY_ID) && 5505 p->disable_acs_redir) { 5506 ret = p->disable_acs_redir(dev); 5507 if (ret >= 0) 5508 return ret; 5509 } 5510 } 5511 5512 return -ENOTTY; 5513 } 5514 5515 /* 5516 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5517 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5518 * Next Capability pointer in the MSI Capability Structure should point to 5519 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5520 * the list. 5521 */ 5522 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5523 { 5524 int pos, i = 0, ret; 5525 u8 next_cap; 5526 u16 reg16, *cap; 5527 struct pci_cap_saved_state *state; 5528 5529 /* Bail if the hardware bug is fixed */ 5530 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5531 return; 5532 5533 /* Bail if MSI Capability Structure is not found for some reason */ 5534 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5535 if (!pos) 5536 return; 5537 5538 /* 5539 * Bail if Next Capability pointer in the MSI Capability Structure 5540 * is not the expected incorrect 0x00. 5541 */ 5542 pci_read_config_byte(pdev, pos + 1, &next_cap); 5543 if (next_cap) 5544 return; 5545 5546 /* 5547 * PCIe Capability Structure is expected to be at 0x50 and should 5548 * terminate the list (Next Capability pointer is 0x00). Verify 5549 * Capability Id and Next Capability pointer is as expected. 5550 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5551 * to correctly set kernel data structures which have already been 5552 * set incorrectly due to the hardware bug. 5553 */ 5554 pos = 0x50; 5555 pci_read_config_word(pdev, pos, ®16); 5556 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5557 u32 status; 5558 #ifndef PCI_EXP_SAVE_REGS 5559 #define PCI_EXP_SAVE_REGS 7 5560 #endif 5561 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5562 5563 pdev->pcie_cap = pos; 5564 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5565 pdev->pcie_flags_reg = reg16; 5566 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5567 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5568 5569 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5570 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5571 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5572 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5573 5574 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5575 return; 5576 5577 /* Save PCIe cap */ 5578 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5579 if (!state) 5580 return; 5581 5582 state->cap.cap_nr = PCI_CAP_ID_EXP; 5583 state->cap.cap_extended = 0; 5584 state->cap.size = size; 5585 cap = (u16 *)&state->cap.data[0]; 5586 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5587 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5588 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5589 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5590 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5591 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5592 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5593 hlist_add_head(&state->next, &pdev->saved_cap_space); 5594 } 5595 } 5596 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5597 5598 /* 5599 * FLR may cause the following to devices to hang: 5600 * 5601 * AMD Starship/Matisse HD Audio Controller 0x1487 5602 * AMD Starship USB 3.0 Host Controller 0x148c 5603 * AMD Matisse USB 3.0 Host Controller 0x149c 5604 * AMD Neural Processing Unit 0x1502 0x17f0 5605 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5606 * Intel 82579V Gigabit Ethernet Controller 0x1503 5607 * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter 5608 */ 5609 static void quirk_no_flr(struct pci_dev *dev) 5610 { 5611 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5612 } 5613 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5614 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5615 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5616 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5617 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1502, quirk_no_flr); 5618 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x17f0, quirk_no_flr); 5619 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5620 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5621 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr); 5622 5623 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5624 static void quirk_no_flr_snet(struct pci_dev *dev) 5625 { 5626 if (dev->revision == 0x1) 5627 quirk_no_flr(dev); 5628 } 5629 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5630 5631 static void quirk_no_ext_tags(struct pci_dev *pdev) 5632 { 5633 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5634 5635 if (!bridge) 5636 return; 5637 5638 bridge->no_ext_tags = 1; 5639 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5640 5641 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5642 } 5643 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); 5644 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1005, quirk_no_ext_tags); 5645 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5646 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5647 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5648 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5649 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5650 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5652 5653 #ifdef CONFIG_PCI_ATS 5654 static void quirk_no_ats(struct pci_dev *pdev) 5655 { 5656 pci_info(pdev, "disabling ATS\n"); 5657 pdev->ats_cap = 0; 5658 } 5659 5660 /* 5661 * Some devices require additional driver setup to enable ATS. Don't use 5662 * ATS for those devices as ATS will be enabled before the driver has had a 5663 * chance to load and configure the device. 5664 */ 5665 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5666 { 5667 if (pdev->device == 0x15d8) { 5668 if (pdev->revision == 0xcf && 5669 pdev->subsystem_vendor == 0xea50 && 5670 (pdev->subsystem_device == 0xce19 || 5671 pdev->subsystem_device == 0xcc10 || 5672 pdev->subsystem_device == 0xcc08)) 5673 quirk_no_ats(pdev); 5674 } else { 5675 quirk_no_ats(pdev); 5676 } 5677 } 5678 5679 /* AMD Stoney platform GPU */ 5680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5681 /* AMD Iceland dGPU */ 5682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5683 /* AMD Navi10 dGPU */ 5684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5692 /* AMD Navi14 dGPU */ 5693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5697 /* AMD Raven platform iGPU */ 5698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5699 5700 /* 5701 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5702 * in ATS Invalidate Request message body. Disable ATS for those devices. 5703 */ 5704 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5705 { 5706 if (pdev->revision < 0x20) 5707 quirk_no_ats(pdev); 5708 } 5709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5712 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5715 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5718 5719 static bool quirk_nvidia_gpu_ats_required(struct pci_dev *pdev) 5720 { 5721 switch (pdev->device) { 5722 case 0x2e00 ... 0x2e3f: /* GB20B */ 5723 return true; 5724 } 5725 return false; 5726 } 5727 5728 static const struct pci_dev_ats_required { 5729 u16 vendor; 5730 u16 device; 5731 bool (*ats_required)(struct pci_dev *dev); 5732 } pci_dev_ats_required[] = { 5733 /* NVIDIA GPUs */ 5734 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, quirk_nvidia_gpu_ats_required }, 5735 /* NVIDIA CX10 Family NVlink-C2C */ 5736 { PCI_VENDOR_ID_MELLANOX, 0x2101, NULL }, 5737 { 0 } 5738 }; 5739 5740 /* 5741 * Some NVIDIA devices do not implement CXL config space, but present as PCIe 5742 * devices that can issue CXL-like cache operations like CXL.cache. Thus, they 5743 * require ATS to obtain host physical addresses, like pci_cxl_ats_required(). 5744 */ 5745 bool pci_dev_specific_ats_required(struct pci_dev *pdev) 5746 { 5747 const struct pci_dev_ats_required *i; 5748 5749 for (i = pci_dev_ats_required; i->vendor; i++) { 5750 if (i->vendor != pdev->vendor) 5751 continue; 5752 if (i->ats_required && i->ats_required(pdev)) 5753 return true; 5754 if (!i->ats_required && i->device == pdev->device) 5755 return true; 5756 } 5757 5758 return false; 5759 } 5760 #endif /* CONFIG_PCI_ATS */ 5761 5762 /* Freescale PCIe doesn't support MSI in RC mode */ 5763 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5764 { 5765 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5766 pdev->no_msi = 1; 5767 } 5768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5769 5770 /* 5771 * Although not allowed by the spec, some multi-function devices have 5772 * dependencies of one function (consumer) on another (supplier). For the 5773 * consumer to work in D0, the supplier must also be in D0. Create a 5774 * device link from the consumer to the supplier to enforce this 5775 * dependency. Runtime PM is allowed by default on the consumer to prevent 5776 * it from permanently keeping the supplier awake. 5777 */ 5778 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5779 unsigned int supplier, unsigned int class, 5780 unsigned int class_shift) 5781 { 5782 struct pci_dev *supplier_pdev; 5783 5784 if (PCI_FUNC(pdev->devfn) != consumer) 5785 return; 5786 5787 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5788 pdev->bus->number, 5789 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5790 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5791 pci_dev_put(supplier_pdev); 5792 return; 5793 } 5794 5795 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5796 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5797 pci_info(pdev, "D0 power state depends on %s\n", 5798 pci_name(supplier_pdev)); 5799 else 5800 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5801 pci_name(supplier_pdev)); 5802 5803 pm_runtime_allow(&pdev->dev); 5804 pci_dev_put(supplier_pdev); 5805 } 5806 5807 /* 5808 * Create device link for GPUs with integrated HDA controller for streaming 5809 * audio to attached displays. 5810 */ 5811 static void quirk_gpu_hda(struct pci_dev *hda) 5812 { 5813 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5814 } 5815 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5816 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5817 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5818 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5819 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5820 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5821 5822 /* 5823 * Create device link for GPUs with integrated USB xHCI Host 5824 * controller to VGA. 5825 */ 5826 static void quirk_gpu_usb(struct pci_dev *usb) 5827 { 5828 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5829 } 5830 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5831 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5832 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5833 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5834 5835 /* 5836 * Create device link for GPUs with integrated Type-C UCSI controller 5837 * to VGA. Currently there is no class code defined for UCSI device over PCI 5838 * so using UNKNOWN class for now and it will be updated when UCSI 5839 * over PCI gets a class code. 5840 */ 5841 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5842 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5843 { 5844 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5845 } 5846 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5847 PCI_CLASS_SERIAL_UNKNOWN, 8, 5848 quirk_gpu_usb_typec_ucsi); 5849 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5850 PCI_CLASS_SERIAL_UNKNOWN, 8, 5851 quirk_gpu_usb_typec_ucsi); 5852 5853 /* 5854 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5855 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5856 */ 5857 static void quirk_nvidia_hda(struct pci_dev *gpu) 5858 { 5859 u8 hdr_type; 5860 u32 val; 5861 5862 /* There was no integrated HDA controller before MCP89 */ 5863 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5864 return; 5865 5866 /* Bit 25 at offset 0x488 enables the HDA controller */ 5867 pci_read_config_dword(gpu, 0x488, &val); 5868 if (val & BIT(25)) 5869 return; 5870 5871 pci_info(gpu, "Enabling HDA controller\n"); 5872 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5873 5874 /* The GPU becomes a multi-function device when the HDA is enabled */ 5875 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5876 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 5877 } 5878 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5879 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5880 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5881 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5882 5883 /* 5884 * Some IDT switches incorrectly flag an ACS Source Validation error on 5885 * completions for config read requests even though PCIe r7.0, sec 5886 * 6.12.1.1, says that completions are never affected by ACS Source 5887 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5888 * 5889 * Item #36 - Downstream port applies ACS Source Validation to Completions 5890 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5891 * completions are never affected by ACS Source Validation. However, 5892 * completions received by a downstream port of the PCIe switch from a 5893 * device that has not yet captured a PCIe bus number are incorrectly 5894 * dropped by ACS Source Validation by the switch downstream port. 5895 * 5896 * The workaround suggested by IDT is to issue a config write to the 5897 * downstream device before issuing the first config read. This allows the 5898 * downstream device to capture its bus and device numbers (see PCIe r7.0, 5899 * sec 2.2.9.1), thus avoiding the ACS error on the completion. 5900 * 5901 * However, we don't know when the device is ready to accept the config 5902 * write, and the issue affects resets of the switch as well as enumeration, 5903 * so disable use of ACS SV for these devices altogether. 5904 */ 5905 void pci_disable_broken_acs_cap(struct pci_dev *pdev) 5906 { 5907 if (pdev->vendor == PCI_VENDOR_ID_IDT && 5908 (pdev->device == 0x80b5 || pdev->device == 0x8090)) { 5909 pci_info(pdev, "Disabling broken ACS SV; downstream device isolation reduced\n"); 5910 pdev->acs_capabilities &= ~PCI_ACS_SV; 5911 } 5912 } 5913 5914 /* 5915 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5916 * NT endpoints via the internal switch fabric. These IDs replace the 5917 * originating Requester ID TLPs which access host memory on peer NTB 5918 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5919 * to permit access when the IOMMU is turned on. 5920 */ 5921 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5922 { 5923 void __iomem *mmio; 5924 struct ntb_info_regs __iomem *mmio_ntb; 5925 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5926 u64 partition_map; 5927 u8 partition; 5928 int pp; 5929 5930 if (pci_enable_device(pdev)) { 5931 pci_err(pdev, "Cannot enable Switchtec device\n"); 5932 return; 5933 } 5934 5935 mmio = pci_iomap(pdev, 0, 0); 5936 if (mmio == NULL) { 5937 pci_disable_device(pdev); 5938 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5939 return; 5940 } 5941 5942 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5943 5944 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5945 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5946 5947 partition = ioread8(&mmio_ntb->partition_id); 5948 5949 partition_map = ioread32(&mmio_ntb->ep_map); 5950 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5951 partition_map &= ~(1ULL << partition); 5952 5953 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5954 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5955 u32 table_sz = 0; 5956 int te; 5957 5958 if (!(partition_map & (1ULL << pp))) 5959 continue; 5960 5961 pci_dbg(pdev, "Processing partition %d\n", pp); 5962 5963 mmio_peer_ctrl = &mmio_ctrl[pp]; 5964 5965 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5966 if (!table_sz) { 5967 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5968 continue; 5969 } 5970 5971 if (table_sz > 512) { 5972 pci_warn(pdev, 5973 "Invalid Switchtec partition %d table_sz %d\n", 5974 pp, table_sz); 5975 continue; 5976 } 5977 5978 for (te = 0; te < table_sz; te++) { 5979 u32 rid_entry; 5980 u8 devfn; 5981 5982 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5983 devfn = (rid_entry >> 1) & 0xFF; 5984 pci_dbg(pdev, 5985 "Aliasing Partition %d Proxy ID %02x.%d\n", 5986 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5987 pci_add_dma_alias(pdev, devfn, 1); 5988 } 5989 } 5990 5991 pci_iounmap(pdev, mmio); 5992 pci_disable_device(pdev); 5993 } 5994 #define SWITCHTEC_QUIRK(vid) \ 5995 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5996 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5997 5998 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5999 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 6000 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 6001 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 6002 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 6003 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 6004 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 6005 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 6006 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 6007 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 6008 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 6009 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 6010 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 6011 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 6012 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 6013 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 6014 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 6015 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 6016 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 6017 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 6018 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 6019 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 6020 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 6021 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 6022 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 6023 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 6024 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 6025 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 6026 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 6027 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 6028 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 6029 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 6030 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 6031 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 6032 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 6033 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 6034 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 6035 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 6036 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 6037 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 6038 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 6039 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 6040 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 6041 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 6042 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 6043 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 6044 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 6045 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 6046 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 6047 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 6048 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 6049 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 6050 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 6051 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 6052 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 6053 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 6054 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 6055 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 6056 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 6057 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 6058 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 6059 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 6060 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 6061 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 6062 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 6063 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 6064 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 6065 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 6066 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 6067 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 6068 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 6069 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 6070 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 6071 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 6072 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 6073 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 6074 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 6075 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 6076 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 6077 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 6078 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 6079 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 6080 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 6081 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 6082 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 6083 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 6084 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 6085 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 6086 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 6087 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 6088 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 6089 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 6090 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 6091 6092 #define SWITCHTEC_PCI100X_QUIRK(vid) \ 6093 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_EFAR, vid, \ 6094 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 6095 SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */ 6096 SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */ 6097 SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */ 6098 SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */ 6099 SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */ 6100 SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */ 6101 6102 6103 /* 6104 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 6105 * These IDs are used to forward responses to the originator on the other 6106 * side of the NTB. Alias all possible IDs to the NTB to permit access when 6107 * the IOMMU is turned on. 6108 */ 6109 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 6110 { 6111 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 6112 /* PLX NTB may use all 256 devfns */ 6113 pci_add_dma_alias(pdev, 0, 256); 6114 } 6115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 6116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 6117 6118 /* 6119 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 6120 * not always reset the secondary Nvidia GPU between reboots if the system 6121 * is configured to use Hybrid Graphics mode. This results in the GPU 6122 * being left in whatever state it was in during the *previous* boot, which 6123 * causes spurious interrupts from the GPU, which in turn causes us to 6124 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 6125 * this also completely breaks nouveau. 6126 * 6127 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 6128 * clean state and fixes all these issues. 6129 * 6130 * When the machine is configured in Dedicated display mode, the issue 6131 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 6132 * mode, so we can detect that and avoid resetting it. 6133 */ 6134 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 6135 { 6136 void __iomem *map; 6137 int ret; 6138 6139 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 6140 pdev->subsystem_device != 0x222e || 6141 !pci_reset_supported(pdev)) 6142 return; 6143 6144 if (pci_enable_device_mem(pdev)) 6145 return; 6146 6147 /* 6148 * Based on nvkm_device_ctor() in 6149 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 6150 */ 6151 map = pci_iomap(pdev, 0, 0x23000); 6152 if (!map) { 6153 pci_err(pdev, "Can't map MMIO space\n"); 6154 goto out_disable; 6155 } 6156 6157 /* 6158 * Make sure the GPU looks like it's been POSTed before resetting 6159 * it. 6160 */ 6161 if (ioread32(map + 0x2240c) & 0x2) { 6162 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 6163 ret = pci_reset_bus(pdev); 6164 if (ret < 0) 6165 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 6166 } 6167 6168 iounmap(map); 6169 out_disable: 6170 pci_disable_device(pdev); 6171 } 6172 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6173 PCI_CLASS_DISPLAY_VGA, 8, 6174 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6175 6176 /* 6177 * Device [1b21:2142] 6178 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6179 */ 6180 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6181 { 6182 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6183 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6184 } 6185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6186 6187 /* 6188 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6189 * 6190 * These devices advertise PME# support in all power states but don't 6191 * reliably assert it. 6192 * 6193 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6194 * says "The MSI Function is not implemented on this device" in chapters 6195 * 7.3.27, 7.3.29-7.3.31. 6196 */ 6197 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6198 { 6199 #ifdef CONFIG_PCI_MSI 6200 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6201 dev->no_msi = 1; 6202 #endif 6203 pci_info(dev, "PME# is unreliable, disabling it\n"); 6204 dev->pme_support = 0; 6205 } 6206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6208 6209 static void apex_pci_fixup_class(struct pci_dev *pdev) 6210 { 6211 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6212 } 6213 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6214 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6215 6216 /* 6217 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6218 * ACS P2P Request Redirect is not functional 6219 * 6220 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6221 * between upstream and downstream ports, packets are queued in an internal 6222 * buffer until CPLD packet. The workaround is to use the switch in store and 6223 * forward mode. 6224 */ 6225 #define PI7C9X2Gxxx_MODE_REG 0x74 6226 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6227 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6228 { 6229 struct pci_dev *upstream; 6230 u16 val; 6231 6232 /* Downstream ports only */ 6233 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6234 return; 6235 6236 /* Check for ACS P2P Request Redirect use */ 6237 if (!pdev->acs_cap) 6238 return; 6239 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6240 if (!(val & PCI_ACS_RR)) 6241 return; 6242 6243 upstream = pci_upstream_bridge(pdev); 6244 if (!upstream) 6245 return; 6246 6247 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6248 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6249 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6250 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6251 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6252 } 6253 } 6254 /* 6255 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6256 * ACS configuration changes or switch mode is reset 6257 */ 6258 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6259 pci_fixup_pericom_acs_store_forward); 6260 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6261 pci_fixup_pericom_acs_store_forward); 6262 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6263 pci_fixup_pericom_acs_store_forward); 6264 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6265 pci_fixup_pericom_acs_store_forward); 6266 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6267 pci_fixup_pericom_acs_store_forward); 6268 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6269 pci_fixup_pericom_acs_store_forward); 6270 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0xb404, 6271 pci_fixup_pericom_acs_store_forward); 6272 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0xb404, 6273 pci_fixup_pericom_acs_store_forward); 6274 6275 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6276 { 6277 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6278 } 6279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6280 6281 static void rom_bar_overlap_defect(struct pci_dev *dev) 6282 { 6283 pci_info(dev, "working around ROM BAR overlap defect\n"); 6284 dev->rom_bar_overlap = 1; 6285 } 6286 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6287 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6288 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6289 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6290 6291 #ifdef CONFIG_PCIEASPM 6292 /* 6293 * Several Intel DG2 graphics devices advertise that they can only tolerate 6294 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6295 * from being enabled. But in fact these devices can tolerate unlimited 6296 * latency. Override their Device Capabilities value to allow ASPM L1 to 6297 * be enabled. 6298 */ 6299 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6300 { 6301 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6302 6303 if (l1_lat < 7) { 6304 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6305 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6306 l1_lat); 6307 } 6308 } 6309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6335 #endif 6336 6337 #ifdef CONFIG_PCIE_DPC 6338 /* 6339 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6340 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6341 * Ports. 6342 */ 6343 static void dpc_log_size(struct pci_dev *dev) 6344 { 6345 u16 dpc, val; 6346 6347 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6348 if (!dpc) 6349 return; 6350 6351 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6352 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6353 return; 6354 6355 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6356 pci_info(dev, "Overriding RP PIO Log Size to %d\n", 6357 PCIE_STD_NUM_TLP_HEADERLOG); 6358 dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG; 6359 } 6360 } 6361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size); 6378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); 6379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); 6380 #endif 6381 6382 /* 6383 * For a PCI device with multiple downstream devices, its driver may use 6384 * a flattened device tree to describe the downstream devices. 6385 * To overlay the flattened device tree, the PCI device and all its ancestor 6386 * devices need to have device tree nodes on system base device tree. Thus, 6387 * before driver probing, it might need to add a device tree node as the final 6388 * fixup. 6389 */ 6390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); 6394 6395 /* 6396 * Devices known to require a longer delay before first config space access 6397 * after reset recovery or resume from D3cold: 6398 * 6399 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6400 */ 6401 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6402 { 6403 pdev->d3cold_delay = 1000; 6404 } 6405 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6406 6407 #ifdef CONFIG_PCIEAER 6408 static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) 6409 { 6410 struct pci_dev *parent = pci_upstream_bridge(pdev); 6411 u32 val; 6412 6413 if (!parent || !parent->aer_cap) 6414 return; 6415 6416 pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", 6417 pci_name(pdev)); 6418 6419 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); 6420 val |= PCI_ERR_COR_REP_TIMER; 6421 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); 6422 } 6423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); 6424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); 6425 #endif 6426