1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 */ 13 14 #include <linux/types.h> 15 #include <linux/kernel.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/acpi.h> 21 #include <linux/kallsyms.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <linux/mm.h> 28 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 29 #include "pci.h" 30 31 /* 32 * Decoding should be disabled for a PCI device during BAR sizing to avoid 33 * conflict. But doing so may cause problems on host bridge and perhaps other 34 * key system devices. For devices that need to have mmio decoding always-on, 35 * we need to set the dev->mmio_always_on bit. 36 */ 37 static void quirk_mmio_always_on(struct pci_dev *dev) 38 { 39 dev->mmio_always_on = 1; 40 } 41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 43 44 /* The Mellanox Tavor device gives false positive parity errors 45 * Mark this device with a broken_parity_status, to allow 46 * PCI scanning code to "skip" this now blacklisted device. 47 */ 48 static void quirk_mellanox_tavor(struct pci_dev *dev) 49 { 50 dev->broken_parity_status = 1; /* This device gives false positives */ 51 } 52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 54 55 /* Deal with broken BIOSes that neglect to enable passive release, 56 which can cause problems in combination with the 82441FX/PPro MTRRs */ 57 static void quirk_passive_release(struct pci_dev *dev) 58 { 59 struct pci_dev *d = NULL; 60 unsigned char dlc; 61 62 /* We have to make sure a particular bit is set in the PIIX3 63 ISA bridge, so we have to go out and find it. */ 64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 65 pci_read_config_byte(d, 0x82, &dlc); 66 if (!(dlc & 1<<1)) { 67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 68 dlc |= 1<<1; 69 pci_write_config_byte(d, 0x82, dlc); 70 } 71 } 72 } 73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 75 76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 77 but VIA don't answer queries. If you happen to have good contacts at VIA 78 ask them for me please -- Alan 79 80 This appears to be BIOS not version dependent. So presumably there is a 81 chipset level fix */ 82 83 static void quirk_isa_dma_hangs(struct pci_dev *dev) 84 { 85 if (!isa_dma_bridge_buggy) { 86 isa_dma_bridge_buggy = 1; 87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 88 } 89 } 90 /* 91 * Its not totally clear which chipsets are the problematic ones 92 * We know 82C586 and 82C596 variants are affected. 93 */ 94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 101 102 /* 103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 104 * for some HT machines to use C4 w/o hanging. 105 */ 106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 107 { 108 u32 pmbase; 109 u16 pm1a; 110 111 pci_read_config_dword(dev, 0x40, &pmbase); 112 pmbase = pmbase & 0xff80; 113 pm1a = inw(pmbase); 114 115 if (pm1a & 0x10) { 116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 117 outw(0x10, pmbase); 118 } 119 } 120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 121 122 /* 123 * Chipsets where PCI->PCI transfers vanish or hang 124 */ 125 static void quirk_nopcipci(struct pci_dev *dev) 126 { 127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 129 pci_pci_problems |= PCIPCI_FAIL; 130 } 131 } 132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 134 135 static void quirk_nopciamd(struct pci_dev *dev) 136 { 137 u8 rev; 138 pci_read_config_byte(dev, 0x08, &rev); 139 if (rev == 0x13) { 140 /* Erratum 24 */ 141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 142 pci_pci_problems |= PCIAGP_FAIL; 143 } 144 } 145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 146 147 /* 148 * Triton requires workarounds to be used by the drivers 149 */ 150 static void quirk_triton(struct pci_dev *dev) 151 { 152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 154 pci_pci_problems |= PCIPCI_TRITON; 155 } 156 } 157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 161 162 /* 163 * VIA Apollo KT133 needs PCI latency patch 164 * Made according to a windows driver based patch by George E. Breese 165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 166 * and http://www.georgebreese.com/net/software/#PCI 167 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 168 * the info on which Mr Breese based his work. 169 * 170 * Updated based on further information from the site and also on 171 * information provided by VIA 172 */ 173 static void quirk_vialatency(struct pci_dev *dev) 174 { 175 struct pci_dev *p; 176 u8 busarb; 177 /* Ok we have a potential problem chipset here. Now see if we have 178 a buggy southbridge */ 179 180 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 181 if (p != NULL) { 182 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 183 /* Check for buggy part revisions */ 184 if (p->revision < 0x40 || p->revision > 0x42) 185 goto exit; 186 } else { 187 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 188 if (p == NULL) /* No problem parts */ 189 goto exit; 190 /* Check for buggy part revisions */ 191 if (p->revision < 0x10 || p->revision > 0x12) 192 goto exit; 193 } 194 195 /* 196 * Ok we have the problem. Now set the PCI master grant to 197 * occur every master grant. The apparent bug is that under high 198 * PCI load (quite common in Linux of course) you can get data 199 * loss when the CPU is held off the bus for 3 bus master requests 200 * This happens to include the IDE controllers.... 201 * 202 * VIA only apply this fix when an SB Live! is present but under 203 * both Linux and Windows this isn't enough, and we have seen 204 * corruption without SB Live! but with things like 3 UDMA IDE 205 * controllers. So we ignore that bit of the VIA recommendation.. 206 */ 207 208 pci_read_config_byte(dev, 0x76, &busarb); 209 /* Set bit 4 and bi 5 of byte 76 to 0x01 210 "Master priority rotation on every PCI master grant */ 211 busarb &= ~(1<<5); 212 busarb |= (1<<4); 213 pci_write_config_byte(dev, 0x76, busarb); 214 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 215 exit: 216 pci_dev_put(p); 217 } 218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 221 /* Must restore this on a resume from RAM */ 222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 225 226 /* 227 * VIA Apollo VP3 needs ETBF on BT848/878 228 */ 229 static void quirk_viaetbf(struct pci_dev *dev) 230 { 231 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 232 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 233 pci_pci_problems |= PCIPCI_VIAETBF; 234 } 235 } 236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 237 238 static void quirk_vsfx(struct pci_dev *dev) 239 { 240 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 242 pci_pci_problems |= PCIPCI_VSFX; 243 } 244 } 245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 246 247 /* 248 * Ali Magik requires workarounds to be used by the drivers 249 * that DMA to AGP space. Latency must be set to 0xA and triton 250 * workaround applied too 251 * [Info kindly provided by ALi] 252 */ 253 static void quirk_alimagik(struct pci_dev *dev) 254 { 255 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 256 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 257 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 258 } 259 } 260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 262 263 /* 264 * Natoma has some interesting boundary conditions with Zoran stuff 265 * at least 266 */ 267 static void quirk_natoma(struct pci_dev *dev) 268 { 269 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 271 pci_pci_problems |= PCIPCI_NATOMA; 272 } 273 } 274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 280 281 /* 282 * This chip can cause PCI parity errors if config register 0xA0 is read 283 * while DMAs are occurring. 284 */ 285 static void quirk_citrine(struct pci_dev *dev) 286 { 287 dev->cfg_size = 0xA0; 288 } 289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 290 291 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 292 static void quirk_extend_bar_to_page(struct pci_dev *dev) 293 { 294 int i; 295 296 for (i = 0; i < PCI_STD_RESOURCE_END; i++) { 297 struct resource *r = &dev->resource[i]; 298 299 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 300 r->end = PAGE_SIZE - 1; 301 r->start = 0; 302 r->flags |= IORESOURCE_UNSET; 303 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", 304 i, r); 305 } 306 } 307 } 308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 309 310 /* 311 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 312 * If it's needed, re-allocate the region. 313 */ 314 static void quirk_s3_64M(struct pci_dev *dev) 315 { 316 struct resource *r = &dev->resource[0]; 317 318 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 319 r->flags |= IORESOURCE_UNSET; 320 r->start = 0; 321 r->end = 0x3ffffff; 322 } 323 } 324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 326 327 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 328 const char *name) 329 { 330 u32 region; 331 struct pci_bus_region bus_region; 332 struct resource *res = dev->resource + pos; 333 334 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 335 336 if (!region) 337 return; 338 339 res->name = pci_name(dev); 340 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 341 res->flags |= 342 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 343 region &= ~(size - 1); 344 345 /* Convert from PCI bus to resource space */ 346 bus_region.start = region; 347 bus_region.end = region + size - 1; 348 pcibios_bus_to_resource(dev->bus, res, &bus_region); 349 350 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 351 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 352 } 353 354 /* 355 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 356 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 357 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 358 * (which conflicts w/ BAR1's memory range). 359 * 360 * CS553x's ISA PCI BARs may also be read-only (ref: 361 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 362 */ 363 static void quirk_cs5536_vsa(struct pci_dev *dev) 364 { 365 static char *name = "CS5536 ISA bridge"; 366 367 if (pci_resource_len(dev, 0) != 8) { 368 quirk_io(dev, 0, 8, name); /* SMB */ 369 quirk_io(dev, 1, 256, name); /* GPIO */ 370 quirk_io(dev, 2, 64, name); /* MFGPT */ 371 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", 372 name); 373 } 374 } 375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 376 377 static void quirk_io_region(struct pci_dev *dev, int port, 378 unsigned size, int nr, const char *name) 379 { 380 u16 region; 381 struct pci_bus_region bus_region; 382 struct resource *res = dev->resource + nr; 383 384 pci_read_config_word(dev, port, ®ion); 385 region &= ~(size - 1); 386 387 if (!region) 388 return; 389 390 res->name = pci_name(dev); 391 res->flags = IORESOURCE_IO; 392 393 /* Convert from PCI bus to resource space */ 394 bus_region.start = region; 395 bus_region.end = region + size - 1; 396 pcibios_bus_to_resource(dev->bus, res, &bus_region); 397 398 if (!pci_claim_resource(dev, nr)) 399 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); 400 } 401 402 /* 403 * ATI Northbridge setups MCE the processor if you even 404 * read somewhere between 0x3b0->0x3bb or read 0x3d3 405 */ 406 static void quirk_ati_exploding_mce(struct pci_dev *dev) 407 { 408 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 409 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 410 request_region(0x3b0, 0x0C, "RadeonIGP"); 411 request_region(0x3d3, 0x01, "RadeonIGP"); 412 } 413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 414 415 /* 416 * In the AMD NL platform, this device ([1022:7912]) has a class code of 417 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 418 * claim it. 419 * But the dwc3 driver is a more specific driver for this device, and we'd 420 * prefer to use it instead of xhci. To prevent xhci from claiming the 421 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 422 * defines as "USB device (not host controller)". The dwc3 driver can then 423 * claim it based on its Vendor and Device ID. 424 */ 425 static void quirk_amd_nl_class(struct pci_dev *pdev) 426 { 427 /* 428 * Use 'USB Device' (0x0c03fe) instead of PCI header provided 429 */ 430 pdev->class = 0x0c03fe; 431 } 432 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 433 quirk_amd_nl_class); 434 435 /* 436 * Let's make the southbridge information explicit instead 437 * of having to worry about people probing the ACPI areas, 438 * for example.. (Yes, it happens, and if you read the wrong 439 * ACPI register it will put the machine to sleep with no 440 * way of waking it up again. Bummer). 441 * 442 * ALI M7101: Two IO regions pointed to by words at 443 * 0xE0 (64 bytes of ACPI registers) 444 * 0xE2 (32 bytes of SMB registers) 445 */ 446 static void quirk_ali7101_acpi(struct pci_dev *dev) 447 { 448 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 449 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 450 } 451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 452 453 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 454 { 455 u32 devres; 456 u32 mask, size, base; 457 458 pci_read_config_dword(dev, port, &devres); 459 if ((devres & enable) != enable) 460 return; 461 mask = (devres >> 16) & 15; 462 base = devres & 0xffff; 463 size = 16; 464 for (;;) { 465 unsigned bit = size >> 1; 466 if ((bit & mask) == bit) 467 break; 468 size = bit; 469 } 470 /* 471 * For now we only print it out. Eventually we'll want to 472 * reserve it (at least if it's in the 0x1000+ range), but 473 * let's get enough confirmation reports first. 474 */ 475 base &= -size; 476 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, 477 base + size - 1); 478 } 479 480 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 481 { 482 u32 devres; 483 u32 mask, size, base; 484 485 pci_read_config_dword(dev, port, &devres); 486 if ((devres & enable) != enable) 487 return; 488 base = devres & 0xffff0000; 489 mask = (devres & 0x3f) << 16; 490 size = 128 << 16; 491 for (;;) { 492 unsigned bit = size >> 1; 493 if ((bit & mask) == bit) 494 break; 495 size = bit; 496 } 497 /* 498 * For now we only print it out. Eventually we'll want to 499 * reserve it, but let's get enough confirmation reports first. 500 */ 501 base &= -size; 502 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, 503 base + size - 1); 504 } 505 506 /* 507 * PIIX4 ACPI: Two IO regions pointed to by longwords at 508 * 0x40 (64 bytes of ACPI registers) 509 * 0x90 (16 bytes of SMB registers) 510 * and a few strange programmable PIIX4 device resources. 511 */ 512 static void quirk_piix4_acpi(struct pci_dev *dev) 513 { 514 u32 res_a; 515 516 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 517 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 518 519 /* Device resource A has enables for some of the other ones */ 520 pci_read_config_dword(dev, 0x5c, &res_a); 521 522 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 523 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 524 525 /* Device resource D is just bitfields for static resources */ 526 527 /* Device 12 enabled? */ 528 if (res_a & (1 << 29)) { 529 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 530 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 531 } 532 /* Device 13 enabled? */ 533 if (res_a & (1 << 30)) { 534 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 535 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 536 } 537 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 538 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 539 } 540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 541 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 542 543 #define ICH_PMBASE 0x40 544 #define ICH_ACPI_CNTL 0x44 545 #define ICH4_ACPI_EN 0x10 546 #define ICH6_ACPI_EN 0x80 547 #define ICH4_GPIOBASE 0x58 548 #define ICH4_GPIO_CNTL 0x5c 549 #define ICH4_GPIO_EN 0x10 550 #define ICH6_GPIOBASE 0x48 551 #define ICH6_GPIO_CNTL 0x4c 552 #define ICH6_GPIO_EN 0x10 553 554 /* 555 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 556 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 557 * 0x58 (64 bytes of GPIO I/O space) 558 */ 559 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 560 { 561 u8 enable; 562 563 /* 564 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 565 * with low legacy (and fixed) ports. We don't know the decoding 566 * priority and can't tell whether the legacy device or the one created 567 * here is really at that address. This happens on boards with broken 568 * BIOSes. 569 */ 570 571 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 572 if (enable & ICH4_ACPI_EN) 573 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 574 "ICH4 ACPI/GPIO/TCO"); 575 576 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 577 if (enable & ICH4_GPIO_EN) 578 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 579 "ICH4 GPIO"); 580 } 581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 582 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 584 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 591 592 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 593 { 594 u8 enable; 595 596 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 597 if (enable & ICH6_ACPI_EN) 598 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 599 "ICH6 ACPI/GPIO/TCO"); 600 601 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 602 if (enable & ICH6_GPIO_EN) 603 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 604 "ICH6 GPIO"); 605 } 606 607 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 608 { 609 u32 val; 610 u32 size, base; 611 612 pci_read_config_dword(dev, reg, &val); 613 614 /* Enabled? */ 615 if (!(val & 1)) 616 return; 617 base = val & 0xfffc; 618 if (dynsize) { 619 /* 620 * This is not correct. It is 16, 32 or 64 bytes depending on 621 * register D31:F0:ADh bits 5:4. 622 * 623 * But this gets us at least _part_ of it. 624 */ 625 size = 16; 626 } else { 627 size = 128; 628 } 629 base &= ~(size-1); 630 631 /* Just print it out for now. We should reserve it after more debugging */ 632 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 633 } 634 635 static void quirk_ich6_lpc(struct pci_dev *dev) 636 { 637 /* Shared ACPI/GPIO decode with all ICH6+ */ 638 ich6_lpc_acpi_gpio(dev); 639 640 /* ICH6-specific generic IO decode */ 641 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 642 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 643 } 644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 646 647 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 648 { 649 u32 val; 650 u32 mask, base; 651 652 pci_read_config_dword(dev, reg, &val); 653 654 /* Enabled? */ 655 if (!(val & 1)) 656 return; 657 658 /* 659 * IO base in bits 15:2, mask in bits 23:18, both 660 * are dword-based 661 */ 662 base = val & 0xfffc; 663 mask = (val >> 16) & 0xfc; 664 mask |= 3; 665 666 /* Just print it out for now. We should reserve it after more debugging */ 667 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 668 } 669 670 /* ICH7-10 has the same common LPC generic IO decode registers */ 671 static void quirk_ich7_lpc(struct pci_dev *dev) 672 { 673 /* We share the common ACPI/GPIO decode with ICH6 */ 674 ich6_lpc_acpi_gpio(dev); 675 676 /* And have 4 ICH7+ generic decodes */ 677 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 678 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 679 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 680 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 681 } 682 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 685 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 686 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 687 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 690 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 691 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 692 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 693 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 694 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 695 696 /* 697 * VIA ACPI: One IO region pointed to by longword at 698 * 0x48 or 0x20 (256 bytes of ACPI registers) 699 */ 700 static void quirk_vt82c586_acpi(struct pci_dev *dev) 701 { 702 if (dev->revision & 0x10) 703 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 704 "vt82c586 ACPI"); 705 } 706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 707 708 /* 709 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 710 * 0x48 (256 bytes of ACPI registers) 711 * 0x70 (128 bytes of hardware monitoring register) 712 * 0x90 (16 bytes of SMB registers) 713 */ 714 static void quirk_vt82c686_acpi(struct pci_dev *dev) 715 { 716 quirk_vt82c586_acpi(dev); 717 718 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 719 "vt82c686 HW-mon"); 720 721 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 722 } 723 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 724 725 /* 726 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 727 * 0x88 (128 bytes of power management registers) 728 * 0xd0 (16 bytes of SMB registers) 729 */ 730 static void quirk_vt8235_acpi(struct pci_dev *dev) 731 { 732 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 733 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 734 } 735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 736 737 /* 738 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 739 * Disable fast back-to-back on the secondary bus segment 740 */ 741 static void quirk_xio2000a(struct pci_dev *dev) 742 { 743 struct pci_dev *pdev; 744 u16 command; 745 746 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 747 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 748 pci_read_config_word(pdev, PCI_COMMAND, &command); 749 if (command & PCI_COMMAND_FAST_BACK) 750 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 751 } 752 } 753 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 754 quirk_xio2000a); 755 756 #ifdef CONFIG_X86_IO_APIC 757 758 #include <asm/io_apic.h> 759 760 /* 761 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 762 * devices to the external APIC. 763 * 764 * TODO: When we have device-specific interrupt routers, 765 * this code will go away from quirks. 766 */ 767 static void quirk_via_ioapic(struct pci_dev *dev) 768 { 769 u8 tmp; 770 771 if (nr_ioapics < 1) 772 tmp = 0; /* nothing routed to external APIC */ 773 else 774 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 775 776 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 777 tmp == 0 ? "Disa" : "Ena"); 778 779 /* Offset 0x58: External APIC IRQ output control */ 780 pci_write_config_byte(dev, 0x58, tmp); 781 } 782 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 783 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 784 785 /* 786 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 787 * This leads to doubled level interrupt rates. 788 * Set this bit to get rid of cycle wastage. 789 * Otherwise uncritical. 790 */ 791 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 792 { 793 u8 misc_control2; 794 #define BYPASS_APIC_DEASSERT 8 795 796 pci_read_config_byte(dev, 0x5B, &misc_control2); 797 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 798 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 799 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 800 } 801 } 802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 803 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 804 805 /* 806 * The AMD io apic can hang the box when an apic irq is masked. 807 * We check all revs >= B0 (yet not in the pre production!) as the bug 808 * is currently marked NoFix 809 * 810 * We have multiple reports of hangs with this chipset that went away with 811 * noapic specified. For the moment we assume it's the erratum. We may be wrong 812 * of course. However the advice is demonstrably good even if so.. 813 */ 814 static void quirk_amd_ioapic(struct pci_dev *dev) 815 { 816 if (dev->revision >= 0x02) { 817 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 818 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 819 } 820 } 821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 822 823 static void quirk_ioapic_rmw(struct pci_dev *dev) 824 { 825 if (dev->devfn == 0 && dev->bus->number == 0) 826 sis_apic_bug = 1; 827 } 828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); 829 #endif /* CONFIG_X86_IO_APIC */ 830 831 /* 832 * Some settings of MMRBC can lead to data corruption so block changes. 833 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 834 */ 835 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 836 { 837 if (dev->subordinate && dev->revision <= 0x12) { 838 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 839 dev->revision); 840 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 841 } 842 } 843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 844 845 /* 846 * FIXME: it is questionable that quirk_via_acpi 847 * is needed. It shows up as an ISA bridge, and does not 848 * support the PCI_INTERRUPT_LINE register at all. Therefore 849 * it seems like setting the pci_dev's 'irq' to the 850 * value of the ACPI SCI interrupt is only done for convenience. 851 * -jgarzik 852 */ 853 static void quirk_via_acpi(struct pci_dev *d) 854 { 855 /* 856 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 857 */ 858 u8 irq; 859 pci_read_config_byte(d, 0x42, &irq); 860 irq &= 0xf; 861 if (irq && (irq != 2)) 862 d->irq = irq; 863 } 864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 866 867 868 /* 869 * VIA bridges which have VLink 870 */ 871 872 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 873 874 static void quirk_via_bridge(struct pci_dev *dev) 875 { 876 /* See what bridge we have and find the device ranges */ 877 switch (dev->device) { 878 case PCI_DEVICE_ID_VIA_82C686: 879 /* The VT82C686 is special, it attaches to PCI and can have 880 any device number. All its subdevices are functions of 881 that single device. */ 882 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 883 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 884 break; 885 case PCI_DEVICE_ID_VIA_8237: 886 case PCI_DEVICE_ID_VIA_8237A: 887 via_vlink_dev_lo = 15; 888 break; 889 case PCI_DEVICE_ID_VIA_8235: 890 via_vlink_dev_lo = 16; 891 break; 892 case PCI_DEVICE_ID_VIA_8231: 893 case PCI_DEVICE_ID_VIA_8233_0: 894 case PCI_DEVICE_ID_VIA_8233A: 895 case PCI_DEVICE_ID_VIA_8233C_0: 896 via_vlink_dev_lo = 17; 897 break; 898 } 899 } 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 908 909 /** 910 * quirk_via_vlink - VIA VLink IRQ number update 911 * @dev: PCI device 912 * 913 * If the device we are dealing with is on a PIC IRQ we need to 914 * ensure that the IRQ line register which usually is not relevant 915 * for PCI cards, is actually written so that interrupts get sent 916 * to the right place. 917 * We only do this on systems where a VIA south bridge was detected, 918 * and only for VIA devices on the motherboard (see quirk_via_bridge 919 * above). 920 */ 921 922 static void quirk_via_vlink(struct pci_dev *dev) 923 { 924 u8 irq, new_irq; 925 926 /* Check if we have VLink at all */ 927 if (via_vlink_dev_lo == -1) 928 return; 929 930 new_irq = dev->irq; 931 932 /* Don't quirk interrupts outside the legacy IRQ range */ 933 if (!new_irq || new_irq > 15) 934 return; 935 936 /* Internal device ? */ 937 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 938 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 939 return; 940 941 /* This is an internal VLink device on a PIC interrupt. The BIOS 942 ought to have set this but may not have, so we redo it */ 943 944 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 945 if (new_irq != irq) { 946 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 947 irq, new_irq); 948 udelay(15); /* unknown if delay really needed */ 949 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 950 } 951 } 952 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 953 954 /* 955 * VIA VT82C598 has its device ID settable and many BIOSes 956 * set it to the ID of VT82C597 for backward compatibility. 957 * We need to switch it off to be able to recognize the real 958 * type of the chip. 959 */ 960 static void quirk_vt82c598_id(struct pci_dev *dev) 961 { 962 pci_write_config_byte(dev, 0xfc, 0); 963 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 964 } 965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 966 967 /* 968 * CardBus controllers have a legacy base address that enables them 969 * to respond as i82365 pcmcia controllers. We don't want them to 970 * do this even if the Linux CardBus driver is not loaded, because 971 * the Linux i82365 driver does not (and should not) handle CardBus. 972 */ 973 static void quirk_cardbus_legacy(struct pci_dev *dev) 974 { 975 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 976 } 977 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 978 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 979 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 980 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 981 982 /* 983 * Following the PCI ordering rules is optional on the AMD762. I'm not 984 * sure what the designers were smoking but let's not inhale... 985 * 986 * To be fair to AMD, it follows the spec by default, its BIOS people 987 * who turn it off! 988 */ 989 static void quirk_amd_ordering(struct pci_dev *dev) 990 { 991 u32 pcic; 992 pci_read_config_dword(dev, 0x4C, &pcic); 993 if ((pcic & 6) != 6) { 994 pcic |= 6; 995 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 996 pci_write_config_dword(dev, 0x4C, pcic); 997 pci_read_config_dword(dev, 0x84, &pcic); 998 pcic |= (1 << 23); /* Required in this mode */ 999 pci_write_config_dword(dev, 0x84, pcic); 1000 } 1001 } 1002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1003 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1004 1005 /* 1006 * DreamWorks provided workaround for Dunord I-3000 problem 1007 * 1008 * This card decodes and responds to addresses not apparently 1009 * assigned to it. We force a larger allocation to ensure that 1010 * nothing gets put too close to it. 1011 */ 1012 static void quirk_dunord(struct pci_dev *dev) 1013 { 1014 struct resource *r = &dev->resource[1]; 1015 1016 r->flags |= IORESOURCE_UNSET; 1017 r->start = 0; 1018 r->end = 0xffffff; 1019 } 1020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1021 1022 /* 1023 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1024 * is subtractive decoding (transparent), and does indicate this 1025 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1026 * instead of 0x01. 1027 */ 1028 static void quirk_transparent_bridge(struct pci_dev *dev) 1029 { 1030 dev->transparent = 1; 1031 } 1032 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1033 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1034 1035 /* 1036 * Common misconfiguration of the MediaGX/Geode PCI master that will 1037 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1038 * datasheets found at http://www.national.com/analog for info on what 1039 * these bits do. <christer@weinigel.se> 1040 */ 1041 static void quirk_mediagx_master(struct pci_dev *dev) 1042 { 1043 u8 reg; 1044 1045 pci_read_config_byte(dev, 0x41, ®); 1046 if (reg & 2) { 1047 reg &= ~2; 1048 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1049 reg); 1050 pci_write_config_byte(dev, 0x41, reg); 1051 } 1052 } 1053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1054 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1055 1056 /* 1057 * Ensure C0 rev restreaming is off. This is normally done by 1058 * the BIOS but in the odd case it is not the results are corruption 1059 * hence the presence of a Linux check 1060 */ 1061 static void quirk_disable_pxb(struct pci_dev *pdev) 1062 { 1063 u16 config; 1064 1065 if (pdev->revision != 0x04) /* Only C0 requires this */ 1066 return; 1067 pci_read_config_word(pdev, 0x40, &config); 1068 if (config & (1<<6)) { 1069 config &= ~(1<<6); 1070 pci_write_config_word(pdev, 0x40, config); 1071 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1072 } 1073 } 1074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1075 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1076 1077 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1078 { 1079 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1080 u8 tmp; 1081 1082 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1083 if (tmp == 0x01) { 1084 pci_read_config_byte(pdev, 0x40, &tmp); 1085 pci_write_config_byte(pdev, 0x40, tmp|1); 1086 pci_write_config_byte(pdev, 0x9, 1); 1087 pci_write_config_byte(pdev, 0xa, 6); 1088 pci_write_config_byte(pdev, 0x40, tmp); 1089 1090 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1091 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1092 } 1093 } 1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1095 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1097 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1099 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1101 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1102 1103 /* 1104 * Serverworks CSB5 IDE does not fully support native mode 1105 */ 1106 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1107 { 1108 u8 prog; 1109 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1110 if (prog & 5) { 1111 prog &= ~5; 1112 pdev->class &= ~5; 1113 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1114 /* PCI layer will sort out resources */ 1115 } 1116 } 1117 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1118 1119 /* 1120 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1121 */ 1122 static void quirk_ide_samemode(struct pci_dev *pdev) 1123 { 1124 u8 prog; 1125 1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1127 1128 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1129 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1130 prog &= ~5; 1131 pdev->class &= ~5; 1132 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1133 } 1134 } 1135 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1136 1137 /* 1138 * Some ATA devices break if put into D3 1139 */ 1140 1141 static void quirk_no_ata_d3(struct pci_dev *pdev) 1142 { 1143 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1144 } 1145 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1146 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1147 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1148 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1149 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1150 /* ALi loses some register settings that we cannot then restore */ 1151 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1152 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1153 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1154 occur when mode detecting */ 1155 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1156 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1157 1158 /* This was originally an Alpha specific thing, but it really fits here. 1159 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1160 */ 1161 static void quirk_eisa_bridge(struct pci_dev *dev) 1162 { 1163 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1164 } 1165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1166 1167 1168 /* 1169 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1170 * is not activated. The myth is that Asus said that they do not want the 1171 * users to be irritated by just another PCI Device in the Win98 device 1172 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1173 * package 2.7.0 for details) 1174 * 1175 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1176 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1177 * becomes necessary to do this tweak in two steps -- the chosen trigger 1178 * is either the Host bridge (preferred) or on-board VGA controller. 1179 * 1180 * Note that we used to unhide the SMBus that way on Toshiba laptops 1181 * (Satellite A40 and Tecra M2) but then found that the thermal management 1182 * was done by SMM code, which could cause unsynchronized concurrent 1183 * accesses to the SMBus registers, with potentially bad effects. Thus you 1184 * should be very careful when adding new entries: if SMM is accessing the 1185 * Intel SMBus, this is a very good reason to leave it hidden. 1186 * 1187 * Likewise, many recent laptops use ACPI for thermal management. If the 1188 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1189 * natively, and keeping the SMBus hidden is the right thing to do. If you 1190 * are about to add an entry in the table below, please first disassemble 1191 * the DSDT and double-check that there is no code accessing the SMBus. 1192 */ 1193 static int asus_hides_smbus; 1194 1195 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1196 { 1197 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1198 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1199 switch (dev->subsystem_device) { 1200 case 0x8025: /* P4B-LX */ 1201 case 0x8070: /* P4B */ 1202 case 0x8088: /* P4B533 */ 1203 case 0x1626: /* L3C notebook */ 1204 asus_hides_smbus = 1; 1205 } 1206 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1207 switch (dev->subsystem_device) { 1208 case 0x80b1: /* P4GE-V */ 1209 case 0x80b2: /* P4PE */ 1210 case 0x8093: /* P4B533-V */ 1211 asus_hides_smbus = 1; 1212 } 1213 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1214 switch (dev->subsystem_device) { 1215 case 0x8030: /* P4T533 */ 1216 asus_hides_smbus = 1; 1217 } 1218 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1219 switch (dev->subsystem_device) { 1220 case 0x8070: /* P4G8X Deluxe */ 1221 asus_hides_smbus = 1; 1222 } 1223 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1224 switch (dev->subsystem_device) { 1225 case 0x80c9: /* PU-DLS */ 1226 asus_hides_smbus = 1; 1227 } 1228 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1229 switch (dev->subsystem_device) { 1230 case 0x1751: /* M2N notebook */ 1231 case 0x1821: /* M5N notebook */ 1232 case 0x1897: /* A6L notebook */ 1233 asus_hides_smbus = 1; 1234 } 1235 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1236 switch (dev->subsystem_device) { 1237 case 0x184b: /* W1N notebook */ 1238 case 0x186a: /* M6Ne notebook */ 1239 asus_hides_smbus = 1; 1240 } 1241 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1242 switch (dev->subsystem_device) { 1243 case 0x80f2: /* P4P800-X */ 1244 asus_hides_smbus = 1; 1245 } 1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1247 switch (dev->subsystem_device) { 1248 case 0x1882: /* M6V notebook */ 1249 case 0x1977: /* A6VA notebook */ 1250 asus_hides_smbus = 1; 1251 } 1252 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1253 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1254 switch (dev->subsystem_device) { 1255 case 0x088C: /* HP Compaq nc8000 */ 1256 case 0x0890: /* HP Compaq nc6000 */ 1257 asus_hides_smbus = 1; 1258 } 1259 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1260 switch (dev->subsystem_device) { 1261 case 0x12bc: /* HP D330L */ 1262 case 0x12bd: /* HP D530 */ 1263 case 0x006a: /* HP Compaq nx9500 */ 1264 asus_hides_smbus = 1; 1265 } 1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1267 switch (dev->subsystem_device) { 1268 case 0x12bf: /* HP xw4100 */ 1269 asus_hides_smbus = 1; 1270 } 1271 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1272 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1273 switch (dev->subsystem_device) { 1274 case 0xC00C: /* Samsung P35 notebook */ 1275 asus_hides_smbus = 1; 1276 } 1277 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1278 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1279 switch (dev->subsystem_device) { 1280 case 0x0058: /* Compaq Evo N620c */ 1281 asus_hides_smbus = 1; 1282 } 1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1284 switch (dev->subsystem_device) { 1285 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1286 /* Motherboard doesn't have Host bridge 1287 * subvendor/subdevice IDs, therefore checking 1288 * its on-board VGA controller */ 1289 asus_hides_smbus = 1; 1290 } 1291 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1292 switch (dev->subsystem_device) { 1293 case 0x00b8: /* Compaq Evo D510 CMT */ 1294 case 0x00b9: /* Compaq Evo D510 SFF */ 1295 case 0x00ba: /* Compaq Evo D510 USDT */ 1296 /* Motherboard doesn't have Host bridge 1297 * subvendor/subdevice IDs and on-board VGA 1298 * controller is disabled if an AGP card is 1299 * inserted, therefore checking USB UHCI 1300 * Controller #1 */ 1301 asus_hides_smbus = 1; 1302 } 1303 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1304 switch (dev->subsystem_device) { 1305 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1306 /* Motherboard doesn't have host bridge 1307 * subvendor/subdevice IDs, therefore checking 1308 * its on-board VGA controller */ 1309 asus_hides_smbus = 1; 1310 } 1311 } 1312 } 1313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1323 1324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1327 1328 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1329 { 1330 u16 val; 1331 1332 if (likely(!asus_hides_smbus)) 1333 return; 1334 1335 pci_read_config_word(dev, 0xF2, &val); 1336 if (val & 0x8) { 1337 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1338 pci_read_config_word(dev, 0xF2, &val); 1339 if (val & 0x8) 1340 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1341 val); 1342 else 1343 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1344 } 1345 } 1346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1353 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1354 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1355 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1356 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1357 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1358 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1359 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1360 1361 /* It appears we just have one such device. If not, we have a warning */ 1362 static void __iomem *asus_rcba_base; 1363 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1364 { 1365 u32 rcba; 1366 1367 if (likely(!asus_hides_smbus)) 1368 return; 1369 WARN_ON(asus_rcba_base); 1370 1371 pci_read_config_dword(dev, 0xF0, &rcba); 1372 /* use bits 31:14, 16 kB aligned */ 1373 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1374 if (asus_rcba_base == NULL) 1375 return; 1376 } 1377 1378 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1379 { 1380 u32 val; 1381 1382 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1383 return; 1384 /* read the Function Disable register, dword mode only */ 1385 val = readl(asus_rcba_base + 0x3418); 1386 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1387 } 1388 1389 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1390 { 1391 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1392 return; 1393 iounmap(asus_rcba_base); 1394 asus_rcba_base = NULL; 1395 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1396 } 1397 1398 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1399 { 1400 asus_hides_smbus_lpc_ich6_suspend(dev); 1401 asus_hides_smbus_lpc_ich6_resume_early(dev); 1402 asus_hides_smbus_lpc_ich6_resume(dev); 1403 } 1404 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1405 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1406 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1407 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1408 1409 /* 1410 * SiS 96x south bridge: BIOS typically hides SMBus device... 1411 */ 1412 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1413 { 1414 u8 val = 0; 1415 pci_read_config_byte(dev, 0x77, &val); 1416 if (val & 0x10) { 1417 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1418 pci_write_config_byte(dev, 0x77, val & ~0x10); 1419 } 1420 } 1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1425 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1426 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1427 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1428 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1429 1430 /* 1431 * ... This is further complicated by the fact that some SiS96x south 1432 * bridges pretend to be 85C503/5513 instead. In that case see if we 1433 * spotted a compatible north bridge to make sure. 1434 * (pci_find_device doesn't work yet) 1435 * 1436 * We can also enable the sis96x bit in the discovery register.. 1437 */ 1438 #define SIS_DETECT_REGISTER 0x40 1439 1440 static void quirk_sis_503(struct pci_dev *dev) 1441 { 1442 u8 reg; 1443 u16 devid; 1444 1445 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1446 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1447 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1448 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1449 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1450 return; 1451 } 1452 1453 /* 1454 * Ok, it now shows up as a 96x.. run the 96x quirk by 1455 * hand in case it has already been processed. 1456 * (depends on link order, which is apparently not guaranteed) 1457 */ 1458 dev->device = devid; 1459 quirk_sis_96x_smbus(dev); 1460 } 1461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1462 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1463 1464 1465 /* 1466 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1467 * and MC97 modem controller are disabled when a second PCI soundcard is 1468 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1469 * -- bjd 1470 */ 1471 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1472 { 1473 u8 val; 1474 int asus_hides_ac97 = 0; 1475 1476 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1477 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1478 asus_hides_ac97 = 1; 1479 } 1480 1481 if (!asus_hides_ac97) 1482 return; 1483 1484 pci_read_config_byte(dev, 0x50, &val); 1485 if (val & 0xc0) { 1486 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1487 pci_read_config_byte(dev, 0x50, &val); 1488 if (val & 0xc0) 1489 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1490 val); 1491 else 1492 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1493 } 1494 } 1495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1496 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1497 1498 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1499 1500 /* 1501 * If we are using libata we can drive this chip properly but must 1502 * do this early on to make the additional device appear during 1503 * the PCI scanning. 1504 */ 1505 static void quirk_jmicron_ata(struct pci_dev *pdev) 1506 { 1507 u32 conf1, conf5, class; 1508 u8 hdr; 1509 1510 /* Only poke fn 0 */ 1511 if (PCI_FUNC(pdev->devfn)) 1512 return; 1513 1514 pci_read_config_dword(pdev, 0x40, &conf1); 1515 pci_read_config_dword(pdev, 0x80, &conf5); 1516 1517 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1518 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1519 1520 switch (pdev->device) { 1521 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1522 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1523 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1524 /* The controller should be in single function ahci mode */ 1525 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1526 break; 1527 1528 case PCI_DEVICE_ID_JMICRON_JMB365: 1529 case PCI_DEVICE_ID_JMICRON_JMB366: 1530 /* Redirect IDE second PATA port to the right spot */ 1531 conf5 |= (1 << 24); 1532 /* Fall through */ 1533 case PCI_DEVICE_ID_JMICRON_JMB361: 1534 case PCI_DEVICE_ID_JMICRON_JMB363: 1535 case PCI_DEVICE_ID_JMICRON_JMB369: 1536 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1537 /* Set the class codes correctly and then direct IDE 0 */ 1538 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1539 break; 1540 1541 case PCI_DEVICE_ID_JMICRON_JMB368: 1542 /* The controller should be in single function IDE mode */ 1543 conf1 |= 0x00C00000; /* Set 22, 23 */ 1544 break; 1545 } 1546 1547 pci_write_config_dword(pdev, 0x40, conf1); 1548 pci_write_config_dword(pdev, 0x80, conf5); 1549 1550 /* Update pdev accordingly */ 1551 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1552 pdev->hdr_type = hdr & 0x7f; 1553 pdev->multifunction = !!(hdr & 0x80); 1554 1555 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1556 pdev->class = class >> 8; 1557 } 1558 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1562 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1563 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1567 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1568 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1569 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1570 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1571 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1572 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1573 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1574 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1575 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1576 1577 #endif 1578 1579 #ifdef CONFIG_X86_IO_APIC 1580 static void quirk_alder_ioapic(struct pci_dev *pdev) 1581 { 1582 int i; 1583 1584 if ((pdev->class >> 8) != 0xff00) 1585 return; 1586 1587 /* the first BAR is the location of the IO APIC...we must 1588 * not touch this (and it's already covered by the fixmap), so 1589 * forcibly insert it into the resource tree */ 1590 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1591 insert_resource(&iomem_resource, &pdev->resource[0]); 1592 1593 /* The next five BARs all seem to be rubbish, so just clean 1594 * them out */ 1595 for (i = 1; i < 6; i++) 1596 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1597 } 1598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1599 #endif 1600 1601 static void quirk_pcie_mch(struct pci_dev *pdev) 1602 { 1603 pci_msi_off(pdev); 1604 pdev->no_msi = 1; 1605 } 1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1609 1610 1611 /* 1612 * It's possible for the MSI to get corrupted if shpc and acpi 1613 * are used together on certain PXH-based systems. 1614 */ 1615 static void quirk_pcie_pxh(struct pci_dev *dev) 1616 { 1617 pci_msi_off(dev); 1618 dev->no_msi = 1; 1619 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1620 } 1621 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1622 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1623 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1624 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1625 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1626 1627 /* 1628 * Some Intel PCI Express chipsets have trouble with downstream 1629 * device power management. 1630 */ 1631 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1632 { 1633 pci_pm_d3_delay = 120; 1634 dev->no_d1d2 = 1; 1635 } 1636 1637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1658 1659 #ifdef CONFIG_X86_IO_APIC 1660 /* 1661 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1662 * remap the original interrupt in the linux kernel to the boot interrupt, so 1663 * that a PCI device's interrupt handler is installed on the boot interrupt 1664 * line instead. 1665 */ 1666 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1667 { 1668 if (noioapicquirk || noioapicreroute) 1669 return; 1670 1671 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1672 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1673 dev->vendor, dev->device); 1674 } 1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1683 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1684 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1685 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1686 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1687 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1688 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1689 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1690 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1691 1692 /* 1693 * On some chipsets we can disable the generation of legacy INTx boot 1694 * interrupts. 1695 */ 1696 1697 /* 1698 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1699 * 300641-004US, section 5.7.3. 1700 */ 1701 #define INTEL_6300_IOAPIC_ABAR 0x40 1702 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1703 1704 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1705 { 1706 u16 pci_config_word; 1707 1708 if (noioapicquirk) 1709 return; 1710 1711 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1712 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1713 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1714 1715 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1716 dev->vendor, dev->device); 1717 } 1718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1719 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1720 1721 /* 1722 * disable boot interrupts on HT-1000 1723 */ 1724 #define BC_HT1000_FEATURE_REG 0x64 1725 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1726 #define BC_HT1000_MAP_IDX 0xC00 1727 #define BC_HT1000_MAP_DATA 0xC01 1728 1729 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1730 { 1731 u32 pci_config_dword; 1732 u8 irq; 1733 1734 if (noioapicquirk) 1735 return; 1736 1737 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1738 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1739 BC_HT1000_PIC_REGS_ENABLE); 1740 1741 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1742 outb(irq, BC_HT1000_MAP_IDX); 1743 outb(0x00, BC_HT1000_MAP_DATA); 1744 } 1745 1746 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1747 1748 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1749 dev->vendor, dev->device); 1750 } 1751 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1752 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1753 1754 /* 1755 * disable boot interrupts on AMD and ATI chipsets 1756 */ 1757 /* 1758 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1759 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1760 * (due to an erratum). 1761 */ 1762 #define AMD_813X_MISC 0x40 1763 #define AMD_813X_NOIOAMODE (1<<0) 1764 #define AMD_813X_REV_B1 0x12 1765 #define AMD_813X_REV_B2 0x13 1766 1767 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1768 { 1769 u32 pci_config_dword; 1770 1771 if (noioapicquirk) 1772 return; 1773 if ((dev->revision == AMD_813X_REV_B1) || 1774 (dev->revision == AMD_813X_REV_B2)) 1775 return; 1776 1777 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1778 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1779 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1780 1781 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1782 dev->vendor, dev->device); 1783 } 1784 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1785 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1786 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1787 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1788 1789 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1790 1791 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1792 { 1793 u16 pci_config_word; 1794 1795 if (noioapicquirk) 1796 return; 1797 1798 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1799 if (!pci_config_word) { 1800 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", 1801 dev->vendor, dev->device); 1802 return; 1803 } 1804 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1805 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1806 dev->vendor, dev->device); 1807 } 1808 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1809 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1810 #endif /* CONFIG_X86_IO_APIC */ 1811 1812 /* 1813 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1814 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1815 * Re-allocate the region if needed... 1816 */ 1817 static void quirk_tc86c001_ide(struct pci_dev *dev) 1818 { 1819 struct resource *r = &dev->resource[0]; 1820 1821 if (r->start & 0x8) { 1822 r->flags |= IORESOURCE_UNSET; 1823 r->start = 0; 1824 r->end = 0xf; 1825 } 1826 } 1827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1828 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1829 quirk_tc86c001_ide); 1830 1831 /* 1832 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 1833 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 1834 * being read correctly if bit 7 of the base address is set. 1835 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 1836 * Re-allocate the regions to a 256-byte boundary if necessary. 1837 */ 1838 static void quirk_plx_pci9050(struct pci_dev *dev) 1839 { 1840 unsigned int bar; 1841 1842 /* Fixed in revision 2 (PCI 9052). */ 1843 if (dev->revision >= 2) 1844 return; 1845 for (bar = 0; bar <= 1; bar++) 1846 if (pci_resource_len(dev, bar) == 0x80 && 1847 (pci_resource_start(dev, bar) & 0x80)) { 1848 struct resource *r = &dev->resource[bar]; 1849 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 1850 bar); 1851 r->flags |= IORESOURCE_UNSET; 1852 r->start = 0; 1853 r->end = 0xff; 1854 } 1855 } 1856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 1857 quirk_plx_pci9050); 1858 /* 1859 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 1860 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 1861 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 1862 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 1863 * 1864 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 1865 * driver. 1866 */ 1867 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 1868 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 1869 1870 static void quirk_netmos(struct pci_dev *dev) 1871 { 1872 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1873 unsigned int num_serial = dev->subsystem_device & 0xf; 1874 1875 /* 1876 * These Netmos parts are multiport serial devices with optional 1877 * parallel ports. Even when parallel ports are present, they 1878 * are identified as class SERIAL, which means the serial driver 1879 * will claim them. To prevent this, mark them as class OTHER. 1880 * These combo devices should be claimed by parport_serial. 1881 * 1882 * The subdevice ID is of the form 0x00PS, where <P> is the number 1883 * of parallel ports and <S> is the number of serial ports. 1884 */ 1885 switch (dev->device) { 1886 case PCI_DEVICE_ID_NETMOS_9835: 1887 /* Well, this rule doesn't hold for the following 9835 device */ 1888 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1889 dev->subsystem_device == 0x0299) 1890 return; 1891 case PCI_DEVICE_ID_NETMOS_9735: 1892 case PCI_DEVICE_ID_NETMOS_9745: 1893 case PCI_DEVICE_ID_NETMOS_9845: 1894 case PCI_DEVICE_ID_NETMOS_9855: 1895 if (num_parallel) { 1896 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 1897 dev->device, num_parallel, num_serial); 1898 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1899 (dev->class & 0xff); 1900 } 1901 } 1902 } 1903 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1904 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 1905 1906 static void quirk_e100_interrupt(struct pci_dev *dev) 1907 { 1908 u16 command, pmcsr; 1909 u8 __iomem *csr; 1910 u8 cmd_hi; 1911 1912 switch (dev->device) { 1913 /* PCI IDs taken from drivers/net/e100.c */ 1914 case 0x1029: 1915 case 0x1030 ... 0x1034: 1916 case 0x1038 ... 0x103E: 1917 case 0x1050 ... 0x1057: 1918 case 0x1059: 1919 case 0x1064 ... 0x106B: 1920 case 0x1091 ... 0x1095: 1921 case 0x1209: 1922 case 0x1229: 1923 case 0x2449: 1924 case 0x2459: 1925 case 0x245D: 1926 case 0x27DC: 1927 break; 1928 default: 1929 return; 1930 } 1931 1932 /* 1933 * Some firmware hands off the e100 with interrupts enabled, 1934 * which can cause a flood of interrupts if packets are 1935 * received before the driver attaches to the device. So 1936 * disable all e100 interrupts here. The driver will 1937 * re-enable them when it's ready. 1938 */ 1939 pci_read_config_word(dev, PCI_COMMAND, &command); 1940 1941 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1942 return; 1943 1944 /* 1945 * Check that the device is in the D0 power state. If it's not, 1946 * there is no point to look any further. 1947 */ 1948 if (dev->pm_cap) { 1949 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1950 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1951 return; 1952 } 1953 1954 /* Convert from PCI bus to resource space. */ 1955 csr = ioremap(pci_resource_start(dev, 0), 8); 1956 if (!csr) { 1957 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1958 return; 1959 } 1960 1961 cmd_hi = readb(csr + 3); 1962 if (cmd_hi == 0) { 1963 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); 1964 writeb(1, csr + 3); 1965 } 1966 1967 iounmap(csr); 1968 } 1969 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1970 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 1971 1972 /* 1973 * The 82575 and 82598 may experience data corruption issues when transitioning 1974 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1975 */ 1976 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 1977 { 1978 dev_info(&dev->dev, "Disabling L0s\n"); 1979 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1980 } 1981 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 1982 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 1983 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 1984 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 1985 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 1986 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 1987 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 1988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 1989 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 1990 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 1991 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 1992 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 1993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 1994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 1995 1996 static void fixup_rev1_53c810(struct pci_dev *dev) 1997 { 1998 /* rev 1 ncr53c810 chips don't set the class at all which means 1999 * they don't get their resources remapped. Fix that here. 2000 */ 2001 2002 if (dev->class == PCI_CLASS_NOT_DEFINED) { 2003 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 2004 dev->class = PCI_CLASS_STORAGE_SCSI; 2005 } 2006 } 2007 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2008 2009 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2010 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2011 { 2012 u16 en1k; 2013 2014 pci_read_config_word(dev, 0x40, &en1k); 2015 2016 if (en1k & 0x200) { 2017 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 2018 dev->io_window_1k = 1; 2019 } 2020 } 2021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2022 2023 /* Under some circumstances, AER is not linked with extended capabilities. 2024 * Force it to be linked by setting the corresponding control bit in the 2025 * config space. 2026 */ 2027 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2028 { 2029 uint8_t b; 2030 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2031 if (!(b & 0x20)) { 2032 pci_write_config_byte(dev, 0xf41, b | 0x20); 2033 dev_info(&dev->dev, "Linking AER extended capability\n"); 2034 } 2035 } 2036 } 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2038 quirk_nvidia_ck804_pcie_aer_ext_cap); 2039 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2040 quirk_nvidia_ck804_pcie_aer_ext_cap); 2041 2042 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2043 { 2044 /* 2045 * Disable PCI Bus Parking and PCI Master read caching on CX700 2046 * which causes unspecified timing errors with a VT6212L on the PCI 2047 * bus leading to USB2.0 packet loss. 2048 * 2049 * This quirk is only enabled if a second (on the external PCI bus) 2050 * VT6212L is found -- the CX700 core itself also contains a USB 2051 * host controller with the same PCI ID as the VT6212L. 2052 */ 2053 2054 /* Count VT6212L instances */ 2055 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2056 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2057 uint8_t b; 2058 2059 /* p should contain the first (internal) VT6212L -- see if we have 2060 an external one by searching again */ 2061 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2062 if (!p) 2063 return; 2064 pci_dev_put(p); 2065 2066 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2067 if (b & 0x40) { 2068 /* Turn off PCI Bus Parking */ 2069 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2070 2071 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); 2072 } 2073 } 2074 2075 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2076 if (b != 0) { 2077 /* Turn off PCI Master read caching */ 2078 pci_write_config_byte(dev, 0x72, 0x0); 2079 2080 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2081 pci_write_config_byte(dev, 0x75, 0x1); 2082 2083 /* Disable "Read FIFO Timer" */ 2084 pci_write_config_byte(dev, 0x77, 0x0); 2085 2086 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); 2087 } 2088 } 2089 } 2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2091 2092 /* 2093 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2094 * VPD end tag will hang the device. This problem was initially 2095 * observed when a vpd entry was created in sysfs 2096 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2097 * will dump 32k of data. Reading a full 32k will cause an access 2098 * beyond the VPD end tag causing the device to hang. Once the device 2099 * is hung, the bnx2 driver will not be able to reset the device. 2100 * We believe that it is legal to read beyond the end tag and 2101 * therefore the solution is to limit the read/write length. 2102 */ 2103 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2104 { 2105 /* 2106 * Only disable the VPD capability for 5706, 5706S, 5708, 2107 * 5708S and 5709 rev. A 2108 */ 2109 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2110 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2111 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2112 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2113 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2114 (dev->revision & 0xf0) == 0x0)) { 2115 if (dev->vpd) 2116 dev->vpd->len = 0x80; 2117 } 2118 } 2119 2120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2121 PCI_DEVICE_ID_NX2_5706, 2122 quirk_brcm_570x_limit_vpd); 2123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2124 PCI_DEVICE_ID_NX2_5706S, 2125 quirk_brcm_570x_limit_vpd); 2126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2127 PCI_DEVICE_ID_NX2_5708, 2128 quirk_brcm_570x_limit_vpd); 2129 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2130 PCI_DEVICE_ID_NX2_5708S, 2131 quirk_brcm_570x_limit_vpd); 2132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2133 PCI_DEVICE_ID_NX2_5709, 2134 quirk_brcm_570x_limit_vpd); 2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2136 PCI_DEVICE_ID_NX2_5709S, 2137 quirk_brcm_570x_limit_vpd); 2138 2139 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2140 { 2141 u32 rev; 2142 2143 pci_read_config_dword(dev, 0xf4, &rev); 2144 2145 /* Only CAP the MRRS if the device is a 5719 A0 */ 2146 if (rev == 0x05719000) { 2147 int readrq = pcie_get_readrq(dev); 2148 if (readrq > 2048) 2149 pcie_set_readrq(dev, 2048); 2150 } 2151 } 2152 2153 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2154 PCI_DEVICE_ID_TIGON3_5719, 2155 quirk_brcm_5719_limit_mrrs); 2156 2157 /* Originally in EDAC sources for i82875P: 2158 * Intel tells BIOS developers to hide device 6 which 2159 * configures the overflow device access containing 2160 * the DRBs - this is where we expose device 6. 2161 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2162 */ 2163 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2164 { 2165 u8 reg; 2166 2167 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2168 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2169 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2170 } 2171 } 2172 2173 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2174 quirk_unhide_mch_dev6); 2175 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2176 quirk_unhide_mch_dev6); 2177 2178 #ifdef CONFIG_TILEPRO 2179 /* 2180 * The Tilera TILEmpower tilepro platform needs to set the link speed 2181 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2182 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2183 * capability register of the PEX8624 PCIe switch. The switch 2184 * supports link speed auto negotiation, but falsely sets 2185 * the link speed to 5GT/s. 2186 */ 2187 static void quirk_tile_plx_gen1(struct pci_dev *dev) 2188 { 2189 if (tile_plx_gen1) { 2190 pci_write_config_dword(dev, 0x98, 0x1); 2191 mdelay(50); 2192 } 2193 } 2194 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2195 #endif /* CONFIG_TILEPRO */ 2196 2197 #ifdef CONFIG_PCI_MSI 2198 /* Some chipsets do not support MSI. We cannot easily rely on setting 2199 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2200 * some other buses controlled by the chipset even if Linux is not 2201 * aware of it. Instead of setting the flag on all buses in the 2202 * machine, simply disable MSI globally. 2203 */ 2204 static void quirk_disable_all_msi(struct pci_dev *dev) 2205 { 2206 pci_no_msi(); 2207 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2208 } 2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2216 2217 /* Disable MSI on chipsets that are known to not support it */ 2218 static void quirk_disable_msi(struct pci_dev *dev) 2219 { 2220 if (dev->subordinate) { 2221 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2222 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2223 } 2224 } 2225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2228 2229 /* 2230 * The APC bridge device in AMD 780 family northbridges has some random 2231 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2232 * we use the possible vendor/device IDs of the host bridge for the 2233 * declared quirk, and search for the APC bridge by slot number. 2234 */ 2235 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2236 { 2237 struct pci_dev *apc_bridge; 2238 2239 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2240 if (apc_bridge) { 2241 if (apc_bridge->device == 0x9602) 2242 quirk_disable_msi(apc_bridge); 2243 pci_dev_put(apc_bridge); 2244 } 2245 } 2246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2248 2249 /* Go through the list of Hypertransport capabilities and 2250 * return 1 if a HT MSI capability is found and enabled */ 2251 static int msi_ht_cap_enabled(struct pci_dev *dev) 2252 { 2253 int pos, ttl = 48; 2254 2255 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2256 while (pos && ttl--) { 2257 u8 flags; 2258 2259 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2260 &flags) == 0) { 2261 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2262 flags & HT_MSI_FLAGS_ENABLE ? 2263 "enabled" : "disabled"); 2264 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2265 } 2266 2267 pos = pci_find_next_ht_capability(dev, pos, 2268 HT_CAPTYPE_MSI_MAPPING); 2269 } 2270 return 0; 2271 } 2272 2273 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2274 static void quirk_msi_ht_cap(struct pci_dev *dev) 2275 { 2276 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2277 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2278 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2279 } 2280 } 2281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2282 quirk_msi_ht_cap); 2283 2284 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2285 * MSI are supported if the MSI capability set in any of these mappings. 2286 */ 2287 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2288 { 2289 struct pci_dev *pdev; 2290 2291 if (!dev->subordinate) 2292 return; 2293 2294 /* check HT MSI cap on this chipset and the root one. 2295 * a single one having MSI is enough to be sure that MSI are supported. 2296 */ 2297 pdev = pci_get_slot(dev->bus, 0); 2298 if (!pdev) 2299 return; 2300 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2301 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2302 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2303 } 2304 pci_dev_put(pdev); 2305 } 2306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2307 quirk_nvidia_ck804_msi_ht_cap); 2308 2309 /* Force enable MSI mapping capability on HT bridges */ 2310 static void ht_enable_msi_mapping(struct pci_dev *dev) 2311 { 2312 int pos, ttl = 48; 2313 2314 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2315 while (pos && ttl--) { 2316 u8 flags; 2317 2318 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2319 &flags) == 0) { 2320 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2321 2322 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2323 flags | HT_MSI_FLAGS_ENABLE); 2324 } 2325 pos = pci_find_next_ht_capability(dev, pos, 2326 HT_CAPTYPE_MSI_MAPPING); 2327 } 2328 } 2329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2330 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2331 ht_enable_msi_mapping); 2332 2333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2334 ht_enable_msi_mapping); 2335 2336 /* The P5N32-SLI motherboards from Asus have a problem with msi 2337 * for the MCP55 NIC. It is not yet determined whether the msi problem 2338 * also affects other devices. As for now, turn off msi for this device. 2339 */ 2340 static void nvenet_msi_disable(struct pci_dev *dev) 2341 { 2342 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2343 2344 if (board_name && 2345 (strstr(board_name, "P5N32-SLI PREMIUM") || 2346 strstr(board_name, "P5N32-E SLI"))) { 2347 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2348 dev->no_msi = 1; 2349 } 2350 } 2351 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2352 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2353 nvenet_msi_disable); 2354 2355 /* 2356 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2357 * config register. This register controls the routing of legacy 2358 * interrupts from devices that route through the MCP55. If this register 2359 * is misprogrammed, interrupts are only sent to the BSP, unlike 2360 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2361 * having this register set properly prevents kdump from booting up 2362 * properly, so let's make sure that we have it set correctly. 2363 * Note that this is an undocumented register. 2364 */ 2365 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2366 { 2367 u32 cfg; 2368 2369 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2370 return; 2371 2372 pci_read_config_dword(dev, 0x74, &cfg); 2373 2374 if (cfg & ((1 << 2) | (1 << 15))) { 2375 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2376 cfg &= ~((1 << 2) | (1 << 15)); 2377 pci_write_config_dword(dev, 0x74, cfg); 2378 } 2379 } 2380 2381 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2382 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2383 nvbridge_check_legacy_irq_routing); 2384 2385 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2386 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2387 nvbridge_check_legacy_irq_routing); 2388 2389 static int ht_check_msi_mapping(struct pci_dev *dev) 2390 { 2391 int pos, ttl = 48; 2392 int found = 0; 2393 2394 /* check if there is HT MSI cap or enabled on this device */ 2395 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2396 while (pos && ttl--) { 2397 u8 flags; 2398 2399 if (found < 1) 2400 found = 1; 2401 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2402 &flags) == 0) { 2403 if (flags & HT_MSI_FLAGS_ENABLE) { 2404 if (found < 2) { 2405 found = 2; 2406 break; 2407 } 2408 } 2409 } 2410 pos = pci_find_next_ht_capability(dev, pos, 2411 HT_CAPTYPE_MSI_MAPPING); 2412 } 2413 2414 return found; 2415 } 2416 2417 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2418 { 2419 struct pci_dev *dev; 2420 int pos; 2421 int i, dev_no; 2422 int found = 0; 2423 2424 dev_no = host_bridge->devfn >> 3; 2425 for (i = dev_no + 1; i < 0x20; i++) { 2426 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2427 if (!dev) 2428 continue; 2429 2430 /* found next host bridge ?*/ 2431 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2432 if (pos != 0) { 2433 pci_dev_put(dev); 2434 break; 2435 } 2436 2437 if (ht_check_msi_mapping(dev)) { 2438 found = 1; 2439 pci_dev_put(dev); 2440 break; 2441 } 2442 pci_dev_put(dev); 2443 } 2444 2445 return found; 2446 } 2447 2448 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2449 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2450 2451 static int is_end_of_ht_chain(struct pci_dev *dev) 2452 { 2453 int pos, ctrl_off; 2454 int end = 0; 2455 u16 flags, ctrl; 2456 2457 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2458 2459 if (!pos) 2460 goto out; 2461 2462 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2463 2464 ctrl_off = ((flags >> 10) & 1) ? 2465 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2466 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2467 2468 if (ctrl & (1 << 6)) 2469 end = 1; 2470 2471 out: 2472 return end; 2473 } 2474 2475 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2476 { 2477 struct pci_dev *host_bridge; 2478 int pos; 2479 int i, dev_no; 2480 int found = 0; 2481 2482 dev_no = dev->devfn >> 3; 2483 for (i = dev_no; i >= 0; i--) { 2484 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2485 if (!host_bridge) 2486 continue; 2487 2488 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2489 if (pos != 0) { 2490 found = 1; 2491 break; 2492 } 2493 pci_dev_put(host_bridge); 2494 } 2495 2496 if (!found) 2497 return; 2498 2499 /* don't enable end_device/host_bridge with leaf directly here */ 2500 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2501 host_bridge_with_leaf(host_bridge)) 2502 goto out; 2503 2504 /* root did that ! */ 2505 if (msi_ht_cap_enabled(host_bridge)) 2506 goto out; 2507 2508 ht_enable_msi_mapping(dev); 2509 2510 out: 2511 pci_dev_put(host_bridge); 2512 } 2513 2514 static void ht_disable_msi_mapping(struct pci_dev *dev) 2515 { 2516 int pos, ttl = 48; 2517 2518 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2519 while (pos && ttl--) { 2520 u8 flags; 2521 2522 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2523 &flags) == 0) { 2524 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2525 2526 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2527 flags & ~HT_MSI_FLAGS_ENABLE); 2528 } 2529 pos = pci_find_next_ht_capability(dev, pos, 2530 HT_CAPTYPE_MSI_MAPPING); 2531 } 2532 } 2533 2534 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2535 { 2536 struct pci_dev *host_bridge; 2537 int pos; 2538 int found; 2539 2540 if (!pci_msi_enabled()) 2541 return; 2542 2543 /* check if there is HT MSI cap or enabled on this device */ 2544 found = ht_check_msi_mapping(dev); 2545 2546 /* no HT MSI CAP */ 2547 if (found == 0) 2548 return; 2549 2550 /* 2551 * HT MSI mapping should be disabled on devices that are below 2552 * a non-Hypertransport host bridge. Locate the host bridge... 2553 */ 2554 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2555 if (host_bridge == NULL) { 2556 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2557 return; 2558 } 2559 2560 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2561 if (pos != 0) { 2562 /* Host bridge is to HT */ 2563 if (found == 1) { 2564 /* it is not enabled, try to enable it */ 2565 if (all) 2566 ht_enable_msi_mapping(dev); 2567 else 2568 nv_ht_enable_msi_mapping(dev); 2569 } 2570 goto out; 2571 } 2572 2573 /* HT MSI is not enabled */ 2574 if (found == 1) 2575 goto out; 2576 2577 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2578 ht_disable_msi_mapping(dev); 2579 2580 out: 2581 pci_dev_put(host_bridge); 2582 } 2583 2584 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2585 { 2586 return __nv_msi_ht_cap_quirk(dev, 1); 2587 } 2588 2589 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2590 { 2591 return __nv_msi_ht_cap_quirk(dev, 0); 2592 } 2593 2594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2595 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2596 2597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2598 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2599 2600 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2601 { 2602 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2603 } 2604 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2605 { 2606 struct pci_dev *p; 2607 2608 /* SB700 MSI issue will be fixed at HW level from revision A21, 2609 * we need check PCI REVISION ID of SMBus controller to get SB700 2610 * revision. 2611 */ 2612 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2613 NULL); 2614 if (!p) 2615 return; 2616 2617 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2618 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2619 pci_dev_put(p); 2620 } 2621 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2622 { 2623 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2624 if (dev->revision < 0x18) { 2625 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2626 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2627 } 2628 } 2629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2630 PCI_DEVICE_ID_TIGON3_5780, 2631 quirk_msi_intx_disable_bug); 2632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2633 PCI_DEVICE_ID_TIGON3_5780S, 2634 quirk_msi_intx_disable_bug); 2635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2636 PCI_DEVICE_ID_TIGON3_5714, 2637 quirk_msi_intx_disable_bug); 2638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2639 PCI_DEVICE_ID_TIGON3_5714S, 2640 quirk_msi_intx_disable_bug); 2641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2642 PCI_DEVICE_ID_TIGON3_5715, 2643 quirk_msi_intx_disable_bug); 2644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2645 PCI_DEVICE_ID_TIGON3_5715S, 2646 quirk_msi_intx_disable_bug); 2647 2648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2649 quirk_msi_intx_disable_ati_bug); 2650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2651 quirk_msi_intx_disable_ati_bug); 2652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2653 quirk_msi_intx_disable_ati_bug); 2654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2655 quirk_msi_intx_disable_ati_bug); 2656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2657 quirk_msi_intx_disable_ati_bug); 2658 2659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2660 quirk_msi_intx_disable_bug); 2661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2662 quirk_msi_intx_disable_bug); 2663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2664 quirk_msi_intx_disable_bug); 2665 2666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2667 quirk_msi_intx_disable_bug); 2668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2669 quirk_msi_intx_disable_bug); 2670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2671 quirk_msi_intx_disable_bug); 2672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2673 quirk_msi_intx_disable_bug); 2674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2675 quirk_msi_intx_disable_bug); 2676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2677 quirk_msi_intx_disable_bug); 2678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2679 quirk_msi_intx_disable_qca_bug); 2680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2681 quirk_msi_intx_disable_qca_bug); 2682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2683 quirk_msi_intx_disable_qca_bug); 2684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2685 quirk_msi_intx_disable_qca_bug); 2686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2687 quirk_msi_intx_disable_qca_bug); 2688 #endif /* CONFIG_PCI_MSI */ 2689 2690 /* Allow manual resource allocation for PCI hotplug bridges 2691 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2692 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2693 * kernel fails to allocate resources when hotplug device is 2694 * inserted and PCI bus is rescanned. 2695 */ 2696 static void quirk_hotplug_bridge(struct pci_dev *dev) 2697 { 2698 dev->is_hotplug_bridge = 1; 2699 } 2700 2701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2702 2703 /* 2704 * This is a quirk for the Ricoh MMC controller found as a part of 2705 * some mulifunction chips. 2706 2707 * This is very similar and based on the ricoh_mmc driver written by 2708 * Philip Langdale. Thank you for these magic sequences. 2709 * 2710 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2711 * and one or both of cardbus or firewire. 2712 * 2713 * It happens that they implement SD and MMC 2714 * support as separate controllers (and PCI functions). The linux SDHCI 2715 * driver supports MMC cards but the chip detects MMC cards in hardware 2716 * and directs them to the MMC controller - so the SDHCI driver never sees 2717 * them. 2718 * 2719 * To get around this, we must disable the useless MMC controller. 2720 * At that point, the SDHCI controller will start seeing them 2721 * It seems to be the case that the relevant PCI registers to deactivate the 2722 * MMC controller live on PCI function 0, which might be the cardbus controller 2723 * or the firewire controller, depending on the particular chip in question 2724 * 2725 * This has to be done early, because as soon as we disable the MMC controller 2726 * other pci functions shift up one level, e.g. function #2 becomes function 2727 * #1, and this will confuse the pci core. 2728 */ 2729 2730 #ifdef CONFIG_MMC_RICOH_MMC 2731 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2732 { 2733 /* disable via cardbus interface */ 2734 u8 write_enable; 2735 u8 write_target; 2736 u8 disable; 2737 2738 /* disable must be done via function #0 */ 2739 if (PCI_FUNC(dev->devfn)) 2740 return; 2741 2742 pci_read_config_byte(dev, 0xB7, &disable); 2743 if (disable & 0x02) 2744 return; 2745 2746 pci_read_config_byte(dev, 0x8E, &write_enable); 2747 pci_write_config_byte(dev, 0x8E, 0xAA); 2748 pci_read_config_byte(dev, 0x8D, &write_target); 2749 pci_write_config_byte(dev, 0x8D, 0xB7); 2750 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2751 pci_write_config_byte(dev, 0x8E, write_enable); 2752 pci_write_config_byte(dev, 0x8D, write_target); 2753 2754 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2755 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2756 } 2757 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2758 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2759 2760 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2761 { 2762 /* disable via firewire interface */ 2763 u8 write_enable; 2764 u8 disable; 2765 2766 /* disable must be done via function #0 */ 2767 if (PCI_FUNC(dev->devfn)) 2768 return; 2769 /* 2770 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2771 * certain types of SD/MMC cards. Lowering the SD base 2772 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2773 * 2774 * 0x150 - SD2.0 mode enable for changing base clock 2775 * frequency to 50Mhz 2776 * 0xe1 - Base clock frequency 2777 * 0x32 - 50Mhz new clock frequency 2778 * 0xf9 - Key register for 0x150 2779 * 0xfc - key register for 0xe1 2780 */ 2781 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2782 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2783 pci_write_config_byte(dev, 0xf9, 0xfc); 2784 pci_write_config_byte(dev, 0x150, 0x10); 2785 pci_write_config_byte(dev, 0xf9, 0x00); 2786 pci_write_config_byte(dev, 0xfc, 0x01); 2787 pci_write_config_byte(dev, 0xe1, 0x32); 2788 pci_write_config_byte(dev, 0xfc, 0x00); 2789 2790 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2791 } 2792 2793 pci_read_config_byte(dev, 0xCB, &disable); 2794 2795 if (disable & 0x02) 2796 return; 2797 2798 pci_read_config_byte(dev, 0xCA, &write_enable); 2799 pci_write_config_byte(dev, 0xCA, 0x57); 2800 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2801 pci_write_config_byte(dev, 0xCA, write_enable); 2802 2803 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2804 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2805 2806 } 2807 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2808 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2809 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2810 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2811 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2812 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2813 #endif /*CONFIG_MMC_RICOH_MMC*/ 2814 2815 #ifdef CONFIG_DMAR_TABLE 2816 #define VTUNCERRMSK_REG 0x1ac 2817 #define VTD_MSK_SPEC_ERRORS (1 << 31) 2818 /* 2819 * This is a quirk for masking vt-d spec defined errors to platform error 2820 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2821 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2822 * on the RAS config settings of the platform) when a vt-d fault happens. 2823 * The resulting SMI caused the system to hang. 2824 * 2825 * VT-d spec related errors are already handled by the VT-d OS code, so no 2826 * need to report the same error through other channels. 2827 */ 2828 static void vtd_mask_spec_errors(struct pci_dev *dev) 2829 { 2830 u32 word; 2831 2832 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2833 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2834 } 2835 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2836 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2837 #endif 2838 2839 static void fixup_ti816x_class(struct pci_dev *dev) 2840 { 2841 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2842 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n"); 2843 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; 2844 } 2845 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2846 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class); 2847 2848 /* Some PCIe devices do not work reliably with the claimed maximum 2849 * payload size supported. 2850 */ 2851 static void fixup_mpss_256(struct pci_dev *dev) 2852 { 2853 dev->pcie_mpss = 1; /* 256 bytes */ 2854 } 2855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2856 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 2857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2858 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 2859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2860 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 2861 2862 /* Intel 5000 and 5100 Memory controllers have an errata with read completion 2863 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 2864 * Since there is no way of knowing what the PCIE MPS on each fabric will be 2865 * until all of the devices are discovered and buses walked, read completion 2866 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 2867 * it is possible to hotplug a device with MPS of 256B. 2868 */ 2869 static void quirk_intel_mc_errata(struct pci_dev *dev) 2870 { 2871 int err; 2872 u16 rcc; 2873 2874 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) 2875 return; 2876 2877 /* Intel errata specifies bits to change but does not say what they are. 2878 * Keeping them magical until such time as the registers and values can 2879 * be explained. 2880 */ 2881 err = pci_read_config_word(dev, 0x48, &rcc); 2882 if (err) { 2883 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); 2884 return; 2885 } 2886 2887 if (!(rcc & (1 << 10))) 2888 return; 2889 2890 rcc &= ~(1 << 10); 2891 2892 err = pci_write_config_word(dev, 0x48, rcc); 2893 if (err) { 2894 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); 2895 return; 2896 } 2897 2898 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 2899 } 2900 /* Intel 5000 series memory controllers and ports 2-7 */ 2901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 2902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 2903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 2904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 2905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 2906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 2907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 2908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 2909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 2910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 2911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 2912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 2913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 2914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 2915 /* Intel 5100 series memory controllers and ports 2-7 */ 2916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 2917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 2918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 2919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 2920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 2921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 2922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 2923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 2924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 2925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 2926 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 2927 2928 2929 /* 2930 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 2931 * work around this, query the size it should be configured to by the device and 2932 * modify the resource end to correspond to this new size. 2933 */ 2934 static void quirk_intel_ntb(struct pci_dev *dev) 2935 { 2936 int rc; 2937 u8 val; 2938 2939 rc = pci_read_config_byte(dev, 0x00D0, &val); 2940 if (rc) 2941 return; 2942 2943 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 2944 2945 rc = pci_read_config_byte(dev, 0x00D1, &val); 2946 if (rc) 2947 return; 2948 2949 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 2950 } 2951 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 2952 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 2953 2954 static ktime_t fixup_debug_start(struct pci_dev *dev, 2955 void (*fn)(struct pci_dev *dev)) 2956 { 2957 ktime_t calltime = ktime_set(0, 0); 2958 2959 dev_dbg(&dev->dev, "calling %pF\n", fn); 2960 if (initcall_debug) { 2961 pr_debug("calling %pF @ %i for %s\n", 2962 fn, task_pid_nr(current), dev_name(&dev->dev)); 2963 calltime = ktime_get(); 2964 } 2965 2966 return calltime; 2967 } 2968 2969 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 2970 void (*fn)(struct pci_dev *dev)) 2971 { 2972 ktime_t delta, rettime; 2973 unsigned long long duration; 2974 2975 if (initcall_debug) { 2976 rettime = ktime_get(); 2977 delta = ktime_sub(rettime, calltime); 2978 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 2979 pr_debug("pci fixup %pF returned after %lld usecs for %s\n", 2980 fn, duration, dev_name(&dev->dev)); 2981 } 2982 } 2983 2984 /* 2985 * Some BIOS implementations leave the Intel GPU interrupts enabled, 2986 * even though no one is handling them (f.e. i915 driver is never loaded). 2987 * Additionally the interrupt destination is not set up properly 2988 * and the interrupt ends up -somewhere-. 2989 * 2990 * These spurious interrupts are "sticky" and the kernel disables 2991 * the (shared) interrupt line after 100.000+ generated interrupts. 2992 * 2993 * Fix it by disabling the still enabled interrupts. 2994 * This resolves crashes often seen on monitor unplug. 2995 */ 2996 #define I915_DEIER_REG 0x4400c 2997 static void disable_igfx_irq(struct pci_dev *dev) 2998 { 2999 void __iomem *regs = pci_iomap(dev, 0, 0); 3000 if (regs == NULL) { 3001 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); 3002 return; 3003 } 3004 3005 /* Check if any interrupt line is still enabled */ 3006 if (readl(regs + I915_DEIER_REG) != 0) { 3007 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3008 3009 writel(0, regs + I915_DEIER_REG); 3010 } 3011 3012 pci_iounmap(dev, regs); 3013 } 3014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3017 3018 /* 3019 * PCI devices which are on Intel chips can skip the 10ms delay 3020 * before entering D3 mode. 3021 */ 3022 static void quirk_remove_d3_delay(struct pci_dev *dev) 3023 { 3024 dev->d3_delay = 0; 3025 } 3026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3040 3041 /* 3042 * Some devices may pass our check in pci_intx_mask_supported if 3043 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3044 * support this feature. 3045 */ 3046 static void quirk_broken_intx_masking(struct pci_dev *dev) 3047 { 3048 dev->broken_intx_masking = 1; 3049 } 3050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030, 3051 quirk_broken_intx_masking); 3052 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3053 quirk_broken_intx_masking); 3054 /* 3055 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3056 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3057 * 3058 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3059 */ 3060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169, 3061 quirk_broken_intx_masking); 3062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3063 quirk_broken_intx_masking); 3064 3065 static void quirk_no_bus_reset(struct pci_dev *dev) 3066 { 3067 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3068 } 3069 3070 /* 3071 * Atheros AR93xx chips do not behave after a bus reset. The device will 3072 * throw a Link Down error on AER-capable systems and regardless of AER, 3073 * config space of the device is never accessible again and typically 3074 * causes the system to hang or reset when access is attempted. 3075 * http://www.spinics.net/lists/linux-pci/msg34797.html 3076 */ 3077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3078 3079 static void quirk_no_pm_reset(struct pci_dev *dev) 3080 { 3081 /* 3082 * We can't do a bus reset on root bus devices, but an ineffective 3083 * PM reset may be better than nothing. 3084 */ 3085 if (!pci_is_root_bus(dev->bus)) 3086 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3087 } 3088 3089 /* 3090 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3091 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3092 * to have no effect on the device: it retains the framebuffer contents and 3093 * monitor sync. Advertising this support makes other layers, like VFIO, 3094 * assume pci_reset_function() is viable for this device. Mark it as 3095 * unavailable to skip it when testing reset methods. 3096 */ 3097 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3098 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3099 3100 #ifdef CONFIG_ACPI 3101 /* 3102 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3103 * 3104 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3105 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3106 * be present after resume if a device was plugged in before suspend. 3107 * 3108 * The thunderbolt controller consists of a pcie switch with downstream 3109 * bridges leading to the NHI and to the tunnel pci bridges. 3110 * 3111 * This quirk cuts power to the whole chip. Therefore we have to apply it 3112 * during suspend_noirq of the upstream bridge. 3113 * 3114 * Power is automagically restored before resume. No action is needed. 3115 */ 3116 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3117 { 3118 acpi_handle bridge, SXIO, SXFP, SXLV; 3119 3120 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3121 return; 3122 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3123 return; 3124 bridge = ACPI_HANDLE(&dev->dev); 3125 if (!bridge) 3126 return; 3127 /* 3128 * SXIO and SXLV are present only on machines requiring this quirk. 3129 * TB bridges in external devices might have the same device id as those 3130 * on the host, but they will not have the associated ACPI methods. This 3131 * implicitly checks that we are at the right bridge. 3132 */ 3133 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3134 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3135 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3136 return; 3137 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); 3138 3139 /* magic sequence */ 3140 acpi_execute_simple_method(SXIO, NULL, 1); 3141 acpi_execute_simple_method(SXFP, NULL, 0); 3142 msleep(300); 3143 acpi_execute_simple_method(SXLV, NULL, 0); 3144 acpi_execute_simple_method(SXIO, NULL, 0); 3145 acpi_execute_simple_method(SXLV, NULL, 0); 3146 } 3147 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547, 3148 quirk_apple_poweroff_thunderbolt); 3149 3150 /* 3151 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. 3152 * 3153 * During suspend the thunderbolt controller is reset and all pci 3154 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3155 * during resume. We have to manually wait for the NHI since there is 3156 * no parent child relationship between the NHI and the tunneled 3157 * bridges. 3158 */ 3159 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3160 { 3161 struct pci_dev *sibling = NULL; 3162 struct pci_dev *nhi = NULL; 3163 3164 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3165 return; 3166 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3167 return; 3168 /* 3169 * Find the NHI and confirm that we are a bridge on the tb host 3170 * controller and not on a tb endpoint. 3171 */ 3172 sibling = pci_get_slot(dev->bus, 0x0); 3173 if (sibling == dev) 3174 goto out; /* we are the downstream bridge to the NHI */ 3175 if (!sibling || !sibling->subordinate) 3176 goto out; 3177 nhi = pci_get_slot(sibling->subordinate, 0x0); 3178 if (!nhi) 3179 goto out; 3180 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3181 || (nhi->device != 0x1547 && nhi->device != 0x156c) 3182 || nhi->subsystem_vendor != 0x2222 3183 || nhi->subsystem_device != 0x1111) 3184 goto out; 3185 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3186 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3187 out: 3188 pci_dev_put(nhi); 3189 pci_dev_put(sibling); 3190 } 3191 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547, 3192 quirk_apple_wait_for_thunderbolt); 3193 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d, 3194 quirk_apple_wait_for_thunderbolt); 3195 #endif 3196 3197 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 3198 struct pci_fixup *end) 3199 { 3200 ktime_t calltime; 3201 3202 for (; f < end; f++) 3203 if ((f->class == (u32) (dev->class >> f->class_shift) || 3204 f->class == (u32) PCI_ANY_ID) && 3205 (f->vendor == dev->vendor || 3206 f->vendor == (u16) PCI_ANY_ID) && 3207 (f->device == dev->device || 3208 f->device == (u16) PCI_ANY_ID)) { 3209 calltime = fixup_debug_start(dev, f->hook); 3210 f->hook(dev); 3211 fixup_debug_report(dev, calltime, f->hook); 3212 } 3213 } 3214 3215 extern struct pci_fixup __start_pci_fixups_early[]; 3216 extern struct pci_fixup __end_pci_fixups_early[]; 3217 extern struct pci_fixup __start_pci_fixups_header[]; 3218 extern struct pci_fixup __end_pci_fixups_header[]; 3219 extern struct pci_fixup __start_pci_fixups_final[]; 3220 extern struct pci_fixup __end_pci_fixups_final[]; 3221 extern struct pci_fixup __start_pci_fixups_enable[]; 3222 extern struct pci_fixup __end_pci_fixups_enable[]; 3223 extern struct pci_fixup __start_pci_fixups_resume[]; 3224 extern struct pci_fixup __end_pci_fixups_resume[]; 3225 extern struct pci_fixup __start_pci_fixups_resume_early[]; 3226 extern struct pci_fixup __end_pci_fixups_resume_early[]; 3227 extern struct pci_fixup __start_pci_fixups_suspend[]; 3228 extern struct pci_fixup __end_pci_fixups_suspend[]; 3229 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 3230 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 3231 3232 static bool pci_apply_fixup_final_quirks; 3233 3234 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 3235 { 3236 struct pci_fixup *start, *end; 3237 3238 switch (pass) { 3239 case pci_fixup_early: 3240 start = __start_pci_fixups_early; 3241 end = __end_pci_fixups_early; 3242 break; 3243 3244 case pci_fixup_header: 3245 start = __start_pci_fixups_header; 3246 end = __end_pci_fixups_header; 3247 break; 3248 3249 case pci_fixup_final: 3250 if (!pci_apply_fixup_final_quirks) 3251 return; 3252 start = __start_pci_fixups_final; 3253 end = __end_pci_fixups_final; 3254 break; 3255 3256 case pci_fixup_enable: 3257 start = __start_pci_fixups_enable; 3258 end = __end_pci_fixups_enable; 3259 break; 3260 3261 case pci_fixup_resume: 3262 start = __start_pci_fixups_resume; 3263 end = __end_pci_fixups_resume; 3264 break; 3265 3266 case pci_fixup_resume_early: 3267 start = __start_pci_fixups_resume_early; 3268 end = __end_pci_fixups_resume_early; 3269 break; 3270 3271 case pci_fixup_suspend: 3272 start = __start_pci_fixups_suspend; 3273 end = __end_pci_fixups_suspend; 3274 break; 3275 3276 case pci_fixup_suspend_late: 3277 start = __start_pci_fixups_suspend_late; 3278 end = __end_pci_fixups_suspend_late; 3279 break; 3280 3281 default: 3282 /* stupid compiler warning, you would think with an enum... */ 3283 return; 3284 } 3285 pci_do_fixups(dev, start, end); 3286 } 3287 EXPORT_SYMBOL(pci_fixup_device); 3288 3289 3290 static int __init pci_apply_final_quirks(void) 3291 { 3292 struct pci_dev *dev = NULL; 3293 u8 cls = 0; 3294 u8 tmp; 3295 3296 if (pci_cache_line_size) 3297 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3298 pci_cache_line_size << 2); 3299 3300 pci_apply_fixup_final_quirks = true; 3301 for_each_pci_dev(dev) { 3302 pci_fixup_device(pci_fixup_final, dev); 3303 /* 3304 * If arch hasn't set it explicitly yet, use the CLS 3305 * value shared by all PCI devices. If there's a 3306 * mismatch, fall back to the default value. 3307 */ 3308 if (!pci_cache_line_size) { 3309 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3310 if (!cls) 3311 cls = tmp; 3312 if (!tmp || cls == tmp) 3313 continue; 3314 3315 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 3316 cls << 2, tmp << 2, 3317 pci_dfl_cache_line_size << 2); 3318 pci_cache_line_size = pci_dfl_cache_line_size; 3319 } 3320 } 3321 3322 if (!pci_cache_line_size) { 3323 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3324 cls << 2, pci_dfl_cache_line_size << 2); 3325 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3326 } 3327 3328 return 0; 3329 } 3330 3331 fs_initcall_sync(pci_apply_final_quirks); 3332 3333 /* 3334 * Followings are device-specific reset methods which can be used to 3335 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3336 * not available. 3337 */ 3338 static int reset_intel_generic_dev(struct pci_dev *dev, int probe) 3339 { 3340 int pos; 3341 3342 /* only implement PCI_CLASS_SERIAL_USB at present */ 3343 if (dev->class == PCI_CLASS_SERIAL_USB) { 3344 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 3345 if (!pos) 3346 return -ENOTTY; 3347 3348 if (probe) 3349 return 0; 3350 3351 pci_write_config_byte(dev, pos + 0x4, 1); 3352 msleep(100); 3353 3354 return 0; 3355 } else { 3356 return -ENOTTY; 3357 } 3358 } 3359 3360 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3361 { 3362 /* 3363 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3364 * 3365 * The 82599 supports FLR on VFs, but FLR support is reported only 3366 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3367 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP. 3368 */ 3369 3370 if (probe) 3371 return 0; 3372 3373 if (!pci_wait_for_pending_transaction(dev)) 3374 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3375 3376 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3377 3378 msleep(100); 3379 3380 return 0; 3381 } 3382 3383 #include "../gpu/drm/i915/i915_reg.h" 3384 #define MSG_CTL 0x45010 3385 #define NSDE_PWR_STATE 0xd0100 3386 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3387 3388 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3389 { 3390 void __iomem *mmio_base; 3391 unsigned long timeout; 3392 u32 val; 3393 3394 if (probe) 3395 return 0; 3396 3397 mmio_base = pci_iomap(dev, 0, 0); 3398 if (!mmio_base) 3399 return -ENOMEM; 3400 3401 iowrite32(0x00000002, mmio_base + MSG_CTL); 3402 3403 /* 3404 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3405 * driver loaded sets the right bits. However, this's a reset and 3406 * the bits have been set by i915 previously, so we clobber 3407 * SOUTH_CHICKEN2 register directly here. 3408 */ 3409 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3410 3411 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3412 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3413 3414 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3415 do { 3416 val = ioread32(mmio_base + PCH_PP_STATUS); 3417 if ((val & 0xb0000000) == 0) 3418 goto reset_complete; 3419 msleep(10); 3420 } while (time_before(jiffies, timeout)); 3421 dev_warn(&dev->dev, "timeout during reset\n"); 3422 3423 reset_complete: 3424 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3425 3426 pci_iounmap(dev, mmio_base); 3427 return 0; 3428 } 3429 3430 /* 3431 * Device-specific reset method for Chelsio T4-based adapters. 3432 */ 3433 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3434 { 3435 u16 old_command; 3436 u16 msix_flags; 3437 3438 /* 3439 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3440 * that we have no device-specific reset method. 3441 */ 3442 if ((dev->device & 0xf000) != 0x4000) 3443 return -ENOTTY; 3444 3445 /* 3446 * If this is the "probe" phase, return 0 indicating that we can 3447 * reset this device. 3448 */ 3449 if (probe) 3450 return 0; 3451 3452 /* 3453 * T4 can wedge if there are DMAs in flight within the chip and Bus 3454 * Master has been disabled. We need to have it on till the Function 3455 * Level Reset completes. (BUS_MASTER is disabled in 3456 * pci_reset_function()). 3457 */ 3458 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3459 pci_write_config_word(dev, PCI_COMMAND, 3460 old_command | PCI_COMMAND_MASTER); 3461 3462 /* 3463 * Perform the actual device function reset, saving and restoring 3464 * configuration information around the reset. 3465 */ 3466 pci_save_state(dev); 3467 3468 /* 3469 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3470 * are disabled when an MSI-X interrupt message needs to be delivered. 3471 * So we briefly re-enable MSI-X interrupts for the duration of the 3472 * FLR. The pci_restore_state() below will restore the original 3473 * MSI-X state. 3474 */ 3475 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3476 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3477 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3478 msix_flags | 3479 PCI_MSIX_FLAGS_ENABLE | 3480 PCI_MSIX_FLAGS_MASKALL); 3481 3482 /* 3483 * Start of pcie_flr() code sequence. This reset code is a copy of 3484 * the guts of pcie_flr() because that's not an exported function. 3485 */ 3486 3487 if (!pci_wait_for_pending_transaction(dev)) 3488 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3489 3490 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3491 msleep(100); 3492 3493 /* 3494 * End of pcie_flr() code sequence. 3495 */ 3496 3497 /* 3498 * Restore the configuration information (BAR values, etc.) including 3499 * the original PCI Configuration Space Command word, and return 3500 * success. 3501 */ 3502 pci_restore_state(dev); 3503 pci_write_config_word(dev, PCI_COMMAND, old_command); 3504 return 0; 3505 } 3506 3507 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3508 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3509 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3510 3511 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3512 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3513 reset_intel_82599_sfp_virtfn }, 3514 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3515 reset_ivb_igd }, 3516 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3517 reset_ivb_igd }, 3518 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 3519 reset_intel_generic_dev }, 3520 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3521 reset_chelsio_generic_dev }, 3522 { 0 } 3523 }; 3524 3525 /* 3526 * These device-specific reset methods are here rather than in a driver 3527 * because when a host assigns a device to a guest VM, the host may need 3528 * to reset the device but probably doesn't have a driver for it. 3529 */ 3530 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3531 { 3532 const struct pci_dev_reset_methods *i; 3533 3534 for (i = pci_dev_reset_methods; i->reset; i++) { 3535 if ((i->vendor == dev->vendor || 3536 i->vendor == (u16)PCI_ANY_ID) && 3537 (i->device == dev->device || 3538 i->device == (u16)PCI_ANY_ID)) 3539 return i->reset(dev, probe); 3540 } 3541 3542 return -ENOTTY; 3543 } 3544 3545 static void quirk_dma_func0_alias(struct pci_dev *dev) 3546 { 3547 if (PCI_FUNC(dev->devfn) != 0) { 3548 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0); 3549 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3550 } 3551 } 3552 3553 /* 3554 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3555 * 3556 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3557 */ 3558 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3559 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3560 3561 static void quirk_dma_func1_alias(struct pci_dev *dev) 3562 { 3563 if (PCI_FUNC(dev->devfn) != 1) { 3564 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1); 3565 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3566 } 3567 } 3568 3569 /* 3570 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3571 * SKUs function 1 is present and is a legacy IDE controller, in other 3572 * SKUs this function is not present, making this a ghost requester. 3573 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3574 */ 3575 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3576 quirk_dma_func1_alias); 3577 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3578 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3579 quirk_dma_func1_alias); 3580 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3582 quirk_dma_func1_alias); 3583 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3584 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3585 quirk_dma_func1_alias); 3586 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3588 quirk_dma_func1_alias); 3589 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3591 quirk_dma_func1_alias); 3592 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3593 quirk_dma_func1_alias); 3594 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3596 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3597 quirk_dma_func1_alias); 3598 3599 /* 3600 * Some devices DMA with the wrong devfn, not just the wrong function. 3601 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3602 * the alias is "fixed" and independent of the device devfn. 3603 * 3604 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3605 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3606 * single device on the secondary bus. In reality, the single exposed 3607 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3608 * that provides a bridge to the internal bus of the I/O processor. The 3609 * controller supports private devices, which can be hidden from PCI config 3610 * space. In the case of the Adaptec 3405, a private device at 01.0 3611 * appears to be the DMA engine, which therefore needs to become a DMA 3612 * alias for the device. 3613 */ 3614 static const struct pci_device_id fixed_dma_alias_tbl[] = { 3615 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3616 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3617 .driver_data = PCI_DEVFN(1, 0) }, 3618 { 0 } 3619 }; 3620 3621 static void quirk_fixed_dma_alias(struct pci_dev *dev) 3622 { 3623 const struct pci_device_id *id; 3624 3625 id = pci_match_id(fixed_dma_alias_tbl, dev); 3626 if (id) { 3627 dev->dma_alias_devfn = id->driver_data; 3628 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3629 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", 3630 PCI_SLOT(dev->dma_alias_devfn), 3631 PCI_FUNC(dev->dma_alias_devfn)); 3632 } 3633 } 3634 3635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3636 3637 /* 3638 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3639 * using the wrong DMA alias for the device. Some of these devices can be 3640 * used as either forward or reverse bridges, so we need to test whether the 3641 * device is operating in the correct mode. We could probably apply this 3642 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3643 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3644 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3645 */ 3646 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3647 { 3648 if (!pci_is_root_bus(pdev->bus) && 3649 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3650 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3651 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3652 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3653 } 3654 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3655 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3656 quirk_use_pcie_bridge_dma_alias); 3657 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3658 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3659 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3660 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3661 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3662 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3663 3664 /* 3665 * AMD has indicated that the devices below do not support peer-to-peer 3666 * in any system where they are found in the southbridge with an AMD 3667 * IOMMU in the system. Multifunction devices that do not support 3668 * peer-to-peer between functions can claim to support a subset of ACS. 3669 * Such devices effectively enable request redirect (RR) and completion 3670 * redirect (CR) since all transactions are redirected to the upstream 3671 * root complex. 3672 * 3673 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 3674 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 3675 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 3676 * 3677 * 1002:4385 SBx00 SMBus Controller 3678 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 3679 * 1002:4383 SBx00 Azalia (Intel HDA) 3680 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 3681 * 1002:4384 SBx00 PCI to PCI Bridge 3682 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 3683 * 3684 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 3685 * 3686 * 1022:780f [AMD] FCH PCI Bridge 3687 * 1022:7809 [AMD] FCH USB OHCI Controller 3688 */ 3689 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 3690 { 3691 #ifdef CONFIG_ACPI 3692 struct acpi_table_header *header = NULL; 3693 acpi_status status; 3694 3695 /* Targeting multifunction devices on the SB (appears on root bus) */ 3696 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 3697 return -ENODEV; 3698 3699 /* The IVRS table describes the AMD IOMMU */ 3700 status = acpi_get_table("IVRS", 0, &header); 3701 if (ACPI_FAILURE(status)) 3702 return -ENODEV; 3703 3704 /* Filter out flags not applicable to multifunction */ 3705 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 3706 3707 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 3708 #else 3709 return -ENODEV; 3710 #endif 3711 } 3712 3713 /* 3714 * Many Intel PCH root ports do provide ACS-like features to disable peer 3715 * transactions and validate bus numbers in requests, but do not provide an 3716 * actual PCIe ACS capability. This is the list of device IDs known to fall 3717 * into that category as provided by Intel in Red Hat bugzilla 1037684. 3718 */ 3719 static const u16 pci_quirk_intel_pch_acs_ids[] = { 3720 /* Ibexpeak PCH */ 3721 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 3722 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 3723 /* Cougarpoint PCH */ 3724 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 3725 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 3726 /* Pantherpoint PCH */ 3727 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 3728 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 3729 /* Lynxpoint-H PCH */ 3730 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 3731 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 3732 /* Lynxpoint-LP PCH */ 3733 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 3734 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 3735 /* Wildcat PCH */ 3736 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 3737 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 3738 /* Patsburg (X79) PCH */ 3739 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 3740 /* Wellsburg (X99) PCH */ 3741 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 3742 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 3743 }; 3744 3745 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 3746 { 3747 int i; 3748 3749 /* Filter out a few obvious non-matches first */ 3750 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 3751 return false; 3752 3753 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 3754 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 3755 return true; 3756 3757 return false; 3758 } 3759 3760 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 3761 3762 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 3763 { 3764 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 3765 INTEL_PCH_ACS_FLAGS : 0; 3766 3767 if (!pci_quirk_intel_pch_acs_match(dev)) 3768 return -ENOTTY; 3769 3770 return acs_flags & ~flags ? 0 : 1; 3771 } 3772 3773 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 3774 { 3775 /* 3776 * SV, TB, and UF are not relevant to multifunction endpoints. 3777 * 3778 * Multifunction devices are only required to implement RR, CR, and DT 3779 * in their ACS capability if they support peer-to-peer transactions. 3780 * Devices matching this quirk have been verified by the vendor to not 3781 * perform peer-to-peer with other functions, allowing us to mask out 3782 * these bits as if they were unimplemented in the ACS capability. 3783 */ 3784 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 3785 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 3786 3787 return acs_flags ? 0 : 1; 3788 } 3789 3790 static const struct pci_dev_acs_enabled { 3791 u16 vendor; 3792 u16 device; 3793 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 3794 } pci_dev_acs_enabled[] = { 3795 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 3796 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 3797 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 3798 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 3799 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 3800 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 3801 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 3802 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 3803 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 3804 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 3805 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 3806 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 3807 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 3808 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 3809 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 3810 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 3811 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 3812 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 3813 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 3814 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 3815 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 3816 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 3817 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 3818 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 3819 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 3820 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 3821 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 3822 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 3823 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 3824 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 3825 /* 82580 */ 3826 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 3827 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 3828 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 3829 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 3830 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 3831 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 3832 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 3833 /* 82576 */ 3834 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 3835 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 3836 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 3837 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 3838 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 3839 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 3840 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 3841 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 3842 /* 82575 */ 3843 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 3844 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 3845 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 3846 /* I350 */ 3847 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 3848 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 3849 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 3850 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 3851 /* 82571 (Quads omitted due to non-ACS switch) */ 3852 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 3853 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 3854 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 3855 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 3856 /* Intel PCH root ports */ 3857 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 3858 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 3859 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 3860 { 0 } 3861 }; 3862 3863 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 3864 { 3865 const struct pci_dev_acs_enabled *i; 3866 int ret; 3867 3868 /* 3869 * Allow devices that do not expose standard PCIe ACS capabilities 3870 * or control to indicate their support here. Multi-function express 3871 * devices which do not allow internal peer-to-peer between functions, 3872 * but do not implement PCIe ACS may wish to return true here. 3873 */ 3874 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 3875 if ((i->vendor == dev->vendor || 3876 i->vendor == (u16)PCI_ANY_ID) && 3877 (i->device == dev->device || 3878 i->device == (u16)PCI_ANY_ID)) { 3879 ret = i->acs_enabled(dev, acs_flags); 3880 if (ret >= 0) 3881 return ret; 3882 } 3883 } 3884 3885 return -ENOTTY; 3886 } 3887 3888 /* Config space offset of Root Complex Base Address register */ 3889 #define INTEL_LPC_RCBA_REG 0xf0 3890 /* 31:14 RCBA address */ 3891 #define INTEL_LPC_RCBA_MASK 0xffffc000 3892 /* RCBA Enable */ 3893 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 3894 3895 /* Backbone Scratch Pad Register */ 3896 #define INTEL_BSPR_REG 0x1104 3897 /* Backbone Peer Non-Posted Disable */ 3898 #define INTEL_BSPR_REG_BPNPD (1 << 8) 3899 /* Backbone Peer Posted Disable */ 3900 #define INTEL_BSPR_REG_BPPD (1 << 9) 3901 3902 /* Upstream Peer Decode Configuration Register */ 3903 #define INTEL_UPDCR_REG 0x1114 3904 /* 5:0 Peer Decode Enable bits */ 3905 #define INTEL_UPDCR_REG_MASK 0x3f 3906 3907 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 3908 { 3909 u32 rcba, bspr, updcr; 3910 void __iomem *rcba_mem; 3911 3912 /* 3913 * Read the RCBA register from the LPC (D31:F0). PCH root ports 3914 * are D28:F* and therefore get probed before LPC, thus we can't 3915 * use pci_get_slot/pci_read_config_dword here. 3916 */ 3917 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 3918 INTEL_LPC_RCBA_REG, &rcba); 3919 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 3920 return -EINVAL; 3921 3922 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 3923 PAGE_ALIGN(INTEL_UPDCR_REG)); 3924 if (!rcba_mem) 3925 return -ENOMEM; 3926 3927 /* 3928 * The BSPR can disallow peer cycles, but it's set by soft strap and 3929 * therefore read-only. If both posted and non-posted peer cycles are 3930 * disallowed, we're ok. If either are allowed, then we need to use 3931 * the UPDCR to disable peer decodes for each port. This provides the 3932 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 3933 */ 3934 bspr = readl(rcba_mem + INTEL_BSPR_REG); 3935 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 3936 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 3937 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 3938 if (updcr & INTEL_UPDCR_REG_MASK) { 3939 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); 3940 updcr &= ~INTEL_UPDCR_REG_MASK; 3941 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 3942 } 3943 } 3944 3945 iounmap(rcba_mem); 3946 return 0; 3947 } 3948 3949 /* Miscellaneous Port Configuration register */ 3950 #define INTEL_MPC_REG 0xd8 3951 /* MPC: Invalid Receive Bus Number Check Enable */ 3952 #define INTEL_MPC_REG_IRBNCE (1 << 26) 3953 3954 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 3955 { 3956 u32 mpc; 3957 3958 /* 3959 * When enabled, the IRBNCE bit of the MPC register enables the 3960 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 3961 * ensures that requester IDs fall within the bus number range 3962 * of the bridge. Enable if not already. 3963 */ 3964 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 3965 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 3966 dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); 3967 mpc |= INTEL_MPC_REG_IRBNCE; 3968 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 3969 } 3970 } 3971 3972 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 3973 { 3974 if (!pci_quirk_intel_pch_acs_match(dev)) 3975 return -ENOTTY; 3976 3977 if (pci_quirk_enable_intel_lpc_acs(dev)) { 3978 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); 3979 return 0; 3980 } 3981 3982 pci_quirk_enable_intel_rp_mpc_acs(dev); 3983 3984 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 3985 3986 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); 3987 3988 return 0; 3989 } 3990 3991 static const struct pci_dev_enable_acs { 3992 u16 vendor; 3993 u16 device; 3994 int (*enable_acs)(struct pci_dev *dev); 3995 } pci_dev_enable_acs[] = { 3996 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, 3997 { 0 } 3998 }; 3999 4000 void pci_dev_specific_enable_acs(struct pci_dev *dev) 4001 { 4002 const struct pci_dev_enable_acs *i; 4003 int ret; 4004 4005 for (i = pci_dev_enable_acs; i->enable_acs; i++) { 4006 if ((i->vendor == dev->vendor || 4007 i->vendor == (u16)PCI_ANY_ID) && 4008 (i->device == dev->device || 4009 i->device == (u16)PCI_ANY_ID)) { 4010 ret = i->enable_acs(dev); 4011 if (ret >= 0) 4012 return; 4013 } 4014 } 4015 } 4016