1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18 #include <linux/config.h> 19 #include <linux/types.h> 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/acpi.h> 25 #include "pci.h" 26 27 /* The Mellanox Tavor device gives false positive parity errors 28 * Mark this device with a broken_parity_status, to allow 29 * PCI scanning code to "skip" this now blacklisted device. 30 */ 31 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 32 { 33 dev->broken_parity_status = 1; /* This device gives false positives */ 34 } 35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 36 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 37 38 /* Deal with broken BIOS'es that neglect to enable passive release, 39 which can cause problems in combination with the 82441FX/PPro MTRRs */ 40 static void __devinit quirk_passive_release(struct pci_dev *dev) 41 { 42 struct pci_dev *d = NULL; 43 unsigned char dlc; 44 45 /* We have to make sure a particular bit is set in the PIIX3 46 ISA bridge, so we have to go out and find it. */ 47 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 48 pci_read_config_byte(d, 0x82, &dlc); 49 if (!(dlc & 1<<1)) { 50 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 51 dlc |= 1<<1; 52 pci_write_config_byte(d, 0x82, dlc); 53 } 54 } 55 } 56 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 57 58 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 59 but VIA don't answer queries. If you happen to have good contacts at VIA 60 ask them for me please -- Alan 61 62 This appears to be BIOS not version dependent. So presumably there is a 63 chipset level fix */ 64 int isa_dma_bridge_buggy; /* Exported */ 65 66 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 67 { 68 if (!isa_dma_bridge_buggy) { 69 isa_dma_bridge_buggy=1; 70 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 71 } 72 } 73 /* 74 * Its not totally clear which chipsets are the problematic ones 75 * We know 82C586 and 82C596 variants are affected. 76 */ 77 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 78 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 84 85 int pci_pci_problems; 86 87 /* 88 * Chipsets where PCI->PCI transfers vanish or hang 89 */ 90 static void __devinit quirk_nopcipci(struct pci_dev *dev) 91 { 92 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 93 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 94 pci_pci_problems |= PCIPCI_FAIL; 95 } 96 } 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 99 100 /* 101 * Triton requires workarounds to be used by the drivers 102 */ 103 static void __devinit quirk_triton(struct pci_dev *dev) 104 { 105 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 106 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 107 pci_pci_problems |= PCIPCI_TRITON; 108 } 109 } 110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 114 115 /* 116 * VIA Apollo KT133 needs PCI latency patch 117 * Made according to a windows driver based patch by George E. Breese 118 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 119 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 120 * the info on which Mr Breese based his work. 121 * 122 * Updated based on further information from the site and also on 123 * information provided by VIA 124 */ 125 static void __devinit quirk_vialatency(struct pci_dev *dev) 126 { 127 struct pci_dev *p; 128 u8 rev; 129 u8 busarb; 130 /* Ok we have a potential problem chipset here. Now see if we have 131 a buggy southbridge */ 132 133 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 134 if (p!=NULL) { 135 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 136 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 137 /* Check for buggy part revisions */ 138 if (rev < 0x40 || rev > 0x42) 139 goto exit; 140 } else { 141 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 142 if (p==NULL) /* No problem parts */ 143 goto exit; 144 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 145 /* Check for buggy part revisions */ 146 if (rev < 0x10 || rev > 0x12) 147 goto exit; 148 } 149 150 /* 151 * Ok we have the problem. Now set the PCI master grant to 152 * occur every master grant. The apparent bug is that under high 153 * PCI load (quite common in Linux of course) you can get data 154 * loss when the CPU is held off the bus for 3 bus master requests 155 * This happens to include the IDE controllers.... 156 * 157 * VIA only apply this fix when an SB Live! is present but under 158 * both Linux and Windows this isnt enough, and we have seen 159 * corruption without SB Live! but with things like 3 UDMA IDE 160 * controllers. So we ignore that bit of the VIA recommendation.. 161 */ 162 163 pci_read_config_byte(dev, 0x76, &busarb); 164 /* Set bit 4 and bi 5 of byte 76 to 0x01 165 "Master priority rotation on every PCI master grant */ 166 busarb &= ~(1<<5); 167 busarb |= (1<<4); 168 pci_write_config_byte(dev, 0x76, busarb); 169 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 170 exit: 171 pci_dev_put(p); 172 } 173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 176 177 /* 178 * VIA Apollo VP3 needs ETBF on BT848/878 179 */ 180 static void __devinit quirk_viaetbf(struct pci_dev *dev) 181 { 182 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 183 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 184 pci_pci_problems |= PCIPCI_VIAETBF; 185 } 186 } 187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 188 189 static void __devinit quirk_vsfx(struct pci_dev *dev) 190 { 191 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 192 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 193 pci_pci_problems |= PCIPCI_VSFX; 194 } 195 } 196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 197 198 /* 199 * Ali Magik requires workarounds to be used by the drivers 200 * that DMA to AGP space. Latency must be set to 0xA and triton 201 * workaround applied too 202 * [Info kindly provided by ALi] 203 */ 204 static void __init quirk_alimagik(struct pci_dev *dev) 205 { 206 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 208 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 209 } 210 } 211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 213 214 /* 215 * Natoma has some interesting boundary conditions with Zoran stuff 216 * at least 217 */ 218 static void __devinit quirk_natoma(struct pci_dev *dev) 219 { 220 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 221 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 222 pci_pci_problems |= PCIPCI_NATOMA; 223 } 224 } 225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 231 232 /* 233 * This chip can cause PCI parity errors if config register 0xA0 is read 234 * while DMAs are occurring. 235 */ 236 static void __devinit quirk_citrine(struct pci_dev *dev) 237 { 238 dev->cfg_size = 0xA0; 239 } 240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 241 242 /* 243 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 244 * If it's needed, re-allocate the region. 245 */ 246 static void __devinit quirk_s3_64M(struct pci_dev *dev) 247 { 248 struct resource *r = &dev->resource[0]; 249 250 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 251 r->start = 0; 252 r->end = 0x3ffffff; 253 } 254 } 255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 257 258 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 259 unsigned size, int nr, const char *name) 260 { 261 region &= ~(size-1); 262 if (region) { 263 struct pci_bus_region bus_region; 264 struct resource *res = dev->resource + nr; 265 266 res->name = pci_name(dev); 267 res->start = region; 268 res->end = region + size - 1; 269 res->flags = IORESOURCE_IO; 270 271 /* Convert from PCI bus to resource space. */ 272 bus_region.start = res->start; 273 bus_region.end = res->end; 274 pcibios_bus_to_resource(dev, res, &bus_region); 275 276 pci_claim_resource(dev, nr); 277 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 278 } 279 } 280 281 /* 282 * ATI Northbridge setups MCE the processor if you even 283 * read somewhere between 0x3b0->0x3bb or read 0x3d3 284 */ 285 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 286 { 287 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 288 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 289 request_region(0x3b0, 0x0C, "RadeonIGP"); 290 request_region(0x3d3, 0x01, "RadeonIGP"); 291 } 292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 293 294 /* 295 * Let's make the southbridge information explicit instead 296 * of having to worry about people probing the ACPI areas, 297 * for example.. (Yes, it happens, and if you read the wrong 298 * ACPI register it will put the machine to sleep with no 299 * way of waking it up again. Bummer). 300 * 301 * ALI M7101: Two IO regions pointed to by words at 302 * 0xE0 (64 bytes of ACPI registers) 303 * 0xE2 (32 bytes of SMB registers) 304 */ 305 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 306 { 307 u16 region; 308 309 pci_read_config_word(dev, 0xE0, ®ion); 310 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 311 pci_read_config_word(dev, 0xE2, ®ion); 312 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 313 } 314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 315 316 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 317 { 318 u32 devres; 319 u32 mask, size, base; 320 321 pci_read_config_dword(dev, port, &devres); 322 if ((devres & enable) != enable) 323 return; 324 mask = (devres >> 16) & 15; 325 base = devres & 0xffff; 326 size = 16; 327 for (;;) { 328 unsigned bit = size >> 1; 329 if ((bit & mask) == bit) 330 break; 331 size = bit; 332 } 333 /* 334 * For now we only print it out. Eventually we'll want to 335 * reserve it (at least if it's in the 0x1000+ range), but 336 * let's get enough confirmation reports first. 337 */ 338 base &= -size; 339 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); 340 } 341 342 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 343 { 344 u32 devres; 345 u32 mask, size, base; 346 347 pci_read_config_dword(dev, port, &devres); 348 if ((devres & enable) != enable) 349 return; 350 base = devres & 0xffff0000; 351 mask = (devres & 0x3f) << 16; 352 size = 128 << 16; 353 for (;;) { 354 unsigned bit = size >> 1; 355 if ((bit & mask) == bit) 356 break; 357 size = bit; 358 } 359 /* 360 * For now we only print it out. Eventually we'll want to 361 * reserve it, but let's get enough confirmation reports first. 362 */ 363 base &= -size; 364 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); 365 } 366 367 /* 368 * PIIX4 ACPI: Two IO regions pointed to by longwords at 369 * 0x40 (64 bytes of ACPI registers) 370 * 0x90 (16 bytes of SMB registers) 371 * and a few strange programmable PIIX4 device resources. 372 */ 373 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 374 { 375 u32 region, res_a; 376 377 pci_read_config_dword(dev, 0x40, ®ion); 378 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 379 pci_read_config_dword(dev, 0x90, ®ion); 380 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 381 382 /* Device resource A has enables for some of the other ones */ 383 pci_read_config_dword(dev, 0x5c, &res_a); 384 385 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 386 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 387 388 /* Device resource D is just bitfields for static resources */ 389 390 /* Device 12 enabled? */ 391 if (res_a & (1 << 29)) { 392 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 393 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 394 } 395 /* Device 13 enabled? */ 396 if (res_a & (1 << 30)) { 397 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 398 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 399 } 400 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 401 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 402 } 403 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 404 405 /* 406 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 407 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 408 * 0x58 (64 bytes of GPIO I/O space) 409 */ 410 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 411 { 412 u32 region; 413 414 pci_read_config_dword(dev, 0x40, ®ion); 415 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); 416 417 pci_read_config_dword(dev, 0x58, ®ion); 418 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 419 } 420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 428 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 429 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 430 431 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) 432 { 433 u32 region; 434 435 pci_read_config_dword(dev, 0x40, ®ion); 436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); 437 438 pci_read_config_dword(dev, 0x48, ®ion); 439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 440 } 441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); 442 443 /* 444 * VIA ACPI: One IO region pointed to by longword at 445 * 0x48 or 0x20 (256 bytes of ACPI registers) 446 */ 447 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 448 { 449 u8 rev; 450 u32 region; 451 452 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 453 if (rev & 0x10) { 454 pci_read_config_dword(dev, 0x48, ®ion); 455 region &= PCI_BASE_ADDRESS_IO_MASK; 456 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 457 } 458 } 459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 460 461 /* 462 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 463 * 0x48 (256 bytes of ACPI registers) 464 * 0x70 (128 bytes of hardware monitoring register) 465 * 0x90 (16 bytes of SMB registers) 466 */ 467 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 468 { 469 u16 hm; 470 u32 smb; 471 472 quirk_vt82c586_acpi(dev); 473 474 pci_read_config_word(dev, 0x70, &hm); 475 hm &= PCI_BASE_ADDRESS_IO_MASK; 476 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 477 478 pci_read_config_dword(dev, 0x90, &smb); 479 smb &= PCI_BASE_ADDRESS_IO_MASK; 480 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 481 } 482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 483 484 /* 485 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 486 * 0x88 (128 bytes of power management registers) 487 * 0xd0 (16 bytes of SMB registers) 488 */ 489 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 490 { 491 u16 pm, smb; 492 493 pci_read_config_word(dev, 0x88, &pm); 494 pm &= PCI_BASE_ADDRESS_IO_MASK; 495 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 496 497 pci_read_config_word(dev, 0xd0, &smb); 498 smb &= PCI_BASE_ADDRESS_IO_MASK; 499 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 500 } 501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 502 503 504 #ifdef CONFIG_X86_IO_APIC 505 506 #include <asm/io_apic.h> 507 508 /* 509 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 510 * devices to the external APIC. 511 * 512 * TODO: When we have device-specific interrupt routers, 513 * this code will go away from quirks. 514 */ 515 static void __devinit quirk_via_ioapic(struct pci_dev *dev) 516 { 517 u8 tmp; 518 519 if (nr_ioapics < 1) 520 tmp = 0; /* nothing routed to external APIC */ 521 else 522 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 523 524 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 525 tmp == 0 ? "Disa" : "Ena"); 526 527 /* Offset 0x58: External APIC IRQ output control */ 528 pci_write_config_byte (dev, 0x58, tmp); 529 } 530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 531 532 /* 533 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 534 * This leads to doubled level interrupt rates. 535 * Set this bit to get rid of cycle wastage. 536 * Otherwise uncritical. 537 */ 538 static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 539 { 540 u8 misc_control2; 541 #define BYPASS_APIC_DEASSERT 8 542 543 pci_read_config_byte(dev, 0x5B, &misc_control2); 544 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 545 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); 546 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 547 } 548 } 549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 550 551 /* 552 * The AMD io apic can hang the box when an apic irq is masked. 553 * We check all revs >= B0 (yet not in the pre production!) as the bug 554 * is currently marked NoFix 555 * 556 * We have multiple reports of hangs with this chipset that went away with 557 * noapic specified. For the moment we assume its the errata. We may be wrong 558 * of course. However the advice is demonstrably good even if so.. 559 */ 560 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 561 { 562 u8 rev; 563 564 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 565 if (rev >= 0x02) { 566 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n"); 567 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 568 } 569 } 570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 571 572 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 573 { 574 if (dev->devfn == 0 && dev->bus->number == 0) 575 sis_apic_bug = 1; 576 } 577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 578 579 int pci_msi_quirk; 580 581 #define AMD8131_revA0 0x01 582 #define AMD8131_revB0 0x11 583 #define AMD8131_MISC 0x40 584 #define AMD8131_NIOAMODE_BIT 0 585 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) 586 { 587 unsigned char revid, tmp; 588 589 if (dev->subordinate) { 590 printk(KERN_WARNING "PCI: MSI quirk detected. " 591 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n"); 592 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 593 } 594 595 if (nr_ioapics == 0) 596 return; 597 598 pci_read_config_byte(dev, PCI_REVISION_ID, &revid); 599 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { 600 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 601 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 602 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 603 pci_write_config_byte( dev, AMD8131_MISC, tmp); 604 } 605 } 606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); 607 608 static void __init quirk_svw_msi(struct pci_dev *dev) 609 { 610 pci_msi_quirk = 1; 611 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 612 } 613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi ); 614 #endif /* CONFIG_X86_IO_APIC */ 615 616 617 /* 618 * FIXME: it is questionable that quirk_via_acpi 619 * is needed. It shows up as an ISA bridge, and does not 620 * support the PCI_INTERRUPT_LINE register at all. Therefore 621 * it seems like setting the pci_dev's 'irq' to the 622 * value of the ACPI SCI interrupt is only done for convenience. 623 * -jgarzik 624 */ 625 static void __devinit quirk_via_acpi(struct pci_dev *d) 626 { 627 /* 628 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 629 */ 630 u8 irq; 631 pci_read_config_byte(d, 0x42, &irq); 632 irq &= 0xf; 633 if (irq && (irq != 2)) 634 d->irq = irq; 635 } 636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 638 639 /* 640 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip 641 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: 642 * when written, it makes an internal connection to the PIC. 643 * For these devices, this register is defined to be 4 bits wide. 644 * Normally this is fine. However for IO-APIC motherboards, or 645 * non-x86 architectures (yes Via exists on PPC among other places), 646 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get 647 * interrupts delivered properly. 648 * 649 * Some of the on-chip devices are actually '586 devices' so they are 650 * listed here. 651 */ 652 static void quirk_via_irq(struct pci_dev *dev) 653 { 654 u8 irq, new_irq; 655 656 new_irq = dev->irq & 0xf; 657 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 658 if (new_irq != irq) { 659 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n", 660 pci_name(dev), irq, new_irq); 661 udelay(15); /* unknown if delay really needed */ 662 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 663 } 664 } 665 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq); 666 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq); 667 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq); 668 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq); 669 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq); 670 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq); 671 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq); 672 673 /* 674 * VIA VT82C598 has its device ID settable and many BIOSes 675 * set it to the ID of VT82C597 for backward compatibility. 676 * We need to switch it off to be able to recognize the real 677 * type of the chip. 678 */ 679 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 680 { 681 pci_write_config_byte(dev, 0xfc, 0); 682 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 683 } 684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 685 686 /* 687 * CardBus controllers have a legacy base address that enables them 688 * to respond as i82365 pcmcia controllers. We don't want them to 689 * do this even if the Linux CardBus driver is not loaded, because 690 * the Linux i82365 driver does not (and should not) handle CardBus. 691 */ 692 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) 693 { 694 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 695 return; 696 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 697 } 698 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 699 700 /* 701 * Following the PCI ordering rules is optional on the AMD762. I'm not 702 * sure what the designers were smoking but let's not inhale... 703 * 704 * To be fair to AMD, it follows the spec by default, its BIOS people 705 * who turn it off! 706 */ 707 static void __devinit quirk_amd_ordering(struct pci_dev *dev) 708 { 709 u32 pcic; 710 pci_read_config_dword(dev, 0x4C, &pcic); 711 if ((pcic&6)!=6) { 712 pcic |= 6; 713 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 714 pci_write_config_dword(dev, 0x4C, pcic); 715 pci_read_config_dword(dev, 0x84, &pcic); 716 pcic |= (1<<23); /* Required in this mode */ 717 pci_write_config_dword(dev, 0x84, pcic); 718 } 719 } 720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 721 722 /* 723 * DreamWorks provided workaround for Dunord I-3000 problem 724 * 725 * This card decodes and responds to addresses not apparently 726 * assigned to it. We force a larger allocation to ensure that 727 * nothing gets put too close to it. 728 */ 729 static void __devinit quirk_dunord ( struct pci_dev * dev ) 730 { 731 struct resource *r = &dev->resource [1]; 732 r->start = 0; 733 r->end = 0xffffff; 734 } 735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 736 737 /* 738 * i82380FB mobile docking controller: its PCI-to-PCI bridge 739 * is subtractive decoding (transparent), and does indicate this 740 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 741 * instead of 0x01. 742 */ 743 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 744 { 745 dev->transparent = 1; 746 } 747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 749 750 /* 751 * Common misconfiguration of the MediaGX/Geode PCI master that will 752 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 753 * datasheets found at http://www.national.com/ds/GX for info on what 754 * these bits do. <christer@weinigel.se> 755 */ 756 static void __init quirk_mediagx_master(struct pci_dev *dev) 757 { 758 u8 reg; 759 pci_read_config_byte(dev, 0x41, ®); 760 if (reg & 2) { 761 reg &= ~2; 762 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 763 pci_write_config_byte(dev, 0x41, reg); 764 } 765 } 766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 767 768 /* 769 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers 770 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and 771 * secondary channels respectively). If the device reports Compatible mode 772 * but does use BAR0-3 for address decoding, we assume that firmware has 773 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374). 774 * Exceptions (if they exist) must be handled in chip/architecture specific 775 * fixups. 776 * 777 * Note: for non x86 people. You may need an arch specific quirk to handle 778 * moving IDE devices to native mode as well. Some plug in card devices power 779 * up in compatible mode and assume the BIOS will adjust them. 780 * 781 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as 782 * we do now ? We don't want is pci_enable_device to come along 783 * and assign new resources. Both approaches work for that. 784 */ 785 static void __devinit quirk_ide_bases(struct pci_dev *dev) 786 { 787 struct resource *res; 788 int first_bar = 2, last_bar = 0; 789 790 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 791 return; 792 793 res = &dev->resource[0]; 794 795 /* primary channel: ProgIf bit 0, BAR0, BAR1 */ 796 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { 797 res[0].start = res[0].end = res[0].flags = 0; 798 res[1].start = res[1].end = res[1].flags = 0; 799 first_bar = 0; 800 last_bar = 1; 801 } 802 803 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */ 804 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { 805 res[2].start = res[2].end = res[2].flags = 0; 806 res[3].start = res[3].end = res[3].flags = 0; 807 last_bar = 3; 808 } 809 810 if (!last_bar) 811 return; 812 813 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n", 814 first_bar, last_bar, pci_name(dev)); 815 } 816 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases); 817 818 /* 819 * Ensure C0 rev restreaming is off. This is normally done by 820 * the BIOS but in the odd case it is not the results are corruption 821 * hence the presence of a Linux check 822 */ 823 static void __init quirk_disable_pxb(struct pci_dev *pdev) 824 { 825 u16 config; 826 u8 rev; 827 828 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 829 if (rev != 0x04) /* Only C0 requires this */ 830 return; 831 pci_read_config_word(pdev, 0x40, &config); 832 if (config & (1<<6)) { 833 config &= ~(1<<6); 834 pci_write_config_word(pdev, 0x40, config); 835 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 836 } 837 } 838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 839 840 841 /* 842 * Serverworks CSB5 IDE does not fully support native mode 843 */ 844 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 845 { 846 u8 prog; 847 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 848 if (prog & 5) { 849 prog &= ~5; 850 pdev->class &= ~5; 851 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 852 /* need to re-assign BARs for compat mode */ 853 quirk_ide_bases(pdev); 854 } 855 } 856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 857 858 /* 859 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 860 */ 861 static void __init quirk_ide_samemode(struct pci_dev *pdev) 862 { 863 u8 prog; 864 865 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 866 867 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 868 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 869 prog &= ~5; 870 pdev->class &= ~5; 871 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 872 /* need to re-assign BARs for compat mode */ 873 quirk_ide_bases(pdev); 874 } 875 } 876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 877 878 /* This was originally an Alpha specific thing, but it really fits here. 879 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 880 */ 881 static void __init quirk_eisa_bridge(struct pci_dev *dev) 882 { 883 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 884 } 885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 886 887 /* 888 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled 889 * when a PCI-Soundcard is added. The BIOS only gives Options 890 * "Disabled" and "AUTO". This Quirk Sets the corresponding 891 * Register-Value to enable the Soundcard. 892 * 893 * FIXME: Presently this quirk will run on anything that has an 8237 894 * which isn't correct, we need to check DMI tables or something in 895 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it 896 * runs everywhere at present we suppress the printk output in most 897 * irrelevant cases. 898 */ 899 static void __init k8t_sound_hostbridge(struct pci_dev *dev) 900 { 901 unsigned char val; 902 903 pci_read_config_byte(dev, 0x50, &val); 904 if (val == 0x88 || val == 0xc8) { 905 /* Assume it's probably a MSI-K8T-Neo2Fir */ 906 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n"); 907 pci_write_config_byte(dev, 0x50, val & (~0x40)); 908 909 /* Verify the Change for Status output */ 910 pci_read_config_byte(dev, 0x50, &val); 911 if (val & 0x40) 912 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n"); 913 else 914 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n"); 915 } 916 } 917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge); 918 919 #ifndef CONFIG_ACPI_SLEEP 920 /* 921 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 922 * is not activated. The myth is that Asus said that they do not want the 923 * users to be irritated by just another PCI Device in the Win98 device 924 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 925 * package 2.7.0 for details) 926 * 927 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 928 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 929 * becomes necessary to do this tweak in two steps -- I've chosen the Host 930 * bridge as trigger. 931 * 932 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram 933 * will cause thermal management to break down, and causing machine to 934 * overheat. 935 */ 936 static int __initdata asus_hides_smbus; 937 938 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 939 { 940 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 941 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 942 switch(dev->subsystem_device) { 943 case 0x8025: /* P4B-LX */ 944 case 0x8070: /* P4B */ 945 case 0x8088: /* P4B533 */ 946 case 0x1626: /* L3C notebook */ 947 asus_hides_smbus = 1; 948 } 949 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 950 switch(dev->subsystem_device) { 951 case 0x80b1: /* P4GE-V */ 952 case 0x80b2: /* P4PE */ 953 case 0x8093: /* P4B533-V */ 954 asus_hides_smbus = 1; 955 } 956 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 957 switch(dev->subsystem_device) { 958 case 0x8030: /* P4T533 */ 959 asus_hides_smbus = 1; 960 } 961 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 962 switch (dev->subsystem_device) { 963 case 0x8070: /* P4G8X Deluxe */ 964 asus_hides_smbus = 1; 965 } 966 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 967 switch (dev->subsystem_device) { 968 case 0x1751: /* M2N notebook */ 969 case 0x1821: /* M5N notebook */ 970 asus_hides_smbus = 1; 971 } 972 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 973 switch (dev->subsystem_device) { 974 case 0x184b: /* W1N notebook */ 975 case 0x186a: /* M6Ne notebook */ 976 asus_hides_smbus = 1; 977 } 978 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { 979 switch (dev->subsystem_device) { 980 case 0x1882: /* M6V notebook */ 981 case 0x1977: /* A6VA notebook */ 982 asus_hides_smbus = 1; 983 } 984 } 985 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 986 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 987 switch(dev->subsystem_device) { 988 case 0x088C: /* HP Compaq nc8000 */ 989 case 0x0890: /* HP Compaq nc6000 */ 990 asus_hides_smbus = 1; 991 } 992 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 993 switch (dev->subsystem_device) { 994 case 0x12bc: /* HP D330L */ 995 case 0x12bd: /* HP D530 */ 996 asus_hides_smbus = 1; 997 } 998 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { 999 switch (dev->subsystem_device) { 1000 case 0x099c: /* HP Compaq nx6110 */ 1001 asus_hides_smbus = 1; 1002 } 1003 } 1004 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { 1005 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1006 switch(dev->subsystem_device) { 1007 case 0x0001: /* Toshiba Satellite A40 */ 1008 asus_hides_smbus = 1; 1009 } 1010 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1011 switch(dev->subsystem_device) { 1012 case 0x0001: /* Toshiba Tecra M2 */ 1013 asus_hides_smbus = 1; 1014 } 1015 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1016 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1017 switch(dev->subsystem_device) { 1018 case 0xC00C: /* Samsung P35 notebook */ 1019 asus_hides_smbus = 1; 1020 } 1021 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1022 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1023 switch(dev->subsystem_device) { 1024 case 0x0058: /* Compaq Evo N620c */ 1025 asus_hides_smbus = 1; 1026 } 1027 } 1028 } 1029 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 1030 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 1031 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 1032 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 1033 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 1034 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 1035 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 1036 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); 1037 1038 static void __init asus_hides_smbus_lpc(struct pci_dev *dev) 1039 { 1040 u16 val; 1041 1042 if (likely(!asus_hides_smbus)) 1043 return; 1044 1045 pci_read_config_word(dev, 0xF2, &val); 1046 if (val & 0x8) { 1047 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1048 pci_read_config_word(dev, 0xF2, &val); 1049 if (val & 0x8) 1050 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1051 else 1052 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 1053 } 1054 } 1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc ); 1061 1062 static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1063 { 1064 u32 val, rcba; 1065 void __iomem *base; 1066 1067 if (likely(!asus_hides_smbus)) 1068 return; 1069 pci_read_config_dword(dev, 0xF0, &rcba); 1070 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ 1071 if (base == NULL) return; 1072 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ 1073 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ 1074 iounmap(base); 1075 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); 1076 } 1077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1078 1079 #endif 1080 1081 /* 1082 * SiS 96x south bridge: BIOS typically hides SMBus device... 1083 */ 1084 static void __init quirk_sis_96x_smbus(struct pci_dev *dev) 1085 { 1086 u8 val = 0; 1087 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 1088 pci_read_config_byte(dev, 0x77, &val); 1089 pci_write_config_byte(dev, 0x77, val & ~0x10); 1090 pci_read_config_byte(dev, 0x77, &val); 1091 } 1092 1093 /* 1094 * ... This is further complicated by the fact that some SiS96x south 1095 * bridges pretend to be 85C503/5513 instead. In that case see if we 1096 * spotted a compatible north bridge to make sure. 1097 * (pci_find_device doesn't work yet) 1098 * 1099 * We can also enable the sis96x bit in the discovery register.. 1100 */ 1101 static int __devinitdata sis_96x_compatible = 0; 1102 1103 #define SIS_DETECT_REGISTER 0x40 1104 1105 static void __init quirk_sis_503(struct pci_dev *dev) 1106 { 1107 u8 reg; 1108 u16 devid; 1109 1110 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1111 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1112 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1113 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1114 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1115 return; 1116 } 1117 1118 /* Make people aware that we changed the config.. */ 1119 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible); 1120 1121 /* 1122 * Ok, it now shows up as a 96x.. The 96x quirks are after 1123 * the 503 quirk in the quirk table, so they'll automatically 1124 * run and enable things like the SMBus device 1125 */ 1126 dev->device = devid; 1127 } 1128 1129 static void __init quirk_sis_96x_compatible(struct pci_dev *dev) 1130 { 1131 sis_96x_compatible = 1; 1132 } 1133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible ); 1134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible ); 1135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible ); 1136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible ); 1137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible ); 1138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible ); 1139 1140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1141 /* 1142 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1143 * and MC97 modem controller are disabled when a second PCI soundcard is 1144 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1145 * -- bjd 1146 */ 1147 static void __init asus_hides_ac97_lpc(struct pci_dev *dev) 1148 { 1149 u8 val; 1150 int asus_hides_ac97 = 0; 1151 1152 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1153 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1154 asus_hides_ac97 = 1; 1155 } 1156 1157 if (!asus_hides_ac97) 1158 return; 1159 1160 pci_read_config_byte(dev, 0x50, &val); 1161 if (val & 0xc0) { 1162 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1163 pci_read_config_byte(dev, 0x50, &val); 1164 if (val & 0xc0) 1165 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1166 else 1167 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); 1168 } 1169 } 1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); 1171 1172 1173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1177 1178 #ifdef CONFIG_X86_IO_APIC 1179 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1180 { 1181 int i; 1182 1183 if ((pdev->class >> 8) != 0xff00) 1184 return; 1185 1186 /* the first BAR is the location of the IO APIC...we must 1187 * not touch this (and it's already covered by the fixmap), so 1188 * forcibly insert it into the resource tree */ 1189 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1190 insert_resource(&iomem_resource, &pdev->resource[0]); 1191 1192 /* The next five BARs all seem to be rubbish, so just clean 1193 * them out */ 1194 for (i=1; i < 6; i++) { 1195 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1196 } 1197 1198 } 1199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1200 #endif 1201 1202 enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 }; 1203 /* Defaults to combined */ 1204 static enum ide_combined_type combined_mode; 1205 1206 static int __init combined_setup(char *str) 1207 { 1208 if (!strncmp(str, "ide", 3)) 1209 combined_mode = IDE; 1210 else if (!strncmp(str, "libata", 6)) 1211 combined_mode = LIBATA; 1212 else /* "combined" or anything else defaults to old behavior */ 1213 combined_mode = COMBINED; 1214 1215 return 1; 1216 } 1217 __setup("combined_mode=", combined_setup); 1218 1219 #ifdef CONFIG_SCSI_SATA_INTEL_COMBINED 1220 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) 1221 { 1222 u8 prog, comb, tmp; 1223 int ich = 0; 1224 1225 /* 1226 * Narrow down to Intel SATA PCI devices. 1227 */ 1228 switch (pdev->device) { 1229 /* PCI ids taken from drivers/scsi/ata_piix.c */ 1230 case 0x24d1: 1231 case 0x24df: 1232 case 0x25a3: 1233 case 0x25b0: 1234 ich = 5; 1235 break; 1236 case 0x2651: 1237 case 0x2652: 1238 case 0x2653: 1239 case 0x2680: /* ESB2 */ 1240 ich = 6; 1241 break; 1242 case 0x27c0: 1243 case 0x27c4: 1244 ich = 7; 1245 break; 1246 case 0x2828: /* ICH8M */ 1247 ich = 8; 1248 break; 1249 default: 1250 /* we do not handle this PCI device */ 1251 return; 1252 } 1253 1254 /* 1255 * Read combined mode register. 1256 */ 1257 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ 1258 1259 if (ich == 5) { 1260 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ 1261 if (tmp == 0x4) /* bits 10x */ 1262 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1263 else if (tmp == 0x6) /* bits 11x */ 1264 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1265 else 1266 return; /* not in combined mode */ 1267 } else { 1268 WARN_ON((ich != 6) && (ich != 7) && (ich != 8)); 1269 tmp &= 0x3; /* interesting bits 1:0 */ 1270 if (tmp & (1 << 0)) 1271 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1272 else if (tmp & (1 << 1)) 1273 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1274 else 1275 return; /* not in combined mode */ 1276 } 1277 1278 /* 1279 * Read programming interface register. 1280 * (Tells us if it's legacy or native mode) 1281 */ 1282 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1283 1284 /* if SATA port is in native mode, we're ok. */ 1285 if (prog & comb) 1286 return; 1287 1288 /* Don't reserve any so the IDE driver can get them (but only if 1289 * combined_mode=ide). 1290 */ 1291 if (combined_mode == IDE) 1292 return; 1293 1294 /* Grab them both for libata if combined_mode=libata. */ 1295 if (combined_mode == LIBATA) { 1296 request_region(0x1f0, 8, "libata"); /* port 0 */ 1297 request_region(0x170, 8, "libata"); /* port 1 */ 1298 return; 1299 } 1300 1301 /* SATA port is in legacy mode. Reserve port so that 1302 * IDE driver does not attempt to use it. If request_region 1303 * fails, it will be obvious at boot time, so we don't bother 1304 * checking return values. 1305 */ 1306 if (comb == (1 << 0)) 1307 request_region(0x1f0, 8, "libata"); /* port 0 */ 1308 else 1309 request_region(0x170, 8, "libata"); /* port 1 */ 1310 } 1311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); 1312 #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */ 1313 1314 1315 int pcie_mch_quirk; 1316 1317 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1318 { 1319 pcie_mch_quirk = 1; 1320 } 1321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1324 1325 1326 /* 1327 * It's possible for the MSI to get corrupted if shpc and acpi 1328 * are used together on certain PXH-based systems. 1329 */ 1330 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1331 { 1332 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), 1333 PCI_CAP_ID_MSI); 1334 dev->no_msi = 1; 1335 1336 printk(KERN_WARNING "PCI: PXH quirk detected, " 1337 "disabling MSI for SHPC device\n"); 1338 } 1339 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1340 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1341 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1342 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1343 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1344 1345 1346 /* 1347 * Fixup the cardbus bridges on the IBM Dock II docking station 1348 */ 1349 static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev) 1350 { 1351 u32 val; 1352 1353 /* 1354 * tie the 2 interrupt pins to INTA, and configure the 1355 * multifunction routing register to handle this. 1356 */ 1357 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) && 1358 (dev->subsystem_device == 0x0148)) { 1359 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge " 1360 "applying quirk\n"); 1361 pci_read_config_dword(dev, 0x8c, &val); 1362 val = ((val & 0xffffff00) | 0x1002); 1363 pci_write_config_dword(dev, 0x8c, val); 1364 pci_read_config_dword(dev, 0x80, &val); 1365 val = ((val & 0x00ffff00) | 0x2864c077); 1366 pci_write_config_dword(dev, 0x80, val); 1367 } 1368 } 1369 1370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, 1371 quirk_ibm_dock2_cardbus); 1372 1373 static void __devinit quirk_netmos(struct pci_dev *dev) 1374 { 1375 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1376 unsigned int num_serial = dev->subsystem_device & 0xf; 1377 1378 /* 1379 * These Netmos parts are multiport serial devices with optional 1380 * parallel ports. Even when parallel ports are present, they 1381 * are identified as class SERIAL, which means the serial driver 1382 * will claim them. To prevent this, mark them as class OTHER. 1383 * These combo devices should be claimed by parport_serial. 1384 * 1385 * The subdevice ID is of the form 0x00PS, where <P> is the number 1386 * of parallel ports and <S> is the number of serial ports. 1387 */ 1388 switch (dev->device) { 1389 case PCI_DEVICE_ID_NETMOS_9735: 1390 case PCI_DEVICE_ID_NETMOS_9745: 1391 case PCI_DEVICE_ID_NETMOS_9835: 1392 case PCI_DEVICE_ID_NETMOS_9845: 1393 case PCI_DEVICE_ID_NETMOS_9855: 1394 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1395 num_parallel) { 1396 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1397 "%u serial); changing class SERIAL to OTHER " 1398 "(use parport_serial)\n", 1399 dev->device, num_parallel, num_serial); 1400 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1401 (dev->class & 0xff); 1402 } 1403 } 1404 } 1405 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1406 1407 1408 static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1409 { 1410 /* rev 1 ncr53c810 chips don't set the class at all which means 1411 * they don't get their resources remapped. Fix that here. 1412 */ 1413 1414 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1415 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); 1416 dev->class = PCI_CLASS_STORAGE_SCSI; 1417 } 1418 } 1419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1420 1421 1422 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1423 { 1424 while (f < end) { 1425 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1426 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1427 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1428 f->hook(dev); 1429 } 1430 f++; 1431 } 1432 } 1433 1434 extern struct pci_fixup __start_pci_fixups_early[]; 1435 extern struct pci_fixup __end_pci_fixups_early[]; 1436 extern struct pci_fixup __start_pci_fixups_header[]; 1437 extern struct pci_fixup __end_pci_fixups_header[]; 1438 extern struct pci_fixup __start_pci_fixups_final[]; 1439 extern struct pci_fixup __end_pci_fixups_final[]; 1440 extern struct pci_fixup __start_pci_fixups_enable[]; 1441 extern struct pci_fixup __end_pci_fixups_enable[]; 1442 1443 1444 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 1445 { 1446 struct pci_fixup *start, *end; 1447 1448 switch(pass) { 1449 case pci_fixup_early: 1450 start = __start_pci_fixups_early; 1451 end = __end_pci_fixups_early; 1452 break; 1453 1454 case pci_fixup_header: 1455 start = __start_pci_fixups_header; 1456 end = __end_pci_fixups_header; 1457 break; 1458 1459 case pci_fixup_final: 1460 start = __start_pci_fixups_final; 1461 end = __end_pci_fixups_final; 1462 break; 1463 1464 case pci_fixup_enable: 1465 start = __start_pci_fixups_enable; 1466 end = __end_pci_fixups_enable; 1467 break; 1468 1469 default: 1470 /* stupid compiler warning, you would think with an enum... */ 1471 return; 1472 } 1473 pci_do_fixups(dev, start, end); 1474 } 1475 1476 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1477 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1478 { 1479 u16 en1k; 1480 u8 io_base_lo, io_limit_lo; 1481 unsigned long base, limit; 1482 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1483 1484 pci_read_config_word(dev, 0x40, &en1k); 1485 1486 if (en1k & 0x200) { 1487 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); 1488 1489 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1490 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1491 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1492 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1493 1494 if (base <= limit) { 1495 res->start = base; 1496 res->end = limit + 0x3ff; 1497 } 1498 } 1499 } 1500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1501 1502 /* Under some circumstances, AER is not linked with extended capabilities. 1503 * Force it to be linked by setting the corresponding control bit in the 1504 * config space. 1505 */ 1506 static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1507 { 1508 uint8_t b; 1509 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1510 if (!(b & 0x20)) { 1511 pci_write_config_byte(dev, 0xf41, b | 0x20); 1512 printk(KERN_INFO 1513 "PCI: Linking AER extended capability on %s\n", 1514 pci_name(dev)); 1515 } 1516 } 1517 } 1518 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1519 quirk_nvidia_ck804_pcie_aer_ext_cap); 1520 1521 EXPORT_SYMBOL(pcie_mch_quirk); 1522 #ifdef CONFIG_HOTPLUG 1523 EXPORT_SYMBOL(pci_fixup_device); 1524 #endif 1525