1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/align.h> 17 #include <linux/bitfield.h> 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/export.h> 21 #include <linux/pci.h> 22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/acpi.h> 26 #include <linux/dmi.h> 27 #include <linux/ioport.h> 28 #include <linux/sched.h> 29 #include <linux/ktime.h> 30 #include <linux/mm.h> 31 #include <linux/nvme.h> 32 #include <linux/platform_data/x86/apple.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/sizes.h> 35 #include <linux/suspend.h> 36 #include <linux/switchtec.h> 37 #include "pci.h" 38 39 static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta) 40 { 41 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) 42 return true; 43 44 return lnksta & PCI_EXP_LNKSTA_LBMS; 45 } 46 47 /* 48 * Retrain the link of a downstream PCIe port by hand if necessary. 49 * 50 * This is needed at least where a downstream port of the ASMedia ASM2824 51 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 52 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 53 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 54 * board. 55 * 56 * In such a configuration the switches are supposed to negotiate the link 57 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 58 * continues switching between the two speeds indefinitely and the data 59 * link layer never reaches the active state, with link training reported 60 * repeatedly active ~84% of the time. Forcing the target link speed to 61 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 62 * each other correctly however. And more interestingly retraining with a 63 * higher target link speed afterwards lets the two successfully negotiate 64 * 5.0GT/s. 65 * 66 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 67 * Link Active status bit and in the failed link training scenario it will 68 * be off along with the Link Bandwidth Management Status indicating that 69 * hardware has changed the link speed or width in an attempt to correct 70 * unreliable link operation. For a port that has been left unconnected 71 * both bits will be clear. So use this information to detect the problem 72 * rather than polling the Link Training bit and watching out for flips or 73 * at least the active status. 74 * 75 * Since the exact nature of the problem isn't known and in principle this 76 * could trigger where an ASM2824 device is downstream rather upstream, 77 * apply this erratum workaround to any downstream ports as long as they 78 * support Link Active reporting and have the Link Control 2 register. 79 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 80 * request a retrain and check the result. 81 * 82 * If this turns out successful and we know by the Vendor:Device ID it is 83 * safe to do so, then lift the restriction, letting the devices negotiate 84 * a higher speed. Also check for a similar 2.5GT/s speed restriction the 85 * firmware may have already arranged and lift it with ports that already 86 * report their data link being up. 87 * 88 * Otherwise revert the speed to the original setting and request a retrain 89 * again to remove any residual state, ignoring the result as it's supposed 90 * to fail anyway. 91 * 92 * Return 0 if the link has been successfully retrained. Return an error 93 * if retraining was not needed or we attempted a retrain and it failed. 94 */ 95 int pcie_failed_link_retrain(struct pci_dev *dev) 96 { 97 static const struct pci_device_id ids[] = { 98 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 99 {} 100 }; 101 u16 lnksta, lnkctl2; 102 int ret = -ENOTTY; 103 104 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 105 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 106 return ret; 107 108 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 109 if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) { 110 u16 oldlnkctl2; 111 112 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 113 114 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2); 115 ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false); 116 if (ret) { 117 pci_info(dev, "retraining failed\n"); 118 pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), 119 true); 120 return ret; 121 } 122 123 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 124 } 125 126 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 127 128 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && 129 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && 130 pci_match_id(ids, dev)) { 131 u32 lnkcap; 132 133 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 134 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 135 ret = pcie_set_target_speed(dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), false); 136 if (ret) { 137 pci_info(dev, "retraining failed\n"); 138 return ret; 139 } 140 } 141 142 return ret; 143 } 144 145 static ktime_t fixup_debug_start(struct pci_dev *dev, 146 void (*fn)(struct pci_dev *dev)) 147 { 148 if (initcall_debug) 149 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 150 151 return ktime_get(); 152 } 153 154 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 155 void (*fn)(struct pci_dev *dev)) 156 { 157 ktime_t delta, rettime; 158 unsigned long long duration; 159 160 rettime = ktime_get(); 161 delta = ktime_sub(rettime, calltime); 162 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 163 if (initcall_debug || duration > 10000) 164 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 165 } 166 167 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 168 struct pci_fixup *end) 169 { 170 ktime_t calltime; 171 172 for (; f < end; f++) 173 if ((f->class == (u32) (dev->class >> f->class_shift) || 174 f->class == (u32) PCI_ANY_ID) && 175 (f->vendor == dev->vendor || 176 f->vendor == (u16) PCI_ANY_ID) && 177 (f->device == dev->device || 178 f->device == (u16) PCI_ANY_ID)) { 179 void (*hook)(struct pci_dev *dev); 180 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 181 hook = offset_to_ptr(&f->hook_offset); 182 #else 183 hook = f->hook; 184 #endif 185 calltime = fixup_debug_start(dev, hook); 186 hook(dev); 187 fixup_debug_report(dev, calltime, hook); 188 } 189 } 190 191 extern struct pci_fixup __start_pci_fixups_early[]; 192 extern struct pci_fixup __end_pci_fixups_early[]; 193 extern struct pci_fixup __start_pci_fixups_header[]; 194 extern struct pci_fixup __end_pci_fixups_header[]; 195 extern struct pci_fixup __start_pci_fixups_final[]; 196 extern struct pci_fixup __end_pci_fixups_final[]; 197 extern struct pci_fixup __start_pci_fixups_enable[]; 198 extern struct pci_fixup __end_pci_fixups_enable[]; 199 extern struct pci_fixup __start_pci_fixups_resume[]; 200 extern struct pci_fixup __end_pci_fixups_resume[]; 201 extern struct pci_fixup __start_pci_fixups_resume_early[]; 202 extern struct pci_fixup __end_pci_fixups_resume_early[]; 203 extern struct pci_fixup __start_pci_fixups_suspend[]; 204 extern struct pci_fixup __end_pci_fixups_suspend[]; 205 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 206 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 207 208 static bool pci_apply_fixup_final_quirks; 209 210 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 211 { 212 struct pci_fixup *start, *end; 213 214 switch (pass) { 215 case pci_fixup_early: 216 start = __start_pci_fixups_early; 217 end = __end_pci_fixups_early; 218 break; 219 220 case pci_fixup_header: 221 start = __start_pci_fixups_header; 222 end = __end_pci_fixups_header; 223 break; 224 225 case pci_fixup_final: 226 if (!pci_apply_fixup_final_quirks) 227 return; 228 start = __start_pci_fixups_final; 229 end = __end_pci_fixups_final; 230 break; 231 232 case pci_fixup_enable: 233 start = __start_pci_fixups_enable; 234 end = __end_pci_fixups_enable; 235 break; 236 237 case pci_fixup_resume: 238 start = __start_pci_fixups_resume; 239 end = __end_pci_fixups_resume; 240 break; 241 242 case pci_fixup_resume_early: 243 start = __start_pci_fixups_resume_early; 244 end = __end_pci_fixups_resume_early; 245 break; 246 247 case pci_fixup_suspend: 248 start = __start_pci_fixups_suspend; 249 end = __end_pci_fixups_suspend; 250 break; 251 252 case pci_fixup_suspend_late: 253 start = __start_pci_fixups_suspend_late; 254 end = __end_pci_fixups_suspend_late; 255 break; 256 257 default: 258 /* stupid compiler warning, you would think with an enum... */ 259 return; 260 } 261 pci_do_fixups(dev, start, end); 262 } 263 EXPORT_SYMBOL(pci_fixup_device); 264 265 static int __init pci_apply_final_quirks(void) 266 { 267 struct pci_dev *dev = NULL; 268 u8 cls = 0; 269 u8 tmp; 270 271 if (pci_cache_line_size) 272 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 273 274 pci_apply_fixup_final_quirks = true; 275 for_each_pci_dev(dev) { 276 pci_fixup_device(pci_fixup_final, dev); 277 /* 278 * If arch hasn't set it explicitly yet, use the CLS 279 * value shared by all PCI devices. If there's a 280 * mismatch, fall back to the default value. 281 */ 282 if (!pci_cache_line_size) { 283 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 284 if (!cls) 285 cls = tmp; 286 if (!tmp || cls == tmp) 287 continue; 288 289 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 290 cls << 2, tmp << 2, 291 pci_dfl_cache_line_size << 2); 292 pci_cache_line_size = pci_dfl_cache_line_size; 293 } 294 } 295 296 if (!pci_cache_line_size) { 297 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 298 pci_dfl_cache_line_size << 2); 299 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 300 } 301 302 return 0; 303 } 304 fs_initcall_sync(pci_apply_final_quirks); 305 306 /* 307 * Decoding should be disabled for a PCI device during BAR sizing to avoid 308 * conflict. But doing so may cause problems on host bridge and perhaps other 309 * key system devices. For devices that need to have mmio decoding always-on, 310 * we need to set the dev->mmio_always_on bit. 311 */ 312 static void quirk_mmio_always_on(struct pci_dev *dev) 313 { 314 dev->mmio_always_on = 1; 315 } 316 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 317 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 318 319 /* 320 * The Mellanox Tavor device gives false positive parity errors. Disable 321 * parity error reporting. 322 */ 323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 325 326 /* 327 * Deal with broken BIOSes that neglect to enable passive release, 328 * which can cause problems in combination with the 82441FX/PPro MTRRs 329 */ 330 static void quirk_passive_release(struct pci_dev *dev) 331 { 332 struct pci_dev *d = NULL; 333 unsigned char dlc; 334 335 /* 336 * We have to make sure a particular bit is set in the PIIX3 337 * ISA bridge, so we have to go out and find it. 338 */ 339 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 340 pci_read_config_byte(d, 0x82, &dlc); 341 if (!(dlc & 1<<1)) { 342 pci_info(d, "PIIX3: Enabling Passive Release\n"); 343 dlc |= 1<<1; 344 pci_write_config_byte(d, 0x82, dlc); 345 } 346 } 347 } 348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 349 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 350 351 #ifdef CONFIG_X86_32 352 /* 353 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 354 * workaround but VIA don't answer queries. If you happen to have good 355 * contacts at VIA ask them for me please -- Alan 356 * 357 * This appears to be BIOS not version dependent. So presumably there is a 358 * chipset level fix. 359 */ 360 static void quirk_isa_dma_hangs(struct pci_dev *dev) 361 { 362 if (!isa_dma_bridge_buggy) { 363 isa_dma_bridge_buggy = 1; 364 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 365 } 366 } 367 /* 368 * It's not totally clear which chipsets are the problematic ones. We know 369 * 82C586 and 82C596 variants are affected. 370 */ 371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 378 #endif 379 380 #ifdef CONFIG_HAS_IOPORT 381 /* 382 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 383 * for some HT machines to use C4 w/o hanging. 384 */ 385 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 386 { 387 u32 pmbase; 388 u16 pm1a; 389 390 pci_read_config_dword(dev, 0x40, &pmbase); 391 pmbase = pmbase & 0xff80; 392 pm1a = inw(pmbase); 393 394 if (pm1a & 0x10) { 395 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 396 outw(0x10, pmbase); 397 } 398 } 399 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 400 #endif 401 402 /* Chipsets where PCI->PCI transfers vanish or hang */ 403 static void quirk_nopcipci(struct pci_dev *dev) 404 { 405 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 406 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 407 pci_pci_problems |= PCIPCI_FAIL; 408 } 409 } 410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 412 413 static void quirk_nopciamd(struct pci_dev *dev) 414 { 415 u8 rev; 416 pci_read_config_byte(dev, 0x08, &rev); 417 if (rev == 0x13) { 418 /* Erratum 24 */ 419 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 420 pci_pci_problems |= PCIAGP_FAIL; 421 } 422 } 423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 424 425 /* Triton requires workarounds to be used by the drivers */ 426 static void quirk_triton(struct pci_dev *dev) 427 { 428 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 429 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 430 pci_pci_problems |= PCIPCI_TRITON; 431 } 432 } 433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 437 438 /* 439 * VIA Apollo KT133 needs PCI latency patch 440 * Made according to a Windows driver-based patch by George E. Breese; 441 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 442 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 443 * which Mr Breese based his work. 444 * 445 * Updated based on further information from the site and also on 446 * information provided by VIA 447 */ 448 static void quirk_vialatency(struct pci_dev *dev) 449 { 450 struct pci_dev *p; 451 u8 busarb; 452 453 /* 454 * Ok, we have a potential problem chipset here. Now see if we have 455 * a buggy southbridge. 456 */ 457 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 458 if (p != NULL) { 459 460 /* 461 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 462 * thanks Dan Hollis. 463 * Check for buggy part revisions 464 */ 465 if (p->revision < 0x40 || p->revision > 0x42) 466 goto exit; 467 } else { 468 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 469 if (p == NULL) /* No problem parts */ 470 goto exit; 471 472 /* Check for buggy part revisions */ 473 if (p->revision < 0x10 || p->revision > 0x12) 474 goto exit; 475 } 476 477 /* 478 * Ok we have the problem. Now set the PCI master grant to occur 479 * every master grant. The apparent bug is that under high PCI load 480 * (quite common in Linux of course) you can get data loss when the 481 * CPU is held off the bus for 3 bus master requests. This happens 482 * to include the IDE controllers.... 483 * 484 * VIA only apply this fix when an SB Live! is present but under 485 * both Linux and Windows this isn't enough, and we have seen 486 * corruption without SB Live! but with things like 3 UDMA IDE 487 * controllers. So we ignore that bit of the VIA recommendation.. 488 */ 489 pci_read_config_byte(dev, 0x76, &busarb); 490 491 /* 492 * Set bit 4 and bit 5 of byte 76 to 0x01 493 * "Master priority rotation on every PCI master grant" 494 */ 495 busarb &= ~(1<<5); 496 busarb |= (1<<4); 497 pci_write_config_byte(dev, 0x76, busarb); 498 pci_info(dev, "Applying VIA southbridge workaround\n"); 499 exit: 500 pci_dev_put(p); 501 } 502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 505 /* Must restore this on a resume from RAM */ 506 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 507 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 508 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 509 510 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 511 static void quirk_viaetbf(struct pci_dev *dev) 512 { 513 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 514 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 515 pci_pci_problems |= PCIPCI_VIAETBF; 516 } 517 } 518 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 519 520 static void quirk_vsfx(struct pci_dev *dev) 521 { 522 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 523 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 524 pci_pci_problems |= PCIPCI_VSFX; 525 } 526 } 527 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 528 529 /* 530 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 531 * space. Latency must be set to 0xA and Triton workaround applied too. 532 * [Info kindly provided by ALi] 533 */ 534 static void quirk_alimagik(struct pci_dev *dev) 535 { 536 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 537 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 538 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 539 } 540 } 541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 543 544 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 545 static void quirk_natoma(struct pci_dev *dev) 546 { 547 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 548 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 549 pci_pci_problems |= PCIPCI_NATOMA; 550 } 551 } 552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 558 559 /* 560 * This chip can cause PCI parity errors if config register 0xA0 is read 561 * while DMAs are occurring. 562 */ 563 static void quirk_citrine(struct pci_dev *dev) 564 { 565 dev->cfg_size = 0xA0; 566 } 567 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 568 569 /* 570 * This chip can cause bus lockups if config addresses above 0x600 571 * are read or written. 572 */ 573 static void quirk_nfp6000(struct pci_dev *dev) 574 { 575 dev->cfg_size = 0x600; 576 } 577 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 578 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 581 582 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 583 static void quirk_extend_bar_to_page(struct pci_dev *dev) 584 { 585 int i; 586 587 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 588 struct resource *r = &dev->resource[i]; 589 const char *r_name = pci_resource_name(dev, i); 590 591 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 592 resource_set_range(r, 0, PAGE_SIZE); 593 r->flags |= IORESOURCE_UNSET; 594 pci_info(dev, "%s %pR: expanded to page size\n", 595 r_name, r); 596 } 597 } 598 } 599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 600 601 /* 602 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 603 * If it's needed, re-allocate the region. 604 */ 605 static void quirk_s3_64M(struct pci_dev *dev) 606 { 607 struct resource *r = &dev->resource[0]; 608 609 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) { 610 r->flags |= IORESOURCE_UNSET; 611 resource_set_range(r, 0, SZ_64M); 612 } 613 } 614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 616 617 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 618 const char *name) 619 { 620 u32 region; 621 struct pci_bus_region bus_region; 622 struct resource *res = pci_resource_n(dev, pos); 623 const char *res_name = pci_resource_name(dev, pos); 624 625 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 626 627 if (!region) 628 return; 629 630 res->name = pci_name(dev); 631 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 632 res->flags |= 633 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 634 region &= ~(size - 1); 635 636 /* Convert from PCI bus to resource space */ 637 bus_region.start = region; 638 bus_region.end = region + size - 1; 639 pcibios_bus_to_resource(dev->bus, res, &bus_region); 640 641 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name); 642 } 643 644 /* 645 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 646 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 647 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 648 * (which conflicts w/ BAR1's memory range). 649 * 650 * CS553x's ISA PCI BARs may also be read-only (ref: 651 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 652 */ 653 static void quirk_cs5536_vsa(struct pci_dev *dev) 654 { 655 static char *name = "CS5536 ISA bridge"; 656 657 if (pci_resource_len(dev, 0) != 8) { 658 quirk_io(dev, 0, 8, name); /* SMB */ 659 quirk_io(dev, 1, 256, name); /* GPIO */ 660 quirk_io(dev, 2, 64, name); /* MFGPT */ 661 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 662 name); 663 } 664 } 665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 666 667 static void quirk_io_region(struct pci_dev *dev, int port, 668 unsigned int size, int nr, const char *name) 669 { 670 u16 region; 671 struct pci_bus_region bus_region; 672 struct resource *res = pci_resource_n(dev, nr); 673 674 pci_read_config_word(dev, port, ®ion); 675 region &= ~(size - 1); 676 677 if (!region) 678 return; 679 680 res->name = pci_name(dev); 681 res->flags = IORESOURCE_IO; 682 683 /* Convert from PCI bus to resource space */ 684 bus_region.start = region; 685 bus_region.end = region + size - 1; 686 pcibios_bus_to_resource(dev->bus, res, &bus_region); 687 688 /* 689 * "res" is typically a bridge window resource that's not being 690 * used for a bridge window, so it's just a place to stash this 691 * non-standard resource. Printing "nr" or pci_resource_name() of 692 * it doesn't really make sense. 693 */ 694 if (!pci_claim_resource(dev, nr)) 695 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 696 } 697 698 /* 699 * ATI Northbridge setups MCE the processor if you even read somewhere 700 * between 0x3b0->0x3bb or read 0x3d3 701 */ 702 static void quirk_ati_exploding_mce(struct pci_dev *dev) 703 { 704 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 705 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 706 request_region(0x3b0, 0x0C, "RadeonIGP"); 707 request_region(0x3d3, 0x01, "RadeonIGP"); 708 } 709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 710 711 /* 712 * In the AMD NL platform, this device ([1022:7912]) has a class code of 713 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 714 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 715 * 716 * But the dwc3 driver is a more specific driver for this device, and we'd 717 * prefer to use it instead of xhci. To prevent xhci from claiming the 718 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 719 * defines as "USB device (not host controller)". The dwc3 driver can then 720 * claim it based on its Vendor and Device ID. 721 */ 722 static void quirk_amd_dwc_class(struct pci_dev *pdev) 723 { 724 u32 class = pdev->class; 725 726 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 727 /* Use "USB Device (not host controller)" class */ 728 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 729 pci_info(pdev, 730 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 731 class, pdev->class); 732 } 733 } 734 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 735 quirk_amd_dwc_class); 736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 737 quirk_amd_dwc_class); 738 739 /* 740 * Synopsys USB 3.x host HAPS platform has a class code of 741 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 742 * devices should use dwc3-haps driver. Change these devices' class code to 743 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 744 * them. 745 */ 746 static void quirk_synopsys_haps(struct pci_dev *pdev) 747 { 748 u32 class = pdev->class; 749 750 switch (pdev->device) { 751 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 752 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 753 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 754 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 755 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 756 class, pdev->class); 757 break; 758 } 759 } 760 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 761 PCI_CLASS_SERIAL_USB_XHCI, 0, 762 quirk_synopsys_haps); 763 764 /* 765 * Let's make the southbridge information explicit instead of having to 766 * worry about people probing the ACPI areas, for example.. (Yes, it 767 * happens, and if you read the wrong ACPI register it will put the machine 768 * to sleep with no way of waking it up again. Bummer). 769 * 770 * ALI M7101: Two IO regions pointed to by words at 771 * 0xE0 (64 bytes of ACPI registers) 772 * 0xE2 (32 bytes of SMB registers) 773 */ 774 static void quirk_ali7101_acpi(struct pci_dev *dev) 775 { 776 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 777 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 778 } 779 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 780 781 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 782 { 783 u32 devres; 784 u32 mask, size, base; 785 786 pci_read_config_dword(dev, port, &devres); 787 if ((devres & enable) != enable) 788 return; 789 mask = (devres >> 16) & 15; 790 base = devres & 0xffff; 791 size = 16; 792 for (;;) { 793 unsigned int bit = size >> 1; 794 if ((bit & mask) == bit) 795 break; 796 size = bit; 797 } 798 /* 799 * For now we only print it out. Eventually we'll want to 800 * reserve it (at least if it's in the 0x1000+ range), but 801 * let's get enough confirmation reports first. 802 */ 803 base &= -size; 804 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 805 } 806 807 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 808 { 809 u32 devres; 810 u32 mask, size, base; 811 812 pci_read_config_dword(dev, port, &devres); 813 if ((devres & enable) != enable) 814 return; 815 base = devres & 0xffff0000; 816 mask = (devres & 0x3f) << 16; 817 size = 128 << 16; 818 for (;;) { 819 unsigned int bit = size >> 1; 820 if ((bit & mask) == bit) 821 break; 822 size = bit; 823 } 824 825 /* 826 * For now we only print it out. Eventually we'll want to 827 * reserve it, but let's get enough confirmation reports first. 828 */ 829 base &= -size; 830 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 831 } 832 833 /* 834 * PIIX4 ACPI: Two IO regions pointed to by longwords at 835 * 0x40 (64 bytes of ACPI registers) 836 * 0x90 (16 bytes of SMB registers) 837 * and a few strange programmable PIIX4 device resources. 838 */ 839 static void quirk_piix4_acpi(struct pci_dev *dev) 840 { 841 u32 res_a; 842 843 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 844 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 845 846 /* Device resource A has enables for some of the other ones */ 847 pci_read_config_dword(dev, 0x5c, &res_a); 848 849 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 850 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 851 852 /* Device resource D is just bitfields for static resources */ 853 854 /* Device 12 enabled? */ 855 if (res_a & (1 << 29)) { 856 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 857 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 858 } 859 /* Device 13 enabled? */ 860 if (res_a & (1 << 30)) { 861 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 862 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 863 } 864 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 865 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 866 } 867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 869 870 #define ICH_PMBASE 0x40 871 #define ICH_ACPI_CNTL 0x44 872 #define ICH4_ACPI_EN 0x10 873 #define ICH6_ACPI_EN 0x80 874 #define ICH4_GPIOBASE 0x58 875 #define ICH4_GPIO_CNTL 0x5c 876 #define ICH4_GPIO_EN 0x10 877 #define ICH6_GPIOBASE 0x48 878 #define ICH6_GPIO_CNTL 0x4c 879 #define ICH6_GPIO_EN 0x10 880 881 /* 882 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 883 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 884 * 0x58 (64 bytes of GPIO I/O space) 885 */ 886 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 887 { 888 u8 enable; 889 890 /* 891 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 892 * with low legacy (and fixed) ports. We don't know the decoding 893 * priority and can't tell whether the legacy device or the one created 894 * here is really at that address. This happens on boards with broken 895 * BIOSes. 896 */ 897 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 898 if (enable & ICH4_ACPI_EN) 899 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 900 "ICH4 ACPI/GPIO/TCO"); 901 902 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 903 if (enable & ICH4_GPIO_EN) 904 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 905 "ICH4 GPIO"); 906 } 907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 917 918 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 919 { 920 u8 enable; 921 922 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 923 if (enable & ICH6_ACPI_EN) 924 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 925 "ICH6 ACPI/GPIO/TCO"); 926 927 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 928 if (enable & ICH6_GPIO_EN) 929 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 930 "ICH6 GPIO"); 931 } 932 933 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 934 const char *name, int dynsize) 935 { 936 u32 val; 937 u32 size, base; 938 939 pci_read_config_dword(dev, reg, &val); 940 941 /* Enabled? */ 942 if (!(val & 1)) 943 return; 944 base = val & 0xfffc; 945 if (dynsize) { 946 /* 947 * This is not correct. It is 16, 32 or 64 bytes depending on 948 * register D31:F0:ADh bits 5:4. 949 * 950 * But this gets us at least _part_ of it. 951 */ 952 size = 16; 953 } else { 954 size = 128; 955 } 956 base &= ~(size-1); 957 958 /* 959 * Just print it out for now. We should reserve it after more 960 * debugging. 961 */ 962 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 963 } 964 965 static void quirk_ich6_lpc(struct pci_dev *dev) 966 { 967 /* Shared ACPI/GPIO decode with all ICH6+ */ 968 ich6_lpc_acpi_gpio(dev); 969 970 /* ICH6-specific generic IO decode */ 971 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 972 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 973 } 974 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 975 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 976 977 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 978 const char *name) 979 { 980 u32 val; 981 u32 mask, base; 982 983 pci_read_config_dword(dev, reg, &val); 984 985 /* Enabled? */ 986 if (!(val & 1)) 987 return; 988 989 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 990 base = val & 0xfffc; 991 mask = (val >> 16) & 0xfc; 992 mask |= 3; 993 994 /* 995 * Just print it out for now. We should reserve it after more 996 * debugging. 997 */ 998 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 999 } 1000 1001 /* ICH7-10 has the same common LPC generic IO decode registers */ 1002 static void quirk_ich7_lpc(struct pci_dev *dev) 1003 { 1004 /* We share the common ACPI/GPIO decode with ICH6 */ 1005 ich6_lpc_acpi_gpio(dev); 1006 1007 /* And have 4 ICH7+ generic decodes */ 1008 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 1009 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 1010 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 1011 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 1012 } 1013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 1014 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 1015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 1016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 1017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 1018 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 1019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 1020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 1021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 1022 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 1023 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1026 1027 /* 1028 * VIA ACPI: One IO region pointed to by longword at 1029 * 0x48 or 0x20 (256 bytes of ACPI registers) 1030 */ 1031 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1032 { 1033 if (dev->revision & 0x10) 1034 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1035 "vt82c586 ACPI"); 1036 } 1037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1038 1039 /* 1040 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1041 * 0x48 (256 bytes of ACPI registers) 1042 * 0x70 (128 bytes of hardware monitoring register) 1043 * 0x90 (16 bytes of SMB registers) 1044 */ 1045 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1046 { 1047 quirk_vt82c586_acpi(dev); 1048 1049 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1050 "vt82c686 HW-mon"); 1051 1052 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1053 } 1054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1055 1056 /* 1057 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1058 * 0x88 (128 bytes of power management registers) 1059 * 0xd0 (16 bytes of SMB registers) 1060 */ 1061 static void quirk_vt8235_acpi(struct pci_dev *dev) 1062 { 1063 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1064 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1065 } 1066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1067 1068 /* 1069 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1070 * back-to-back: Disable fast back-to-back on the secondary bus segment 1071 */ 1072 static void quirk_xio2000a(struct pci_dev *dev) 1073 { 1074 struct pci_dev *pdev; 1075 u16 command; 1076 1077 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1078 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1079 pci_read_config_word(pdev, PCI_COMMAND, &command); 1080 if (command & PCI_COMMAND_FAST_BACK) 1081 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1082 } 1083 } 1084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1085 quirk_xio2000a); 1086 1087 #ifdef CONFIG_X86_IO_APIC 1088 1089 #include <asm/io_apic.h> 1090 1091 /* 1092 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1093 * devices to the external APIC. 1094 * 1095 * TODO: When we have device-specific interrupt routers, this code will go 1096 * away from quirks. 1097 */ 1098 static void quirk_via_ioapic(struct pci_dev *dev) 1099 { 1100 u8 tmp; 1101 1102 if (nr_ioapics < 1) 1103 tmp = 0; /* nothing routed to external APIC */ 1104 else 1105 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1106 1107 pci_info(dev, "%s VIA external APIC routing\n", 1108 tmp ? "Enabling" : "Disabling"); 1109 1110 /* Offset 0x58: External APIC IRQ output control */ 1111 pci_write_config_byte(dev, 0x58, tmp); 1112 } 1113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1114 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1115 1116 /* 1117 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1118 * This leads to doubled level interrupt rates. 1119 * Set this bit to get rid of cycle wastage. 1120 * Otherwise uncritical. 1121 */ 1122 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1123 { 1124 u8 misc_control2; 1125 #define BYPASS_APIC_DEASSERT 8 1126 1127 pci_read_config_byte(dev, 0x5B, &misc_control2); 1128 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1129 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1130 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1131 } 1132 } 1133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1134 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1135 1136 /* 1137 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1138 * We check all revs >= B0 (yet not in the pre production!) as the bug 1139 * is currently marked NoFix 1140 * 1141 * We have multiple reports of hangs with this chipset that went away with 1142 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1143 * of course. However the advice is demonstrably good even if so. 1144 */ 1145 static void quirk_amd_ioapic(struct pci_dev *dev) 1146 { 1147 if (dev->revision >= 0x02) { 1148 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1149 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1150 } 1151 } 1152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1153 #endif /* CONFIG_X86_IO_APIC */ 1154 1155 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1156 1157 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1158 { 1159 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1160 if (dev->subsystem_device == 0xa118) 1161 dev->sriov->link = dev->devfn; 1162 } 1163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1164 #endif 1165 1166 /* 1167 * Some settings of MMRBC can lead to data corruption so block changes. 1168 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1169 */ 1170 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1171 { 1172 if (dev->subordinate && dev->revision <= 0x12) { 1173 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1174 dev->revision); 1175 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1176 } 1177 } 1178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1179 1180 /* 1181 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1182 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1183 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1184 * of the ACPI SCI interrupt is only done for convenience. 1185 * -jgarzik 1186 */ 1187 static void quirk_via_acpi(struct pci_dev *d) 1188 { 1189 u8 irq; 1190 1191 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1192 pci_read_config_byte(d, 0x42, &irq); 1193 irq &= 0xf; 1194 if (irq && (irq != 2)) 1195 d->irq = irq; 1196 } 1197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1199 1200 /* VIA bridges which have VLink */ 1201 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1202 1203 static void quirk_via_bridge(struct pci_dev *dev) 1204 { 1205 /* See what bridge we have and find the device ranges */ 1206 switch (dev->device) { 1207 case PCI_DEVICE_ID_VIA_82C686: 1208 /* 1209 * The VT82C686 is special; it attaches to PCI and can have 1210 * any device number. All its subdevices are functions of 1211 * that single device. 1212 */ 1213 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1214 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1215 break; 1216 case PCI_DEVICE_ID_VIA_8237: 1217 case PCI_DEVICE_ID_VIA_8237A: 1218 via_vlink_dev_lo = 15; 1219 break; 1220 case PCI_DEVICE_ID_VIA_8235: 1221 via_vlink_dev_lo = 16; 1222 break; 1223 case PCI_DEVICE_ID_VIA_8231: 1224 case PCI_DEVICE_ID_VIA_8233_0: 1225 case PCI_DEVICE_ID_VIA_8233A: 1226 case PCI_DEVICE_ID_VIA_8233C_0: 1227 via_vlink_dev_lo = 17; 1228 break; 1229 } 1230 } 1231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1239 1240 /* 1241 * quirk_via_vlink - VIA VLink IRQ number update 1242 * @dev: PCI device 1243 * 1244 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1245 * the IRQ line register which usually is not relevant for PCI cards, is 1246 * actually written so that interrupts get sent to the right place. 1247 * 1248 * We only do this on systems where a VIA south bridge was detected, and 1249 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1250 */ 1251 static void quirk_via_vlink(struct pci_dev *dev) 1252 { 1253 u8 irq, new_irq; 1254 1255 /* Check if we have VLink at all */ 1256 if (via_vlink_dev_lo == -1) 1257 return; 1258 1259 new_irq = dev->irq; 1260 1261 /* Don't quirk interrupts outside the legacy IRQ range */ 1262 if (!new_irq || new_irq > 15) 1263 return; 1264 1265 /* Internal device ? */ 1266 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1267 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1268 return; 1269 1270 /* 1271 * This is an internal VLink device on a PIC interrupt. The BIOS 1272 * ought to have set this but may not have, so we redo it. 1273 */ 1274 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1275 if (new_irq != irq) { 1276 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1277 irq, new_irq); 1278 udelay(15); /* unknown if delay really needed */ 1279 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1280 } 1281 } 1282 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1283 1284 /* 1285 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1286 * of VT82C597 for backward compatibility. We need to switch it off to be 1287 * able to recognize the real type of the chip. 1288 */ 1289 static void quirk_vt82c598_id(struct pci_dev *dev) 1290 { 1291 pci_write_config_byte(dev, 0xfc, 0); 1292 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1293 } 1294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1295 1296 /* 1297 * CardBus controllers have a legacy base address that enables them to 1298 * respond as i82365 pcmcia controllers. We don't want them to do this 1299 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1300 * driver does not (and should not) handle CardBus. 1301 */ 1302 static void quirk_cardbus_legacy(struct pci_dev *dev) 1303 { 1304 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1305 } 1306 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1307 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1308 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1309 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1310 1311 /* 1312 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1313 * what the designers were smoking but let's not inhale... 1314 * 1315 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1316 * turn it off! 1317 */ 1318 static void quirk_amd_ordering(struct pci_dev *dev) 1319 { 1320 u32 pcic; 1321 pci_read_config_dword(dev, 0x4C, &pcic); 1322 if ((pcic & 6) != 6) { 1323 pcic |= 6; 1324 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1325 pci_write_config_dword(dev, 0x4C, pcic); 1326 pci_read_config_dword(dev, 0x84, &pcic); 1327 pcic |= (1 << 23); /* Required in this mode */ 1328 pci_write_config_dword(dev, 0x84, pcic); 1329 } 1330 } 1331 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1332 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1333 1334 /* 1335 * DreamWorks-provided workaround for Dunord I-3000 problem 1336 * 1337 * This card decodes and responds to addresses not apparently assigned to 1338 * it. We force a larger allocation to ensure that nothing gets put too 1339 * close to it. 1340 */ 1341 static void quirk_dunord(struct pci_dev *dev) 1342 { 1343 struct resource *r = &dev->resource[1]; 1344 1345 r->flags |= IORESOURCE_UNSET; 1346 resource_set_range(r, 0, SZ_16M); 1347 } 1348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1349 1350 /* 1351 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1352 * decoding (transparent), and does indicate this in the ProgIf. 1353 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1354 */ 1355 static void quirk_transparent_bridge(struct pci_dev *dev) 1356 { 1357 dev->transparent = 1; 1358 } 1359 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1361 1362 /* 1363 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1364 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1365 * found at http://www.national.com/analog for info on what these bits do. 1366 * <christer@weinigel.se> 1367 */ 1368 static void quirk_mediagx_master(struct pci_dev *dev) 1369 { 1370 u8 reg; 1371 1372 pci_read_config_byte(dev, 0x41, ®); 1373 if (reg & 2) { 1374 reg &= ~2; 1375 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1376 reg); 1377 pci_write_config_byte(dev, 0x41, reg); 1378 } 1379 } 1380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1381 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1382 1383 /* 1384 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1385 * in the odd case it is not the results are corruption hence the presence 1386 * of a Linux check. 1387 */ 1388 static void quirk_disable_pxb(struct pci_dev *pdev) 1389 { 1390 u16 config; 1391 1392 if (pdev->revision != 0x04) /* Only C0 requires this */ 1393 return; 1394 pci_read_config_word(pdev, 0x40, &config); 1395 if (config & (1<<6)) { 1396 config &= ~(1<<6); 1397 pci_write_config_word(pdev, 0x40, config); 1398 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1399 } 1400 } 1401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1402 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1403 1404 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1405 { 1406 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1407 u8 tmp; 1408 1409 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1410 if (tmp == 0x01) { 1411 pci_read_config_byte(pdev, 0x40, &tmp); 1412 pci_write_config_byte(pdev, 0x40, tmp|1); 1413 pci_write_config_byte(pdev, 0x9, 1); 1414 pci_write_config_byte(pdev, 0xa, 6); 1415 pci_write_config_byte(pdev, 0x40, tmp); 1416 1417 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1418 pci_info(pdev, "set SATA to AHCI mode\n"); 1419 } 1420 } 1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1422 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1426 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1428 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1429 1430 /* Serverworks CSB5 IDE does not fully support native mode */ 1431 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1432 { 1433 u8 prog; 1434 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1435 if (prog & 5) { 1436 prog &= ~5; 1437 pdev->class &= ~5; 1438 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1439 /* PCI layer will sort out resources */ 1440 } 1441 } 1442 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1443 1444 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1445 static void quirk_ide_samemode(struct pci_dev *pdev) 1446 { 1447 u8 prog; 1448 1449 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1450 1451 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1452 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1453 prog &= ~5; 1454 pdev->class &= ~5; 1455 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1456 } 1457 } 1458 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1459 1460 /* Some ATA devices break if put into D3 */ 1461 static void quirk_no_ata_d3(struct pci_dev *pdev) 1462 { 1463 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1464 } 1465 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1466 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1467 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1468 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1469 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1470 /* ALi loses some register settings that we cannot then restore */ 1471 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1472 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1473 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1474 occur when mode detecting */ 1475 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1476 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1477 1478 /* 1479 * This was originally an Alpha-specific thing, but it really fits here. 1480 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1481 */ 1482 static void quirk_eisa_bridge(struct pci_dev *dev) 1483 { 1484 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1485 } 1486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1487 1488 /* 1489 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1490 * is not activated. The myth is that Asus said that they do not want the 1491 * users to be irritated by just another PCI Device in the Win98 device 1492 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1493 * package 2.7.0 for details) 1494 * 1495 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1496 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1497 * becomes necessary to do this tweak in two steps -- the chosen trigger 1498 * is either the Host bridge (preferred) or on-board VGA controller. 1499 * 1500 * Note that we used to unhide the SMBus that way on Toshiba laptops 1501 * (Satellite A40 and Tecra M2) but then found that the thermal management 1502 * was done by SMM code, which could cause unsynchronized concurrent 1503 * accesses to the SMBus registers, with potentially bad effects. Thus you 1504 * should be very careful when adding new entries: if SMM is accessing the 1505 * Intel SMBus, this is a very good reason to leave it hidden. 1506 * 1507 * Likewise, many recent laptops use ACPI for thermal management. If the 1508 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1509 * natively, and keeping the SMBus hidden is the right thing to do. If you 1510 * are about to add an entry in the table below, please first disassemble 1511 * the DSDT and double-check that there is no code accessing the SMBus. 1512 */ 1513 static int asus_hides_smbus; 1514 1515 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1516 { 1517 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1518 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1519 switch (dev->subsystem_device) { 1520 case 0x8025: /* P4B-LX */ 1521 case 0x8070: /* P4B */ 1522 case 0x8088: /* P4B533 */ 1523 case 0x1626: /* L3C notebook */ 1524 asus_hides_smbus = 1; 1525 } 1526 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1527 switch (dev->subsystem_device) { 1528 case 0x80b1: /* P4GE-V */ 1529 case 0x80b2: /* P4PE */ 1530 case 0x8093: /* P4B533-V */ 1531 asus_hides_smbus = 1; 1532 } 1533 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1534 switch (dev->subsystem_device) { 1535 case 0x8030: /* P4T533 */ 1536 asus_hides_smbus = 1; 1537 } 1538 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1539 switch (dev->subsystem_device) { 1540 case 0x8070: /* P4G8X Deluxe */ 1541 asus_hides_smbus = 1; 1542 } 1543 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1544 switch (dev->subsystem_device) { 1545 case 0x80c9: /* PU-DLS */ 1546 asus_hides_smbus = 1; 1547 } 1548 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1549 switch (dev->subsystem_device) { 1550 case 0x1751: /* M2N notebook */ 1551 case 0x1821: /* M5N notebook */ 1552 case 0x1897: /* A6L notebook */ 1553 asus_hides_smbus = 1; 1554 } 1555 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1556 switch (dev->subsystem_device) { 1557 case 0x184b: /* W1N notebook */ 1558 case 0x186a: /* M6Ne notebook */ 1559 asus_hides_smbus = 1; 1560 } 1561 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1562 switch (dev->subsystem_device) { 1563 case 0x80f2: /* P4P800-X */ 1564 asus_hides_smbus = 1; 1565 } 1566 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1567 switch (dev->subsystem_device) { 1568 case 0x1882: /* M6V notebook */ 1569 case 0x1977: /* A6VA notebook */ 1570 asus_hides_smbus = 1; 1571 } 1572 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1573 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1574 switch (dev->subsystem_device) { 1575 case 0x088C: /* HP Compaq nc8000 */ 1576 case 0x0890: /* HP Compaq nc6000 */ 1577 asus_hides_smbus = 1; 1578 } 1579 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1580 switch (dev->subsystem_device) { 1581 case 0x12bc: /* HP D330L */ 1582 case 0x12bd: /* HP D530 */ 1583 case 0x006a: /* HP Compaq nx9500 */ 1584 asus_hides_smbus = 1; 1585 } 1586 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1587 switch (dev->subsystem_device) { 1588 case 0x12bf: /* HP xw4100 */ 1589 asus_hides_smbus = 1; 1590 } 1591 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1592 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1593 switch (dev->subsystem_device) { 1594 case 0xC00C: /* Samsung P35 notebook */ 1595 asus_hides_smbus = 1; 1596 } 1597 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1598 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1599 switch (dev->subsystem_device) { 1600 case 0x0058: /* Compaq Evo N620c */ 1601 asus_hides_smbus = 1; 1602 } 1603 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1604 switch (dev->subsystem_device) { 1605 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1606 /* Motherboard doesn't have Host bridge 1607 * subvendor/subdevice IDs, therefore checking 1608 * its on-board VGA controller */ 1609 asus_hides_smbus = 1; 1610 } 1611 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1612 switch (dev->subsystem_device) { 1613 case 0x00b8: /* Compaq Evo D510 CMT */ 1614 case 0x00b9: /* Compaq Evo D510 SFF */ 1615 case 0x00ba: /* Compaq Evo D510 USDT */ 1616 /* Motherboard doesn't have Host bridge 1617 * subvendor/subdevice IDs and on-board VGA 1618 * controller is disabled if an AGP card is 1619 * inserted, therefore checking USB UHCI 1620 * Controller #1 */ 1621 asus_hides_smbus = 1; 1622 } 1623 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1624 switch (dev->subsystem_device) { 1625 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1626 /* Motherboard doesn't have host bridge 1627 * subvendor/subdevice IDs, therefore checking 1628 * its on-board VGA controller */ 1629 asus_hides_smbus = 1; 1630 } 1631 } 1632 } 1633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1643 1644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1647 1648 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1649 { 1650 u16 val; 1651 1652 if (likely(!asus_hides_smbus)) 1653 return; 1654 1655 pci_read_config_word(dev, 0xF2, &val); 1656 if (val & 0x8) { 1657 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1658 pci_read_config_word(dev, 0xF2, &val); 1659 if (val & 0x8) 1660 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1661 val); 1662 else 1663 pci_info(dev, "Enabled i801 SMBus device\n"); 1664 } 1665 } 1666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1668 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1669 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1670 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1673 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1674 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1675 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1676 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1677 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1678 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1679 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1680 1681 /* It appears we just have one such device. If not, we have a warning */ 1682 static void __iomem *asus_rcba_base; 1683 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1684 { 1685 u32 rcba; 1686 1687 if (likely(!asus_hides_smbus)) 1688 return; 1689 WARN_ON(asus_rcba_base); 1690 1691 pci_read_config_dword(dev, 0xF0, &rcba); 1692 /* use bits 31:14, 16 kB aligned */ 1693 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1694 if (asus_rcba_base == NULL) 1695 return; 1696 } 1697 1698 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1699 { 1700 u32 val; 1701 1702 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1703 return; 1704 1705 /* read the Function Disable register, dword mode only */ 1706 val = readl(asus_rcba_base + 0x3418); 1707 1708 /* enable the SMBus device */ 1709 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1710 } 1711 1712 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1713 { 1714 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1715 return; 1716 1717 iounmap(asus_rcba_base); 1718 asus_rcba_base = NULL; 1719 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1720 } 1721 1722 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1723 { 1724 asus_hides_smbus_lpc_ich6_suspend(dev); 1725 asus_hides_smbus_lpc_ich6_resume_early(dev); 1726 asus_hides_smbus_lpc_ich6_resume(dev); 1727 } 1728 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1729 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1730 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1731 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1732 1733 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1734 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1735 { 1736 u8 val = 0; 1737 pci_read_config_byte(dev, 0x77, &val); 1738 if (val & 0x10) { 1739 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1740 pci_write_config_byte(dev, 0x77, val & ~0x10); 1741 } 1742 } 1743 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1745 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1746 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1747 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1748 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1749 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1750 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1751 1752 /* 1753 * ... This is further complicated by the fact that some SiS96x south 1754 * bridges pretend to be 85C503/5513 instead. In that case see if we 1755 * spotted a compatible north bridge to make sure. 1756 * (pci_find_device() doesn't work yet) 1757 * 1758 * We can also enable the sis96x bit in the discovery register.. 1759 */ 1760 #define SIS_DETECT_REGISTER 0x40 1761 1762 static void quirk_sis_503(struct pci_dev *dev) 1763 { 1764 u8 reg; 1765 u16 devid; 1766 1767 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1768 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1769 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1770 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1771 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1772 return; 1773 } 1774 1775 /* 1776 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1777 * it has already been processed. (Depends on link order, which is 1778 * apparently not guaranteed) 1779 */ 1780 dev->device = devid; 1781 quirk_sis_96x_smbus(dev); 1782 } 1783 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1784 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1785 1786 /* 1787 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1788 * and MC97 modem controller are disabled when a second PCI soundcard is 1789 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1790 * -- bjd 1791 */ 1792 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1793 { 1794 u8 val; 1795 int asus_hides_ac97 = 0; 1796 1797 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1798 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1799 asus_hides_ac97 = 1; 1800 } 1801 1802 if (!asus_hides_ac97) 1803 return; 1804 1805 pci_read_config_byte(dev, 0x50, &val); 1806 if (val & 0xc0) { 1807 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1808 pci_read_config_byte(dev, 0x50, &val); 1809 if (val & 0xc0) 1810 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1811 val); 1812 else 1813 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1814 } 1815 } 1816 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1817 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1818 1819 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1820 1821 /* 1822 * If we are using libata we can drive this chip properly but must do this 1823 * early on to make the additional device appear during the PCI scanning. 1824 */ 1825 static void quirk_jmicron_ata(struct pci_dev *pdev) 1826 { 1827 u32 conf1, conf5, class; 1828 u8 hdr; 1829 1830 /* Only poke fn 0 */ 1831 if (PCI_FUNC(pdev->devfn)) 1832 return; 1833 1834 pci_read_config_dword(pdev, 0x40, &conf1); 1835 pci_read_config_dword(pdev, 0x80, &conf5); 1836 1837 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1838 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1839 1840 switch (pdev->device) { 1841 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1842 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1843 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1844 /* The controller should be in single function ahci mode */ 1845 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1846 break; 1847 1848 case PCI_DEVICE_ID_JMICRON_JMB365: 1849 case PCI_DEVICE_ID_JMICRON_JMB366: 1850 /* Redirect IDE second PATA port to the right spot */ 1851 conf5 |= (1 << 24); 1852 fallthrough; 1853 case PCI_DEVICE_ID_JMICRON_JMB361: 1854 case PCI_DEVICE_ID_JMICRON_JMB363: 1855 case PCI_DEVICE_ID_JMICRON_JMB369: 1856 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1857 /* Set the class codes correctly and then direct IDE 0 */ 1858 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1859 break; 1860 1861 case PCI_DEVICE_ID_JMICRON_JMB368: 1862 /* The controller should be in single function IDE mode */ 1863 conf1 |= 0x00C00000; /* Set 22, 23 */ 1864 break; 1865 } 1866 1867 pci_write_config_dword(pdev, 0x40, conf1); 1868 pci_write_config_dword(pdev, 0x80, conf5); 1869 1870 /* Update pdev accordingly */ 1871 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1872 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; 1873 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); 1874 1875 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1876 pdev->class = class >> 8; 1877 } 1878 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1879 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1880 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1881 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1882 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1883 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1884 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1885 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1886 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1887 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1888 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1889 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1890 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1891 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1892 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1893 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1894 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1895 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1896 1897 #endif 1898 1899 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1900 { 1901 if (dev->multifunction) { 1902 device_disable_async_suspend(&dev->dev); 1903 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1904 } 1905 } 1906 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1907 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1910 1911 #ifdef CONFIG_X86_IO_APIC 1912 static void quirk_alder_ioapic(struct pci_dev *pdev) 1913 { 1914 int i; 1915 1916 if ((pdev->class >> 8) != 0xff00) 1917 return; 1918 1919 /* 1920 * The first BAR is the location of the IO-APIC... we must 1921 * not touch this (and it's already covered by the fixmap), so 1922 * forcibly insert it into the resource tree. 1923 */ 1924 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1925 insert_resource(&iomem_resource, &pdev->resource[0]); 1926 1927 /* 1928 * The next five BARs all seem to be rubbish, so just clean 1929 * them out. 1930 */ 1931 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1932 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1933 } 1934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1935 #endif 1936 1937 static void quirk_no_msi(struct pci_dev *dev) 1938 { 1939 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1940 dev->no_msi = 1; 1941 } 1942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1943 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1945 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1948 1949 static void quirk_pcie_mch(struct pci_dev *pdev) 1950 { 1951 pdev->no_msi = 1; 1952 } 1953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1956 1957 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1958 1959 /* 1960 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1961 * actually on the AMBA bus. These fake PCI devices can support SVA via 1962 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1963 * 1964 * Normally stalling must not be enabled for PCI devices, since it would 1965 * break the PCI requirement for free-flowing writes and may lead to 1966 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1967 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1968 * even when a "PCI" device turns out to be a regular old SoC device 1969 * dressed up as a RCiEP and normal rules don't apply. 1970 */ 1971 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1972 { 1973 struct property_entry properties[] = { 1974 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1975 {}, 1976 }; 1977 1978 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1979 return; 1980 1981 pdev->pasid_no_tlp = 1; 1982 1983 /* 1984 * Set the dma-can-stall property on ACPI platforms. Device tree 1985 * can set it directly. 1986 */ 1987 if (!pdev->dev.of_node && 1988 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1989 pci_warn(pdev, "could not add stall property"); 1990 } 1991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 1992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 1993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 1994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 1995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 1996 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 1997 1998 /* 1999 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 2000 * together on certain PXH-based systems. 2001 */ 2002 static void quirk_pcie_pxh(struct pci_dev *dev) 2003 { 2004 dev->no_msi = 1; 2005 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 2006 } 2007 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 2008 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 2009 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 2010 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 2011 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 2012 2013 /* 2014 * Some Intel PCI Express chipsets have trouble with downstream device 2015 * power management. 2016 */ 2017 static void quirk_intel_pcie_pm(struct pci_dev *dev) 2018 { 2019 pci_pm_d3hot_delay = 120; 2020 dev->no_d1d2 = 1; 2021 } 2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2043 2044 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2045 { 2046 if (dev->d3hot_delay >= delay) 2047 return; 2048 2049 dev->d3hot_delay = delay; 2050 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2051 dev->d3hot_delay); 2052 } 2053 2054 static void quirk_radeon_pm(struct pci_dev *dev) 2055 { 2056 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2057 dev->subsystem_device == 0x00e2) 2058 quirk_d3hot_delay(dev, 20); 2059 } 2060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2061 2062 /* 2063 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2064 * reset is performed too soon after transition to D0, extend d3hot_delay 2065 * to previous effective default for all NVIDIA HDA controllers. 2066 */ 2067 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2068 { 2069 quirk_d3hot_delay(dev, 20); 2070 } 2071 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2072 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2073 quirk_nvidia_hda_pm); 2074 2075 /* 2076 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2077 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2078 * 2079 * The kernel attempts to transition these devices to D3cold, but that seems 2080 * to be ineffective on the platforms in question; the PCI device appears to 2081 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2082 * extended delay in order to succeed. 2083 */ 2084 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2085 { 2086 quirk_d3hot_delay(dev, 20); 2087 } 2088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2089 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2091 2092 #ifdef CONFIG_X86_IO_APIC 2093 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2094 { 2095 noioapicreroute = 1; 2096 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2097 2098 return 0; 2099 } 2100 2101 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2102 /* 2103 * Systems to exclude from boot interrupt reroute quirks 2104 */ 2105 { 2106 .callback = dmi_disable_ioapicreroute, 2107 .ident = "ASUSTek Computer INC. M2N-LR", 2108 .matches = { 2109 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2110 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2111 }, 2112 }, 2113 {} 2114 }; 2115 2116 /* 2117 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2118 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2119 * that a PCI device's interrupt handler is installed on the boot interrupt 2120 * line instead. 2121 */ 2122 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2123 { 2124 dmi_check_system(boot_interrupt_dmi_table); 2125 if (noioapicquirk || noioapicreroute) 2126 return; 2127 2128 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2129 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2130 dev->vendor, dev->device); 2131 } 2132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2140 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2141 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2142 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2143 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2144 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2145 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2146 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2147 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2148 2149 /* 2150 * On some chipsets we can disable the generation of legacy INTx boot 2151 * interrupts. 2152 */ 2153 2154 /* 2155 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2156 * 300641-004US, section 5.7.3. 2157 * 2158 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2159 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2160 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2161 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2162 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2163 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2164 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2165 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2166 * Core IO on Xeon Scalable, see Intel order no 610950. 2167 */ 2168 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2169 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2170 2171 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2172 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2173 2174 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2175 { 2176 u16 pci_config_word; 2177 u32 pci_config_dword; 2178 2179 if (noioapicquirk) 2180 return; 2181 2182 switch (dev->device) { 2183 case PCI_DEVICE_ID_INTEL_ESB_10: 2184 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2185 &pci_config_word); 2186 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2187 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2188 pci_config_word); 2189 break; 2190 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2191 case 0x0e28: /* Xeon E5/E7 V2 */ 2192 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2193 case 0x6f28: /* Xeon D-1500 */ 2194 case 0x2034: /* Xeon Scalable Family */ 2195 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2196 &pci_config_dword); 2197 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2198 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2199 pci_config_dword); 2200 break; 2201 default: 2202 return; 2203 } 2204 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2205 dev->vendor, dev->device); 2206 } 2207 /* 2208 * Device 29 Func 5 Device IDs of IO-APIC 2209 * containing ABAR—APIC1 Alternate Base Address Register 2210 */ 2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2212 quirk_disable_intel_boot_interrupt); 2213 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2214 quirk_disable_intel_boot_interrupt); 2215 2216 /* 2217 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2218 * containing Coherent Interface Protocol Interrupt Control 2219 * 2220 * Device IDs obtained from volume 2 datasheets of commented 2221 * families above. 2222 */ 2223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2224 quirk_disable_intel_boot_interrupt); 2225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2226 quirk_disable_intel_boot_interrupt); 2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2228 quirk_disable_intel_boot_interrupt); 2229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2230 quirk_disable_intel_boot_interrupt); 2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2232 quirk_disable_intel_boot_interrupt); 2233 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2234 quirk_disable_intel_boot_interrupt); 2235 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2236 quirk_disable_intel_boot_interrupt); 2237 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2238 quirk_disable_intel_boot_interrupt); 2239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2240 quirk_disable_intel_boot_interrupt); 2241 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2242 quirk_disable_intel_boot_interrupt); 2243 2244 /* Disable boot interrupts on HT-1000 */ 2245 #define BC_HT1000_FEATURE_REG 0x64 2246 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2247 #define BC_HT1000_MAP_IDX 0xC00 2248 #define BC_HT1000_MAP_DATA 0xC01 2249 2250 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2251 { 2252 u32 pci_config_dword; 2253 u8 irq; 2254 2255 if (noioapicquirk) 2256 return; 2257 2258 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2259 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2260 BC_HT1000_PIC_REGS_ENABLE); 2261 2262 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2263 outb(irq, BC_HT1000_MAP_IDX); 2264 outb(0x00, BC_HT1000_MAP_DATA); 2265 } 2266 2267 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2268 2269 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2270 dev->vendor, dev->device); 2271 } 2272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2273 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2274 2275 /* Disable boot interrupts on AMD and ATI chipsets */ 2276 2277 /* 2278 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2279 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2280 * (due to an erratum). 2281 */ 2282 #define AMD_813X_MISC 0x40 2283 #define AMD_813X_NOIOAMODE (1<<0) 2284 #define AMD_813X_REV_B1 0x12 2285 #define AMD_813X_REV_B2 0x13 2286 2287 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2288 { 2289 u32 pci_config_dword; 2290 2291 if (noioapicquirk) 2292 return; 2293 if ((dev->revision == AMD_813X_REV_B1) || 2294 (dev->revision == AMD_813X_REV_B2)) 2295 return; 2296 2297 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2298 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2299 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2300 2301 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2302 dev->vendor, dev->device); 2303 } 2304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2305 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2307 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2308 2309 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2310 2311 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2312 { 2313 u16 pci_config_word; 2314 2315 if (noioapicquirk) 2316 return; 2317 2318 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2319 if (!pci_config_word) { 2320 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2321 dev->vendor, dev->device); 2322 return; 2323 } 2324 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2325 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2326 dev->vendor, dev->device); 2327 } 2328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2329 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2330 #endif /* CONFIG_X86_IO_APIC */ 2331 2332 /* 2333 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2334 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2335 * Re-allocate the region if needed... 2336 */ 2337 static void quirk_tc86c001_ide(struct pci_dev *dev) 2338 { 2339 struct resource *r = &dev->resource[0]; 2340 2341 if (r->start & 0x8) { 2342 r->flags |= IORESOURCE_UNSET; 2343 resource_set_range(r, 0, SZ_16); 2344 } 2345 } 2346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2347 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2348 quirk_tc86c001_ide); 2349 2350 /* 2351 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2352 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2353 * being read correctly if bit 7 of the base address is set. 2354 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2355 * Re-allocate the regions to a 256-byte boundary if necessary. 2356 */ 2357 static void quirk_plx_pci9050(struct pci_dev *dev) 2358 { 2359 unsigned int bar; 2360 2361 /* Fixed in revision 2 (PCI 9052). */ 2362 if (dev->revision >= 2) 2363 return; 2364 for (bar = 0; bar <= 1; bar++) 2365 if (pci_resource_len(dev, bar) == 0x80 && 2366 (pci_resource_start(dev, bar) & 0x80)) { 2367 struct resource *r = &dev->resource[bar]; 2368 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2369 bar); 2370 r->flags |= IORESOURCE_UNSET; 2371 resource_set_range(r, 0, SZ_256); 2372 } 2373 } 2374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2375 quirk_plx_pci9050); 2376 /* 2377 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2378 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2379 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2380 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2381 * 2382 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2383 * driver. 2384 */ 2385 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2386 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2387 2388 static void quirk_netmos(struct pci_dev *dev) 2389 { 2390 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2391 unsigned int num_serial = dev->subsystem_device & 0xf; 2392 2393 /* 2394 * These Netmos parts are multiport serial devices with optional 2395 * parallel ports. Even when parallel ports are present, they 2396 * are identified as class SERIAL, which means the serial driver 2397 * will claim them. To prevent this, mark them as class OTHER. 2398 * These combo devices should be claimed by parport_serial. 2399 * 2400 * The subdevice ID is of the form 0x00PS, where <P> is the number 2401 * of parallel ports and <S> is the number of serial ports. 2402 */ 2403 switch (dev->device) { 2404 case PCI_DEVICE_ID_NETMOS_9835: 2405 /* Well, this rule doesn't hold for the following 9835 device */ 2406 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2407 dev->subsystem_device == 0x0299) 2408 return; 2409 fallthrough; 2410 case PCI_DEVICE_ID_NETMOS_9735: 2411 case PCI_DEVICE_ID_NETMOS_9745: 2412 case PCI_DEVICE_ID_NETMOS_9845: 2413 case PCI_DEVICE_ID_NETMOS_9855: 2414 if (num_parallel) { 2415 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2416 dev->device, num_parallel, num_serial); 2417 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2418 (dev->class & 0xff); 2419 } 2420 } 2421 } 2422 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2423 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2424 2425 static void quirk_e100_interrupt(struct pci_dev *dev) 2426 { 2427 u16 command, pmcsr; 2428 u8 __iomem *csr; 2429 u8 cmd_hi; 2430 2431 switch (dev->device) { 2432 /* PCI IDs taken from drivers/net/e100.c */ 2433 case 0x1029: 2434 case 0x1030 ... 0x1034: 2435 case 0x1038 ... 0x103E: 2436 case 0x1050 ... 0x1057: 2437 case 0x1059: 2438 case 0x1064 ... 0x106B: 2439 case 0x1091 ... 0x1095: 2440 case 0x1209: 2441 case 0x1229: 2442 case 0x2449: 2443 case 0x2459: 2444 case 0x245D: 2445 case 0x27DC: 2446 break; 2447 default: 2448 return; 2449 } 2450 2451 /* 2452 * Some firmware hands off the e100 with interrupts enabled, 2453 * which can cause a flood of interrupts if packets are 2454 * received before the driver attaches to the device. So 2455 * disable all e100 interrupts here. The driver will 2456 * re-enable them when it's ready. 2457 */ 2458 pci_read_config_word(dev, PCI_COMMAND, &command); 2459 2460 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2461 return; 2462 2463 /* 2464 * Check that the device is in the D0 power state. If it's not, 2465 * there is no point to look any further. 2466 */ 2467 if (dev->pm_cap) { 2468 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2469 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2470 return; 2471 } 2472 2473 /* Convert from PCI bus to resource space. */ 2474 csr = ioremap(pci_resource_start(dev, 0), 8); 2475 if (!csr) { 2476 pci_warn(dev, "Can't map e100 registers\n"); 2477 return; 2478 } 2479 2480 cmd_hi = readb(csr + 3); 2481 if (cmd_hi == 0) { 2482 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2483 writeb(1, csr + 3); 2484 } 2485 2486 iounmap(csr); 2487 } 2488 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2489 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2490 2491 /* 2492 * The 82575 and 82598 may experience data corruption issues when transitioning 2493 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2494 */ 2495 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2496 { 2497 pcie_aspm_remove_cap(dev, PCI_EXP_LNKCAP_ASPM_L0S); 2498 } 2499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2513 2514 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2515 { 2516 pcie_aspm_remove_cap(dev, 2517 PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1); 2518 } 2519 2520 /* 2521 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2522 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2523 * disable both L0s and L1 for now to be safe. 2524 */ 2525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1); 2527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1); 2528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1); 2529 2530 /* 2531 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2532 * Link bit cleared after starting the link retrain process to allow this 2533 * process to finish. 2534 * 2535 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2536 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2537 */ 2538 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2539 { 2540 dev->clear_retrain_link = 1; 2541 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2542 } 2543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2544 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2545 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2546 2547 static void fixup_rev1_53c810(struct pci_dev *dev) 2548 { 2549 u32 class = dev->class; 2550 2551 /* 2552 * rev 1 ncr53c810 chips don't set the class at all which means 2553 * they don't get their resources remapped. Fix that here. 2554 */ 2555 if (class) 2556 return; 2557 2558 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2559 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2560 class, dev->class); 2561 } 2562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2563 2564 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2565 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2566 { 2567 u16 en1k; 2568 2569 pci_read_config_word(dev, 0x40, &en1k); 2570 2571 if (en1k & 0x200) { 2572 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2573 dev->io_window_1k = 1; 2574 } 2575 } 2576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2577 2578 /* 2579 * Under some circumstances, AER is not linked with extended capabilities. 2580 * Force it to be linked by setting the corresponding control bit in the 2581 * config space. 2582 */ 2583 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2584 { 2585 uint8_t b; 2586 2587 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2588 if (!(b & 0x20)) { 2589 pci_write_config_byte(dev, 0xf41, b | 0x20); 2590 pci_info(dev, "Linking AER extended capability\n"); 2591 } 2592 } 2593 } 2594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2595 quirk_nvidia_ck804_pcie_aer_ext_cap); 2596 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2597 quirk_nvidia_ck804_pcie_aer_ext_cap); 2598 2599 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2600 { 2601 /* 2602 * Disable PCI Bus Parking and PCI Master read caching on CX700 2603 * which causes unspecified timing errors with a VT6212L on the PCI 2604 * bus leading to USB2.0 packet loss. 2605 * 2606 * This quirk is only enabled if a second (on the external PCI bus) 2607 * VT6212L is found -- the CX700 core itself also contains a USB 2608 * host controller with the same PCI ID as the VT6212L. 2609 */ 2610 2611 /* Count VT6212L instances */ 2612 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2613 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2614 uint8_t b; 2615 2616 /* 2617 * p should contain the first (internal) VT6212L -- see if we have 2618 * an external one by searching again. 2619 */ 2620 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2621 if (!p) 2622 return; 2623 pci_dev_put(p); 2624 2625 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2626 if (b & 0x40) { 2627 /* Turn off PCI Bus Parking */ 2628 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2629 2630 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2631 } 2632 } 2633 2634 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2635 if (b != 0) { 2636 /* Turn off PCI Master read caching */ 2637 pci_write_config_byte(dev, 0x72, 0x0); 2638 2639 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2640 pci_write_config_byte(dev, 0x75, 0x1); 2641 2642 /* Disable "Read FIFO Timer" */ 2643 pci_write_config_byte(dev, 0x77, 0x0); 2644 2645 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2646 } 2647 } 2648 } 2649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2650 2651 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2652 { 2653 u32 rev; 2654 2655 pci_read_config_dword(dev, 0xf4, &rev); 2656 2657 /* Only CAP the MRRS if the device is a 5719 A0 */ 2658 if (rev == 0x05719000) { 2659 int readrq = pcie_get_readrq(dev); 2660 if (readrq > 2048) 2661 pcie_set_readrq(dev, 2048); 2662 } 2663 } 2664 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2665 PCI_DEVICE_ID_TIGON3_5719, 2666 quirk_brcm_5719_limit_mrrs); 2667 2668 /* 2669 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2670 * hide device 6 which configures the overflow device access containing the 2671 * DRBs - this is where we expose device 6. 2672 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2673 */ 2674 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2675 { 2676 u8 reg; 2677 2678 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2679 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2680 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2681 } 2682 } 2683 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2684 quirk_unhide_mch_dev6); 2685 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2686 quirk_unhide_mch_dev6); 2687 2688 #ifdef CONFIG_PCI_MSI 2689 /* 2690 * Some chipsets do not support MSI. We cannot easily rely on setting 2691 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2692 * other buses controlled by the chipset even if Linux is not aware of it. 2693 * Instead of setting the flag on all buses in the machine, simply disable 2694 * MSI globally. 2695 */ 2696 static void quirk_disable_all_msi(struct pci_dev *dev) 2697 { 2698 pci_no_msi(); 2699 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2700 } 2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2710 2711 /* Disable MSI on chipsets that are known to not support it */ 2712 static void quirk_disable_msi(struct pci_dev *dev) 2713 { 2714 if (dev->subordinate) { 2715 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2716 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2717 } 2718 } 2719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); 2723 2724 /* 2725 * The APC bridge device in AMD 780 family northbridges has some random 2726 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2727 * we use the possible vendor/device IDs of the host bridge for the 2728 * declared quirk, and search for the APC bridge by slot number. 2729 */ 2730 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2731 { 2732 struct pci_dev *apc_bridge; 2733 2734 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2735 if (apc_bridge) { 2736 if (apc_bridge->device == 0x9602) 2737 quirk_disable_msi(apc_bridge); 2738 pci_dev_put(apc_bridge); 2739 } 2740 } 2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2743 2744 /* 2745 * Go through the list of HyperTransport capabilities and return 1 if a HT 2746 * MSI capability is found and enabled. 2747 */ 2748 static int msi_ht_cap_enabled(struct pci_dev *dev) 2749 { 2750 int pos, ttl = PCI_FIND_CAP_TTL; 2751 2752 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2753 while (pos && ttl--) { 2754 u8 flags; 2755 2756 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2757 &flags) == 0) { 2758 pci_info(dev, "Found %s HT MSI Mapping\n", 2759 flags & HT_MSI_FLAGS_ENABLE ? 2760 "enabled" : "disabled"); 2761 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2762 } 2763 2764 pos = pci_find_next_ht_capability(dev, pos, 2765 HT_CAPTYPE_MSI_MAPPING); 2766 } 2767 return 0; 2768 } 2769 2770 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2771 static void quirk_msi_ht_cap(struct pci_dev *dev) 2772 { 2773 if (!msi_ht_cap_enabled(dev)) 2774 quirk_disable_msi(dev); 2775 } 2776 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2777 quirk_msi_ht_cap); 2778 2779 /* 2780 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2781 * if the MSI capability is set in any of these mappings. 2782 */ 2783 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2784 { 2785 struct pci_dev *pdev; 2786 2787 /* 2788 * Check HT MSI cap on this chipset and the root one. A single one 2789 * having MSI is enough to be sure that MSI is supported. 2790 */ 2791 pdev = pci_get_slot(dev->bus, 0); 2792 if (!pdev) 2793 return; 2794 if (!msi_ht_cap_enabled(pdev)) 2795 quirk_msi_ht_cap(dev); 2796 pci_dev_put(pdev); 2797 } 2798 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2799 quirk_nvidia_ck804_msi_ht_cap); 2800 2801 /* Force enable MSI mapping capability on HT bridges */ 2802 static void ht_enable_msi_mapping(struct pci_dev *dev) 2803 { 2804 int pos, ttl = PCI_FIND_CAP_TTL; 2805 2806 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2807 while (pos && ttl--) { 2808 u8 flags; 2809 2810 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2811 &flags) == 0) { 2812 pci_info(dev, "Enabling HT MSI Mapping\n"); 2813 2814 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2815 flags | HT_MSI_FLAGS_ENABLE); 2816 } 2817 pos = pci_find_next_ht_capability(dev, pos, 2818 HT_CAPTYPE_MSI_MAPPING); 2819 } 2820 } 2821 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2822 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2823 ht_enable_msi_mapping); 2824 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2825 ht_enable_msi_mapping); 2826 2827 /* 2828 * The P5N32-SLI motherboards from Asus have a problem with MSI 2829 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2830 * also affects other devices. As for now, turn off MSI for this device. 2831 */ 2832 static void nvenet_msi_disable(struct pci_dev *dev) 2833 { 2834 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2835 2836 if (board_name && 2837 (strstr(board_name, "P5N32-SLI PREMIUM") || 2838 strstr(board_name, "P5N32-E SLI"))) { 2839 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2840 dev->no_msi = 1; 2841 } 2842 } 2843 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2844 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2845 nvenet_msi_disable); 2846 2847 /* 2848 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2849 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2850 * interrupts for PME and AER events; instead only INTx interrupts are 2851 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2852 * for other events, since PCIe specification doesn't support using a mix of 2853 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2854 * service drivers registering their respective ISRs for MSIs. 2855 */ 2856 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2857 { 2858 dev->no_msi = 1; 2859 } 2860 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2861 PCI_CLASS_BRIDGE_PCI, 8, 2862 pci_quirk_nvidia_tegra_disable_rp_msi); 2863 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2864 PCI_CLASS_BRIDGE_PCI, 8, 2865 pci_quirk_nvidia_tegra_disable_rp_msi); 2866 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2867 PCI_CLASS_BRIDGE_PCI, 8, 2868 pci_quirk_nvidia_tegra_disable_rp_msi); 2869 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2870 PCI_CLASS_BRIDGE_PCI, 8, 2871 pci_quirk_nvidia_tegra_disable_rp_msi); 2872 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2873 PCI_CLASS_BRIDGE_PCI, 8, 2874 pci_quirk_nvidia_tegra_disable_rp_msi); 2875 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2876 PCI_CLASS_BRIDGE_PCI, 8, 2877 pci_quirk_nvidia_tegra_disable_rp_msi); 2878 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2879 PCI_CLASS_BRIDGE_PCI, 8, 2880 pci_quirk_nvidia_tegra_disable_rp_msi); 2881 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2882 PCI_CLASS_BRIDGE_PCI, 8, 2883 pci_quirk_nvidia_tegra_disable_rp_msi); 2884 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2885 PCI_CLASS_BRIDGE_PCI, 8, 2886 pci_quirk_nvidia_tegra_disable_rp_msi); 2887 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2888 PCI_CLASS_BRIDGE_PCI, 8, 2889 pci_quirk_nvidia_tegra_disable_rp_msi); 2890 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2891 PCI_CLASS_BRIDGE_PCI, 8, 2892 pci_quirk_nvidia_tegra_disable_rp_msi); 2893 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2894 PCI_CLASS_BRIDGE_PCI, 8, 2895 pci_quirk_nvidia_tegra_disable_rp_msi); 2896 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2897 PCI_CLASS_BRIDGE_PCI, 8, 2898 pci_quirk_nvidia_tegra_disable_rp_msi); 2899 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2900 PCI_CLASS_BRIDGE_PCI, 8, 2901 pci_quirk_nvidia_tegra_disable_rp_msi); 2902 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2903 PCI_CLASS_BRIDGE_PCI, 8, 2904 pci_quirk_nvidia_tegra_disable_rp_msi); 2905 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2906 PCI_CLASS_BRIDGE_PCI, 8, 2907 pci_quirk_nvidia_tegra_disable_rp_msi); 2908 2909 /* 2910 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2911 * config register. This register controls the routing of legacy 2912 * interrupts from devices that route through the MCP55. If this register 2913 * is misprogrammed, interrupts are only sent to the BSP, unlike 2914 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2915 * having this register set properly prevents kdump from booting up 2916 * properly, so let's make sure that we have it set correctly. 2917 * Note that this is an undocumented register. 2918 */ 2919 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2920 { 2921 u32 cfg; 2922 2923 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2924 return; 2925 2926 pci_read_config_dword(dev, 0x74, &cfg); 2927 2928 if (cfg & ((1 << 2) | (1 << 15))) { 2929 pr_info("Rewriting IRQ routing register on MCP55\n"); 2930 cfg &= ~((1 << 2) | (1 << 15)); 2931 pci_write_config_dword(dev, 0x74, cfg); 2932 } 2933 } 2934 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2935 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2936 nvbridge_check_legacy_irq_routing); 2937 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2938 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2939 nvbridge_check_legacy_irq_routing); 2940 2941 static int ht_check_msi_mapping(struct pci_dev *dev) 2942 { 2943 int pos, ttl = PCI_FIND_CAP_TTL; 2944 int found = 0; 2945 2946 /* Check if there is HT MSI cap or enabled on this device */ 2947 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2948 while (pos && ttl--) { 2949 u8 flags; 2950 2951 if (found < 1) 2952 found = 1; 2953 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2954 &flags) == 0) { 2955 if (flags & HT_MSI_FLAGS_ENABLE) { 2956 if (found < 2) { 2957 found = 2; 2958 break; 2959 } 2960 } 2961 } 2962 pos = pci_find_next_ht_capability(dev, pos, 2963 HT_CAPTYPE_MSI_MAPPING); 2964 } 2965 2966 return found; 2967 } 2968 2969 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2970 { 2971 struct pci_dev *dev; 2972 int pos; 2973 int i, dev_no; 2974 int found = 0; 2975 2976 dev_no = host_bridge->devfn >> 3; 2977 for (i = dev_no + 1; i < 0x20; i++) { 2978 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2979 if (!dev) 2980 continue; 2981 2982 /* found next host bridge? */ 2983 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2984 if (pos != 0) { 2985 pci_dev_put(dev); 2986 break; 2987 } 2988 2989 if (ht_check_msi_mapping(dev)) { 2990 found = 1; 2991 pci_dev_put(dev); 2992 break; 2993 } 2994 pci_dev_put(dev); 2995 } 2996 2997 return found; 2998 } 2999 3000 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 3001 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 3002 3003 static int is_end_of_ht_chain(struct pci_dev *dev) 3004 { 3005 int pos, ctrl_off; 3006 int end = 0; 3007 u16 flags, ctrl; 3008 3009 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3010 3011 if (!pos) 3012 goto out; 3013 3014 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 3015 3016 ctrl_off = ((flags >> 10) & 1) ? 3017 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 3018 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 3019 3020 if (ctrl & (1 << 6)) 3021 end = 1; 3022 3023 out: 3024 return end; 3025 } 3026 3027 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3028 { 3029 struct pci_dev *host_bridge; 3030 int pos; 3031 int i, dev_no; 3032 int found = 0; 3033 3034 dev_no = dev->devfn >> 3; 3035 for (i = dev_no; i >= 0; i--) { 3036 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3037 if (!host_bridge) 3038 continue; 3039 3040 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3041 if (pos != 0) { 3042 found = 1; 3043 break; 3044 } 3045 pci_dev_put(host_bridge); 3046 } 3047 3048 if (!found) 3049 return; 3050 3051 /* don't enable end_device/host_bridge with leaf directly here */ 3052 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3053 host_bridge_with_leaf(host_bridge)) 3054 goto out; 3055 3056 /* root did that ! */ 3057 if (msi_ht_cap_enabled(host_bridge)) 3058 goto out; 3059 3060 ht_enable_msi_mapping(dev); 3061 3062 out: 3063 pci_dev_put(host_bridge); 3064 } 3065 3066 static void ht_disable_msi_mapping(struct pci_dev *dev) 3067 { 3068 int pos, ttl = PCI_FIND_CAP_TTL; 3069 3070 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3071 while (pos && ttl--) { 3072 u8 flags; 3073 3074 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3075 &flags) == 0) { 3076 pci_info(dev, "Disabling HT MSI Mapping\n"); 3077 3078 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3079 flags & ~HT_MSI_FLAGS_ENABLE); 3080 } 3081 pos = pci_find_next_ht_capability(dev, pos, 3082 HT_CAPTYPE_MSI_MAPPING); 3083 } 3084 } 3085 3086 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3087 { 3088 struct pci_dev *host_bridge; 3089 int pos; 3090 int found; 3091 3092 if (!pci_msi_enabled()) 3093 return; 3094 3095 /* check if there is HT MSI cap or enabled on this device */ 3096 found = ht_check_msi_mapping(dev); 3097 3098 /* no HT MSI CAP */ 3099 if (found == 0) 3100 return; 3101 3102 /* 3103 * HT MSI mapping should be disabled on devices that are below 3104 * a non-HyperTransport host bridge. Locate the host bridge. 3105 */ 3106 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3107 PCI_DEVFN(0, 0)); 3108 if (host_bridge == NULL) { 3109 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3110 return; 3111 } 3112 3113 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3114 if (pos != 0) { 3115 /* Host bridge is to HT */ 3116 if (found == 1) { 3117 /* it is not enabled, try to enable it */ 3118 if (all) 3119 ht_enable_msi_mapping(dev); 3120 else 3121 nv_ht_enable_msi_mapping(dev); 3122 } 3123 goto out; 3124 } 3125 3126 /* HT MSI is not enabled */ 3127 if (found == 1) 3128 goto out; 3129 3130 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3131 ht_disable_msi_mapping(dev); 3132 3133 out: 3134 pci_dev_put(host_bridge); 3135 } 3136 3137 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3138 { 3139 return __nv_msi_ht_cap_quirk(dev, 1); 3140 } 3141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3142 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3143 3144 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3145 { 3146 return __nv_msi_ht_cap_quirk(dev, 0); 3147 } 3148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3149 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3150 3151 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3152 { 3153 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3154 } 3155 3156 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3157 { 3158 struct pci_dev *p; 3159 3160 /* 3161 * SB700 MSI issue will be fixed at HW level from revision A21; 3162 * we need check PCI REVISION ID of SMBus controller to get SB700 3163 * revision. 3164 */ 3165 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3166 NULL); 3167 if (!p) 3168 return; 3169 3170 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3171 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3172 pci_dev_put(p); 3173 } 3174 3175 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3176 { 3177 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3178 if (dev->revision < 0x18) { 3179 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3180 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3181 } 3182 } 3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3184 PCI_DEVICE_ID_TIGON3_5780, 3185 quirk_msi_intx_disable_bug); 3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3187 PCI_DEVICE_ID_TIGON3_5780S, 3188 quirk_msi_intx_disable_bug); 3189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3190 PCI_DEVICE_ID_TIGON3_5714, 3191 quirk_msi_intx_disable_bug); 3192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3193 PCI_DEVICE_ID_TIGON3_5714S, 3194 quirk_msi_intx_disable_bug); 3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3196 PCI_DEVICE_ID_TIGON3_5715, 3197 quirk_msi_intx_disable_bug); 3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3199 PCI_DEVICE_ID_TIGON3_5715S, 3200 quirk_msi_intx_disable_bug); 3201 3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3203 quirk_msi_intx_disable_ati_bug); 3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3205 quirk_msi_intx_disable_ati_bug); 3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3207 quirk_msi_intx_disable_ati_bug); 3208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3209 quirk_msi_intx_disable_ati_bug); 3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3211 quirk_msi_intx_disable_ati_bug); 3212 3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3214 quirk_msi_intx_disable_bug); 3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3216 quirk_msi_intx_disable_bug); 3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3218 quirk_msi_intx_disable_bug); 3219 3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3221 quirk_msi_intx_disable_bug); 3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3223 quirk_msi_intx_disable_bug); 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3225 quirk_msi_intx_disable_bug); 3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3227 quirk_msi_intx_disable_bug); 3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3229 quirk_msi_intx_disable_bug); 3230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3231 quirk_msi_intx_disable_bug); 3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3233 quirk_msi_intx_disable_qca_bug); 3234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3235 quirk_msi_intx_disable_qca_bug); 3236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3237 quirk_msi_intx_disable_qca_bug); 3238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3239 quirk_msi_intx_disable_qca_bug); 3240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3241 quirk_msi_intx_disable_qca_bug); 3242 3243 /* 3244 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3245 * should be disabled on platforms where the device (mistakenly) advertises it. 3246 * 3247 * Notice that this quirk also disables MSI (which may work, but hasn't been 3248 * tested), since currently there is no standard way to disable only MSI-X. 3249 * 3250 * The 0031 device id is reused for other non Root Port device types, 3251 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3252 */ 3253 static void quirk_al_msi_disable(struct pci_dev *dev) 3254 { 3255 dev->no_msi = 1; 3256 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3257 } 3258 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3259 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3260 #endif /* CONFIG_PCI_MSI */ 3261 3262 /* 3263 * Allow manual resource allocation for PCI hotplug bridges via 3264 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3265 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3266 * allocate resources when hotplug device is inserted and PCI bus is 3267 * rescanned. 3268 */ 3269 static void quirk_hotplug_bridge(struct pci_dev *dev) 3270 { 3271 dev->is_hotplug_bridge = 1; 3272 } 3273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3274 3275 /* 3276 * This is a quirk for the Ricoh MMC controller found as a part of some 3277 * multifunction chips. 3278 * 3279 * This is very similar and based on the ricoh_mmc driver written by 3280 * Philip Langdale. Thank you for these magic sequences. 3281 * 3282 * These chips implement the four main memory card controllers (SD, MMC, 3283 * MS, xD) and one or both of CardBus or FireWire. 3284 * 3285 * It happens that they implement SD and MMC support as separate 3286 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3287 * cards but the chip detects MMC cards in hardware and directs them to the 3288 * MMC controller - so the SDHCI driver never sees them. 3289 * 3290 * To get around this, we must disable the useless MMC controller. At that 3291 * point, the SDHCI controller will start seeing them. It seems to be the 3292 * case that the relevant PCI registers to deactivate the MMC controller 3293 * live on PCI function 0, which might be the CardBus controller or the 3294 * FireWire controller, depending on the particular chip in question 3295 * 3296 * This has to be done early, because as soon as we disable the MMC controller 3297 * other PCI functions shift up one level, e.g. function #2 becomes function 3298 * #1, and this will confuse the PCI core. 3299 */ 3300 #ifdef CONFIG_MMC_RICOH_MMC 3301 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3302 { 3303 u8 write_enable; 3304 u8 write_target; 3305 u8 disable; 3306 3307 /* 3308 * Disable via CardBus interface 3309 * 3310 * This must be done via function #0 3311 */ 3312 if (PCI_FUNC(dev->devfn)) 3313 return; 3314 3315 pci_read_config_byte(dev, 0xB7, &disable); 3316 if (disable & 0x02) 3317 return; 3318 3319 pci_read_config_byte(dev, 0x8E, &write_enable); 3320 pci_write_config_byte(dev, 0x8E, 0xAA); 3321 pci_read_config_byte(dev, 0x8D, &write_target); 3322 pci_write_config_byte(dev, 0x8D, 0xB7); 3323 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3324 pci_write_config_byte(dev, 0x8E, write_enable); 3325 pci_write_config_byte(dev, 0x8D, write_target); 3326 3327 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3328 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3329 } 3330 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3331 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3332 3333 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3334 { 3335 u8 write_enable; 3336 u8 disable; 3337 3338 /* 3339 * Disable via FireWire interface 3340 * 3341 * This must be done via function #0 3342 */ 3343 if (PCI_FUNC(dev->devfn)) 3344 return; 3345 /* 3346 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3347 * certain types of SD/MMC cards. Lowering the SD base clock 3348 * frequency from 200Mhz to 50Mhz fixes this issue. 3349 * 3350 * 0x150 - SD2.0 mode enable for changing base clock 3351 * frequency to 50Mhz 3352 * 0xe1 - Base clock frequency 3353 * 0x32 - 50Mhz new clock frequency 3354 * 0xf9 - Key register for 0x150 3355 * 0xfc - key register for 0xe1 3356 */ 3357 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3358 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3359 pci_write_config_byte(dev, 0xf9, 0xfc); 3360 pci_write_config_byte(dev, 0x150, 0x10); 3361 pci_write_config_byte(dev, 0xf9, 0x00); 3362 pci_write_config_byte(dev, 0xfc, 0x01); 3363 pci_write_config_byte(dev, 0xe1, 0x32); 3364 pci_write_config_byte(dev, 0xfc, 0x00); 3365 3366 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3367 } 3368 3369 pci_read_config_byte(dev, 0xCB, &disable); 3370 3371 if (disable & 0x02) 3372 return; 3373 3374 pci_read_config_byte(dev, 0xCA, &write_enable); 3375 pci_write_config_byte(dev, 0xCA, 0x57); 3376 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3377 pci_write_config_byte(dev, 0xCA, write_enable); 3378 3379 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3380 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3381 3382 } 3383 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3384 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3385 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3386 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3387 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3388 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3389 #endif /*CONFIG_MMC_RICOH_MMC*/ 3390 3391 #ifdef CONFIG_DMAR_TABLE 3392 #define VTUNCERRMSK_REG 0x1ac 3393 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3394 /* 3395 * This is a quirk for masking VT-d spec-defined errors to platform error 3396 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3397 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3398 * on the RAS config settings of the platform) when a VT-d fault happens. 3399 * The resulting SMI caused the system to hang. 3400 * 3401 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3402 * need to report the same error through other channels. 3403 */ 3404 static void vtd_mask_spec_errors(struct pci_dev *dev) 3405 { 3406 u32 word; 3407 3408 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3409 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3410 } 3411 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3412 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3413 #endif 3414 3415 static void fixup_ti816x_class(struct pci_dev *dev) 3416 { 3417 u32 class = dev->class; 3418 3419 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3420 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3421 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3422 class, dev->class); 3423 } 3424 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3425 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3426 3427 /* 3428 * Some PCIe devices do not work reliably with the claimed maximum 3429 * payload size supported. 3430 */ 3431 static void fixup_mpss_256(struct pci_dev *dev) 3432 { 3433 dev->pcie_mpss = 1; /* 256 bytes */ 3434 } 3435 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3436 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3437 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3438 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3439 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3440 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3441 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3442 3443 /* 3444 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3445 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3446 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3447 * until all of the devices are discovered and buses walked, read completion 3448 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3449 * it is possible to hotplug a device with MPS of 256B. 3450 */ 3451 static void quirk_intel_mc_errata(struct pci_dev *dev) 3452 { 3453 int err; 3454 u16 rcc; 3455 3456 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3457 pcie_bus_config == PCIE_BUS_DEFAULT) 3458 return; 3459 3460 /* 3461 * Intel erratum specifies bits to change but does not say what 3462 * they are. Keeping them magical until such time as the registers 3463 * and values can be explained. 3464 */ 3465 err = pci_read_config_word(dev, 0x48, &rcc); 3466 if (err) { 3467 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3468 return; 3469 } 3470 3471 if (!(rcc & (1 << 10))) 3472 return; 3473 3474 rcc &= ~(1 << 10); 3475 3476 err = pci_write_config_word(dev, 0x48, rcc); 3477 if (err) { 3478 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3479 return; 3480 } 3481 3482 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3483 } 3484 /* Intel 5000 series memory controllers and ports 2-7 */ 3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3499 /* Intel 5100 series memory controllers and ports 2-7 */ 3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3511 3512 /* 3513 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3514 * To work around this, query the size it should be configured to by the 3515 * device and modify the resource end to correspond to this new size. 3516 */ 3517 static void quirk_intel_ntb(struct pci_dev *dev) 3518 { 3519 int rc; 3520 u8 val; 3521 3522 rc = pci_read_config_byte(dev, 0x00D0, &val); 3523 if (rc) 3524 return; 3525 3526 resource_set_size(&dev->resource[2], (resource_size_t)1 << val); 3527 3528 rc = pci_read_config_byte(dev, 0x00D1, &val); 3529 if (rc) 3530 return; 3531 3532 resource_set_size(&dev->resource[4], (resource_size_t)1 << val); 3533 } 3534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3536 3537 /* 3538 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3539 * though no one is handling them (e.g., if the i915 driver is never 3540 * loaded). Additionally the interrupt destination is not set up properly 3541 * and the interrupt ends up -somewhere-. 3542 * 3543 * These spurious interrupts are "sticky" and the kernel disables the 3544 * (shared) interrupt line after 100,000+ generated interrupts. 3545 * 3546 * Fix it by disabling the still enabled interrupts. This resolves crashes 3547 * often seen on monitor unplug. 3548 */ 3549 #define I915_DEIER_REG 0x4400c 3550 static void disable_igfx_irq(struct pci_dev *dev) 3551 { 3552 void __iomem *regs = pci_iomap(dev, 0, 0); 3553 if (regs == NULL) { 3554 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3555 return; 3556 } 3557 3558 /* Check if any interrupt line is still enabled */ 3559 if (readl(regs + I915_DEIER_REG) != 0) { 3560 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3561 3562 writel(0, regs + I915_DEIER_REG); 3563 } 3564 3565 pci_iounmap(dev, regs); 3566 } 3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3574 3575 /* 3576 * PCI devices which are on Intel chips can skip the 10ms delay 3577 * before entering D3 mode. 3578 */ 3579 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3580 { 3581 dev->d3hot_delay = 0; 3582 } 3583 /* C600 Series devices do not need 10ms d3hot_delay */ 3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3587 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3599 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3609 3610 /* 3611 * Some devices may pass our check in pci_intx_mask_supported() if 3612 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3613 * support this feature. 3614 */ 3615 static void quirk_broken_intx_masking(struct pci_dev *dev) 3616 { 3617 dev->broken_intx_masking = 1; 3618 } 3619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3620 quirk_broken_intx_masking); 3621 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3622 quirk_broken_intx_masking); 3623 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3624 quirk_broken_intx_masking); 3625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, 3626 quirk_broken_intx_masking); 3627 3628 /* 3629 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3630 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3631 * 3632 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3633 */ 3634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3635 quirk_broken_intx_masking); 3636 3637 /* 3638 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3639 * DisINTx can be set but the interrupt status bit is non-functional. 3640 */ 3641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3657 3658 static u16 mellanox_broken_intx_devs[] = { 3659 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3660 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3661 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3662 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3663 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3664 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3665 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3666 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3667 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3668 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3669 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3670 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3671 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3672 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3673 }; 3674 3675 #define CONNECTX_4_CURR_MAX_MINOR 99 3676 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3677 3678 /* 3679 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3680 * If so, don't mark it as broken. 3681 * FW minor > 99 means older FW version format and no INTx masking support. 3682 * FW minor < 14 means new FW version format and no INTx masking support. 3683 */ 3684 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3685 { 3686 __be32 __iomem *fw_ver; 3687 u16 fw_major; 3688 u16 fw_minor; 3689 u16 fw_subminor; 3690 u32 fw_maj_min; 3691 u32 fw_sub_min; 3692 int i; 3693 3694 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3695 if (pdev->device == mellanox_broken_intx_devs[i]) { 3696 pdev->broken_intx_masking = 1; 3697 return; 3698 } 3699 } 3700 3701 /* 3702 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3703 * support so shouldn't be checked further 3704 */ 3705 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3706 return; 3707 3708 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3709 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3710 return; 3711 3712 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3713 if (pci_enable_device_mem(pdev)) { 3714 pci_warn(pdev, "Can't enable device memory\n"); 3715 return; 3716 } 3717 3718 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3719 if (!fw_ver) { 3720 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3721 goto out; 3722 } 3723 3724 /* Reading from resource space should be 32b aligned */ 3725 fw_maj_min = ioread32be(fw_ver); 3726 fw_sub_min = ioread32be(fw_ver + 1); 3727 fw_major = fw_maj_min & 0xffff; 3728 fw_minor = fw_maj_min >> 16; 3729 fw_subminor = fw_sub_min & 0xffff; 3730 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3731 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3732 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3733 fw_major, fw_minor, fw_subminor, pdev->device == 3734 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3735 pdev->broken_intx_masking = 1; 3736 } 3737 3738 iounmap(fw_ver); 3739 3740 out: 3741 pci_disable_device(pdev); 3742 } 3743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3744 mellanox_check_broken_intx_masking); 3745 3746 static void quirk_no_bus_reset(struct pci_dev *dev) 3747 { 3748 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3749 } 3750 3751 /* 3752 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3753 * prevented for those affected devices. 3754 */ 3755 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3756 { 3757 if ((dev->device & 0xffc0) == 0x2340) 3758 quirk_no_bus_reset(dev); 3759 } 3760 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3761 quirk_nvidia_no_bus_reset); 3762 3763 /* 3764 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3765 * The device will throw a Link Down error on AER-capable systems and 3766 * regardless of AER, config space of the device is never accessible again 3767 * and typically causes the system to hang or reset when access is attempted. 3768 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3769 */ 3770 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3771 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3772 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3773 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3774 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3775 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3776 3777 /* 3778 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3779 * reset when used with certain child devices. After the reset, config 3780 * accesses to the child may fail. 3781 */ 3782 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3783 3784 /* 3785 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3786 * automatically disables LTSSM when Secondary Bus Reset is received and 3787 * the device stops working. Prevent bus reset for these devices. With 3788 * this change, the device can be assigned to VMs with VFIO, but it will 3789 * leak state between VMs. Reference 3790 * https://e2e.ti.com/support/processors/f/791/t/954382 3791 */ 3792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3793 3794 static void quirk_no_pm_reset(struct pci_dev *dev) 3795 { 3796 /* 3797 * We can't do a bus reset on root bus devices, but an ineffective 3798 * PM reset may be better than nothing. 3799 */ 3800 if (!pci_is_root_bus(dev->bus)) 3801 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3802 } 3803 3804 /* 3805 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3806 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3807 * to have no effect on the device: it retains the framebuffer contents and 3808 * monitor sync. Advertising this support makes other layers, like VFIO, 3809 * assume pci_reset_function() is viable for this device. Mark it as 3810 * unavailable to skip it when testing reset methods. 3811 */ 3812 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3813 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3814 3815 /* 3816 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3817 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3818 * any effect on the device: It continues to be operational and network ports 3819 * remain up. Advertising this support makes it seem as if a PM reset is viable 3820 * for these devices. Mark it as unavailable to skip it when testing reset 3821 * methods. 3822 */ 3823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3824 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3826 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3827 3828 /* 3829 * Thunderbolt controllers with broken MSI hotplug signaling: 3830 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3831 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3832 */ 3833 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3834 { 3835 if (pdev->is_pciehp && 3836 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3837 pdev->revision <= 1)) 3838 pdev->no_msi = 1; 3839 } 3840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3841 quirk_thunderbolt_hotplug_msi); 3842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3843 quirk_thunderbolt_hotplug_msi); 3844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3845 quirk_thunderbolt_hotplug_msi); 3846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3847 quirk_thunderbolt_hotplug_msi); 3848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3849 quirk_thunderbolt_hotplug_msi); 3850 3851 #ifdef CONFIG_ACPI 3852 /* 3853 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3854 * 3855 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3856 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3857 * be present after resume if a device was plugged in before suspend. 3858 * 3859 * The Thunderbolt controller consists of a PCIe switch with downstream 3860 * bridges leading to the NHI and to the tunnel PCI bridges. 3861 * 3862 * This quirk cuts power to the whole chip. Therefore we have to apply it 3863 * during suspend_noirq of the upstream bridge. 3864 * 3865 * Power is automagically restored before resume. No action is needed. 3866 */ 3867 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3868 { 3869 acpi_handle bridge, SXIO, SXFP, SXLV; 3870 3871 if (!x86_apple_machine) 3872 return; 3873 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3874 return; 3875 3876 /* 3877 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3878 * We don't know how to turn it back on again, but firmware does, 3879 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3880 * firmware. 3881 */ 3882 if (!pm_suspend_via_firmware()) 3883 return; 3884 3885 bridge = ACPI_HANDLE(&dev->dev); 3886 if (!bridge) 3887 return; 3888 3889 /* 3890 * SXIO and SXLV are present only on machines requiring this quirk. 3891 * Thunderbolt bridges in external devices might have the same 3892 * device ID as those on the host, but they will not have the 3893 * associated ACPI methods. This implicitly checks that we are at 3894 * the right bridge. 3895 */ 3896 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3897 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3898 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3899 return; 3900 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3901 3902 /* magic sequence */ 3903 acpi_execute_simple_method(SXIO, NULL, 1); 3904 acpi_execute_simple_method(SXFP, NULL, 0); 3905 msleep(300); 3906 acpi_execute_simple_method(SXLV, NULL, 0); 3907 acpi_execute_simple_method(SXIO, NULL, 0); 3908 acpi_execute_simple_method(SXLV, NULL, 0); 3909 } 3910 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3911 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3912 quirk_apple_poweroff_thunderbolt); 3913 #endif 3914 3915 /* 3916 * Following are device-specific reset methods which can be used to 3917 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3918 * not available. 3919 */ 3920 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3921 { 3922 /* 3923 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3924 * 3925 * The 82599 supports FLR on VFs, but FLR support is reported only 3926 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3927 * Thus we must call pcie_flr() directly without first checking if it is 3928 * supported. 3929 */ 3930 if (!probe) 3931 pcie_flr(dev); 3932 return 0; 3933 } 3934 3935 #define SOUTH_CHICKEN2 0xc2004 3936 #define PCH_PP_STATUS 0xc7200 3937 #define PCH_PP_CONTROL 0xc7204 3938 #define MSG_CTL 0x45010 3939 #define NSDE_PWR_STATE 0xd0100 3940 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3941 3942 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3943 { 3944 void __iomem *mmio_base; 3945 unsigned long timeout; 3946 u32 val; 3947 3948 if (probe) 3949 return 0; 3950 3951 mmio_base = pci_iomap(dev, 0, 0); 3952 if (!mmio_base) 3953 return -ENOMEM; 3954 3955 iowrite32(0x00000002, mmio_base + MSG_CTL); 3956 3957 /* 3958 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3959 * driver loaded sets the right bits. However, this's a reset and 3960 * the bits have been set by i915 previously, so we clobber 3961 * SOUTH_CHICKEN2 register directly here. 3962 */ 3963 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3964 3965 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3966 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3967 3968 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3969 do { 3970 val = ioread32(mmio_base + PCH_PP_STATUS); 3971 if ((val & 0xb0000000) == 0) 3972 goto reset_complete; 3973 msleep(10); 3974 } while (time_before(jiffies, timeout)); 3975 pci_warn(dev, "timeout during reset\n"); 3976 3977 reset_complete: 3978 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3979 3980 pci_iounmap(dev, mmio_base); 3981 return 0; 3982 } 3983 3984 /* Device-specific reset method for Chelsio T4-based adapters */ 3985 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 3986 { 3987 u16 old_command; 3988 u16 msix_flags; 3989 3990 /* 3991 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3992 * that we have no device-specific reset method. 3993 */ 3994 if ((dev->device & 0xf000) != 0x4000) 3995 return -ENOTTY; 3996 3997 /* 3998 * If this is the "probe" phase, return 0 indicating that we can 3999 * reset this device. 4000 */ 4001 if (probe) 4002 return 0; 4003 4004 /* 4005 * T4 can wedge if there are DMAs in flight within the chip and Bus 4006 * Master has been disabled. We need to have it on till the Function 4007 * Level Reset completes. (BUS_MASTER is disabled in 4008 * pci_reset_function()). 4009 */ 4010 pci_read_config_word(dev, PCI_COMMAND, &old_command); 4011 pci_write_config_word(dev, PCI_COMMAND, 4012 old_command | PCI_COMMAND_MASTER); 4013 4014 /* 4015 * Perform the actual device function reset, saving and restoring 4016 * configuration information around the reset. 4017 */ 4018 pci_save_state(dev); 4019 4020 /* 4021 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 4022 * are disabled when an MSI-X interrupt message needs to be delivered. 4023 * So we briefly re-enable MSI-X interrupts for the duration of the 4024 * FLR. The pci_restore_state() below will restore the original 4025 * MSI-X state. 4026 */ 4027 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 4028 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 4029 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 4030 msix_flags | 4031 PCI_MSIX_FLAGS_ENABLE | 4032 PCI_MSIX_FLAGS_MASKALL); 4033 4034 pcie_flr(dev); 4035 4036 /* 4037 * Restore the configuration information (BAR values, etc.) including 4038 * the original PCI Configuration Space Command word, and return 4039 * success. 4040 */ 4041 pci_restore_state(dev); 4042 pci_write_config_word(dev, PCI_COMMAND, old_command); 4043 return 0; 4044 } 4045 4046 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4047 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4048 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4049 4050 /* 4051 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4052 * FLR where config space reads from the device return -1. We seem to be 4053 * able to avoid this condition if we disable the NVMe controller prior to 4054 * FLR. This quirk is generic for any NVMe class device requiring similar 4055 * assistance to quiesce the device prior to FLR. 4056 * 4057 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4058 * Revision 1.0e: 4059 * Chapter 2: Required and optional PCI config registers 4060 * Chapter 3: NVMe control registers 4061 * Chapter 7.3: Reset behavior 4062 */ 4063 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4064 { 4065 void __iomem *bar; 4066 u16 cmd; 4067 u32 cfg; 4068 4069 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4070 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4071 return -ENOTTY; 4072 4073 if (probe) 4074 return 0; 4075 4076 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4077 if (!bar) 4078 return -ENOTTY; 4079 4080 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4081 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4082 4083 cfg = readl(bar + NVME_REG_CC); 4084 4085 /* Disable controller if enabled */ 4086 if (cfg & NVME_CC_ENABLE) { 4087 u32 cap = readl(bar + NVME_REG_CAP); 4088 unsigned long timeout; 4089 4090 /* 4091 * Per nvme_disable_ctrl() skip shutdown notification as it 4092 * could complete commands to the admin queue. We only intend 4093 * to quiesce the device before reset. 4094 */ 4095 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4096 4097 writel(cfg, bar + NVME_REG_CC); 4098 4099 /* 4100 * Some controllers require an additional delay here, see 4101 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4102 * supported by this quirk. 4103 */ 4104 4105 /* Cap register provides max timeout in 500ms increments */ 4106 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4107 4108 for (;;) { 4109 u32 status = readl(bar + NVME_REG_CSTS); 4110 4111 /* Ready status becomes zero on disable complete */ 4112 if (!(status & NVME_CSTS_RDY)) 4113 break; 4114 4115 msleep(100); 4116 4117 if (time_after(jiffies, timeout)) { 4118 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4119 break; 4120 } 4121 } 4122 } 4123 4124 pci_iounmap(dev, bar); 4125 4126 pcie_flr(dev); 4127 4128 return 0; 4129 } 4130 4131 /* 4132 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4133 * timeout waiting for ready status to change after NVMe enable if the driver 4134 * starts interacting with the device too soon after FLR. A 250ms delay after 4135 * FLR has heuristically proven to produce reliably working results for device 4136 * assignment cases. 4137 */ 4138 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4139 { 4140 if (probe) 4141 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4142 4143 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4144 4145 msleep(250); 4146 4147 return 0; 4148 } 4149 4150 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4151 #define HINIC_VF_FLR_TYPE 0x1000 4152 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4153 #define HINIC_VF_OP 0xE80 4154 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4155 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4156 4157 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4158 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4159 { 4160 unsigned long timeout; 4161 void __iomem *bar; 4162 u32 val; 4163 4164 if (probe) 4165 return 0; 4166 4167 bar = pci_iomap(pdev, 0, 0); 4168 if (!bar) 4169 return -ENOTTY; 4170 4171 /* Get and check firmware capabilities */ 4172 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4173 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4174 pci_iounmap(pdev, bar); 4175 return -ENOTTY; 4176 } 4177 4178 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4179 val = ioread32be(bar + HINIC_VF_OP); 4180 val = val | HINIC_VF_FLR_PROC_BIT; 4181 iowrite32be(val, bar + HINIC_VF_OP); 4182 4183 pcie_flr(pdev); 4184 4185 /* 4186 * The device must recapture its Bus and Device Numbers after FLR 4187 * in order generate Completions. Issue a config write to let the 4188 * device capture this information. 4189 */ 4190 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4191 4192 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4193 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4194 do { 4195 val = ioread32be(bar + HINIC_VF_OP); 4196 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4197 goto reset_complete; 4198 msleep(20); 4199 } while (time_before(jiffies, timeout)); 4200 4201 val = ioread32be(bar + HINIC_VF_OP); 4202 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4203 goto reset_complete; 4204 4205 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4206 4207 reset_complete: 4208 pci_iounmap(pdev, bar); 4209 4210 return 0; 4211 } 4212 4213 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4214 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4215 reset_intel_82599_sfp_virtfn }, 4216 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4217 reset_ivb_igd }, 4218 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4219 reset_ivb_igd }, 4220 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4221 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4222 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4223 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4224 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4225 reset_chelsio_generic_dev }, 4226 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4227 reset_hinic_vf_dev }, 4228 { 0 } 4229 }; 4230 4231 /* 4232 * These device-specific reset methods are here rather than in a driver 4233 * because when a host assigns a device to a guest VM, the host may need 4234 * to reset the device but probably doesn't have a driver for it. 4235 */ 4236 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4237 { 4238 const struct pci_dev_reset_methods *i; 4239 4240 for (i = pci_dev_reset_methods; i->reset; i++) { 4241 if ((i->vendor == dev->vendor || 4242 i->vendor == (u16)PCI_ANY_ID) && 4243 (i->device == dev->device || 4244 i->device == (u16)PCI_ANY_ID)) 4245 return i->reset(dev, probe); 4246 } 4247 4248 return -ENOTTY; 4249 } 4250 4251 static void quirk_dma_func0_alias(struct pci_dev *dev) 4252 { 4253 if (PCI_FUNC(dev->devfn) != 0) 4254 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4255 } 4256 4257 /* 4258 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4259 * 4260 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4261 */ 4262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4264 4265 /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ 4266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); 4267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); 4268 4269 static void quirk_dma_func1_alias(struct pci_dev *dev) 4270 { 4271 if (PCI_FUNC(dev->devfn) != 1) 4272 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4273 } 4274 4275 /* 4276 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4277 * SKUs function 1 is present and is a legacy IDE controller, in other 4278 * SKUs this function is not present, making this a ghost requester. 4279 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4280 */ 4281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4282 quirk_dma_func1_alias); 4283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4284 quirk_dma_func1_alias); 4285 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4287 quirk_dma_func1_alias); 4288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4289 quirk_dma_func1_alias); 4290 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4292 quirk_dma_func1_alias); 4293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4294 quirk_dma_func1_alias); 4295 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4297 quirk_dma_func1_alias); 4298 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4300 quirk_dma_func1_alias); 4301 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4303 quirk_dma_func1_alias); 4304 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4306 quirk_dma_func1_alias); 4307 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4309 quirk_dma_func1_alias); 4310 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4312 quirk_dma_func1_alias); 4313 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4315 quirk_dma_func1_alias); 4316 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4318 quirk_dma_func1_alias); 4319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4320 quirk_dma_func1_alias); 4321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4322 quirk_dma_func1_alias); 4323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4324 quirk_dma_func1_alias); 4325 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4327 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4328 quirk_dma_func1_alias); 4329 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4330 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4331 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4332 quirk_dma_func1_alias); 4333 4334 /* 4335 * Some devices DMA with the wrong devfn, not just the wrong function. 4336 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4337 * the alias is "fixed" and independent of the device devfn. 4338 * 4339 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4340 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4341 * single device on the secondary bus. In reality, the single exposed 4342 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4343 * that provides a bridge to the internal bus of the I/O processor. The 4344 * controller supports private devices, which can be hidden from PCI config 4345 * space. In the case of the Adaptec 3405, a private device at 01.0 4346 * appears to be the DMA engine, which therefore needs to become a DMA 4347 * alias for the device. 4348 */ 4349 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4350 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4351 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4352 .driver_data = PCI_DEVFN(1, 0) }, 4353 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4354 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4355 .driver_data = PCI_DEVFN(1, 0) }, 4356 { 0 } 4357 }; 4358 4359 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4360 { 4361 const struct pci_device_id *id; 4362 4363 id = pci_match_id(fixed_dma_alias_tbl, dev); 4364 if (id) 4365 pci_add_dma_alias(dev, id->driver_data, 1); 4366 } 4367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4368 4369 /* 4370 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4371 * using the wrong DMA alias for the device. Some of these devices can be 4372 * used as either forward or reverse bridges, so we need to test whether the 4373 * device is operating in the correct mode. We could probably apply this 4374 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4375 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4376 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4377 */ 4378 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4379 { 4380 if (!pci_is_root_bus(pdev->bus) && 4381 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4382 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4383 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4384 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4385 } 4386 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4388 quirk_use_pcie_bridge_dma_alias); 4389 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4390 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4391 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4392 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4393 /* ITE 8893 has the same problem as the 8892 */ 4394 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4395 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4396 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4397 4398 /* 4399 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4400 * be added as aliases to the DMA device in order to allow buffer access 4401 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4402 * programmed in the EEPROM. 4403 */ 4404 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4405 { 4406 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4407 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4408 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4409 } 4410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4411 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4412 4413 /* 4414 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4415 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4416 * 4417 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4418 * when IOMMU is enabled. These aliases allow computational unit access to 4419 * host memory. These aliases mark the whole VCA device as one IOMMU 4420 * group. 4421 * 4422 * All possible slot numbers (0x20) are used, since we are unable to tell 4423 * what slot is used on other side. This quirk is intended for both host 4424 * and computational unit sides. The VCA devices have up to five functions 4425 * (four for DMA channels and one additional). 4426 */ 4427 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4428 { 4429 const unsigned int num_pci_slots = 0x20; 4430 unsigned int slot; 4431 4432 for (slot = 0; slot < num_pci_slots; slot++) 4433 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4434 } 4435 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4441 4442 /* 4443 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4444 * associated not at the root bus, but at a bridge below. This quirk avoids 4445 * generating invalid DMA aliases. 4446 */ 4447 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4448 { 4449 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4450 } 4451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4452 quirk_bridge_cavm_thrx2_pcie_root); 4453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4454 quirk_bridge_cavm_thrx2_pcie_root); 4455 4456 /* 4457 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4458 * class code. Fix it. 4459 */ 4460 static void quirk_tw686x_class(struct pci_dev *pdev) 4461 { 4462 u32 class = pdev->class; 4463 4464 /* Use "Multimedia controller" class */ 4465 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4466 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4467 class, pdev->class); 4468 } 4469 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4470 quirk_tw686x_class); 4471 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4472 quirk_tw686x_class); 4473 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4474 quirk_tw686x_class); 4475 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4476 quirk_tw686x_class); 4477 4478 /* 4479 * Some devices have problems with Transaction Layer Packets with the Relaxed 4480 * Ordering Attribute set. Such devices should mark themselves and other 4481 * device drivers should check before sending TLPs with RO set. 4482 */ 4483 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4484 { 4485 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4486 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4487 } 4488 4489 /* 4490 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4491 * Complex have a Flow Control Credit issue which can cause performance 4492 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4493 */ 4494 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4495 quirk_relaxedordering_disable); 4496 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4497 quirk_relaxedordering_disable); 4498 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4499 quirk_relaxedordering_disable); 4500 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4501 quirk_relaxedordering_disable); 4502 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4503 quirk_relaxedordering_disable); 4504 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4505 quirk_relaxedordering_disable); 4506 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4507 quirk_relaxedordering_disable); 4508 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4509 quirk_relaxedordering_disable); 4510 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4511 quirk_relaxedordering_disable); 4512 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4513 quirk_relaxedordering_disable); 4514 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4515 quirk_relaxedordering_disable); 4516 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4517 quirk_relaxedordering_disable); 4518 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4519 quirk_relaxedordering_disable); 4520 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4521 quirk_relaxedordering_disable); 4522 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4523 quirk_relaxedordering_disable); 4524 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4525 quirk_relaxedordering_disable); 4526 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4527 quirk_relaxedordering_disable); 4528 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4529 quirk_relaxedordering_disable); 4530 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4531 quirk_relaxedordering_disable); 4532 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4533 quirk_relaxedordering_disable); 4534 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4535 quirk_relaxedordering_disable); 4536 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4537 quirk_relaxedordering_disable); 4538 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4539 quirk_relaxedordering_disable); 4540 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4541 quirk_relaxedordering_disable); 4542 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4543 quirk_relaxedordering_disable); 4544 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4545 quirk_relaxedordering_disable); 4546 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4547 quirk_relaxedordering_disable); 4548 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4549 quirk_relaxedordering_disable); 4550 4551 /* 4552 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4553 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4554 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4555 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4556 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4557 * November 10, 2010). As a result, on this platform we can't use Relaxed 4558 * Ordering for Upstream TLPs. 4559 */ 4560 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4561 quirk_relaxedordering_disable); 4562 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4563 quirk_relaxedordering_disable); 4564 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4565 quirk_relaxedordering_disable); 4566 4567 /* 4568 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4569 * values for the Attribute as were supplied in the header of the 4570 * corresponding Request, except as explicitly allowed when IDO is used." 4571 * 4572 * If a non-compliant device generates a completion with a different 4573 * attribute than the request, the receiver may accept it (which itself 4574 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4575 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4576 * device access timeout. 4577 * 4578 * If the non-compliant device generates completions with zero attributes 4579 * (instead of copying the attributes from the request), we can work around 4580 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4581 * upstream devices so they always generate requests with zero attributes. 4582 * 4583 * This affects other devices under the same Root Port, but since these 4584 * attributes are performance hints, there should be no functional problem. 4585 * 4586 * Note that Configuration Space accesses are never supposed to have TLP 4587 * Attributes, so we're safe waiting till after any Configuration Space 4588 * accesses to do the Root Port fixup. 4589 */ 4590 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4591 { 4592 struct pci_dev *root_port = pcie_find_root_port(pdev); 4593 4594 if (!root_port) { 4595 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4596 return; 4597 } 4598 4599 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4600 dev_name(&pdev->dev)); 4601 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL, 4602 PCI_EXP_DEVCTL_RELAX_EN | 4603 PCI_EXP_DEVCTL_NOSNOOP_EN); 4604 } 4605 4606 /* 4607 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4608 * Completion it generates. 4609 */ 4610 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4611 { 4612 /* 4613 * This mask/compare operation selects for Physical Function 4 on a 4614 * T5. We only need to fix up the Root Port once for any of the 4615 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4616 * 0x54xx so we use that one. 4617 */ 4618 if ((pdev->device & 0xff00) == 0x5400) 4619 quirk_disable_root_port_attributes(pdev); 4620 } 4621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4622 quirk_chelsio_T5_disable_root_port_attributes); 4623 4624 /* 4625 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4626 * by a device 4627 * @acs_ctrl_req: Bitmask of desired ACS controls 4628 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4629 * the hardware design 4630 * 4631 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4632 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4633 * caller desires. Return 0 otherwise. 4634 */ 4635 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4636 { 4637 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4638 return 1; 4639 return 0; 4640 } 4641 4642 /* 4643 * AMD has indicated that the devices below do not support peer-to-peer 4644 * in any system where they are found in the southbridge with an AMD 4645 * IOMMU in the system. Multifunction devices that do not support 4646 * peer-to-peer between functions can claim to support a subset of ACS. 4647 * Such devices effectively enable request redirect (RR) and completion 4648 * redirect (CR) since all transactions are redirected to the upstream 4649 * root complex. 4650 * 4651 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4652 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4653 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4654 * 4655 * 1002:4385 SBx00 SMBus Controller 4656 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4657 * 1002:4383 SBx00 Azalia (Intel HDA) 4658 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4659 * 1002:4384 SBx00 PCI to PCI Bridge 4660 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4661 * 4662 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4663 * 4664 * 1022:780f [AMD] FCH PCI Bridge 4665 * 1022:7809 [AMD] FCH USB OHCI Controller 4666 */ 4667 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4668 { 4669 #ifdef CONFIG_ACPI 4670 struct acpi_table_header *header = NULL; 4671 acpi_status status; 4672 4673 /* Targeting multifunction devices on the SB (appears on root bus) */ 4674 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4675 return -ENODEV; 4676 4677 /* The IVRS table describes the AMD IOMMU */ 4678 status = acpi_get_table("IVRS", 0, &header); 4679 if (ACPI_FAILURE(status)) 4680 return -ENODEV; 4681 4682 acpi_put_table(header); 4683 4684 /* Filter out flags not applicable to multifunction */ 4685 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4686 4687 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4688 #else 4689 return -ENODEV; 4690 #endif 4691 } 4692 4693 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4694 { 4695 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4696 return false; 4697 4698 switch (dev->device) { 4699 /* 4700 * Effectively selects all downstream ports for whole ThunderX1 4701 * (which represents 8 SoCs). 4702 */ 4703 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4704 case 0xaf84: /* ThunderX2 */ 4705 case 0xb884: /* ThunderX3 */ 4706 return true; 4707 default: 4708 return false; 4709 } 4710 } 4711 4712 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4713 { 4714 if (!pci_quirk_cavium_acs_match(dev)) 4715 return -ENOTTY; 4716 4717 /* 4718 * Cavium Root Ports don't advertise an ACS capability. However, 4719 * the RTL internally implements similar protection as if ACS had 4720 * Source Validation, Request Redirection, Completion Redirection, 4721 * and Upstream Forwarding features enabled. Assert that the 4722 * hardware implements and enables equivalent ACS functionality for 4723 * these flags. 4724 */ 4725 return pci_acs_ctrl_enabled(acs_flags, 4726 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4727 } 4728 4729 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4730 { 4731 /* 4732 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4733 * transactions with others, allowing masking out these bits as if they 4734 * were unimplemented in the ACS capability. 4735 */ 4736 return pci_acs_ctrl_enabled(acs_flags, 4737 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4738 } 4739 4740 /* 4741 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4742 * But the implementation could block peer-to-peer transactions between them 4743 * and provide ACS-like functionality. 4744 */ 4745 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4746 { 4747 if (!pci_is_pcie(dev) || 4748 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4749 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4750 return -ENOTTY; 4751 4752 /* 4753 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4754 * implement ACS capability in accordance with the PCIe Spec. 4755 */ 4756 switch (dev->device) { 4757 case 0x0710 ... 0x071e: 4758 case 0x0721: 4759 case 0x0723 ... 0x0752: 4760 return pci_acs_ctrl_enabled(acs_flags, 4761 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4762 } 4763 4764 return false; 4765 } 4766 4767 /* 4768 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4769 * transactions and validate bus numbers in requests, but do not provide an 4770 * actual PCIe ACS capability. This is the list of device IDs known to fall 4771 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4772 */ 4773 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4774 /* Ibexpeak PCH */ 4775 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4776 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4777 /* Cougarpoint PCH */ 4778 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4779 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4780 /* Pantherpoint PCH */ 4781 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4782 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4783 /* Lynxpoint-H PCH */ 4784 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4785 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4786 /* Lynxpoint-LP PCH */ 4787 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4788 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4789 /* Wildcat PCH */ 4790 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4791 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4792 /* Patsburg (X79) PCH */ 4793 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4794 /* Wellsburg (X99) PCH */ 4795 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4796 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4797 /* Lynx Point (9 series) PCH */ 4798 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4799 }; 4800 4801 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4802 { 4803 int i; 4804 4805 /* Filter out a few obvious non-matches first */ 4806 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4807 return false; 4808 4809 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4810 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4811 return true; 4812 4813 return false; 4814 } 4815 4816 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4817 { 4818 if (!pci_quirk_intel_pch_acs_match(dev)) 4819 return -ENOTTY; 4820 4821 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4822 return pci_acs_ctrl_enabled(acs_flags, 4823 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4824 4825 return pci_acs_ctrl_enabled(acs_flags, 0); 4826 } 4827 4828 /* 4829 * These QCOM Root Ports do provide ACS-like features to disable peer 4830 * transactions and validate bus numbers in requests, but do not provide an 4831 * actual PCIe ACS capability. Hardware supports source validation but it 4832 * will report the issue as Completer Abort instead of ACS Violation. 4833 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4834 * Complex with unique segment numbers. It is not possible for one Root 4835 * Port to pass traffic to another Root Port. All PCIe transactions are 4836 * terminated inside the Root Port. 4837 */ 4838 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4839 { 4840 return pci_acs_ctrl_enabled(acs_flags, 4841 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4842 } 4843 4844 /* 4845 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4846 * number and does provide isolation features to disable peer transactions 4847 * and validate bus numbers in requests, but does not provide an ACS 4848 * capability. 4849 */ 4850 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4851 { 4852 return pci_acs_ctrl_enabled(acs_flags, 4853 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4854 } 4855 4856 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4857 { 4858 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4859 return -ENOTTY; 4860 4861 /* 4862 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4863 * but do include ACS-like functionality. The hardware doesn't support 4864 * peer-to-peer transactions via the root port and each has a unique 4865 * segment number. 4866 * 4867 * Additionally, the root ports cannot send traffic to each other. 4868 */ 4869 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4870 4871 return acs_flags ? 0 : 1; 4872 } 4873 4874 /* 4875 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4876 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4877 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4878 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4879 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4880 * control register is at offset 8 instead of 6 and we should probably use 4881 * dword accesses to them. This applies to the following PCI Device IDs, as 4882 * found in volume 1 of the datasheet[2]: 4883 * 4884 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4885 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4886 * 4887 * N.B. This doesn't fix what lspci shows. 4888 * 4889 * The 100 series chipset specification update includes this as errata #23[3]. 4890 * 4891 * The 200 series chipset (Union Point) has the same bug according to the 4892 * specification update (Intel 200 Series Chipset Family Platform Controller 4893 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4894 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4895 * chipset include: 4896 * 4897 * 0xa290-0xa29f PCI Express Root port #{0-16} 4898 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4899 * 4900 * Mobile chipsets are also affected, 7th & 8th Generation 4901 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4902 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4903 * Processor Family I/O for U Quad Core Platforms Specification Update, 4904 * August 2017, Revision 002, Document#: 334660-002)[6] 4905 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4906 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4907 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4908 * 4909 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4910 * 4911 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4912 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4913 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4914 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4915 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4916 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4917 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4918 */ 4919 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4920 { 4921 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4922 return false; 4923 4924 switch (dev->device) { 4925 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4926 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4927 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4928 return true; 4929 } 4930 4931 return false; 4932 } 4933 4934 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4935 4936 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4937 { 4938 int pos; 4939 u32 cap, ctrl; 4940 4941 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4942 return -ENOTTY; 4943 4944 pos = dev->acs_cap; 4945 if (!pos) 4946 return -ENOTTY; 4947 4948 /* see pci_acs_flags_enabled() */ 4949 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4950 acs_flags &= (cap | PCI_ACS_EC); 4951 4952 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4953 4954 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4955 } 4956 4957 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4958 { 4959 /* 4960 * SV, TB, and UF are not relevant to multifunction endpoints. 4961 * 4962 * Multifunction devices are only required to implement RR, CR, and DT 4963 * in their ACS capability if they support peer-to-peer transactions. 4964 * Devices matching this quirk have been verified by the vendor to not 4965 * perform peer-to-peer with other functions, allowing us to mask out 4966 * these bits as if they were unimplemented in the ACS capability. 4967 */ 4968 return pci_acs_ctrl_enabled(acs_flags, 4969 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4970 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4971 } 4972 4973 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 4974 { 4975 /* 4976 * Intel RCiEP's are required to allow p2p only on translated 4977 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 4978 * "Root-Complex Peer to Peer Considerations". 4979 */ 4980 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 4981 return -ENOTTY; 4982 4983 return pci_acs_ctrl_enabled(acs_flags, 4984 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4985 } 4986 4987 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 4988 { 4989 /* 4990 * iProc PAXB Root Ports don't advertise an ACS capability, but 4991 * they do not allow peer-to-peer transactions between Root Ports. 4992 * Allow each Root Port to be in a separate IOMMU group by masking 4993 * SV/RR/CR/UF bits. 4994 */ 4995 return pci_acs_ctrl_enabled(acs_flags, 4996 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4997 } 4998 4999 static int pci_quirk_loongson_acs(struct pci_dev *dev, u16 acs_flags) 5000 { 5001 /* 5002 * Loongson PCIe Root Ports don't advertise an ACS capability, but 5003 * they do not allow peer-to-peer transactions between Root Ports. 5004 * Allow each Root Port to be in a separate IOMMU group by masking 5005 * SV/RR/CR/UF bits. 5006 */ 5007 return pci_acs_ctrl_enabled(acs_flags, 5008 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5009 } 5010 5011 /* 5012 * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on 5013 * multi-function devices, the hardware isolates the functions by 5014 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and 5015 * PCI_ACS_CR were set. 5016 * SFxxx 1G NICs(em). 5017 * RP1000/RP2000 10G NICs(sp). 5018 * FF5xxx 40G/25G/10G NICs(aml). 5019 */ 5020 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 5021 { 5022 switch (dev->device) { 5023 case 0x0100 ... 0x010F: /* EM */ 5024 case 0x1001: case 0x2001: /* SP */ 5025 case 0x5010: case 0x5025: case 0x5040: /* AML */ 5026 case 0x5110: case 0x5125: case 0x5140: /* AML */ 5027 return pci_acs_ctrl_enabled(acs_flags, 5028 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5029 } 5030 5031 return false; 5032 } 5033 5034 static const struct pci_dev_acs_enabled { 5035 u16 vendor; 5036 u16 device; 5037 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 5038 } pci_dev_acs_enabled[] = { 5039 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 5040 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 5041 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 5042 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 5043 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 5044 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 5045 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 5046 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 5047 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 5048 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 5049 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 5050 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 5051 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 5052 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 5053 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 5054 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 5055 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 5056 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 5057 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 5058 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 5059 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 5060 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 5061 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5062 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5063 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5064 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5065 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5066 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5067 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5068 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5069 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5070 /* 82580 */ 5071 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5072 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5073 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5074 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5075 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5076 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5077 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5078 /* 82576 */ 5079 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5080 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5081 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5082 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5083 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5084 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5085 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5086 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5087 /* 82575 */ 5088 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5089 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5090 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5091 /* I350 */ 5092 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5093 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5094 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5095 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5096 /* 82571 (Quads omitted due to non-ACS switch) */ 5097 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5098 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5099 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5100 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5101 /* I219 */ 5102 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5103 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5104 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5105 /* QCOM QDF2xxx root ports */ 5106 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5107 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5108 /* QCOM SA8775P root port */ 5109 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5110 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5111 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5112 /* Intel PCH root ports */ 5113 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5114 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5115 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5116 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5117 /* Cavium ThunderX */ 5118 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5119 /* Cavium multi-function devices */ 5120 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5121 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5122 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5123 /* APM X-Gene */ 5124 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5125 /* Ampere Computing */ 5126 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5127 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5128 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5129 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5130 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5131 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5132 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5133 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5134 /* Broadcom multi-function device */ 5135 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5136 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5137 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5138 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5139 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs }, 5140 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs }, 5141 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs }, 5142 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs }, 5143 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5144 /* Loongson PCIe Root Ports */ 5145 { PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs }, 5146 { PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs }, 5147 { PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs }, 5148 { PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs }, 5149 { PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs }, 5150 { PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs }, 5151 { PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs }, 5152 { PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs }, 5153 { PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs }, 5154 { PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs }, 5155 /* Amazon Annapurna Labs */ 5156 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5157 /* Zhaoxin multi-function devices */ 5158 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5159 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5160 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5161 /* NXP root ports, xx=16, 12, or 08 cores */ 5162 /* LX2xx0A : without security features + CAN-FD */ 5163 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5164 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5165 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5166 /* LX2xx0C : security features + CAN-FD */ 5167 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5168 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5169 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5170 /* LX2xx0E : security features + CAN */ 5171 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5172 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5173 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5174 /* LX2xx0N : without security features + CAN */ 5175 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5176 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5177 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5178 /* LX2xx2A : without security features + CAN-FD */ 5179 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5180 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5181 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5182 /* LX2xx2C : security features + CAN-FD */ 5183 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5184 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5185 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5186 /* LX2xx2E : security features + CAN */ 5187 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5188 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5189 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5190 /* LX2xx2N : without security features + CAN */ 5191 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5192 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5193 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5194 /* Zhaoxin Root/Downstream Ports */ 5195 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5196 /* Wangxun nics */ 5197 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5198 { 0 } 5199 }; 5200 5201 /* 5202 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5203 * @dev: PCI device 5204 * @acs_flags: Bitmask of desired ACS controls 5205 * 5206 * Returns: 5207 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5208 * device provides the desired controls 5209 * 0: Device does not provide all the desired controls 5210 * >0: Device provides all the controls in @acs_flags 5211 */ 5212 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5213 { 5214 const struct pci_dev_acs_enabled *i; 5215 int ret; 5216 5217 /* 5218 * Allow devices that do not expose standard PCIe ACS capabilities 5219 * or control to indicate their support here. Multi-function express 5220 * devices which do not allow internal peer-to-peer between functions, 5221 * but do not implement PCIe ACS may wish to return true here. 5222 */ 5223 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5224 if ((i->vendor == dev->vendor || 5225 i->vendor == (u16)PCI_ANY_ID) && 5226 (i->device == dev->device || 5227 i->device == (u16)PCI_ANY_ID)) { 5228 ret = i->acs_enabled(dev, acs_flags); 5229 if (ret >= 0) 5230 return ret; 5231 } 5232 } 5233 5234 return -ENOTTY; 5235 } 5236 5237 /* Config space offset of Root Complex Base Address register */ 5238 #define INTEL_LPC_RCBA_REG 0xf0 5239 /* 31:14 RCBA address */ 5240 #define INTEL_LPC_RCBA_MASK 0xffffc000 5241 /* RCBA Enable */ 5242 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5243 5244 /* Backbone Scratch Pad Register */ 5245 #define INTEL_BSPR_REG 0x1104 5246 /* Backbone Peer Non-Posted Disable */ 5247 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5248 /* Backbone Peer Posted Disable */ 5249 #define INTEL_BSPR_REG_BPPD (1 << 9) 5250 5251 /* Upstream Peer Decode Configuration Register */ 5252 #define INTEL_UPDCR_REG 0x1014 5253 /* 5:0 Peer Decode Enable bits */ 5254 #define INTEL_UPDCR_REG_MASK 0x3f 5255 5256 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5257 { 5258 u32 rcba, bspr, updcr; 5259 void __iomem *rcba_mem; 5260 5261 /* 5262 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5263 * are D28:F* and therefore get probed before LPC, thus we can't 5264 * use pci_get_slot()/pci_read_config_dword() here. 5265 */ 5266 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5267 INTEL_LPC_RCBA_REG, &rcba); 5268 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5269 return -EINVAL; 5270 5271 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5272 PAGE_ALIGN(INTEL_UPDCR_REG)); 5273 if (!rcba_mem) 5274 return -ENOMEM; 5275 5276 /* 5277 * The BSPR can disallow peer cycles, but it's set by soft strap and 5278 * therefore read-only. If both posted and non-posted peer cycles are 5279 * disallowed, we're ok. If either are allowed, then we need to use 5280 * the UPDCR to disable peer decodes for each port. This provides the 5281 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5282 */ 5283 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5284 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5285 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5286 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5287 if (updcr & INTEL_UPDCR_REG_MASK) { 5288 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5289 updcr &= ~INTEL_UPDCR_REG_MASK; 5290 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5291 } 5292 } 5293 5294 iounmap(rcba_mem); 5295 return 0; 5296 } 5297 5298 /* Miscellaneous Port Configuration register */ 5299 #define INTEL_MPC_REG 0xd8 5300 /* MPC: Invalid Receive Bus Number Check Enable */ 5301 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5302 5303 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5304 { 5305 u32 mpc; 5306 5307 /* 5308 * When enabled, the IRBNCE bit of the MPC register enables the 5309 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5310 * ensures that requester IDs fall within the bus number range 5311 * of the bridge. Enable if not already. 5312 */ 5313 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5314 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5315 pci_info(dev, "Enabling MPC IRBNCE\n"); 5316 mpc |= INTEL_MPC_REG_IRBNCE; 5317 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5318 } 5319 } 5320 5321 /* 5322 * Currently this quirk does the equivalent of 5323 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5324 * 5325 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5326 * if dev->external_facing || dev->untrusted 5327 */ 5328 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5329 { 5330 if (!pci_quirk_intel_pch_acs_match(dev)) 5331 return -ENOTTY; 5332 5333 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5334 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5335 return 0; 5336 } 5337 5338 pci_quirk_enable_intel_rp_mpc_acs(dev); 5339 5340 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5341 5342 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5343 5344 return 0; 5345 } 5346 5347 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5348 { 5349 int pos; 5350 u32 cap, ctrl; 5351 5352 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5353 return -ENOTTY; 5354 5355 pos = dev->acs_cap; 5356 if (!pos) 5357 return -ENOTTY; 5358 5359 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5360 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5361 5362 ctrl |= (cap & PCI_ACS_SV); 5363 ctrl |= (cap & PCI_ACS_RR); 5364 ctrl |= (cap & PCI_ACS_CR); 5365 ctrl |= (cap & PCI_ACS_UF); 5366 5367 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5368 ctrl |= (cap & PCI_ACS_TB); 5369 5370 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5371 5372 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5373 5374 return 0; 5375 } 5376 5377 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5378 { 5379 int pos; 5380 u32 cap, ctrl; 5381 5382 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5383 return -ENOTTY; 5384 5385 pos = dev->acs_cap; 5386 if (!pos) 5387 return -ENOTTY; 5388 5389 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5390 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5391 5392 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5393 5394 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5395 5396 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5397 5398 return 0; 5399 } 5400 5401 static const struct pci_dev_acs_ops { 5402 u16 vendor; 5403 u16 device; 5404 int (*enable_acs)(struct pci_dev *dev); 5405 int (*disable_acs_redir)(struct pci_dev *dev); 5406 } pci_dev_acs_ops[] = { 5407 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5408 .enable_acs = pci_quirk_enable_intel_pch_acs, 5409 }, 5410 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5411 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5412 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5413 }, 5414 }; 5415 5416 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5417 { 5418 const struct pci_dev_acs_ops *p; 5419 int i, ret; 5420 5421 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5422 p = &pci_dev_acs_ops[i]; 5423 if ((p->vendor == dev->vendor || 5424 p->vendor == (u16)PCI_ANY_ID) && 5425 (p->device == dev->device || 5426 p->device == (u16)PCI_ANY_ID) && 5427 p->enable_acs) { 5428 ret = p->enable_acs(dev); 5429 if (ret >= 0) 5430 return ret; 5431 } 5432 } 5433 5434 return -ENOTTY; 5435 } 5436 5437 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5438 { 5439 const struct pci_dev_acs_ops *p; 5440 int i, ret; 5441 5442 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5443 p = &pci_dev_acs_ops[i]; 5444 if ((p->vendor == dev->vendor || 5445 p->vendor == (u16)PCI_ANY_ID) && 5446 (p->device == dev->device || 5447 p->device == (u16)PCI_ANY_ID) && 5448 p->disable_acs_redir) { 5449 ret = p->disable_acs_redir(dev); 5450 if (ret >= 0) 5451 return ret; 5452 } 5453 } 5454 5455 return -ENOTTY; 5456 } 5457 5458 /* 5459 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5460 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5461 * Next Capability pointer in the MSI Capability Structure should point to 5462 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5463 * the list. 5464 */ 5465 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5466 { 5467 int pos, i = 0, ret; 5468 u8 next_cap; 5469 u16 reg16, *cap; 5470 struct pci_cap_saved_state *state; 5471 5472 /* Bail if the hardware bug is fixed */ 5473 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5474 return; 5475 5476 /* Bail if MSI Capability Structure is not found for some reason */ 5477 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5478 if (!pos) 5479 return; 5480 5481 /* 5482 * Bail if Next Capability pointer in the MSI Capability Structure 5483 * is not the expected incorrect 0x00. 5484 */ 5485 pci_read_config_byte(pdev, pos + 1, &next_cap); 5486 if (next_cap) 5487 return; 5488 5489 /* 5490 * PCIe Capability Structure is expected to be at 0x50 and should 5491 * terminate the list (Next Capability pointer is 0x00). Verify 5492 * Capability Id and Next Capability pointer is as expected. 5493 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5494 * to correctly set kernel data structures which have already been 5495 * set incorrectly due to the hardware bug. 5496 */ 5497 pos = 0x50; 5498 pci_read_config_word(pdev, pos, ®16); 5499 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5500 u32 status; 5501 #ifndef PCI_EXP_SAVE_REGS 5502 #define PCI_EXP_SAVE_REGS 7 5503 #endif 5504 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5505 5506 pdev->pcie_cap = pos; 5507 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5508 pdev->pcie_flags_reg = reg16; 5509 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5510 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5511 5512 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5513 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5514 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5515 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5516 5517 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5518 return; 5519 5520 /* Save PCIe cap */ 5521 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5522 if (!state) 5523 return; 5524 5525 state->cap.cap_nr = PCI_CAP_ID_EXP; 5526 state->cap.cap_extended = 0; 5527 state->cap.size = size; 5528 cap = (u16 *)&state->cap.data[0]; 5529 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5530 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5531 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5532 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5533 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5534 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5535 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5536 hlist_add_head(&state->next, &pdev->saved_cap_space); 5537 } 5538 } 5539 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5540 5541 /* 5542 * FLR may cause the following to devices to hang: 5543 * 5544 * AMD Starship/Matisse HD Audio Controller 0x1487 5545 * AMD Starship USB 3.0 Host Controller 0x148c 5546 * AMD Matisse USB 3.0 Host Controller 0x149c 5547 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5548 * Intel 82579V Gigabit Ethernet Controller 0x1503 5549 * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter 5550 */ 5551 static void quirk_no_flr(struct pci_dev *dev) 5552 { 5553 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5554 } 5555 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5556 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5557 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5558 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr); 5562 5563 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5564 static void quirk_no_flr_snet(struct pci_dev *dev) 5565 { 5566 if (dev->revision == 0x1) 5567 quirk_no_flr(dev); 5568 } 5569 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5570 5571 static void quirk_no_ext_tags(struct pci_dev *pdev) 5572 { 5573 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5574 5575 if (!bridge) 5576 return; 5577 5578 bridge->no_ext_tags = 1; 5579 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5580 5581 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5582 } 5583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); 5584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5585 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5586 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5587 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5588 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5589 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5590 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5591 5592 #ifdef CONFIG_PCI_ATS 5593 static void quirk_no_ats(struct pci_dev *pdev) 5594 { 5595 pci_info(pdev, "disabling ATS\n"); 5596 pdev->ats_cap = 0; 5597 } 5598 5599 /* 5600 * Some devices require additional driver setup to enable ATS. Don't use 5601 * ATS for those devices as ATS will be enabled before the driver has had a 5602 * chance to load and configure the device. 5603 */ 5604 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5605 { 5606 if (pdev->device == 0x15d8) { 5607 if (pdev->revision == 0xcf && 5608 pdev->subsystem_vendor == 0xea50 && 5609 (pdev->subsystem_device == 0xce19 || 5610 pdev->subsystem_device == 0xcc10 || 5611 pdev->subsystem_device == 0xcc08)) 5612 quirk_no_ats(pdev); 5613 } else { 5614 quirk_no_ats(pdev); 5615 } 5616 } 5617 5618 /* AMD Stoney platform GPU */ 5619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5620 /* AMD Iceland dGPU */ 5621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5622 /* AMD Navi10 dGPU */ 5623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5631 /* AMD Navi14 dGPU */ 5632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5636 /* AMD Raven platform iGPU */ 5637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5638 5639 /* 5640 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5641 * in ATS Invalidate Request message body. Disable ATS for those devices. 5642 */ 5643 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5644 { 5645 if (pdev->revision < 0x20) 5646 quirk_no_ats(pdev); 5647 } 5648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5657 #endif /* CONFIG_PCI_ATS */ 5658 5659 /* Freescale PCIe doesn't support MSI in RC mode */ 5660 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5661 { 5662 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5663 pdev->no_msi = 1; 5664 } 5665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5666 5667 /* 5668 * Although not allowed by the spec, some multi-function devices have 5669 * dependencies of one function (consumer) on another (supplier). For the 5670 * consumer to work in D0, the supplier must also be in D0. Create a 5671 * device link from the consumer to the supplier to enforce this 5672 * dependency. Runtime PM is allowed by default on the consumer to prevent 5673 * it from permanently keeping the supplier awake. 5674 */ 5675 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5676 unsigned int supplier, unsigned int class, 5677 unsigned int class_shift) 5678 { 5679 struct pci_dev *supplier_pdev; 5680 5681 if (PCI_FUNC(pdev->devfn) != consumer) 5682 return; 5683 5684 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5685 pdev->bus->number, 5686 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5687 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5688 pci_dev_put(supplier_pdev); 5689 return; 5690 } 5691 5692 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5693 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5694 pci_info(pdev, "D0 power state depends on %s\n", 5695 pci_name(supplier_pdev)); 5696 else 5697 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5698 pci_name(supplier_pdev)); 5699 5700 pm_runtime_allow(&pdev->dev); 5701 pci_dev_put(supplier_pdev); 5702 } 5703 5704 /* 5705 * Create device link for GPUs with integrated HDA controller for streaming 5706 * audio to attached displays. 5707 */ 5708 static void quirk_gpu_hda(struct pci_dev *hda) 5709 { 5710 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5711 } 5712 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5713 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5714 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5715 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5716 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5717 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5718 5719 /* 5720 * Create device link for GPUs with integrated USB xHCI Host 5721 * controller to VGA. 5722 */ 5723 static void quirk_gpu_usb(struct pci_dev *usb) 5724 { 5725 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5726 } 5727 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5728 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5729 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5730 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5731 5732 /* 5733 * Create device link for GPUs with integrated Type-C UCSI controller 5734 * to VGA. Currently there is no class code defined for UCSI device over PCI 5735 * so using UNKNOWN class for now and it will be updated when UCSI 5736 * over PCI gets a class code. 5737 */ 5738 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5739 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5740 { 5741 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5742 } 5743 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5744 PCI_CLASS_SERIAL_UNKNOWN, 8, 5745 quirk_gpu_usb_typec_ucsi); 5746 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5747 PCI_CLASS_SERIAL_UNKNOWN, 8, 5748 quirk_gpu_usb_typec_ucsi); 5749 5750 /* 5751 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5752 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5753 */ 5754 static void quirk_nvidia_hda(struct pci_dev *gpu) 5755 { 5756 u8 hdr_type; 5757 u32 val; 5758 5759 /* There was no integrated HDA controller before MCP89 */ 5760 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5761 return; 5762 5763 /* Bit 25 at offset 0x488 enables the HDA controller */ 5764 pci_read_config_dword(gpu, 0x488, &val); 5765 if (val & BIT(25)) 5766 return; 5767 5768 pci_info(gpu, "Enabling HDA controller\n"); 5769 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5770 5771 /* The GPU becomes a multi-function device when the HDA is enabled */ 5772 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5773 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 5774 } 5775 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5776 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5777 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5778 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5779 5780 /* 5781 * Some IDT switches incorrectly flag an ACS Source Validation error on 5782 * completions for config read requests even though PCIe r4.0, sec 5783 * 6.12.1.1, says that completions are never affected by ACS Source 5784 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5785 * 5786 * Item #36 - Downstream port applies ACS Source Validation to Completions 5787 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5788 * completions are never affected by ACS Source Validation. However, 5789 * completions received by a downstream port of the PCIe switch from a 5790 * device that has not yet captured a PCIe bus number are incorrectly 5791 * dropped by ACS Source Validation by the switch downstream port. 5792 * 5793 * The workaround suggested by IDT is to issue a config write to the 5794 * downstream device before issuing the first config read. This allows the 5795 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5796 * sec 2.2.9), thus avoiding the ACS error on the completion. 5797 * 5798 * However, we don't know when the device is ready to accept the config 5799 * write, so we do config reads until we receive a non-Config Request Retry 5800 * Status, then do the config write. 5801 * 5802 * To avoid hitting the erratum when doing the config reads, we disable ACS 5803 * SV around this process. 5804 */ 5805 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5806 { 5807 int pos; 5808 u16 ctrl = 0; 5809 bool found; 5810 struct pci_dev *bridge = bus->self; 5811 5812 pos = bridge->acs_cap; 5813 5814 /* Disable ACS SV before initial config reads */ 5815 if (pos) { 5816 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5817 if (ctrl & PCI_ACS_SV) 5818 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5819 ctrl & ~PCI_ACS_SV); 5820 } 5821 5822 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5823 5824 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5825 if (found) 5826 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5827 5828 /* Re-enable ACS_SV if it was previously enabled */ 5829 if (ctrl & PCI_ACS_SV) 5830 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5831 5832 return found; 5833 } 5834 5835 /* 5836 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5837 * NT endpoints via the internal switch fabric. These IDs replace the 5838 * originating Requester ID TLPs which access host memory on peer NTB 5839 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5840 * to permit access when the IOMMU is turned on. 5841 */ 5842 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5843 { 5844 void __iomem *mmio; 5845 struct ntb_info_regs __iomem *mmio_ntb; 5846 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5847 u64 partition_map; 5848 u8 partition; 5849 int pp; 5850 5851 if (pci_enable_device(pdev)) { 5852 pci_err(pdev, "Cannot enable Switchtec device\n"); 5853 return; 5854 } 5855 5856 mmio = pci_iomap(pdev, 0, 0); 5857 if (mmio == NULL) { 5858 pci_disable_device(pdev); 5859 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5860 return; 5861 } 5862 5863 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5864 5865 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5866 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5867 5868 partition = ioread8(&mmio_ntb->partition_id); 5869 5870 partition_map = ioread32(&mmio_ntb->ep_map); 5871 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5872 partition_map &= ~(1ULL << partition); 5873 5874 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5875 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5876 u32 table_sz = 0; 5877 int te; 5878 5879 if (!(partition_map & (1ULL << pp))) 5880 continue; 5881 5882 pci_dbg(pdev, "Processing partition %d\n", pp); 5883 5884 mmio_peer_ctrl = &mmio_ctrl[pp]; 5885 5886 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5887 if (!table_sz) { 5888 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5889 continue; 5890 } 5891 5892 if (table_sz > 512) { 5893 pci_warn(pdev, 5894 "Invalid Switchtec partition %d table_sz %d\n", 5895 pp, table_sz); 5896 continue; 5897 } 5898 5899 for (te = 0; te < table_sz; te++) { 5900 u32 rid_entry; 5901 u8 devfn; 5902 5903 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5904 devfn = (rid_entry >> 1) & 0xFF; 5905 pci_dbg(pdev, 5906 "Aliasing Partition %d Proxy ID %02x.%d\n", 5907 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5908 pci_add_dma_alias(pdev, devfn, 1); 5909 } 5910 } 5911 5912 pci_iounmap(pdev, mmio); 5913 pci_disable_device(pdev); 5914 } 5915 #define SWITCHTEC_QUIRK(vid) \ 5916 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5917 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5918 5919 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5920 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5921 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5922 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5923 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5924 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5925 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5926 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5927 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5928 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5929 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5930 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5931 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5932 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5933 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5934 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5935 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5936 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5937 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5938 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5939 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5940 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5941 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5942 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5943 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5944 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5945 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5946 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5947 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5948 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5949 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5950 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5951 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5952 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5953 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5954 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5955 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5956 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5957 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5958 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5959 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5960 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5961 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5962 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5963 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5964 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5965 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5966 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 5967 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 5968 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 5969 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 5970 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 5971 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 5972 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 5973 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 5974 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 5975 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 5976 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 5977 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 5978 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 5979 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 5980 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 5981 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 5982 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 5983 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 5984 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 5985 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 5986 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 5987 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 5988 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 5989 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 5990 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 5991 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 5992 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 5993 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 5994 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 5995 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 5996 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 5997 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 5998 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 5999 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 6000 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 6001 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 6002 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 6003 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 6004 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 6005 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 6006 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 6007 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 6008 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 6009 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 6010 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 6011 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 6012 6013 #define SWITCHTEC_PCI100X_QUIRK(vid) \ 6014 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_EFAR, vid, \ 6015 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 6016 SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */ 6017 SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */ 6018 SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */ 6019 SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */ 6020 SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */ 6021 SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */ 6022 6023 6024 /* 6025 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 6026 * These IDs are used to forward responses to the originator on the other 6027 * side of the NTB. Alias all possible IDs to the NTB to permit access when 6028 * the IOMMU is turned on. 6029 */ 6030 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 6031 { 6032 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 6033 /* PLX NTB may use all 256 devfns */ 6034 pci_add_dma_alias(pdev, 0, 256); 6035 } 6036 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 6037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 6038 6039 /* 6040 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 6041 * not always reset the secondary Nvidia GPU between reboots if the system 6042 * is configured to use Hybrid Graphics mode. This results in the GPU 6043 * being left in whatever state it was in during the *previous* boot, which 6044 * causes spurious interrupts from the GPU, which in turn causes us to 6045 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 6046 * this also completely breaks nouveau. 6047 * 6048 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 6049 * clean state and fixes all these issues. 6050 * 6051 * When the machine is configured in Dedicated display mode, the issue 6052 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 6053 * mode, so we can detect that and avoid resetting it. 6054 */ 6055 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 6056 { 6057 void __iomem *map; 6058 int ret; 6059 6060 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 6061 pdev->subsystem_device != 0x222e || 6062 !pci_reset_supported(pdev)) 6063 return; 6064 6065 if (pci_enable_device_mem(pdev)) 6066 return; 6067 6068 /* 6069 * Based on nvkm_device_ctor() in 6070 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 6071 */ 6072 map = pci_iomap(pdev, 0, 0x23000); 6073 if (!map) { 6074 pci_err(pdev, "Can't map MMIO space\n"); 6075 goto out_disable; 6076 } 6077 6078 /* 6079 * Make sure the GPU looks like it's been POSTed before resetting 6080 * it. 6081 */ 6082 if (ioread32(map + 0x2240c) & 0x2) { 6083 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 6084 ret = pci_reset_bus(pdev); 6085 if (ret < 0) 6086 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 6087 } 6088 6089 iounmap(map); 6090 out_disable: 6091 pci_disable_device(pdev); 6092 } 6093 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6094 PCI_CLASS_DISPLAY_VGA, 8, 6095 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6096 6097 /* 6098 * Device [1b21:2142] 6099 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6100 */ 6101 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6102 { 6103 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6104 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6105 } 6106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6107 6108 /* 6109 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6110 * 6111 * These devices advertise PME# support in all power states but don't 6112 * reliably assert it. 6113 * 6114 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6115 * says "The MSI Function is not implemented on this device" in chapters 6116 * 7.3.27, 7.3.29-7.3.31. 6117 */ 6118 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6119 { 6120 #ifdef CONFIG_PCI_MSI 6121 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6122 dev->no_msi = 1; 6123 #endif 6124 pci_info(dev, "PME# is unreliable, disabling it\n"); 6125 dev->pme_support = 0; 6126 } 6127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6129 6130 static void apex_pci_fixup_class(struct pci_dev *pdev) 6131 { 6132 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6133 } 6134 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6135 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6136 6137 /* 6138 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6139 * ACS P2P Request Redirect is not functional 6140 * 6141 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6142 * between upstream and downstream ports, packets are queued in an internal 6143 * buffer until CPLD packet. The workaround is to use the switch in store and 6144 * forward mode. 6145 */ 6146 #define PI7C9X2Gxxx_MODE_REG 0x74 6147 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6148 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6149 { 6150 struct pci_dev *upstream; 6151 u16 val; 6152 6153 /* Downstream ports only */ 6154 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6155 return; 6156 6157 /* Check for ACS P2P Request Redirect use */ 6158 if (!pdev->acs_cap) 6159 return; 6160 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6161 if (!(val & PCI_ACS_RR)) 6162 return; 6163 6164 upstream = pci_upstream_bridge(pdev); 6165 if (!upstream) 6166 return; 6167 6168 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6169 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6170 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6171 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6172 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6173 } 6174 } 6175 /* 6176 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6177 * ACS configuration changes or switch mode is reset 6178 */ 6179 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6180 pci_fixup_pericom_acs_store_forward); 6181 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6182 pci_fixup_pericom_acs_store_forward); 6183 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6184 pci_fixup_pericom_acs_store_forward); 6185 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6186 pci_fixup_pericom_acs_store_forward); 6187 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6188 pci_fixup_pericom_acs_store_forward); 6189 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6190 pci_fixup_pericom_acs_store_forward); 6191 6192 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6193 { 6194 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6195 } 6196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6197 6198 static void rom_bar_overlap_defect(struct pci_dev *dev) 6199 { 6200 pci_info(dev, "working around ROM BAR overlap defect\n"); 6201 dev->rom_bar_overlap = 1; 6202 } 6203 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6204 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6205 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6206 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6207 6208 #ifdef CONFIG_PCIEASPM 6209 /* 6210 * Several Intel DG2 graphics devices advertise that they can only tolerate 6211 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6212 * from being enabled. But in fact these devices can tolerate unlimited 6213 * latency. Override their Device Capabilities value to allow ASPM L1 to 6214 * be enabled. 6215 */ 6216 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6217 { 6218 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6219 6220 if (l1_lat < 7) { 6221 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6222 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6223 l1_lat); 6224 } 6225 } 6226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6249 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6251 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6252 #endif 6253 6254 #ifdef CONFIG_PCIE_DPC 6255 /* 6256 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6257 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6258 * Ports. 6259 */ 6260 static void dpc_log_size(struct pci_dev *dev) 6261 { 6262 u16 dpc, val; 6263 6264 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6265 if (!dpc) 6266 return; 6267 6268 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6269 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6270 return; 6271 6272 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6273 pci_info(dev, "Overriding RP PIO Log Size to %d\n", 6274 PCIE_STD_NUM_TLP_HEADERLOG); 6275 dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG; 6276 } 6277 } 6278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size); 6295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); 6296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); 6297 #endif 6298 6299 /* 6300 * For a PCI device with multiple downstream devices, its driver may use 6301 * a flattened device tree to describe the downstream devices. 6302 * To overlay the flattened device tree, the PCI device and all its ancestor 6303 * devices need to have device tree nodes on system base device tree. Thus, 6304 * before driver probing, it might need to add a device tree node as the final 6305 * fixup. 6306 */ 6307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); 6311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RPI_RP1_C0, of_pci_make_dev_node); 6312 6313 /* 6314 * Devices known to require a longer delay before first config space access 6315 * after reset recovery or resume from D3cold: 6316 * 6317 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6318 */ 6319 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6320 { 6321 pdev->d3cold_delay = 1000; 6322 } 6323 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6324 6325 #ifdef CONFIG_PCIEAER 6326 static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) 6327 { 6328 struct pci_dev *parent = pci_upstream_bridge(pdev); 6329 u32 val; 6330 6331 if (!parent || !parent->aer_cap) 6332 return; 6333 6334 pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", 6335 pci_name(pdev)); 6336 6337 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); 6338 val |= PCI_ERR_COR_REP_TIMER; 6339 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); 6340 } 6341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); 6342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); 6343 #endif 6344