1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/align.h> 16 #include <linux/bitfield.h> 17 #include <linux/types.h> 18 #include <linux/kernel.h> 19 #include <linux/export.h> 20 #include <linux/pci.h> 21 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/acpi.h> 25 #include <linux/dmi.h> 26 #include <linux/ioport.h> 27 #include <linux/sched.h> 28 #include <linux/ktime.h> 29 #include <linux/mm.h> 30 #include <linux/nvme.h> 31 #include <linux/platform_data/x86/apple.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/sizes.h> 34 #include <linux/suspend.h> 35 #include <linux/switchtec.h> 36 #include "pci.h" 37 38 static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta) 39 { 40 unsigned long count; 41 int ret; 42 43 ret = pcie_lbms_count(dev, &count); 44 if (ret < 0) 45 return lnksta & PCI_EXP_LNKSTA_LBMS; 46 47 return count > 0; 48 } 49 50 /* 51 * Retrain the link of a downstream PCIe port by hand if necessary. 52 * 53 * This is needed at least where a downstream port of the ASMedia ASM2824 54 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 55 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 56 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 57 * board. 58 * 59 * In such a configuration the switches are supposed to negotiate the link 60 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 61 * continues switching between the two speeds indefinitely and the data 62 * link layer never reaches the active state, with link training reported 63 * repeatedly active ~84% of the time. Forcing the target link speed to 64 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 65 * each other correctly however. And more interestingly retraining with a 66 * higher target link speed afterwards lets the two successfully negotiate 67 * 5.0GT/s. 68 * 69 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 70 * Link Active status bit and in the failed link training scenario it will 71 * be off along with the Link Bandwidth Management Status indicating that 72 * hardware has changed the link speed or width in an attempt to correct 73 * unreliable link operation. For a port that has been left unconnected 74 * both bits will be clear. So use this information to detect the problem 75 * rather than polling the Link Training bit and watching out for flips or 76 * at least the active status. 77 * 78 * Since the exact nature of the problem isn't known and in principle this 79 * could trigger where an ASM2824 device is downstream rather upstream, 80 * apply this erratum workaround to any downstream ports as long as they 81 * support Link Active reporting and have the Link Control 2 register. 82 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 83 * request a retrain and check the result. 84 * 85 * If this turns out successful and we know by the Vendor:Device ID it is 86 * safe to do so, then lift the restriction, letting the devices negotiate 87 * a higher speed. Also check for a similar 2.5GT/s speed restriction the 88 * firmware may have already arranged and lift it with ports that already 89 * report their data link being up. 90 * 91 * Otherwise revert the speed to the original setting and request a retrain 92 * again to remove any residual state, ignoring the result as it's supposed 93 * to fail anyway. 94 * 95 * Return 0 if the link has been successfully retrained. Return an error 96 * if retraining was not needed or we attempted a retrain and it failed. 97 */ 98 int pcie_failed_link_retrain(struct pci_dev *dev) 99 { 100 static const struct pci_device_id ids[] = { 101 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 102 {} 103 }; 104 u16 lnksta, lnkctl2; 105 int ret = -ENOTTY; 106 107 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 108 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 109 return ret; 110 111 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 112 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 113 if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) { 114 u16 oldlnkctl2 = lnkctl2; 115 116 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 117 118 ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false); 119 if (ret) { 120 pci_info(dev, "retraining failed\n"); 121 pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), 122 true); 123 return ret; 124 } 125 126 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 127 } 128 129 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && 130 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && 131 pci_match_id(ids, dev)) { 132 u32 lnkcap; 133 134 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 135 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 136 ret = pcie_set_target_speed(dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), false); 137 if (ret) { 138 pci_info(dev, "retraining failed\n"); 139 return ret; 140 } 141 } 142 143 return ret; 144 } 145 146 static ktime_t fixup_debug_start(struct pci_dev *dev, 147 void (*fn)(struct pci_dev *dev)) 148 { 149 if (initcall_debug) 150 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 151 152 return ktime_get(); 153 } 154 155 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 156 void (*fn)(struct pci_dev *dev)) 157 { 158 ktime_t delta, rettime; 159 unsigned long long duration; 160 161 rettime = ktime_get(); 162 delta = ktime_sub(rettime, calltime); 163 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 164 if (initcall_debug || duration > 10000) 165 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 166 } 167 168 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 169 struct pci_fixup *end) 170 { 171 ktime_t calltime; 172 173 for (; f < end; f++) 174 if ((f->class == (u32) (dev->class >> f->class_shift) || 175 f->class == (u32) PCI_ANY_ID) && 176 (f->vendor == dev->vendor || 177 f->vendor == (u16) PCI_ANY_ID) && 178 (f->device == dev->device || 179 f->device == (u16) PCI_ANY_ID)) { 180 void (*hook)(struct pci_dev *dev); 181 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 182 hook = offset_to_ptr(&f->hook_offset); 183 #else 184 hook = f->hook; 185 #endif 186 calltime = fixup_debug_start(dev, hook); 187 hook(dev); 188 fixup_debug_report(dev, calltime, hook); 189 } 190 } 191 192 extern struct pci_fixup __start_pci_fixups_early[]; 193 extern struct pci_fixup __end_pci_fixups_early[]; 194 extern struct pci_fixup __start_pci_fixups_header[]; 195 extern struct pci_fixup __end_pci_fixups_header[]; 196 extern struct pci_fixup __start_pci_fixups_final[]; 197 extern struct pci_fixup __end_pci_fixups_final[]; 198 extern struct pci_fixup __start_pci_fixups_enable[]; 199 extern struct pci_fixup __end_pci_fixups_enable[]; 200 extern struct pci_fixup __start_pci_fixups_resume[]; 201 extern struct pci_fixup __end_pci_fixups_resume[]; 202 extern struct pci_fixup __start_pci_fixups_resume_early[]; 203 extern struct pci_fixup __end_pci_fixups_resume_early[]; 204 extern struct pci_fixup __start_pci_fixups_suspend[]; 205 extern struct pci_fixup __end_pci_fixups_suspend[]; 206 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 207 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 208 209 static bool pci_apply_fixup_final_quirks; 210 211 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 212 { 213 struct pci_fixup *start, *end; 214 215 switch (pass) { 216 case pci_fixup_early: 217 start = __start_pci_fixups_early; 218 end = __end_pci_fixups_early; 219 break; 220 221 case pci_fixup_header: 222 start = __start_pci_fixups_header; 223 end = __end_pci_fixups_header; 224 break; 225 226 case pci_fixup_final: 227 if (!pci_apply_fixup_final_quirks) 228 return; 229 start = __start_pci_fixups_final; 230 end = __end_pci_fixups_final; 231 break; 232 233 case pci_fixup_enable: 234 start = __start_pci_fixups_enable; 235 end = __end_pci_fixups_enable; 236 break; 237 238 case pci_fixup_resume: 239 start = __start_pci_fixups_resume; 240 end = __end_pci_fixups_resume; 241 break; 242 243 case pci_fixup_resume_early: 244 start = __start_pci_fixups_resume_early; 245 end = __end_pci_fixups_resume_early; 246 break; 247 248 case pci_fixup_suspend: 249 start = __start_pci_fixups_suspend; 250 end = __end_pci_fixups_suspend; 251 break; 252 253 case pci_fixup_suspend_late: 254 start = __start_pci_fixups_suspend_late; 255 end = __end_pci_fixups_suspend_late; 256 break; 257 258 default: 259 /* stupid compiler warning, you would think with an enum... */ 260 return; 261 } 262 pci_do_fixups(dev, start, end); 263 } 264 EXPORT_SYMBOL(pci_fixup_device); 265 266 static int __init pci_apply_final_quirks(void) 267 { 268 struct pci_dev *dev = NULL; 269 u8 cls = 0; 270 u8 tmp; 271 272 if (pci_cache_line_size) 273 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 274 275 pci_apply_fixup_final_quirks = true; 276 for_each_pci_dev(dev) { 277 pci_fixup_device(pci_fixup_final, dev); 278 /* 279 * If arch hasn't set it explicitly yet, use the CLS 280 * value shared by all PCI devices. If there's a 281 * mismatch, fall back to the default value. 282 */ 283 if (!pci_cache_line_size) { 284 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 285 if (!cls) 286 cls = tmp; 287 if (!tmp || cls == tmp) 288 continue; 289 290 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 291 cls << 2, tmp << 2, 292 pci_dfl_cache_line_size << 2); 293 pci_cache_line_size = pci_dfl_cache_line_size; 294 } 295 } 296 297 if (!pci_cache_line_size) { 298 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 299 pci_dfl_cache_line_size << 2); 300 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 301 } 302 303 return 0; 304 } 305 fs_initcall_sync(pci_apply_final_quirks); 306 307 /* 308 * Decoding should be disabled for a PCI device during BAR sizing to avoid 309 * conflict. But doing so may cause problems on host bridge and perhaps other 310 * key system devices. For devices that need to have mmio decoding always-on, 311 * we need to set the dev->mmio_always_on bit. 312 */ 313 static void quirk_mmio_always_on(struct pci_dev *dev) 314 { 315 dev->mmio_always_on = 1; 316 } 317 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 318 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 319 320 /* 321 * The Mellanox Tavor device gives false positive parity errors. Disable 322 * parity error reporting. 323 */ 324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 326 327 /* 328 * Deal with broken BIOSes that neglect to enable passive release, 329 * which can cause problems in combination with the 82441FX/PPro MTRRs 330 */ 331 static void quirk_passive_release(struct pci_dev *dev) 332 { 333 struct pci_dev *d = NULL; 334 unsigned char dlc; 335 336 /* 337 * We have to make sure a particular bit is set in the PIIX3 338 * ISA bridge, so we have to go out and find it. 339 */ 340 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 341 pci_read_config_byte(d, 0x82, &dlc); 342 if (!(dlc & 1<<1)) { 343 pci_info(d, "PIIX3: Enabling Passive Release\n"); 344 dlc |= 1<<1; 345 pci_write_config_byte(d, 0x82, dlc); 346 } 347 } 348 } 349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 350 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 351 352 #ifdef CONFIG_X86_32 353 /* 354 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 355 * workaround but VIA don't answer queries. If you happen to have good 356 * contacts at VIA ask them for me please -- Alan 357 * 358 * This appears to be BIOS not version dependent. So presumably there is a 359 * chipset level fix. 360 */ 361 static void quirk_isa_dma_hangs(struct pci_dev *dev) 362 { 363 if (!isa_dma_bridge_buggy) { 364 isa_dma_bridge_buggy = 1; 365 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 366 } 367 } 368 /* 369 * It's not totally clear which chipsets are the problematic ones. We know 370 * 82C586 and 82C596 variants are affected. 371 */ 372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 379 #endif 380 381 #ifdef CONFIG_HAS_IOPORT 382 /* 383 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 384 * for some HT machines to use C4 w/o hanging. 385 */ 386 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 387 { 388 u32 pmbase; 389 u16 pm1a; 390 391 pci_read_config_dword(dev, 0x40, &pmbase); 392 pmbase = pmbase & 0xff80; 393 pm1a = inw(pmbase); 394 395 if (pm1a & 0x10) { 396 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 397 outw(0x10, pmbase); 398 } 399 } 400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 401 #endif 402 403 /* Chipsets where PCI->PCI transfers vanish or hang */ 404 static void quirk_nopcipci(struct pci_dev *dev) 405 { 406 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 407 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 408 pci_pci_problems |= PCIPCI_FAIL; 409 } 410 } 411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 413 414 static void quirk_nopciamd(struct pci_dev *dev) 415 { 416 u8 rev; 417 pci_read_config_byte(dev, 0x08, &rev); 418 if (rev == 0x13) { 419 /* Erratum 24 */ 420 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 421 pci_pci_problems |= PCIAGP_FAIL; 422 } 423 } 424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 425 426 /* Triton requires workarounds to be used by the drivers */ 427 static void quirk_triton(struct pci_dev *dev) 428 { 429 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 430 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 431 pci_pci_problems |= PCIPCI_TRITON; 432 } 433 } 434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 438 439 /* 440 * VIA Apollo KT133 needs PCI latency patch 441 * Made according to a Windows driver-based patch by George E. Breese; 442 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 443 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 444 * which Mr Breese based his work. 445 * 446 * Updated based on further information from the site and also on 447 * information provided by VIA 448 */ 449 static void quirk_vialatency(struct pci_dev *dev) 450 { 451 struct pci_dev *p; 452 u8 busarb; 453 454 /* 455 * Ok, we have a potential problem chipset here. Now see if we have 456 * a buggy southbridge. 457 */ 458 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 459 if (p != NULL) { 460 461 /* 462 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 463 * thanks Dan Hollis. 464 * Check for buggy part revisions 465 */ 466 if (p->revision < 0x40 || p->revision > 0x42) 467 goto exit; 468 } else { 469 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 470 if (p == NULL) /* No problem parts */ 471 goto exit; 472 473 /* Check for buggy part revisions */ 474 if (p->revision < 0x10 || p->revision > 0x12) 475 goto exit; 476 } 477 478 /* 479 * Ok we have the problem. Now set the PCI master grant to occur 480 * every master grant. The apparent bug is that under high PCI load 481 * (quite common in Linux of course) you can get data loss when the 482 * CPU is held off the bus for 3 bus master requests. This happens 483 * to include the IDE controllers.... 484 * 485 * VIA only apply this fix when an SB Live! is present but under 486 * both Linux and Windows this isn't enough, and we have seen 487 * corruption without SB Live! but with things like 3 UDMA IDE 488 * controllers. So we ignore that bit of the VIA recommendation.. 489 */ 490 pci_read_config_byte(dev, 0x76, &busarb); 491 492 /* 493 * Set bit 4 and bit 5 of byte 76 to 0x01 494 * "Master priority rotation on every PCI master grant" 495 */ 496 busarb &= ~(1<<5); 497 busarb |= (1<<4); 498 pci_write_config_byte(dev, 0x76, busarb); 499 pci_info(dev, "Applying VIA southbridge workaround\n"); 500 exit: 501 pci_dev_put(p); 502 } 503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 506 /* Must restore this on a resume from RAM */ 507 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 508 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 509 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 510 511 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 512 static void quirk_viaetbf(struct pci_dev *dev) 513 { 514 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 515 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 516 pci_pci_problems |= PCIPCI_VIAETBF; 517 } 518 } 519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 520 521 static void quirk_vsfx(struct pci_dev *dev) 522 { 523 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 524 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 525 pci_pci_problems |= PCIPCI_VSFX; 526 } 527 } 528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 529 530 /* 531 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 532 * space. Latency must be set to 0xA and Triton workaround applied too. 533 * [Info kindly provided by ALi] 534 */ 535 static void quirk_alimagik(struct pci_dev *dev) 536 { 537 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 538 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 539 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 540 } 541 } 542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 544 545 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 546 static void quirk_natoma(struct pci_dev *dev) 547 { 548 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 549 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 550 pci_pci_problems |= PCIPCI_NATOMA; 551 } 552 } 553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 559 560 /* 561 * This chip can cause PCI parity errors if config register 0xA0 is read 562 * while DMAs are occurring. 563 */ 564 static void quirk_citrine(struct pci_dev *dev) 565 { 566 dev->cfg_size = 0xA0; 567 } 568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 569 570 /* 571 * This chip can cause bus lockups if config addresses above 0x600 572 * are read or written. 573 */ 574 static void quirk_nfp6000(struct pci_dev *dev) 575 { 576 dev->cfg_size = 0x600; 577 } 578 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 582 583 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 584 static void quirk_extend_bar_to_page(struct pci_dev *dev) 585 { 586 int i; 587 588 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 589 struct resource *r = &dev->resource[i]; 590 const char *r_name = pci_resource_name(dev, i); 591 592 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 593 resource_set_range(r, 0, PAGE_SIZE); 594 r->flags |= IORESOURCE_UNSET; 595 pci_info(dev, "%s %pR: expanded to page size\n", 596 r_name, r); 597 } 598 } 599 } 600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 601 602 /* 603 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 604 * If it's needed, re-allocate the region. 605 */ 606 static void quirk_s3_64M(struct pci_dev *dev) 607 { 608 struct resource *r = &dev->resource[0]; 609 610 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) { 611 r->flags |= IORESOURCE_UNSET; 612 resource_set_range(r, 0, SZ_64M); 613 } 614 } 615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 617 618 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 619 const char *name) 620 { 621 u32 region; 622 struct pci_bus_region bus_region; 623 struct resource *res = dev->resource + pos; 624 const char *res_name = pci_resource_name(dev, pos); 625 626 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 627 628 if (!region) 629 return; 630 631 res->name = pci_name(dev); 632 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 633 res->flags |= 634 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 635 region &= ~(size - 1); 636 637 /* Convert from PCI bus to resource space */ 638 bus_region.start = region; 639 bus_region.end = region + size - 1; 640 pcibios_bus_to_resource(dev->bus, res, &bus_region); 641 642 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name); 643 } 644 645 /* 646 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 647 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 648 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 649 * (which conflicts w/ BAR1's memory range). 650 * 651 * CS553x's ISA PCI BARs may also be read-only (ref: 652 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 653 */ 654 static void quirk_cs5536_vsa(struct pci_dev *dev) 655 { 656 static char *name = "CS5536 ISA bridge"; 657 658 if (pci_resource_len(dev, 0) != 8) { 659 quirk_io(dev, 0, 8, name); /* SMB */ 660 quirk_io(dev, 1, 256, name); /* GPIO */ 661 quirk_io(dev, 2, 64, name); /* MFGPT */ 662 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 663 name); 664 } 665 } 666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 667 668 static void quirk_io_region(struct pci_dev *dev, int port, 669 unsigned int size, int nr, const char *name) 670 { 671 u16 region; 672 struct pci_bus_region bus_region; 673 struct resource *res = dev->resource + nr; 674 675 pci_read_config_word(dev, port, ®ion); 676 region &= ~(size - 1); 677 678 if (!region) 679 return; 680 681 res->name = pci_name(dev); 682 res->flags = IORESOURCE_IO; 683 684 /* Convert from PCI bus to resource space */ 685 bus_region.start = region; 686 bus_region.end = region + size - 1; 687 pcibios_bus_to_resource(dev->bus, res, &bus_region); 688 689 /* 690 * "res" is typically a bridge window resource that's not being 691 * used for a bridge window, so it's just a place to stash this 692 * non-standard resource. Printing "nr" or pci_resource_name() of 693 * it doesn't really make sense. 694 */ 695 if (!pci_claim_resource(dev, nr)) 696 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 697 } 698 699 /* 700 * ATI Northbridge setups MCE the processor if you even read somewhere 701 * between 0x3b0->0x3bb or read 0x3d3 702 */ 703 static void quirk_ati_exploding_mce(struct pci_dev *dev) 704 { 705 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 706 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 707 request_region(0x3b0, 0x0C, "RadeonIGP"); 708 request_region(0x3d3, 0x01, "RadeonIGP"); 709 } 710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 711 712 /* 713 * In the AMD NL platform, this device ([1022:7912]) has a class code of 714 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 715 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 716 * 717 * But the dwc3 driver is a more specific driver for this device, and we'd 718 * prefer to use it instead of xhci. To prevent xhci from claiming the 719 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 720 * defines as "USB device (not host controller)". The dwc3 driver can then 721 * claim it based on its Vendor and Device ID. 722 */ 723 static void quirk_amd_dwc_class(struct pci_dev *pdev) 724 { 725 u32 class = pdev->class; 726 727 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 728 /* Use "USB Device (not host controller)" class */ 729 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 730 pci_info(pdev, 731 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 732 class, pdev->class); 733 } 734 } 735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 736 quirk_amd_dwc_class); 737 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 738 quirk_amd_dwc_class); 739 740 /* 741 * Synopsys USB 3.x host HAPS platform has a class code of 742 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 743 * devices should use dwc3-haps driver. Change these devices' class code to 744 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 745 * them. 746 */ 747 static void quirk_synopsys_haps(struct pci_dev *pdev) 748 { 749 u32 class = pdev->class; 750 751 switch (pdev->device) { 752 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 753 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 754 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 755 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 756 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 757 class, pdev->class); 758 break; 759 } 760 } 761 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 762 PCI_CLASS_SERIAL_USB_XHCI, 0, 763 quirk_synopsys_haps); 764 765 /* 766 * Let's make the southbridge information explicit instead of having to 767 * worry about people probing the ACPI areas, for example.. (Yes, it 768 * happens, and if you read the wrong ACPI register it will put the machine 769 * to sleep with no way of waking it up again. Bummer). 770 * 771 * ALI M7101: Two IO regions pointed to by words at 772 * 0xE0 (64 bytes of ACPI registers) 773 * 0xE2 (32 bytes of SMB registers) 774 */ 775 static void quirk_ali7101_acpi(struct pci_dev *dev) 776 { 777 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 778 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 779 } 780 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 781 782 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 783 { 784 u32 devres; 785 u32 mask, size, base; 786 787 pci_read_config_dword(dev, port, &devres); 788 if ((devres & enable) != enable) 789 return; 790 mask = (devres >> 16) & 15; 791 base = devres & 0xffff; 792 size = 16; 793 for (;;) { 794 unsigned int bit = size >> 1; 795 if ((bit & mask) == bit) 796 break; 797 size = bit; 798 } 799 /* 800 * For now we only print it out. Eventually we'll want to 801 * reserve it (at least if it's in the 0x1000+ range), but 802 * let's get enough confirmation reports first. 803 */ 804 base &= -size; 805 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 806 } 807 808 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 809 { 810 u32 devres; 811 u32 mask, size, base; 812 813 pci_read_config_dword(dev, port, &devres); 814 if ((devres & enable) != enable) 815 return; 816 base = devres & 0xffff0000; 817 mask = (devres & 0x3f) << 16; 818 size = 128 << 16; 819 for (;;) { 820 unsigned int bit = size >> 1; 821 if ((bit & mask) == bit) 822 break; 823 size = bit; 824 } 825 826 /* 827 * For now we only print it out. Eventually we'll want to 828 * reserve it, but let's get enough confirmation reports first. 829 */ 830 base &= -size; 831 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 832 } 833 834 /* 835 * PIIX4 ACPI: Two IO regions pointed to by longwords at 836 * 0x40 (64 bytes of ACPI registers) 837 * 0x90 (16 bytes of SMB registers) 838 * and a few strange programmable PIIX4 device resources. 839 */ 840 static void quirk_piix4_acpi(struct pci_dev *dev) 841 { 842 u32 res_a; 843 844 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 845 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 846 847 /* Device resource A has enables for some of the other ones */ 848 pci_read_config_dword(dev, 0x5c, &res_a); 849 850 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 851 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 852 853 /* Device resource D is just bitfields for static resources */ 854 855 /* Device 12 enabled? */ 856 if (res_a & (1 << 29)) { 857 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 858 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 859 } 860 /* Device 13 enabled? */ 861 if (res_a & (1 << 30)) { 862 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 863 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 864 } 865 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 866 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 867 } 868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 870 871 #define ICH_PMBASE 0x40 872 #define ICH_ACPI_CNTL 0x44 873 #define ICH4_ACPI_EN 0x10 874 #define ICH6_ACPI_EN 0x80 875 #define ICH4_GPIOBASE 0x58 876 #define ICH4_GPIO_CNTL 0x5c 877 #define ICH4_GPIO_EN 0x10 878 #define ICH6_GPIOBASE 0x48 879 #define ICH6_GPIO_CNTL 0x4c 880 #define ICH6_GPIO_EN 0x10 881 882 /* 883 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 884 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 885 * 0x58 (64 bytes of GPIO I/O space) 886 */ 887 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 888 { 889 u8 enable; 890 891 /* 892 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 893 * with low legacy (and fixed) ports. We don't know the decoding 894 * priority and can't tell whether the legacy device or the one created 895 * here is really at that address. This happens on boards with broken 896 * BIOSes. 897 */ 898 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 899 if (enable & ICH4_ACPI_EN) 900 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 901 "ICH4 ACPI/GPIO/TCO"); 902 903 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 904 if (enable & ICH4_GPIO_EN) 905 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 906 "ICH4 GPIO"); 907 } 908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 918 919 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 920 { 921 u8 enable; 922 923 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 924 if (enable & ICH6_ACPI_EN) 925 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 926 "ICH6 ACPI/GPIO/TCO"); 927 928 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 929 if (enable & ICH6_GPIO_EN) 930 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 931 "ICH6 GPIO"); 932 } 933 934 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 935 const char *name, int dynsize) 936 { 937 u32 val; 938 u32 size, base; 939 940 pci_read_config_dword(dev, reg, &val); 941 942 /* Enabled? */ 943 if (!(val & 1)) 944 return; 945 base = val & 0xfffc; 946 if (dynsize) { 947 /* 948 * This is not correct. It is 16, 32 or 64 bytes depending on 949 * register D31:F0:ADh bits 5:4. 950 * 951 * But this gets us at least _part_ of it. 952 */ 953 size = 16; 954 } else { 955 size = 128; 956 } 957 base &= ~(size-1); 958 959 /* 960 * Just print it out for now. We should reserve it after more 961 * debugging. 962 */ 963 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 964 } 965 966 static void quirk_ich6_lpc(struct pci_dev *dev) 967 { 968 /* Shared ACPI/GPIO decode with all ICH6+ */ 969 ich6_lpc_acpi_gpio(dev); 970 971 /* ICH6-specific generic IO decode */ 972 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 973 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 974 } 975 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 977 978 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 979 const char *name) 980 { 981 u32 val; 982 u32 mask, base; 983 984 pci_read_config_dword(dev, reg, &val); 985 986 /* Enabled? */ 987 if (!(val & 1)) 988 return; 989 990 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 991 base = val & 0xfffc; 992 mask = (val >> 16) & 0xfc; 993 mask |= 3; 994 995 /* 996 * Just print it out for now. We should reserve it after more 997 * debugging. 998 */ 999 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 1000 } 1001 1002 /* ICH7-10 has the same common LPC generic IO decode registers */ 1003 static void quirk_ich7_lpc(struct pci_dev *dev) 1004 { 1005 /* We share the common ACPI/GPIO decode with ICH6 */ 1006 ich6_lpc_acpi_gpio(dev); 1007 1008 /* And have 4 ICH7+ generic decodes */ 1009 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 1010 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 1011 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 1012 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 1013 } 1014 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 1015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 1016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 1017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 1018 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 1019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 1020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 1021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 1022 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 1023 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 1024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1027 1028 /* 1029 * VIA ACPI: One IO region pointed to by longword at 1030 * 0x48 or 0x20 (256 bytes of ACPI registers) 1031 */ 1032 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1033 { 1034 if (dev->revision & 0x10) 1035 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1036 "vt82c586 ACPI"); 1037 } 1038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1039 1040 /* 1041 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1042 * 0x48 (256 bytes of ACPI registers) 1043 * 0x70 (128 bytes of hardware monitoring register) 1044 * 0x90 (16 bytes of SMB registers) 1045 */ 1046 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1047 { 1048 quirk_vt82c586_acpi(dev); 1049 1050 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1051 "vt82c686 HW-mon"); 1052 1053 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1054 } 1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1056 1057 /* 1058 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1059 * 0x88 (128 bytes of power management registers) 1060 * 0xd0 (16 bytes of SMB registers) 1061 */ 1062 static void quirk_vt8235_acpi(struct pci_dev *dev) 1063 { 1064 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1065 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1066 } 1067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1068 1069 /* 1070 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1071 * back-to-back: Disable fast back-to-back on the secondary bus segment 1072 */ 1073 static void quirk_xio2000a(struct pci_dev *dev) 1074 { 1075 struct pci_dev *pdev; 1076 u16 command; 1077 1078 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1079 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1080 pci_read_config_word(pdev, PCI_COMMAND, &command); 1081 if (command & PCI_COMMAND_FAST_BACK) 1082 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1083 } 1084 } 1085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1086 quirk_xio2000a); 1087 1088 #ifdef CONFIG_X86_IO_APIC 1089 1090 #include <asm/io_apic.h> 1091 1092 /* 1093 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1094 * devices to the external APIC. 1095 * 1096 * TODO: When we have device-specific interrupt routers, this code will go 1097 * away from quirks. 1098 */ 1099 static void quirk_via_ioapic(struct pci_dev *dev) 1100 { 1101 u8 tmp; 1102 1103 if (nr_ioapics < 1) 1104 tmp = 0; /* nothing routed to external APIC */ 1105 else 1106 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1107 1108 pci_info(dev, "%s VIA external APIC routing\n", 1109 tmp ? "Enabling" : "Disabling"); 1110 1111 /* Offset 0x58: External APIC IRQ output control */ 1112 pci_write_config_byte(dev, 0x58, tmp); 1113 } 1114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1115 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1116 1117 /* 1118 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1119 * This leads to doubled level interrupt rates. 1120 * Set this bit to get rid of cycle wastage. 1121 * Otherwise uncritical. 1122 */ 1123 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1124 { 1125 u8 misc_control2; 1126 #define BYPASS_APIC_DEASSERT 8 1127 1128 pci_read_config_byte(dev, 0x5B, &misc_control2); 1129 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1130 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1131 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1132 } 1133 } 1134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1135 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1136 1137 /* 1138 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1139 * We check all revs >= B0 (yet not in the pre production!) as the bug 1140 * is currently marked NoFix 1141 * 1142 * We have multiple reports of hangs with this chipset that went away with 1143 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1144 * of course. However the advice is demonstrably good even if so. 1145 */ 1146 static void quirk_amd_ioapic(struct pci_dev *dev) 1147 { 1148 if (dev->revision >= 0x02) { 1149 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1150 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1151 } 1152 } 1153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1154 #endif /* CONFIG_X86_IO_APIC */ 1155 1156 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1157 1158 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1159 { 1160 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1161 if (dev->subsystem_device == 0xa118) 1162 dev->sriov->link = dev->devfn; 1163 } 1164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1165 #endif 1166 1167 /* 1168 * Some settings of MMRBC can lead to data corruption so block changes. 1169 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1170 */ 1171 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1172 { 1173 if (dev->subordinate && dev->revision <= 0x12) { 1174 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1175 dev->revision); 1176 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1177 } 1178 } 1179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1180 1181 /* 1182 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1183 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1184 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1185 * of the ACPI SCI interrupt is only done for convenience. 1186 * -jgarzik 1187 */ 1188 static void quirk_via_acpi(struct pci_dev *d) 1189 { 1190 u8 irq; 1191 1192 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1193 pci_read_config_byte(d, 0x42, &irq); 1194 irq &= 0xf; 1195 if (irq && (irq != 2)) 1196 d->irq = irq; 1197 } 1198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1200 1201 /* VIA bridges which have VLink */ 1202 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1203 1204 static void quirk_via_bridge(struct pci_dev *dev) 1205 { 1206 /* See what bridge we have and find the device ranges */ 1207 switch (dev->device) { 1208 case PCI_DEVICE_ID_VIA_82C686: 1209 /* 1210 * The VT82C686 is special; it attaches to PCI and can have 1211 * any device number. All its subdevices are functions of 1212 * that single device. 1213 */ 1214 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1215 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1216 break; 1217 case PCI_DEVICE_ID_VIA_8237: 1218 case PCI_DEVICE_ID_VIA_8237A: 1219 via_vlink_dev_lo = 15; 1220 break; 1221 case PCI_DEVICE_ID_VIA_8235: 1222 via_vlink_dev_lo = 16; 1223 break; 1224 case PCI_DEVICE_ID_VIA_8231: 1225 case PCI_DEVICE_ID_VIA_8233_0: 1226 case PCI_DEVICE_ID_VIA_8233A: 1227 case PCI_DEVICE_ID_VIA_8233C_0: 1228 via_vlink_dev_lo = 17; 1229 break; 1230 } 1231 } 1232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1240 1241 /* 1242 * quirk_via_vlink - VIA VLink IRQ number update 1243 * @dev: PCI device 1244 * 1245 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1246 * the IRQ line register which usually is not relevant for PCI cards, is 1247 * actually written so that interrupts get sent to the right place. 1248 * 1249 * We only do this on systems where a VIA south bridge was detected, and 1250 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1251 */ 1252 static void quirk_via_vlink(struct pci_dev *dev) 1253 { 1254 u8 irq, new_irq; 1255 1256 /* Check if we have VLink at all */ 1257 if (via_vlink_dev_lo == -1) 1258 return; 1259 1260 new_irq = dev->irq; 1261 1262 /* Don't quirk interrupts outside the legacy IRQ range */ 1263 if (!new_irq || new_irq > 15) 1264 return; 1265 1266 /* Internal device ? */ 1267 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1268 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1269 return; 1270 1271 /* 1272 * This is an internal VLink device on a PIC interrupt. The BIOS 1273 * ought to have set this but may not have, so we redo it. 1274 */ 1275 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1276 if (new_irq != irq) { 1277 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1278 irq, new_irq); 1279 udelay(15); /* unknown if delay really needed */ 1280 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1281 } 1282 } 1283 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1284 1285 /* 1286 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1287 * of VT82C597 for backward compatibility. We need to switch it off to be 1288 * able to recognize the real type of the chip. 1289 */ 1290 static void quirk_vt82c598_id(struct pci_dev *dev) 1291 { 1292 pci_write_config_byte(dev, 0xfc, 0); 1293 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1294 } 1295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1296 1297 /* 1298 * CardBus controllers have a legacy base address that enables them to 1299 * respond as i82365 pcmcia controllers. We don't want them to do this 1300 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1301 * driver does not (and should not) handle CardBus. 1302 */ 1303 static void quirk_cardbus_legacy(struct pci_dev *dev) 1304 { 1305 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1306 } 1307 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1308 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1309 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1310 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1311 1312 /* 1313 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1314 * what the designers were smoking but let's not inhale... 1315 * 1316 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1317 * turn it off! 1318 */ 1319 static void quirk_amd_ordering(struct pci_dev *dev) 1320 { 1321 u32 pcic; 1322 pci_read_config_dword(dev, 0x4C, &pcic); 1323 if ((pcic & 6) != 6) { 1324 pcic |= 6; 1325 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1326 pci_write_config_dword(dev, 0x4C, pcic); 1327 pci_read_config_dword(dev, 0x84, &pcic); 1328 pcic |= (1 << 23); /* Required in this mode */ 1329 pci_write_config_dword(dev, 0x84, pcic); 1330 } 1331 } 1332 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1333 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1334 1335 /* 1336 * DreamWorks-provided workaround for Dunord I-3000 problem 1337 * 1338 * This card decodes and responds to addresses not apparently assigned to 1339 * it. We force a larger allocation to ensure that nothing gets put too 1340 * close to it. 1341 */ 1342 static void quirk_dunord(struct pci_dev *dev) 1343 { 1344 struct resource *r = &dev->resource[1]; 1345 1346 r->flags |= IORESOURCE_UNSET; 1347 resource_set_range(r, 0, SZ_16M); 1348 } 1349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1350 1351 /* 1352 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1353 * decoding (transparent), and does indicate this in the ProgIf. 1354 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1355 */ 1356 static void quirk_transparent_bridge(struct pci_dev *dev) 1357 { 1358 dev->transparent = 1; 1359 } 1360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1362 1363 /* 1364 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1365 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1366 * found at http://www.national.com/analog for info on what these bits do. 1367 * <christer@weinigel.se> 1368 */ 1369 static void quirk_mediagx_master(struct pci_dev *dev) 1370 { 1371 u8 reg; 1372 1373 pci_read_config_byte(dev, 0x41, ®); 1374 if (reg & 2) { 1375 reg &= ~2; 1376 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1377 reg); 1378 pci_write_config_byte(dev, 0x41, reg); 1379 } 1380 } 1381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1382 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1383 1384 /* 1385 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1386 * in the odd case it is not the results are corruption hence the presence 1387 * of a Linux check. 1388 */ 1389 static void quirk_disable_pxb(struct pci_dev *pdev) 1390 { 1391 u16 config; 1392 1393 if (pdev->revision != 0x04) /* Only C0 requires this */ 1394 return; 1395 pci_read_config_word(pdev, 0x40, &config); 1396 if (config & (1<<6)) { 1397 config &= ~(1<<6); 1398 pci_write_config_word(pdev, 0x40, config); 1399 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1400 } 1401 } 1402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1403 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1404 1405 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1406 { 1407 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1408 u8 tmp; 1409 1410 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1411 if (tmp == 0x01) { 1412 pci_read_config_byte(pdev, 0x40, &tmp); 1413 pci_write_config_byte(pdev, 0x40, tmp|1); 1414 pci_write_config_byte(pdev, 0x9, 1); 1415 pci_write_config_byte(pdev, 0xa, 6); 1416 pci_write_config_byte(pdev, 0x40, tmp); 1417 1418 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1419 pci_info(pdev, "set SATA to AHCI mode\n"); 1420 } 1421 } 1422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1423 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1425 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1427 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1428 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1429 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1430 1431 /* Serverworks CSB5 IDE does not fully support native mode */ 1432 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1433 { 1434 u8 prog; 1435 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1436 if (prog & 5) { 1437 prog &= ~5; 1438 pdev->class &= ~5; 1439 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1440 /* PCI layer will sort out resources */ 1441 } 1442 } 1443 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1444 1445 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1446 static void quirk_ide_samemode(struct pci_dev *pdev) 1447 { 1448 u8 prog; 1449 1450 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1451 1452 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1453 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1454 prog &= ~5; 1455 pdev->class &= ~5; 1456 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1457 } 1458 } 1459 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1460 1461 /* Some ATA devices break if put into D3 */ 1462 static void quirk_no_ata_d3(struct pci_dev *pdev) 1463 { 1464 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1465 } 1466 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1467 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1468 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1469 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1470 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1471 /* ALi loses some register settings that we cannot then restore */ 1472 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1473 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1474 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1475 occur when mode detecting */ 1476 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1477 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1478 1479 /* 1480 * This was originally an Alpha-specific thing, but it really fits here. 1481 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1482 */ 1483 static void quirk_eisa_bridge(struct pci_dev *dev) 1484 { 1485 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1486 } 1487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1488 1489 /* 1490 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1491 * is not activated. The myth is that Asus said that they do not want the 1492 * users to be irritated by just another PCI Device in the Win98 device 1493 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1494 * package 2.7.0 for details) 1495 * 1496 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1497 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1498 * becomes necessary to do this tweak in two steps -- the chosen trigger 1499 * is either the Host bridge (preferred) or on-board VGA controller. 1500 * 1501 * Note that we used to unhide the SMBus that way on Toshiba laptops 1502 * (Satellite A40 and Tecra M2) but then found that the thermal management 1503 * was done by SMM code, which could cause unsynchronized concurrent 1504 * accesses to the SMBus registers, with potentially bad effects. Thus you 1505 * should be very careful when adding new entries: if SMM is accessing the 1506 * Intel SMBus, this is a very good reason to leave it hidden. 1507 * 1508 * Likewise, many recent laptops use ACPI for thermal management. If the 1509 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1510 * natively, and keeping the SMBus hidden is the right thing to do. If you 1511 * are about to add an entry in the table below, please first disassemble 1512 * the DSDT and double-check that there is no code accessing the SMBus. 1513 */ 1514 static int asus_hides_smbus; 1515 1516 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1517 { 1518 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1519 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1520 switch (dev->subsystem_device) { 1521 case 0x8025: /* P4B-LX */ 1522 case 0x8070: /* P4B */ 1523 case 0x8088: /* P4B533 */ 1524 case 0x1626: /* L3C notebook */ 1525 asus_hides_smbus = 1; 1526 } 1527 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1528 switch (dev->subsystem_device) { 1529 case 0x80b1: /* P4GE-V */ 1530 case 0x80b2: /* P4PE */ 1531 case 0x8093: /* P4B533-V */ 1532 asus_hides_smbus = 1; 1533 } 1534 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1535 switch (dev->subsystem_device) { 1536 case 0x8030: /* P4T533 */ 1537 asus_hides_smbus = 1; 1538 } 1539 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1540 switch (dev->subsystem_device) { 1541 case 0x8070: /* P4G8X Deluxe */ 1542 asus_hides_smbus = 1; 1543 } 1544 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1545 switch (dev->subsystem_device) { 1546 case 0x80c9: /* PU-DLS */ 1547 asus_hides_smbus = 1; 1548 } 1549 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1550 switch (dev->subsystem_device) { 1551 case 0x1751: /* M2N notebook */ 1552 case 0x1821: /* M5N notebook */ 1553 case 0x1897: /* A6L notebook */ 1554 asus_hides_smbus = 1; 1555 } 1556 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1557 switch (dev->subsystem_device) { 1558 case 0x184b: /* W1N notebook */ 1559 case 0x186a: /* M6Ne notebook */ 1560 asus_hides_smbus = 1; 1561 } 1562 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1563 switch (dev->subsystem_device) { 1564 case 0x80f2: /* P4P800-X */ 1565 asus_hides_smbus = 1; 1566 } 1567 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1568 switch (dev->subsystem_device) { 1569 case 0x1882: /* M6V notebook */ 1570 case 0x1977: /* A6VA notebook */ 1571 asus_hides_smbus = 1; 1572 } 1573 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1574 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1575 switch (dev->subsystem_device) { 1576 case 0x088C: /* HP Compaq nc8000 */ 1577 case 0x0890: /* HP Compaq nc6000 */ 1578 asus_hides_smbus = 1; 1579 } 1580 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1581 switch (dev->subsystem_device) { 1582 case 0x12bc: /* HP D330L */ 1583 case 0x12bd: /* HP D530 */ 1584 case 0x006a: /* HP Compaq nx9500 */ 1585 asus_hides_smbus = 1; 1586 } 1587 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1588 switch (dev->subsystem_device) { 1589 case 0x12bf: /* HP xw4100 */ 1590 asus_hides_smbus = 1; 1591 } 1592 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1593 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1594 switch (dev->subsystem_device) { 1595 case 0xC00C: /* Samsung P35 notebook */ 1596 asus_hides_smbus = 1; 1597 } 1598 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1599 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1600 switch (dev->subsystem_device) { 1601 case 0x0058: /* Compaq Evo N620c */ 1602 asus_hides_smbus = 1; 1603 } 1604 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1605 switch (dev->subsystem_device) { 1606 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1607 /* Motherboard doesn't have Host bridge 1608 * subvendor/subdevice IDs, therefore checking 1609 * its on-board VGA controller */ 1610 asus_hides_smbus = 1; 1611 } 1612 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1613 switch (dev->subsystem_device) { 1614 case 0x00b8: /* Compaq Evo D510 CMT */ 1615 case 0x00b9: /* Compaq Evo D510 SFF */ 1616 case 0x00ba: /* Compaq Evo D510 USDT */ 1617 /* Motherboard doesn't have Host bridge 1618 * subvendor/subdevice IDs and on-board VGA 1619 * controller is disabled if an AGP card is 1620 * inserted, therefore checking USB UHCI 1621 * Controller #1 */ 1622 asus_hides_smbus = 1; 1623 } 1624 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1625 switch (dev->subsystem_device) { 1626 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1627 /* Motherboard doesn't have host bridge 1628 * subvendor/subdevice IDs, therefore checking 1629 * its on-board VGA controller */ 1630 asus_hides_smbus = 1; 1631 } 1632 } 1633 } 1634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1644 1645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1648 1649 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1650 { 1651 u16 val; 1652 1653 if (likely(!asus_hides_smbus)) 1654 return; 1655 1656 pci_read_config_word(dev, 0xF2, &val); 1657 if (val & 0x8) { 1658 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1659 pci_read_config_word(dev, 0xF2, &val); 1660 if (val & 0x8) 1661 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1662 val); 1663 else 1664 pci_info(dev, "Enabled i801 SMBus device\n"); 1665 } 1666 } 1667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1668 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1669 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1670 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1673 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1674 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1675 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1676 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1677 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1678 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1679 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1680 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1681 1682 /* It appears we just have one such device. If not, we have a warning */ 1683 static void __iomem *asus_rcba_base; 1684 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1685 { 1686 u32 rcba; 1687 1688 if (likely(!asus_hides_smbus)) 1689 return; 1690 WARN_ON(asus_rcba_base); 1691 1692 pci_read_config_dword(dev, 0xF0, &rcba); 1693 /* use bits 31:14, 16 kB aligned */ 1694 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1695 if (asus_rcba_base == NULL) 1696 return; 1697 } 1698 1699 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1700 { 1701 u32 val; 1702 1703 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1704 return; 1705 1706 /* read the Function Disable register, dword mode only */ 1707 val = readl(asus_rcba_base + 0x3418); 1708 1709 /* enable the SMBus device */ 1710 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1711 } 1712 1713 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1714 { 1715 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1716 return; 1717 1718 iounmap(asus_rcba_base); 1719 asus_rcba_base = NULL; 1720 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1721 } 1722 1723 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1724 { 1725 asus_hides_smbus_lpc_ich6_suspend(dev); 1726 asus_hides_smbus_lpc_ich6_resume_early(dev); 1727 asus_hides_smbus_lpc_ich6_resume(dev); 1728 } 1729 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1730 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1731 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1732 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1733 1734 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1735 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1736 { 1737 u8 val = 0; 1738 pci_read_config_byte(dev, 0x77, &val); 1739 if (val & 0x10) { 1740 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1741 pci_write_config_byte(dev, 0x77, val & ~0x10); 1742 } 1743 } 1744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1745 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1746 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1748 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1749 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1750 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1751 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1752 1753 /* 1754 * ... This is further complicated by the fact that some SiS96x south 1755 * bridges pretend to be 85C503/5513 instead. In that case see if we 1756 * spotted a compatible north bridge to make sure. 1757 * (pci_find_device() doesn't work yet) 1758 * 1759 * We can also enable the sis96x bit in the discovery register.. 1760 */ 1761 #define SIS_DETECT_REGISTER 0x40 1762 1763 static void quirk_sis_503(struct pci_dev *dev) 1764 { 1765 u8 reg; 1766 u16 devid; 1767 1768 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1769 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1770 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1771 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1772 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1773 return; 1774 } 1775 1776 /* 1777 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1778 * it has already been processed. (Depends on link order, which is 1779 * apparently not guaranteed) 1780 */ 1781 dev->device = devid; 1782 quirk_sis_96x_smbus(dev); 1783 } 1784 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1785 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1786 1787 /* 1788 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1789 * and MC97 modem controller are disabled when a second PCI soundcard is 1790 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1791 * -- bjd 1792 */ 1793 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1794 { 1795 u8 val; 1796 int asus_hides_ac97 = 0; 1797 1798 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1799 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1800 asus_hides_ac97 = 1; 1801 } 1802 1803 if (!asus_hides_ac97) 1804 return; 1805 1806 pci_read_config_byte(dev, 0x50, &val); 1807 if (val & 0xc0) { 1808 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1809 pci_read_config_byte(dev, 0x50, &val); 1810 if (val & 0xc0) 1811 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1812 val); 1813 else 1814 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1815 } 1816 } 1817 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1818 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1819 1820 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1821 1822 /* 1823 * If we are using libata we can drive this chip properly but must do this 1824 * early on to make the additional device appear during the PCI scanning. 1825 */ 1826 static void quirk_jmicron_ata(struct pci_dev *pdev) 1827 { 1828 u32 conf1, conf5, class; 1829 u8 hdr; 1830 1831 /* Only poke fn 0 */ 1832 if (PCI_FUNC(pdev->devfn)) 1833 return; 1834 1835 pci_read_config_dword(pdev, 0x40, &conf1); 1836 pci_read_config_dword(pdev, 0x80, &conf5); 1837 1838 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1839 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1840 1841 switch (pdev->device) { 1842 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1843 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1844 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1845 /* The controller should be in single function ahci mode */ 1846 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1847 break; 1848 1849 case PCI_DEVICE_ID_JMICRON_JMB365: 1850 case PCI_DEVICE_ID_JMICRON_JMB366: 1851 /* Redirect IDE second PATA port to the right spot */ 1852 conf5 |= (1 << 24); 1853 fallthrough; 1854 case PCI_DEVICE_ID_JMICRON_JMB361: 1855 case PCI_DEVICE_ID_JMICRON_JMB363: 1856 case PCI_DEVICE_ID_JMICRON_JMB369: 1857 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1858 /* Set the class codes correctly and then direct IDE 0 */ 1859 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1860 break; 1861 1862 case PCI_DEVICE_ID_JMICRON_JMB368: 1863 /* The controller should be in single function IDE mode */ 1864 conf1 |= 0x00C00000; /* Set 22, 23 */ 1865 break; 1866 } 1867 1868 pci_write_config_dword(pdev, 0x40, conf1); 1869 pci_write_config_dword(pdev, 0x80, conf5); 1870 1871 /* Update pdev accordingly */ 1872 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1873 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; 1874 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); 1875 1876 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1877 pdev->class = class >> 8; 1878 } 1879 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1880 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1881 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1882 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1883 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1884 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1885 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1886 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1887 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1888 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1889 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1890 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1891 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1892 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1893 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1894 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1895 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1896 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1897 1898 #endif 1899 1900 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1901 { 1902 if (dev->multifunction) { 1903 device_disable_async_suspend(&dev->dev); 1904 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1905 } 1906 } 1907 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1908 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1911 1912 #ifdef CONFIG_X86_IO_APIC 1913 static void quirk_alder_ioapic(struct pci_dev *pdev) 1914 { 1915 int i; 1916 1917 if ((pdev->class >> 8) != 0xff00) 1918 return; 1919 1920 /* 1921 * The first BAR is the location of the IO-APIC... we must 1922 * not touch this (and it's already covered by the fixmap), so 1923 * forcibly insert it into the resource tree. 1924 */ 1925 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1926 insert_resource(&iomem_resource, &pdev->resource[0]); 1927 1928 /* 1929 * The next five BARs all seem to be rubbish, so just clean 1930 * them out. 1931 */ 1932 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1933 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1934 } 1935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1936 #endif 1937 1938 static void quirk_no_msi(struct pci_dev *dev) 1939 { 1940 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1941 dev->no_msi = 1; 1942 } 1943 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1945 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1949 1950 static void quirk_pcie_mch(struct pci_dev *pdev) 1951 { 1952 pdev->no_msi = 1; 1953 } 1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1957 1958 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1959 1960 /* 1961 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1962 * actually on the AMBA bus. These fake PCI devices can support SVA via 1963 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1964 * 1965 * Normally stalling must not be enabled for PCI devices, since it would 1966 * break the PCI requirement for free-flowing writes and may lead to 1967 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1968 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1969 * even when a "PCI" device turns out to be a regular old SoC device 1970 * dressed up as a RCiEP and normal rules don't apply. 1971 */ 1972 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1973 { 1974 struct property_entry properties[] = { 1975 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1976 {}, 1977 }; 1978 1979 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1980 return; 1981 1982 pdev->pasid_no_tlp = 1; 1983 1984 /* 1985 * Set the dma-can-stall property on ACPI platforms. Device tree 1986 * can set it directly. 1987 */ 1988 if (!pdev->dev.of_node && 1989 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1990 pci_warn(pdev, "could not add stall property"); 1991 } 1992 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 1993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 1994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 1995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 1996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 1997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 1998 1999 /* 2000 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 2001 * together on certain PXH-based systems. 2002 */ 2003 static void quirk_pcie_pxh(struct pci_dev *dev) 2004 { 2005 dev->no_msi = 1; 2006 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 2007 } 2008 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 2009 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 2010 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 2011 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 2012 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 2013 2014 /* 2015 * Some Intel PCI Express chipsets have trouble with downstream device 2016 * power management. 2017 */ 2018 static void quirk_intel_pcie_pm(struct pci_dev *dev) 2019 { 2020 pci_pm_d3hot_delay = 120; 2021 dev->no_d1d2 = 1; 2022 } 2023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2044 2045 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2046 { 2047 if (dev->d3hot_delay >= delay) 2048 return; 2049 2050 dev->d3hot_delay = delay; 2051 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2052 dev->d3hot_delay); 2053 } 2054 2055 static void quirk_radeon_pm(struct pci_dev *dev) 2056 { 2057 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2058 dev->subsystem_device == 0x00e2) 2059 quirk_d3hot_delay(dev, 20); 2060 } 2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2062 2063 /* 2064 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2065 * reset is performed too soon after transition to D0, extend d3hot_delay 2066 * to previous effective default for all NVIDIA HDA controllers. 2067 */ 2068 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2069 { 2070 quirk_d3hot_delay(dev, 20); 2071 } 2072 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2073 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2074 quirk_nvidia_hda_pm); 2075 2076 /* 2077 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2078 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2079 * 2080 * The kernel attempts to transition these devices to D3cold, but that seems 2081 * to be ineffective on the platforms in question; the PCI device appears to 2082 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2083 * extended delay in order to succeed. 2084 */ 2085 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2086 { 2087 quirk_d3hot_delay(dev, 20); 2088 } 2089 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2092 2093 #ifdef CONFIG_X86_IO_APIC 2094 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2095 { 2096 noioapicreroute = 1; 2097 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2098 2099 return 0; 2100 } 2101 2102 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2103 /* 2104 * Systems to exclude from boot interrupt reroute quirks 2105 */ 2106 { 2107 .callback = dmi_disable_ioapicreroute, 2108 .ident = "ASUSTek Computer INC. M2N-LR", 2109 .matches = { 2110 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2111 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2112 }, 2113 }, 2114 {} 2115 }; 2116 2117 /* 2118 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2119 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2120 * that a PCI device's interrupt handler is installed on the boot interrupt 2121 * line instead. 2122 */ 2123 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2124 { 2125 dmi_check_system(boot_interrupt_dmi_table); 2126 if (noioapicquirk || noioapicreroute) 2127 return; 2128 2129 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2130 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2131 dev->vendor, dev->device); 2132 } 2133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2141 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2142 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2143 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2144 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2145 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2146 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2147 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2148 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2149 2150 /* 2151 * On some chipsets we can disable the generation of legacy INTx boot 2152 * interrupts. 2153 */ 2154 2155 /* 2156 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2157 * 300641-004US, section 5.7.3. 2158 * 2159 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2160 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2161 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2162 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2163 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2164 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2165 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2166 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2167 * Core IO on Xeon Scalable, see Intel order no 610950. 2168 */ 2169 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2170 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2171 2172 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2173 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2174 2175 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2176 { 2177 u16 pci_config_word; 2178 u32 pci_config_dword; 2179 2180 if (noioapicquirk) 2181 return; 2182 2183 switch (dev->device) { 2184 case PCI_DEVICE_ID_INTEL_ESB_10: 2185 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2186 &pci_config_word); 2187 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2188 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2189 pci_config_word); 2190 break; 2191 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2192 case 0x0e28: /* Xeon E5/E7 V2 */ 2193 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2194 case 0x6f28: /* Xeon D-1500 */ 2195 case 0x2034: /* Xeon Scalable Family */ 2196 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2197 &pci_config_dword); 2198 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2199 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2200 pci_config_dword); 2201 break; 2202 default: 2203 return; 2204 } 2205 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2206 dev->vendor, dev->device); 2207 } 2208 /* 2209 * Device 29 Func 5 Device IDs of IO-APIC 2210 * containing ABAR—APIC1 Alternate Base Address Register 2211 */ 2212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2213 quirk_disable_intel_boot_interrupt); 2214 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2215 quirk_disable_intel_boot_interrupt); 2216 2217 /* 2218 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2219 * containing Coherent Interface Protocol Interrupt Control 2220 * 2221 * Device IDs obtained from volume 2 datasheets of commented 2222 * families above. 2223 */ 2224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2225 quirk_disable_intel_boot_interrupt); 2226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2227 quirk_disable_intel_boot_interrupt); 2228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2229 quirk_disable_intel_boot_interrupt); 2230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2231 quirk_disable_intel_boot_interrupt); 2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2233 quirk_disable_intel_boot_interrupt); 2234 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2235 quirk_disable_intel_boot_interrupt); 2236 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2237 quirk_disable_intel_boot_interrupt); 2238 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2239 quirk_disable_intel_boot_interrupt); 2240 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2241 quirk_disable_intel_boot_interrupt); 2242 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2243 quirk_disable_intel_boot_interrupt); 2244 2245 /* Disable boot interrupts on HT-1000 */ 2246 #define BC_HT1000_FEATURE_REG 0x64 2247 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2248 #define BC_HT1000_MAP_IDX 0xC00 2249 #define BC_HT1000_MAP_DATA 0xC01 2250 2251 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2252 { 2253 u32 pci_config_dword; 2254 u8 irq; 2255 2256 if (noioapicquirk) 2257 return; 2258 2259 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2260 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2261 BC_HT1000_PIC_REGS_ENABLE); 2262 2263 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2264 outb(irq, BC_HT1000_MAP_IDX); 2265 outb(0x00, BC_HT1000_MAP_DATA); 2266 } 2267 2268 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2269 2270 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2271 dev->vendor, dev->device); 2272 } 2273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2274 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2275 2276 /* Disable boot interrupts on AMD and ATI chipsets */ 2277 2278 /* 2279 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2280 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2281 * (due to an erratum). 2282 */ 2283 #define AMD_813X_MISC 0x40 2284 #define AMD_813X_NOIOAMODE (1<<0) 2285 #define AMD_813X_REV_B1 0x12 2286 #define AMD_813X_REV_B2 0x13 2287 2288 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2289 { 2290 u32 pci_config_dword; 2291 2292 if (noioapicquirk) 2293 return; 2294 if ((dev->revision == AMD_813X_REV_B1) || 2295 (dev->revision == AMD_813X_REV_B2)) 2296 return; 2297 2298 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2299 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2300 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2301 2302 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2303 dev->vendor, dev->device); 2304 } 2305 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2306 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2308 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2309 2310 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2311 2312 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2313 { 2314 u16 pci_config_word; 2315 2316 if (noioapicquirk) 2317 return; 2318 2319 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2320 if (!pci_config_word) { 2321 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2322 dev->vendor, dev->device); 2323 return; 2324 } 2325 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2326 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2327 dev->vendor, dev->device); 2328 } 2329 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2330 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2331 #endif /* CONFIG_X86_IO_APIC */ 2332 2333 /* 2334 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2335 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2336 * Re-allocate the region if needed... 2337 */ 2338 static void quirk_tc86c001_ide(struct pci_dev *dev) 2339 { 2340 struct resource *r = &dev->resource[0]; 2341 2342 if (r->start & 0x8) { 2343 r->flags |= IORESOURCE_UNSET; 2344 resource_set_range(r, 0, SZ_16); 2345 } 2346 } 2347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2348 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2349 quirk_tc86c001_ide); 2350 2351 /* 2352 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2353 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2354 * being read correctly if bit 7 of the base address is set. 2355 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2356 * Re-allocate the regions to a 256-byte boundary if necessary. 2357 */ 2358 static void quirk_plx_pci9050(struct pci_dev *dev) 2359 { 2360 unsigned int bar; 2361 2362 /* Fixed in revision 2 (PCI 9052). */ 2363 if (dev->revision >= 2) 2364 return; 2365 for (bar = 0; bar <= 1; bar++) 2366 if (pci_resource_len(dev, bar) == 0x80 && 2367 (pci_resource_start(dev, bar) & 0x80)) { 2368 struct resource *r = &dev->resource[bar]; 2369 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2370 bar); 2371 r->flags |= IORESOURCE_UNSET; 2372 resource_set_range(r, 0, SZ_256); 2373 } 2374 } 2375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2376 quirk_plx_pci9050); 2377 /* 2378 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2379 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2380 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2381 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2382 * 2383 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2384 * driver. 2385 */ 2386 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2387 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2388 2389 static void quirk_netmos(struct pci_dev *dev) 2390 { 2391 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2392 unsigned int num_serial = dev->subsystem_device & 0xf; 2393 2394 /* 2395 * These Netmos parts are multiport serial devices with optional 2396 * parallel ports. Even when parallel ports are present, they 2397 * are identified as class SERIAL, which means the serial driver 2398 * will claim them. To prevent this, mark them as class OTHER. 2399 * These combo devices should be claimed by parport_serial. 2400 * 2401 * The subdevice ID is of the form 0x00PS, where <P> is the number 2402 * of parallel ports and <S> is the number of serial ports. 2403 */ 2404 switch (dev->device) { 2405 case PCI_DEVICE_ID_NETMOS_9835: 2406 /* Well, this rule doesn't hold for the following 9835 device */ 2407 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2408 dev->subsystem_device == 0x0299) 2409 return; 2410 fallthrough; 2411 case PCI_DEVICE_ID_NETMOS_9735: 2412 case PCI_DEVICE_ID_NETMOS_9745: 2413 case PCI_DEVICE_ID_NETMOS_9845: 2414 case PCI_DEVICE_ID_NETMOS_9855: 2415 if (num_parallel) { 2416 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2417 dev->device, num_parallel, num_serial); 2418 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2419 (dev->class & 0xff); 2420 } 2421 } 2422 } 2423 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2424 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2425 2426 static void quirk_e100_interrupt(struct pci_dev *dev) 2427 { 2428 u16 command, pmcsr; 2429 u8 __iomem *csr; 2430 u8 cmd_hi; 2431 2432 switch (dev->device) { 2433 /* PCI IDs taken from drivers/net/e100.c */ 2434 case 0x1029: 2435 case 0x1030 ... 0x1034: 2436 case 0x1038 ... 0x103E: 2437 case 0x1050 ... 0x1057: 2438 case 0x1059: 2439 case 0x1064 ... 0x106B: 2440 case 0x1091 ... 0x1095: 2441 case 0x1209: 2442 case 0x1229: 2443 case 0x2449: 2444 case 0x2459: 2445 case 0x245D: 2446 case 0x27DC: 2447 break; 2448 default: 2449 return; 2450 } 2451 2452 /* 2453 * Some firmware hands off the e100 with interrupts enabled, 2454 * which can cause a flood of interrupts if packets are 2455 * received before the driver attaches to the device. So 2456 * disable all e100 interrupts here. The driver will 2457 * re-enable them when it's ready. 2458 */ 2459 pci_read_config_word(dev, PCI_COMMAND, &command); 2460 2461 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2462 return; 2463 2464 /* 2465 * Check that the device is in the D0 power state. If it's not, 2466 * there is no point to look any further. 2467 */ 2468 if (dev->pm_cap) { 2469 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2470 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2471 return; 2472 } 2473 2474 /* Convert from PCI bus to resource space. */ 2475 csr = ioremap(pci_resource_start(dev, 0), 8); 2476 if (!csr) { 2477 pci_warn(dev, "Can't map e100 registers\n"); 2478 return; 2479 } 2480 2481 cmd_hi = readb(csr + 3); 2482 if (cmd_hi == 0) { 2483 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2484 writeb(1, csr + 3); 2485 } 2486 2487 iounmap(csr); 2488 } 2489 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2490 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2491 2492 /* 2493 * The 82575 and 82598 may experience data corruption issues when transitioning 2494 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2495 */ 2496 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2497 { 2498 pci_info(dev, "Disabling L0s\n"); 2499 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2500 } 2501 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2506 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2507 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2508 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2509 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2510 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2511 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2512 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2513 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2514 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2515 2516 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2517 { 2518 pci_info(dev, "Disabling ASPM L0s/L1\n"); 2519 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 2520 } 2521 2522 /* 2523 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2524 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2525 * disable both L0s and L1 for now to be safe. 2526 */ 2527 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2528 2529 /* 2530 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2531 * Link bit cleared after starting the link retrain process to allow this 2532 * process to finish. 2533 * 2534 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2535 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2536 */ 2537 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2538 { 2539 dev->clear_retrain_link = 1; 2540 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2541 } 2542 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2544 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2545 2546 static void fixup_rev1_53c810(struct pci_dev *dev) 2547 { 2548 u32 class = dev->class; 2549 2550 /* 2551 * rev 1 ncr53c810 chips don't set the class at all which means 2552 * they don't get their resources remapped. Fix that here. 2553 */ 2554 if (class) 2555 return; 2556 2557 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2558 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2559 class, dev->class); 2560 } 2561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2562 2563 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2564 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2565 { 2566 u16 en1k; 2567 2568 pci_read_config_word(dev, 0x40, &en1k); 2569 2570 if (en1k & 0x200) { 2571 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2572 dev->io_window_1k = 1; 2573 } 2574 } 2575 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2576 2577 /* 2578 * Under some circumstances, AER is not linked with extended capabilities. 2579 * Force it to be linked by setting the corresponding control bit in the 2580 * config space. 2581 */ 2582 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2583 { 2584 uint8_t b; 2585 2586 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2587 if (!(b & 0x20)) { 2588 pci_write_config_byte(dev, 0xf41, b | 0x20); 2589 pci_info(dev, "Linking AER extended capability\n"); 2590 } 2591 } 2592 } 2593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2594 quirk_nvidia_ck804_pcie_aer_ext_cap); 2595 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2596 quirk_nvidia_ck804_pcie_aer_ext_cap); 2597 2598 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2599 { 2600 /* 2601 * Disable PCI Bus Parking and PCI Master read caching on CX700 2602 * which causes unspecified timing errors with a VT6212L on the PCI 2603 * bus leading to USB2.0 packet loss. 2604 * 2605 * This quirk is only enabled if a second (on the external PCI bus) 2606 * VT6212L is found -- the CX700 core itself also contains a USB 2607 * host controller with the same PCI ID as the VT6212L. 2608 */ 2609 2610 /* Count VT6212L instances */ 2611 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2612 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2613 uint8_t b; 2614 2615 /* 2616 * p should contain the first (internal) VT6212L -- see if we have 2617 * an external one by searching again. 2618 */ 2619 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2620 if (!p) 2621 return; 2622 pci_dev_put(p); 2623 2624 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2625 if (b & 0x40) { 2626 /* Turn off PCI Bus Parking */ 2627 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2628 2629 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2630 } 2631 } 2632 2633 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2634 if (b != 0) { 2635 /* Turn off PCI Master read caching */ 2636 pci_write_config_byte(dev, 0x72, 0x0); 2637 2638 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2639 pci_write_config_byte(dev, 0x75, 0x1); 2640 2641 /* Disable "Read FIFO Timer" */ 2642 pci_write_config_byte(dev, 0x77, 0x0); 2643 2644 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2645 } 2646 } 2647 } 2648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2649 2650 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2651 { 2652 u32 rev; 2653 2654 pci_read_config_dword(dev, 0xf4, &rev); 2655 2656 /* Only CAP the MRRS if the device is a 5719 A0 */ 2657 if (rev == 0x05719000) { 2658 int readrq = pcie_get_readrq(dev); 2659 if (readrq > 2048) 2660 pcie_set_readrq(dev, 2048); 2661 } 2662 } 2663 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2664 PCI_DEVICE_ID_TIGON3_5719, 2665 quirk_brcm_5719_limit_mrrs); 2666 2667 /* 2668 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2669 * hide device 6 which configures the overflow device access containing the 2670 * DRBs - this is where we expose device 6. 2671 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2672 */ 2673 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2674 { 2675 u8 reg; 2676 2677 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2678 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2679 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2680 } 2681 } 2682 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2683 quirk_unhide_mch_dev6); 2684 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2685 quirk_unhide_mch_dev6); 2686 2687 #ifdef CONFIG_PCI_MSI 2688 /* 2689 * Some chipsets do not support MSI. We cannot easily rely on setting 2690 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2691 * other buses controlled by the chipset even if Linux is not aware of it. 2692 * Instead of setting the flag on all buses in the machine, simply disable 2693 * MSI globally. 2694 */ 2695 static void quirk_disable_all_msi(struct pci_dev *dev) 2696 { 2697 pci_no_msi(); 2698 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2699 } 2700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2709 2710 /* Disable MSI on chipsets that are known to not support it */ 2711 static void quirk_disable_msi(struct pci_dev *dev) 2712 { 2713 if (dev->subordinate) { 2714 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2715 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2716 } 2717 } 2718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2721 2722 /* 2723 * The APC bridge device in AMD 780 family northbridges has some random 2724 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2725 * we use the possible vendor/device IDs of the host bridge for the 2726 * declared quirk, and search for the APC bridge by slot number. 2727 */ 2728 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2729 { 2730 struct pci_dev *apc_bridge; 2731 2732 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2733 if (apc_bridge) { 2734 if (apc_bridge->device == 0x9602) 2735 quirk_disable_msi(apc_bridge); 2736 pci_dev_put(apc_bridge); 2737 } 2738 } 2739 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2741 2742 /* 2743 * Go through the list of HyperTransport capabilities and return 1 if a HT 2744 * MSI capability is found and enabled. 2745 */ 2746 static int msi_ht_cap_enabled(struct pci_dev *dev) 2747 { 2748 int pos, ttl = PCI_FIND_CAP_TTL; 2749 2750 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2751 while (pos && ttl--) { 2752 u8 flags; 2753 2754 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2755 &flags) == 0) { 2756 pci_info(dev, "Found %s HT MSI Mapping\n", 2757 flags & HT_MSI_FLAGS_ENABLE ? 2758 "enabled" : "disabled"); 2759 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2760 } 2761 2762 pos = pci_find_next_ht_capability(dev, pos, 2763 HT_CAPTYPE_MSI_MAPPING); 2764 } 2765 return 0; 2766 } 2767 2768 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2769 static void quirk_msi_ht_cap(struct pci_dev *dev) 2770 { 2771 if (!msi_ht_cap_enabled(dev)) 2772 quirk_disable_msi(dev); 2773 } 2774 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2775 quirk_msi_ht_cap); 2776 2777 /* 2778 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2779 * if the MSI capability is set in any of these mappings. 2780 */ 2781 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2782 { 2783 struct pci_dev *pdev; 2784 2785 /* 2786 * Check HT MSI cap on this chipset and the root one. A single one 2787 * having MSI is enough to be sure that MSI is supported. 2788 */ 2789 pdev = pci_get_slot(dev->bus, 0); 2790 if (!pdev) 2791 return; 2792 if (!msi_ht_cap_enabled(pdev)) 2793 quirk_msi_ht_cap(dev); 2794 pci_dev_put(pdev); 2795 } 2796 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2797 quirk_nvidia_ck804_msi_ht_cap); 2798 2799 /* Force enable MSI mapping capability on HT bridges */ 2800 static void ht_enable_msi_mapping(struct pci_dev *dev) 2801 { 2802 int pos, ttl = PCI_FIND_CAP_TTL; 2803 2804 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2805 while (pos && ttl--) { 2806 u8 flags; 2807 2808 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2809 &flags) == 0) { 2810 pci_info(dev, "Enabling HT MSI Mapping\n"); 2811 2812 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2813 flags | HT_MSI_FLAGS_ENABLE); 2814 } 2815 pos = pci_find_next_ht_capability(dev, pos, 2816 HT_CAPTYPE_MSI_MAPPING); 2817 } 2818 } 2819 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2820 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2821 ht_enable_msi_mapping); 2822 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2823 ht_enable_msi_mapping); 2824 2825 /* 2826 * The P5N32-SLI motherboards from Asus have a problem with MSI 2827 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2828 * also affects other devices. As for now, turn off MSI for this device. 2829 */ 2830 static void nvenet_msi_disable(struct pci_dev *dev) 2831 { 2832 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2833 2834 if (board_name && 2835 (strstr(board_name, "P5N32-SLI PREMIUM") || 2836 strstr(board_name, "P5N32-E SLI"))) { 2837 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2838 dev->no_msi = 1; 2839 } 2840 } 2841 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2842 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2843 nvenet_msi_disable); 2844 2845 /* 2846 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2847 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2848 * interrupts for PME and AER events; instead only INTx interrupts are 2849 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2850 * for other events, since PCIe specification doesn't support using a mix of 2851 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2852 * service drivers registering their respective ISRs for MSIs. 2853 */ 2854 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2855 { 2856 dev->no_msi = 1; 2857 } 2858 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2859 PCI_CLASS_BRIDGE_PCI, 8, 2860 pci_quirk_nvidia_tegra_disable_rp_msi); 2861 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2862 PCI_CLASS_BRIDGE_PCI, 8, 2863 pci_quirk_nvidia_tegra_disable_rp_msi); 2864 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2865 PCI_CLASS_BRIDGE_PCI, 8, 2866 pci_quirk_nvidia_tegra_disable_rp_msi); 2867 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2868 PCI_CLASS_BRIDGE_PCI, 8, 2869 pci_quirk_nvidia_tegra_disable_rp_msi); 2870 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2871 PCI_CLASS_BRIDGE_PCI, 8, 2872 pci_quirk_nvidia_tegra_disable_rp_msi); 2873 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2874 PCI_CLASS_BRIDGE_PCI, 8, 2875 pci_quirk_nvidia_tegra_disable_rp_msi); 2876 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2877 PCI_CLASS_BRIDGE_PCI, 8, 2878 pci_quirk_nvidia_tegra_disable_rp_msi); 2879 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2880 PCI_CLASS_BRIDGE_PCI, 8, 2881 pci_quirk_nvidia_tegra_disable_rp_msi); 2882 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2883 PCI_CLASS_BRIDGE_PCI, 8, 2884 pci_quirk_nvidia_tegra_disable_rp_msi); 2885 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2886 PCI_CLASS_BRIDGE_PCI, 8, 2887 pci_quirk_nvidia_tegra_disable_rp_msi); 2888 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2889 PCI_CLASS_BRIDGE_PCI, 8, 2890 pci_quirk_nvidia_tegra_disable_rp_msi); 2891 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2892 PCI_CLASS_BRIDGE_PCI, 8, 2893 pci_quirk_nvidia_tegra_disable_rp_msi); 2894 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2895 PCI_CLASS_BRIDGE_PCI, 8, 2896 pci_quirk_nvidia_tegra_disable_rp_msi); 2897 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2898 PCI_CLASS_BRIDGE_PCI, 8, 2899 pci_quirk_nvidia_tegra_disable_rp_msi); 2900 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2901 PCI_CLASS_BRIDGE_PCI, 8, 2902 pci_quirk_nvidia_tegra_disable_rp_msi); 2903 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2904 PCI_CLASS_BRIDGE_PCI, 8, 2905 pci_quirk_nvidia_tegra_disable_rp_msi); 2906 2907 /* 2908 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2909 * config register. This register controls the routing of legacy 2910 * interrupts from devices that route through the MCP55. If this register 2911 * is misprogrammed, interrupts are only sent to the BSP, unlike 2912 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2913 * having this register set properly prevents kdump from booting up 2914 * properly, so let's make sure that we have it set correctly. 2915 * Note that this is an undocumented register. 2916 */ 2917 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2918 { 2919 u32 cfg; 2920 2921 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2922 return; 2923 2924 pci_read_config_dword(dev, 0x74, &cfg); 2925 2926 if (cfg & ((1 << 2) | (1 << 15))) { 2927 pr_info("Rewriting IRQ routing register on MCP55\n"); 2928 cfg &= ~((1 << 2) | (1 << 15)); 2929 pci_write_config_dword(dev, 0x74, cfg); 2930 } 2931 } 2932 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2933 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2934 nvbridge_check_legacy_irq_routing); 2935 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2936 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2937 nvbridge_check_legacy_irq_routing); 2938 2939 static int ht_check_msi_mapping(struct pci_dev *dev) 2940 { 2941 int pos, ttl = PCI_FIND_CAP_TTL; 2942 int found = 0; 2943 2944 /* Check if there is HT MSI cap or enabled on this device */ 2945 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2946 while (pos && ttl--) { 2947 u8 flags; 2948 2949 if (found < 1) 2950 found = 1; 2951 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2952 &flags) == 0) { 2953 if (flags & HT_MSI_FLAGS_ENABLE) { 2954 if (found < 2) { 2955 found = 2; 2956 break; 2957 } 2958 } 2959 } 2960 pos = pci_find_next_ht_capability(dev, pos, 2961 HT_CAPTYPE_MSI_MAPPING); 2962 } 2963 2964 return found; 2965 } 2966 2967 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2968 { 2969 struct pci_dev *dev; 2970 int pos; 2971 int i, dev_no; 2972 int found = 0; 2973 2974 dev_no = host_bridge->devfn >> 3; 2975 for (i = dev_no + 1; i < 0x20; i++) { 2976 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2977 if (!dev) 2978 continue; 2979 2980 /* found next host bridge? */ 2981 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2982 if (pos != 0) { 2983 pci_dev_put(dev); 2984 break; 2985 } 2986 2987 if (ht_check_msi_mapping(dev)) { 2988 found = 1; 2989 pci_dev_put(dev); 2990 break; 2991 } 2992 pci_dev_put(dev); 2993 } 2994 2995 return found; 2996 } 2997 2998 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2999 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 3000 3001 static int is_end_of_ht_chain(struct pci_dev *dev) 3002 { 3003 int pos, ctrl_off; 3004 int end = 0; 3005 u16 flags, ctrl; 3006 3007 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3008 3009 if (!pos) 3010 goto out; 3011 3012 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 3013 3014 ctrl_off = ((flags >> 10) & 1) ? 3015 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 3016 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 3017 3018 if (ctrl & (1 << 6)) 3019 end = 1; 3020 3021 out: 3022 return end; 3023 } 3024 3025 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3026 { 3027 struct pci_dev *host_bridge; 3028 int pos; 3029 int i, dev_no; 3030 int found = 0; 3031 3032 dev_no = dev->devfn >> 3; 3033 for (i = dev_no; i >= 0; i--) { 3034 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3035 if (!host_bridge) 3036 continue; 3037 3038 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3039 if (pos != 0) { 3040 found = 1; 3041 break; 3042 } 3043 pci_dev_put(host_bridge); 3044 } 3045 3046 if (!found) 3047 return; 3048 3049 /* don't enable end_device/host_bridge with leaf directly here */ 3050 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3051 host_bridge_with_leaf(host_bridge)) 3052 goto out; 3053 3054 /* root did that ! */ 3055 if (msi_ht_cap_enabled(host_bridge)) 3056 goto out; 3057 3058 ht_enable_msi_mapping(dev); 3059 3060 out: 3061 pci_dev_put(host_bridge); 3062 } 3063 3064 static void ht_disable_msi_mapping(struct pci_dev *dev) 3065 { 3066 int pos, ttl = PCI_FIND_CAP_TTL; 3067 3068 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3069 while (pos && ttl--) { 3070 u8 flags; 3071 3072 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3073 &flags) == 0) { 3074 pci_info(dev, "Disabling HT MSI Mapping\n"); 3075 3076 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3077 flags & ~HT_MSI_FLAGS_ENABLE); 3078 } 3079 pos = pci_find_next_ht_capability(dev, pos, 3080 HT_CAPTYPE_MSI_MAPPING); 3081 } 3082 } 3083 3084 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3085 { 3086 struct pci_dev *host_bridge; 3087 int pos; 3088 int found; 3089 3090 if (!pci_msi_enabled()) 3091 return; 3092 3093 /* check if there is HT MSI cap or enabled on this device */ 3094 found = ht_check_msi_mapping(dev); 3095 3096 /* no HT MSI CAP */ 3097 if (found == 0) 3098 return; 3099 3100 /* 3101 * HT MSI mapping should be disabled on devices that are below 3102 * a non-HyperTransport host bridge. Locate the host bridge. 3103 */ 3104 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3105 PCI_DEVFN(0, 0)); 3106 if (host_bridge == NULL) { 3107 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3108 return; 3109 } 3110 3111 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3112 if (pos != 0) { 3113 /* Host bridge is to HT */ 3114 if (found == 1) { 3115 /* it is not enabled, try to enable it */ 3116 if (all) 3117 ht_enable_msi_mapping(dev); 3118 else 3119 nv_ht_enable_msi_mapping(dev); 3120 } 3121 goto out; 3122 } 3123 3124 /* HT MSI is not enabled */ 3125 if (found == 1) 3126 goto out; 3127 3128 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3129 ht_disable_msi_mapping(dev); 3130 3131 out: 3132 pci_dev_put(host_bridge); 3133 } 3134 3135 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3136 { 3137 return __nv_msi_ht_cap_quirk(dev, 1); 3138 } 3139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3140 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3141 3142 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3143 { 3144 return __nv_msi_ht_cap_quirk(dev, 0); 3145 } 3146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3147 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3148 3149 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3150 { 3151 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3152 } 3153 3154 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3155 { 3156 struct pci_dev *p; 3157 3158 /* 3159 * SB700 MSI issue will be fixed at HW level from revision A21; 3160 * we need check PCI REVISION ID of SMBus controller to get SB700 3161 * revision. 3162 */ 3163 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3164 NULL); 3165 if (!p) 3166 return; 3167 3168 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3169 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3170 pci_dev_put(p); 3171 } 3172 3173 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3174 { 3175 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3176 if (dev->revision < 0x18) { 3177 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3178 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3179 } 3180 } 3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3182 PCI_DEVICE_ID_TIGON3_5780, 3183 quirk_msi_intx_disable_bug); 3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3185 PCI_DEVICE_ID_TIGON3_5780S, 3186 quirk_msi_intx_disable_bug); 3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3188 PCI_DEVICE_ID_TIGON3_5714, 3189 quirk_msi_intx_disable_bug); 3190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3191 PCI_DEVICE_ID_TIGON3_5714S, 3192 quirk_msi_intx_disable_bug); 3193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3194 PCI_DEVICE_ID_TIGON3_5715, 3195 quirk_msi_intx_disable_bug); 3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3197 PCI_DEVICE_ID_TIGON3_5715S, 3198 quirk_msi_intx_disable_bug); 3199 3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3201 quirk_msi_intx_disable_ati_bug); 3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3203 quirk_msi_intx_disable_ati_bug); 3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3205 quirk_msi_intx_disable_ati_bug); 3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3207 quirk_msi_intx_disable_ati_bug); 3208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3209 quirk_msi_intx_disable_ati_bug); 3210 3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3212 quirk_msi_intx_disable_bug); 3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3214 quirk_msi_intx_disable_bug); 3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3216 quirk_msi_intx_disable_bug); 3217 3218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3219 quirk_msi_intx_disable_bug); 3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3221 quirk_msi_intx_disable_bug); 3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3223 quirk_msi_intx_disable_bug); 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3225 quirk_msi_intx_disable_bug); 3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3227 quirk_msi_intx_disable_bug); 3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3229 quirk_msi_intx_disable_bug); 3230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3231 quirk_msi_intx_disable_qca_bug); 3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3233 quirk_msi_intx_disable_qca_bug); 3234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3235 quirk_msi_intx_disable_qca_bug); 3236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3237 quirk_msi_intx_disable_qca_bug); 3238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3239 quirk_msi_intx_disable_qca_bug); 3240 3241 /* 3242 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3243 * should be disabled on platforms where the device (mistakenly) advertises it. 3244 * 3245 * Notice that this quirk also disables MSI (which may work, but hasn't been 3246 * tested), since currently there is no standard way to disable only MSI-X. 3247 * 3248 * The 0031 device id is reused for other non Root Port device types, 3249 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3250 */ 3251 static void quirk_al_msi_disable(struct pci_dev *dev) 3252 { 3253 dev->no_msi = 1; 3254 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3255 } 3256 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3257 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3258 #endif /* CONFIG_PCI_MSI */ 3259 3260 /* 3261 * Allow manual resource allocation for PCI hotplug bridges via 3262 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3263 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3264 * allocate resources when hotplug device is inserted and PCI bus is 3265 * rescanned. 3266 */ 3267 static void quirk_hotplug_bridge(struct pci_dev *dev) 3268 { 3269 dev->is_hotplug_bridge = 1; 3270 } 3271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3272 3273 /* 3274 * This is a quirk for the Ricoh MMC controller found as a part of some 3275 * multifunction chips. 3276 * 3277 * This is very similar and based on the ricoh_mmc driver written by 3278 * Philip Langdale. Thank you for these magic sequences. 3279 * 3280 * These chips implement the four main memory card controllers (SD, MMC, 3281 * MS, xD) and one or both of CardBus or FireWire. 3282 * 3283 * It happens that they implement SD and MMC support as separate 3284 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3285 * cards but the chip detects MMC cards in hardware and directs them to the 3286 * MMC controller - so the SDHCI driver never sees them. 3287 * 3288 * To get around this, we must disable the useless MMC controller. At that 3289 * point, the SDHCI controller will start seeing them. It seems to be the 3290 * case that the relevant PCI registers to deactivate the MMC controller 3291 * live on PCI function 0, which might be the CardBus controller or the 3292 * FireWire controller, depending on the particular chip in question 3293 * 3294 * This has to be done early, because as soon as we disable the MMC controller 3295 * other PCI functions shift up one level, e.g. function #2 becomes function 3296 * #1, and this will confuse the PCI core. 3297 */ 3298 #ifdef CONFIG_MMC_RICOH_MMC 3299 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3300 { 3301 u8 write_enable; 3302 u8 write_target; 3303 u8 disable; 3304 3305 /* 3306 * Disable via CardBus interface 3307 * 3308 * This must be done via function #0 3309 */ 3310 if (PCI_FUNC(dev->devfn)) 3311 return; 3312 3313 pci_read_config_byte(dev, 0xB7, &disable); 3314 if (disable & 0x02) 3315 return; 3316 3317 pci_read_config_byte(dev, 0x8E, &write_enable); 3318 pci_write_config_byte(dev, 0x8E, 0xAA); 3319 pci_read_config_byte(dev, 0x8D, &write_target); 3320 pci_write_config_byte(dev, 0x8D, 0xB7); 3321 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3322 pci_write_config_byte(dev, 0x8E, write_enable); 3323 pci_write_config_byte(dev, 0x8D, write_target); 3324 3325 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3326 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3327 } 3328 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3329 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3330 3331 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3332 { 3333 u8 write_enable; 3334 u8 disable; 3335 3336 /* 3337 * Disable via FireWire interface 3338 * 3339 * This must be done via function #0 3340 */ 3341 if (PCI_FUNC(dev->devfn)) 3342 return; 3343 /* 3344 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3345 * certain types of SD/MMC cards. Lowering the SD base clock 3346 * frequency from 200Mhz to 50Mhz fixes this issue. 3347 * 3348 * 0x150 - SD2.0 mode enable for changing base clock 3349 * frequency to 50Mhz 3350 * 0xe1 - Base clock frequency 3351 * 0x32 - 50Mhz new clock frequency 3352 * 0xf9 - Key register for 0x150 3353 * 0xfc - key register for 0xe1 3354 */ 3355 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3356 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3357 pci_write_config_byte(dev, 0xf9, 0xfc); 3358 pci_write_config_byte(dev, 0x150, 0x10); 3359 pci_write_config_byte(dev, 0xf9, 0x00); 3360 pci_write_config_byte(dev, 0xfc, 0x01); 3361 pci_write_config_byte(dev, 0xe1, 0x32); 3362 pci_write_config_byte(dev, 0xfc, 0x00); 3363 3364 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3365 } 3366 3367 pci_read_config_byte(dev, 0xCB, &disable); 3368 3369 if (disable & 0x02) 3370 return; 3371 3372 pci_read_config_byte(dev, 0xCA, &write_enable); 3373 pci_write_config_byte(dev, 0xCA, 0x57); 3374 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3375 pci_write_config_byte(dev, 0xCA, write_enable); 3376 3377 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3378 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3379 3380 } 3381 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3382 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3383 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3384 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3385 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3386 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3387 #endif /*CONFIG_MMC_RICOH_MMC*/ 3388 3389 #ifdef CONFIG_DMAR_TABLE 3390 #define VTUNCERRMSK_REG 0x1ac 3391 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3392 /* 3393 * This is a quirk for masking VT-d spec-defined errors to platform error 3394 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3395 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3396 * on the RAS config settings of the platform) when a VT-d fault happens. 3397 * The resulting SMI caused the system to hang. 3398 * 3399 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3400 * need to report the same error through other channels. 3401 */ 3402 static void vtd_mask_spec_errors(struct pci_dev *dev) 3403 { 3404 u32 word; 3405 3406 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3407 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3408 } 3409 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3410 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3411 #endif 3412 3413 static void fixup_ti816x_class(struct pci_dev *dev) 3414 { 3415 u32 class = dev->class; 3416 3417 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3418 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3419 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3420 class, dev->class); 3421 } 3422 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3423 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3424 3425 /* 3426 * Some PCIe devices do not work reliably with the claimed maximum 3427 * payload size supported. 3428 */ 3429 static void fixup_mpss_256(struct pci_dev *dev) 3430 { 3431 dev->pcie_mpss = 1; /* 256 bytes */ 3432 } 3433 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3434 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3435 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3436 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3437 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3438 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3439 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3440 3441 /* 3442 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3443 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3444 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3445 * until all of the devices are discovered and buses walked, read completion 3446 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3447 * it is possible to hotplug a device with MPS of 256B. 3448 */ 3449 static void quirk_intel_mc_errata(struct pci_dev *dev) 3450 { 3451 int err; 3452 u16 rcc; 3453 3454 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3455 pcie_bus_config == PCIE_BUS_DEFAULT) 3456 return; 3457 3458 /* 3459 * Intel erratum specifies bits to change but does not say what 3460 * they are. Keeping them magical until such time as the registers 3461 * and values can be explained. 3462 */ 3463 err = pci_read_config_word(dev, 0x48, &rcc); 3464 if (err) { 3465 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3466 return; 3467 } 3468 3469 if (!(rcc & (1 << 10))) 3470 return; 3471 3472 rcc &= ~(1 << 10); 3473 3474 err = pci_write_config_word(dev, 0x48, rcc); 3475 if (err) { 3476 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3477 return; 3478 } 3479 3480 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3481 } 3482 /* Intel 5000 series memory controllers and ports 2-7 */ 3483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3497 /* Intel 5100 series memory controllers and ports 2-7 */ 3498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3509 3510 /* 3511 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3512 * To work around this, query the size it should be configured to by the 3513 * device and modify the resource end to correspond to this new size. 3514 */ 3515 static void quirk_intel_ntb(struct pci_dev *dev) 3516 { 3517 int rc; 3518 u8 val; 3519 3520 rc = pci_read_config_byte(dev, 0x00D0, &val); 3521 if (rc) 3522 return; 3523 3524 resource_set_size(&dev->resource[2], (resource_size_t)1 << val); 3525 3526 rc = pci_read_config_byte(dev, 0x00D1, &val); 3527 if (rc) 3528 return; 3529 3530 resource_set_size(&dev->resource[4], (resource_size_t)1 << val); 3531 } 3532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3534 3535 /* 3536 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3537 * though no one is handling them (e.g., if the i915 driver is never 3538 * loaded). Additionally the interrupt destination is not set up properly 3539 * and the interrupt ends up -somewhere-. 3540 * 3541 * These spurious interrupts are "sticky" and the kernel disables the 3542 * (shared) interrupt line after 100,000+ generated interrupts. 3543 * 3544 * Fix it by disabling the still enabled interrupts. This resolves crashes 3545 * often seen on monitor unplug. 3546 */ 3547 #define I915_DEIER_REG 0x4400c 3548 static void disable_igfx_irq(struct pci_dev *dev) 3549 { 3550 void __iomem *regs = pci_iomap(dev, 0, 0); 3551 if (regs == NULL) { 3552 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3553 return; 3554 } 3555 3556 /* Check if any interrupt line is still enabled */ 3557 if (readl(regs + I915_DEIER_REG) != 0) { 3558 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3559 3560 writel(0, regs + I915_DEIER_REG); 3561 } 3562 3563 pci_iounmap(dev, regs); 3564 } 3565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3572 3573 /* 3574 * PCI devices which are on Intel chips can skip the 10ms delay 3575 * before entering D3 mode. 3576 */ 3577 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3578 { 3579 dev->d3hot_delay = 0; 3580 } 3581 /* C600 Series devices do not need 10ms d3hot_delay */ 3582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3585 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3597 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3607 3608 /* 3609 * Some devices may pass our check in pci_intx_mask_supported() if 3610 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3611 * support this feature. 3612 */ 3613 static void quirk_broken_intx_masking(struct pci_dev *dev) 3614 { 3615 dev->broken_intx_masking = 1; 3616 } 3617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3618 quirk_broken_intx_masking); 3619 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3620 quirk_broken_intx_masking); 3621 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3622 quirk_broken_intx_masking); 3623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, 3624 quirk_broken_intx_masking); 3625 3626 /* 3627 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3628 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3629 * 3630 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3631 */ 3632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3633 quirk_broken_intx_masking); 3634 3635 /* 3636 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3637 * DisINTx can be set but the interrupt status bit is non-functional. 3638 */ 3639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3655 3656 static u16 mellanox_broken_intx_devs[] = { 3657 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3658 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3659 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3660 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3661 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3662 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3663 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3664 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3665 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3666 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3667 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3668 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3669 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3670 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3671 }; 3672 3673 #define CONNECTX_4_CURR_MAX_MINOR 99 3674 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3675 3676 /* 3677 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3678 * If so, don't mark it as broken. 3679 * FW minor > 99 means older FW version format and no INTx masking support. 3680 * FW minor < 14 means new FW version format and no INTx masking support. 3681 */ 3682 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3683 { 3684 __be32 __iomem *fw_ver; 3685 u16 fw_major; 3686 u16 fw_minor; 3687 u16 fw_subminor; 3688 u32 fw_maj_min; 3689 u32 fw_sub_min; 3690 int i; 3691 3692 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3693 if (pdev->device == mellanox_broken_intx_devs[i]) { 3694 pdev->broken_intx_masking = 1; 3695 return; 3696 } 3697 } 3698 3699 /* 3700 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3701 * support so shouldn't be checked further 3702 */ 3703 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3704 return; 3705 3706 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3707 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3708 return; 3709 3710 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3711 if (pci_enable_device_mem(pdev)) { 3712 pci_warn(pdev, "Can't enable device memory\n"); 3713 return; 3714 } 3715 3716 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3717 if (!fw_ver) { 3718 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3719 goto out; 3720 } 3721 3722 /* Reading from resource space should be 32b aligned */ 3723 fw_maj_min = ioread32be(fw_ver); 3724 fw_sub_min = ioread32be(fw_ver + 1); 3725 fw_major = fw_maj_min & 0xffff; 3726 fw_minor = fw_maj_min >> 16; 3727 fw_subminor = fw_sub_min & 0xffff; 3728 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3729 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3730 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3731 fw_major, fw_minor, fw_subminor, pdev->device == 3732 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3733 pdev->broken_intx_masking = 1; 3734 } 3735 3736 iounmap(fw_ver); 3737 3738 out: 3739 pci_disable_device(pdev); 3740 } 3741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3742 mellanox_check_broken_intx_masking); 3743 3744 static void quirk_no_bus_reset(struct pci_dev *dev) 3745 { 3746 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3747 } 3748 3749 /* 3750 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3751 * prevented for those affected devices. 3752 */ 3753 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3754 { 3755 if ((dev->device & 0xffc0) == 0x2340) 3756 quirk_no_bus_reset(dev); 3757 } 3758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3759 quirk_nvidia_no_bus_reset); 3760 3761 /* 3762 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3763 * The device will throw a Link Down error on AER-capable systems and 3764 * regardless of AER, config space of the device is never accessible again 3765 * and typically causes the system to hang or reset when access is attempted. 3766 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3767 */ 3768 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3769 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3770 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3771 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3772 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3773 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3774 3775 /* 3776 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3777 * reset when used with certain child devices. After the reset, config 3778 * accesses to the child may fail. 3779 */ 3780 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3781 3782 /* 3783 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3784 * automatically disables LTSSM when Secondary Bus Reset is received and 3785 * the device stops working. Prevent bus reset for these devices. With 3786 * this change, the device can be assigned to VMs with VFIO, but it will 3787 * leak state between VMs. Reference 3788 * https://e2e.ti.com/support/processors/f/791/t/954382 3789 */ 3790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3791 3792 static void quirk_no_pm_reset(struct pci_dev *dev) 3793 { 3794 /* 3795 * We can't do a bus reset on root bus devices, but an ineffective 3796 * PM reset may be better than nothing. 3797 */ 3798 if (!pci_is_root_bus(dev->bus)) 3799 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3800 } 3801 3802 /* 3803 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3804 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3805 * to have no effect on the device: it retains the framebuffer contents and 3806 * monitor sync. Advertising this support makes other layers, like VFIO, 3807 * assume pci_reset_function() is viable for this device. Mark it as 3808 * unavailable to skip it when testing reset methods. 3809 */ 3810 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3811 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3812 3813 /* 3814 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3815 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3816 * any effect on the device: It continues to be operational and network ports 3817 * remain up. Advertising this support makes it seem as if a PM reset is viable 3818 * for these devices. Mark it as unavailable to skip it when testing reset 3819 * methods. 3820 */ 3821 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3822 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3824 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3825 3826 /* 3827 * Thunderbolt controllers with broken MSI hotplug signaling: 3828 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3829 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3830 */ 3831 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3832 { 3833 if (pdev->is_hotplug_bridge && 3834 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3835 pdev->revision <= 1)) 3836 pdev->no_msi = 1; 3837 } 3838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3839 quirk_thunderbolt_hotplug_msi); 3840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3841 quirk_thunderbolt_hotplug_msi); 3842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3843 quirk_thunderbolt_hotplug_msi); 3844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3845 quirk_thunderbolt_hotplug_msi); 3846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3847 quirk_thunderbolt_hotplug_msi); 3848 3849 #ifdef CONFIG_ACPI 3850 /* 3851 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3852 * 3853 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3854 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3855 * be present after resume if a device was plugged in before suspend. 3856 * 3857 * The Thunderbolt controller consists of a PCIe switch with downstream 3858 * bridges leading to the NHI and to the tunnel PCI bridges. 3859 * 3860 * This quirk cuts power to the whole chip. Therefore we have to apply it 3861 * during suspend_noirq of the upstream bridge. 3862 * 3863 * Power is automagically restored before resume. No action is needed. 3864 */ 3865 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3866 { 3867 acpi_handle bridge, SXIO, SXFP, SXLV; 3868 3869 if (!x86_apple_machine) 3870 return; 3871 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3872 return; 3873 3874 /* 3875 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3876 * We don't know how to turn it back on again, but firmware does, 3877 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3878 * firmware. 3879 */ 3880 if (!pm_suspend_via_firmware()) 3881 return; 3882 3883 bridge = ACPI_HANDLE(&dev->dev); 3884 if (!bridge) 3885 return; 3886 3887 /* 3888 * SXIO and SXLV are present only on machines requiring this quirk. 3889 * Thunderbolt bridges in external devices might have the same 3890 * device ID as those on the host, but they will not have the 3891 * associated ACPI methods. This implicitly checks that we are at 3892 * the right bridge. 3893 */ 3894 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3895 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3896 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3897 return; 3898 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3899 3900 /* magic sequence */ 3901 acpi_execute_simple_method(SXIO, NULL, 1); 3902 acpi_execute_simple_method(SXFP, NULL, 0); 3903 msleep(300); 3904 acpi_execute_simple_method(SXLV, NULL, 0); 3905 acpi_execute_simple_method(SXIO, NULL, 0); 3906 acpi_execute_simple_method(SXLV, NULL, 0); 3907 } 3908 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3909 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3910 quirk_apple_poweroff_thunderbolt); 3911 #endif 3912 3913 /* 3914 * Following are device-specific reset methods which can be used to 3915 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3916 * not available. 3917 */ 3918 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3919 { 3920 /* 3921 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3922 * 3923 * The 82599 supports FLR on VFs, but FLR support is reported only 3924 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3925 * Thus we must call pcie_flr() directly without first checking if it is 3926 * supported. 3927 */ 3928 if (!probe) 3929 pcie_flr(dev); 3930 return 0; 3931 } 3932 3933 #define SOUTH_CHICKEN2 0xc2004 3934 #define PCH_PP_STATUS 0xc7200 3935 #define PCH_PP_CONTROL 0xc7204 3936 #define MSG_CTL 0x45010 3937 #define NSDE_PWR_STATE 0xd0100 3938 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3939 3940 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3941 { 3942 void __iomem *mmio_base; 3943 unsigned long timeout; 3944 u32 val; 3945 3946 if (probe) 3947 return 0; 3948 3949 mmio_base = pci_iomap(dev, 0, 0); 3950 if (!mmio_base) 3951 return -ENOMEM; 3952 3953 iowrite32(0x00000002, mmio_base + MSG_CTL); 3954 3955 /* 3956 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3957 * driver loaded sets the right bits. However, this's a reset and 3958 * the bits have been set by i915 previously, so we clobber 3959 * SOUTH_CHICKEN2 register directly here. 3960 */ 3961 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3962 3963 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3964 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3965 3966 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3967 do { 3968 val = ioread32(mmio_base + PCH_PP_STATUS); 3969 if ((val & 0xb0000000) == 0) 3970 goto reset_complete; 3971 msleep(10); 3972 } while (time_before(jiffies, timeout)); 3973 pci_warn(dev, "timeout during reset\n"); 3974 3975 reset_complete: 3976 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3977 3978 pci_iounmap(dev, mmio_base); 3979 return 0; 3980 } 3981 3982 /* Device-specific reset method for Chelsio T4-based adapters */ 3983 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 3984 { 3985 u16 old_command; 3986 u16 msix_flags; 3987 3988 /* 3989 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3990 * that we have no device-specific reset method. 3991 */ 3992 if ((dev->device & 0xf000) != 0x4000) 3993 return -ENOTTY; 3994 3995 /* 3996 * If this is the "probe" phase, return 0 indicating that we can 3997 * reset this device. 3998 */ 3999 if (probe) 4000 return 0; 4001 4002 /* 4003 * T4 can wedge if there are DMAs in flight within the chip and Bus 4004 * Master has been disabled. We need to have it on till the Function 4005 * Level Reset completes. (BUS_MASTER is disabled in 4006 * pci_reset_function()). 4007 */ 4008 pci_read_config_word(dev, PCI_COMMAND, &old_command); 4009 pci_write_config_word(dev, PCI_COMMAND, 4010 old_command | PCI_COMMAND_MASTER); 4011 4012 /* 4013 * Perform the actual device function reset, saving and restoring 4014 * configuration information around the reset. 4015 */ 4016 pci_save_state(dev); 4017 4018 /* 4019 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 4020 * are disabled when an MSI-X interrupt message needs to be delivered. 4021 * So we briefly re-enable MSI-X interrupts for the duration of the 4022 * FLR. The pci_restore_state() below will restore the original 4023 * MSI-X state. 4024 */ 4025 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 4026 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 4027 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 4028 msix_flags | 4029 PCI_MSIX_FLAGS_ENABLE | 4030 PCI_MSIX_FLAGS_MASKALL); 4031 4032 pcie_flr(dev); 4033 4034 /* 4035 * Restore the configuration information (BAR values, etc.) including 4036 * the original PCI Configuration Space Command word, and return 4037 * success. 4038 */ 4039 pci_restore_state(dev); 4040 pci_write_config_word(dev, PCI_COMMAND, old_command); 4041 return 0; 4042 } 4043 4044 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4045 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4046 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4047 4048 /* 4049 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4050 * FLR where config space reads from the device return -1. We seem to be 4051 * able to avoid this condition if we disable the NVMe controller prior to 4052 * FLR. This quirk is generic for any NVMe class device requiring similar 4053 * assistance to quiesce the device prior to FLR. 4054 * 4055 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4056 * Revision 1.0e: 4057 * Chapter 2: Required and optional PCI config registers 4058 * Chapter 3: NVMe control registers 4059 * Chapter 7.3: Reset behavior 4060 */ 4061 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4062 { 4063 void __iomem *bar; 4064 u16 cmd; 4065 u32 cfg; 4066 4067 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4068 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4069 return -ENOTTY; 4070 4071 if (probe) 4072 return 0; 4073 4074 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4075 if (!bar) 4076 return -ENOTTY; 4077 4078 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4079 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4080 4081 cfg = readl(bar + NVME_REG_CC); 4082 4083 /* Disable controller if enabled */ 4084 if (cfg & NVME_CC_ENABLE) { 4085 u32 cap = readl(bar + NVME_REG_CAP); 4086 unsigned long timeout; 4087 4088 /* 4089 * Per nvme_disable_ctrl() skip shutdown notification as it 4090 * could complete commands to the admin queue. We only intend 4091 * to quiesce the device before reset. 4092 */ 4093 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4094 4095 writel(cfg, bar + NVME_REG_CC); 4096 4097 /* 4098 * Some controllers require an additional delay here, see 4099 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4100 * supported by this quirk. 4101 */ 4102 4103 /* Cap register provides max timeout in 500ms increments */ 4104 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4105 4106 for (;;) { 4107 u32 status = readl(bar + NVME_REG_CSTS); 4108 4109 /* Ready status becomes zero on disable complete */ 4110 if (!(status & NVME_CSTS_RDY)) 4111 break; 4112 4113 msleep(100); 4114 4115 if (time_after(jiffies, timeout)) { 4116 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4117 break; 4118 } 4119 } 4120 } 4121 4122 pci_iounmap(dev, bar); 4123 4124 pcie_flr(dev); 4125 4126 return 0; 4127 } 4128 4129 /* 4130 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4131 * timeout waiting for ready status to change after NVMe enable if the driver 4132 * starts interacting with the device too soon after FLR. A 250ms delay after 4133 * FLR has heuristically proven to produce reliably working results for device 4134 * assignment cases. 4135 */ 4136 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4137 { 4138 if (probe) 4139 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4140 4141 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4142 4143 msleep(250); 4144 4145 return 0; 4146 } 4147 4148 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4149 #define HINIC_VF_FLR_TYPE 0x1000 4150 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4151 #define HINIC_VF_OP 0xE80 4152 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4153 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4154 4155 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4156 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4157 { 4158 unsigned long timeout; 4159 void __iomem *bar; 4160 u32 val; 4161 4162 if (probe) 4163 return 0; 4164 4165 bar = pci_iomap(pdev, 0, 0); 4166 if (!bar) 4167 return -ENOTTY; 4168 4169 /* Get and check firmware capabilities */ 4170 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4171 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4172 pci_iounmap(pdev, bar); 4173 return -ENOTTY; 4174 } 4175 4176 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4177 val = ioread32be(bar + HINIC_VF_OP); 4178 val = val | HINIC_VF_FLR_PROC_BIT; 4179 iowrite32be(val, bar + HINIC_VF_OP); 4180 4181 pcie_flr(pdev); 4182 4183 /* 4184 * The device must recapture its Bus and Device Numbers after FLR 4185 * in order generate Completions. Issue a config write to let the 4186 * device capture this information. 4187 */ 4188 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4189 4190 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4191 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4192 do { 4193 val = ioread32be(bar + HINIC_VF_OP); 4194 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4195 goto reset_complete; 4196 msleep(20); 4197 } while (time_before(jiffies, timeout)); 4198 4199 val = ioread32be(bar + HINIC_VF_OP); 4200 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4201 goto reset_complete; 4202 4203 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4204 4205 reset_complete: 4206 pci_iounmap(pdev, bar); 4207 4208 return 0; 4209 } 4210 4211 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4212 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4213 reset_intel_82599_sfp_virtfn }, 4214 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4215 reset_ivb_igd }, 4216 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4217 reset_ivb_igd }, 4218 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4219 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4220 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4221 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4222 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4223 reset_chelsio_generic_dev }, 4224 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4225 reset_hinic_vf_dev }, 4226 { 0 } 4227 }; 4228 4229 /* 4230 * These device-specific reset methods are here rather than in a driver 4231 * because when a host assigns a device to a guest VM, the host may need 4232 * to reset the device but probably doesn't have a driver for it. 4233 */ 4234 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4235 { 4236 const struct pci_dev_reset_methods *i; 4237 4238 for (i = pci_dev_reset_methods; i->reset; i++) { 4239 if ((i->vendor == dev->vendor || 4240 i->vendor == (u16)PCI_ANY_ID) && 4241 (i->device == dev->device || 4242 i->device == (u16)PCI_ANY_ID)) 4243 return i->reset(dev, probe); 4244 } 4245 4246 return -ENOTTY; 4247 } 4248 4249 static void quirk_dma_func0_alias(struct pci_dev *dev) 4250 { 4251 if (PCI_FUNC(dev->devfn) != 0) 4252 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4253 } 4254 4255 /* 4256 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4257 * 4258 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4259 */ 4260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4262 4263 /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ 4264 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); 4265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); 4266 4267 static void quirk_dma_func1_alias(struct pci_dev *dev) 4268 { 4269 if (PCI_FUNC(dev->devfn) != 1) 4270 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4271 } 4272 4273 /* 4274 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4275 * SKUs function 1 is present and is a legacy IDE controller, in other 4276 * SKUs this function is not present, making this a ghost requester. 4277 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4278 */ 4279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4280 quirk_dma_func1_alias); 4281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4282 quirk_dma_func1_alias); 4283 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4285 quirk_dma_func1_alias); 4286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4287 quirk_dma_func1_alias); 4288 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4290 quirk_dma_func1_alias); 4291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4292 quirk_dma_func1_alias); 4293 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4295 quirk_dma_func1_alias); 4296 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4297 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4298 quirk_dma_func1_alias); 4299 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4301 quirk_dma_func1_alias); 4302 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4304 quirk_dma_func1_alias); 4305 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4307 quirk_dma_func1_alias); 4308 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4310 quirk_dma_func1_alias); 4311 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4313 quirk_dma_func1_alias); 4314 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4316 quirk_dma_func1_alias); 4317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4318 quirk_dma_func1_alias); 4319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4320 quirk_dma_func1_alias); 4321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4322 quirk_dma_func1_alias); 4323 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4325 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4326 quirk_dma_func1_alias); 4327 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4328 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4329 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4330 quirk_dma_func1_alias); 4331 4332 /* 4333 * Some devices DMA with the wrong devfn, not just the wrong function. 4334 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4335 * the alias is "fixed" and independent of the device devfn. 4336 * 4337 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4338 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4339 * single device on the secondary bus. In reality, the single exposed 4340 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4341 * that provides a bridge to the internal bus of the I/O processor. The 4342 * controller supports private devices, which can be hidden from PCI config 4343 * space. In the case of the Adaptec 3405, a private device at 01.0 4344 * appears to be the DMA engine, which therefore needs to become a DMA 4345 * alias for the device. 4346 */ 4347 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4348 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4349 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4350 .driver_data = PCI_DEVFN(1, 0) }, 4351 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4352 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4353 .driver_data = PCI_DEVFN(1, 0) }, 4354 { 0 } 4355 }; 4356 4357 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4358 { 4359 const struct pci_device_id *id; 4360 4361 id = pci_match_id(fixed_dma_alias_tbl, dev); 4362 if (id) 4363 pci_add_dma_alias(dev, id->driver_data, 1); 4364 } 4365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4366 4367 /* 4368 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4369 * using the wrong DMA alias for the device. Some of these devices can be 4370 * used as either forward or reverse bridges, so we need to test whether the 4371 * device is operating in the correct mode. We could probably apply this 4372 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4373 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4374 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4375 */ 4376 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4377 { 4378 if (!pci_is_root_bus(pdev->bus) && 4379 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4380 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4381 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4382 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4383 } 4384 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4386 quirk_use_pcie_bridge_dma_alias); 4387 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4388 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4389 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4390 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4391 /* ITE 8893 has the same problem as the 8892 */ 4392 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4393 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4394 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4395 4396 /* 4397 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4398 * be added as aliases to the DMA device in order to allow buffer access 4399 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4400 * programmed in the EEPROM. 4401 */ 4402 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4403 { 4404 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4405 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4406 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4407 } 4408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4410 4411 /* 4412 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4413 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4414 * 4415 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4416 * when IOMMU is enabled. These aliases allow computational unit access to 4417 * host memory. These aliases mark the whole VCA device as one IOMMU 4418 * group. 4419 * 4420 * All possible slot numbers (0x20) are used, since we are unable to tell 4421 * what slot is used on other side. This quirk is intended for both host 4422 * and computational unit sides. The VCA devices have up to five functions 4423 * (four for DMA channels and one additional). 4424 */ 4425 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4426 { 4427 const unsigned int num_pci_slots = 0x20; 4428 unsigned int slot; 4429 4430 for (slot = 0; slot < num_pci_slots; slot++) 4431 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4432 } 4433 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4435 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4439 4440 /* 4441 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4442 * associated not at the root bus, but at a bridge below. This quirk avoids 4443 * generating invalid DMA aliases. 4444 */ 4445 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4446 { 4447 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4448 } 4449 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4450 quirk_bridge_cavm_thrx2_pcie_root); 4451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4452 quirk_bridge_cavm_thrx2_pcie_root); 4453 4454 /* 4455 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4456 * class code. Fix it. 4457 */ 4458 static void quirk_tw686x_class(struct pci_dev *pdev) 4459 { 4460 u32 class = pdev->class; 4461 4462 /* Use "Multimedia controller" class */ 4463 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4464 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4465 class, pdev->class); 4466 } 4467 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4468 quirk_tw686x_class); 4469 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4470 quirk_tw686x_class); 4471 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4472 quirk_tw686x_class); 4473 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4474 quirk_tw686x_class); 4475 4476 /* 4477 * Some devices have problems with Transaction Layer Packets with the Relaxed 4478 * Ordering Attribute set. Such devices should mark themselves and other 4479 * device drivers should check before sending TLPs with RO set. 4480 */ 4481 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4482 { 4483 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4484 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4485 } 4486 4487 /* 4488 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4489 * Complex have a Flow Control Credit issue which can cause performance 4490 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4491 */ 4492 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4493 quirk_relaxedordering_disable); 4494 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4495 quirk_relaxedordering_disable); 4496 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4497 quirk_relaxedordering_disable); 4498 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4499 quirk_relaxedordering_disable); 4500 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4501 quirk_relaxedordering_disable); 4502 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4503 quirk_relaxedordering_disable); 4504 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4505 quirk_relaxedordering_disable); 4506 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4507 quirk_relaxedordering_disable); 4508 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4509 quirk_relaxedordering_disable); 4510 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4511 quirk_relaxedordering_disable); 4512 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4513 quirk_relaxedordering_disable); 4514 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4515 quirk_relaxedordering_disable); 4516 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4517 quirk_relaxedordering_disable); 4518 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4519 quirk_relaxedordering_disable); 4520 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4521 quirk_relaxedordering_disable); 4522 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4523 quirk_relaxedordering_disable); 4524 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4525 quirk_relaxedordering_disable); 4526 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4527 quirk_relaxedordering_disable); 4528 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4529 quirk_relaxedordering_disable); 4530 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4531 quirk_relaxedordering_disable); 4532 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4533 quirk_relaxedordering_disable); 4534 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4535 quirk_relaxedordering_disable); 4536 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4537 quirk_relaxedordering_disable); 4538 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4539 quirk_relaxedordering_disable); 4540 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4541 quirk_relaxedordering_disable); 4542 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4543 quirk_relaxedordering_disable); 4544 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4545 quirk_relaxedordering_disable); 4546 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4547 quirk_relaxedordering_disable); 4548 4549 /* 4550 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4551 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4552 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4553 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4554 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4555 * November 10, 2010). As a result, on this platform we can't use Relaxed 4556 * Ordering for Upstream TLPs. 4557 */ 4558 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4559 quirk_relaxedordering_disable); 4560 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4561 quirk_relaxedordering_disable); 4562 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4563 quirk_relaxedordering_disable); 4564 4565 /* 4566 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4567 * values for the Attribute as were supplied in the header of the 4568 * corresponding Request, except as explicitly allowed when IDO is used." 4569 * 4570 * If a non-compliant device generates a completion with a different 4571 * attribute than the request, the receiver may accept it (which itself 4572 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4573 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4574 * device access timeout. 4575 * 4576 * If the non-compliant device generates completions with zero attributes 4577 * (instead of copying the attributes from the request), we can work around 4578 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4579 * upstream devices so they always generate requests with zero attributes. 4580 * 4581 * This affects other devices under the same Root Port, but since these 4582 * attributes are performance hints, there should be no functional problem. 4583 * 4584 * Note that Configuration Space accesses are never supposed to have TLP 4585 * Attributes, so we're safe waiting till after any Configuration Space 4586 * accesses to do the Root Port fixup. 4587 */ 4588 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4589 { 4590 struct pci_dev *root_port = pcie_find_root_port(pdev); 4591 4592 if (!root_port) { 4593 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4594 return; 4595 } 4596 4597 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4598 dev_name(&pdev->dev)); 4599 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL, 4600 PCI_EXP_DEVCTL_RELAX_EN | 4601 PCI_EXP_DEVCTL_NOSNOOP_EN); 4602 } 4603 4604 /* 4605 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4606 * Completion it generates. 4607 */ 4608 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4609 { 4610 /* 4611 * This mask/compare operation selects for Physical Function 4 on a 4612 * T5. We only need to fix up the Root Port once for any of the 4613 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4614 * 0x54xx so we use that one. 4615 */ 4616 if ((pdev->device & 0xff00) == 0x5400) 4617 quirk_disable_root_port_attributes(pdev); 4618 } 4619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4620 quirk_chelsio_T5_disable_root_port_attributes); 4621 4622 /* 4623 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4624 * by a device 4625 * @acs_ctrl_req: Bitmask of desired ACS controls 4626 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4627 * the hardware design 4628 * 4629 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4630 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4631 * caller desires. Return 0 otherwise. 4632 */ 4633 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4634 { 4635 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4636 return 1; 4637 return 0; 4638 } 4639 4640 /* 4641 * AMD has indicated that the devices below do not support peer-to-peer 4642 * in any system where they are found in the southbridge with an AMD 4643 * IOMMU in the system. Multifunction devices that do not support 4644 * peer-to-peer between functions can claim to support a subset of ACS. 4645 * Such devices effectively enable request redirect (RR) and completion 4646 * redirect (CR) since all transactions are redirected to the upstream 4647 * root complex. 4648 * 4649 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4650 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4651 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4652 * 4653 * 1002:4385 SBx00 SMBus Controller 4654 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4655 * 1002:4383 SBx00 Azalia (Intel HDA) 4656 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4657 * 1002:4384 SBx00 PCI to PCI Bridge 4658 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4659 * 4660 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4661 * 4662 * 1022:780f [AMD] FCH PCI Bridge 4663 * 1022:7809 [AMD] FCH USB OHCI Controller 4664 */ 4665 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4666 { 4667 #ifdef CONFIG_ACPI 4668 struct acpi_table_header *header = NULL; 4669 acpi_status status; 4670 4671 /* Targeting multifunction devices on the SB (appears on root bus) */ 4672 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4673 return -ENODEV; 4674 4675 /* The IVRS table describes the AMD IOMMU */ 4676 status = acpi_get_table("IVRS", 0, &header); 4677 if (ACPI_FAILURE(status)) 4678 return -ENODEV; 4679 4680 acpi_put_table(header); 4681 4682 /* Filter out flags not applicable to multifunction */ 4683 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4684 4685 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4686 #else 4687 return -ENODEV; 4688 #endif 4689 } 4690 4691 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4692 { 4693 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4694 return false; 4695 4696 switch (dev->device) { 4697 /* 4698 * Effectively selects all downstream ports for whole ThunderX1 4699 * (which represents 8 SoCs). 4700 */ 4701 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4702 case 0xaf84: /* ThunderX2 */ 4703 case 0xb884: /* ThunderX3 */ 4704 return true; 4705 default: 4706 return false; 4707 } 4708 } 4709 4710 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4711 { 4712 if (!pci_quirk_cavium_acs_match(dev)) 4713 return -ENOTTY; 4714 4715 /* 4716 * Cavium Root Ports don't advertise an ACS capability. However, 4717 * the RTL internally implements similar protection as if ACS had 4718 * Source Validation, Request Redirection, Completion Redirection, 4719 * and Upstream Forwarding features enabled. Assert that the 4720 * hardware implements and enables equivalent ACS functionality for 4721 * these flags. 4722 */ 4723 return pci_acs_ctrl_enabled(acs_flags, 4724 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4725 } 4726 4727 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4728 { 4729 /* 4730 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4731 * transactions with others, allowing masking out these bits as if they 4732 * were unimplemented in the ACS capability. 4733 */ 4734 return pci_acs_ctrl_enabled(acs_flags, 4735 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4736 } 4737 4738 /* 4739 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4740 * But the implementation could block peer-to-peer transactions between them 4741 * and provide ACS-like functionality. 4742 */ 4743 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4744 { 4745 if (!pci_is_pcie(dev) || 4746 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4747 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4748 return -ENOTTY; 4749 4750 /* 4751 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4752 * implement ACS capability in accordance with the PCIe Spec. 4753 */ 4754 switch (dev->device) { 4755 case 0x0710 ... 0x071e: 4756 case 0x0721: 4757 case 0x0723 ... 0x0752: 4758 return pci_acs_ctrl_enabled(acs_flags, 4759 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4760 } 4761 4762 return false; 4763 } 4764 4765 /* 4766 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4767 * transactions and validate bus numbers in requests, but do not provide an 4768 * actual PCIe ACS capability. This is the list of device IDs known to fall 4769 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4770 */ 4771 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4772 /* Ibexpeak PCH */ 4773 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4774 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4775 /* Cougarpoint PCH */ 4776 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4777 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4778 /* Pantherpoint PCH */ 4779 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4780 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4781 /* Lynxpoint-H PCH */ 4782 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4783 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4784 /* Lynxpoint-LP PCH */ 4785 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4786 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4787 /* Wildcat PCH */ 4788 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4789 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4790 /* Patsburg (X79) PCH */ 4791 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4792 /* Wellsburg (X99) PCH */ 4793 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4794 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4795 /* Lynx Point (9 series) PCH */ 4796 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4797 }; 4798 4799 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4800 { 4801 int i; 4802 4803 /* Filter out a few obvious non-matches first */ 4804 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4805 return false; 4806 4807 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4808 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4809 return true; 4810 4811 return false; 4812 } 4813 4814 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4815 { 4816 if (!pci_quirk_intel_pch_acs_match(dev)) 4817 return -ENOTTY; 4818 4819 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4820 return pci_acs_ctrl_enabled(acs_flags, 4821 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4822 4823 return pci_acs_ctrl_enabled(acs_flags, 0); 4824 } 4825 4826 /* 4827 * These QCOM Root Ports do provide ACS-like features to disable peer 4828 * transactions and validate bus numbers in requests, but do not provide an 4829 * actual PCIe ACS capability. Hardware supports source validation but it 4830 * will report the issue as Completer Abort instead of ACS Violation. 4831 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4832 * Complex with unique segment numbers. It is not possible for one Root 4833 * Port to pass traffic to another Root Port. All PCIe transactions are 4834 * terminated inside the Root Port. 4835 */ 4836 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4837 { 4838 return pci_acs_ctrl_enabled(acs_flags, 4839 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4840 } 4841 4842 /* 4843 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4844 * number and does provide isolation features to disable peer transactions 4845 * and validate bus numbers in requests, but does not provide an ACS 4846 * capability. 4847 */ 4848 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4849 { 4850 return pci_acs_ctrl_enabled(acs_flags, 4851 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4852 } 4853 4854 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4855 { 4856 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4857 return -ENOTTY; 4858 4859 /* 4860 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4861 * but do include ACS-like functionality. The hardware doesn't support 4862 * peer-to-peer transactions via the root port and each has a unique 4863 * segment number. 4864 * 4865 * Additionally, the root ports cannot send traffic to each other. 4866 */ 4867 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4868 4869 return acs_flags ? 0 : 1; 4870 } 4871 4872 /* 4873 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4874 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4875 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4876 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4877 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4878 * control register is at offset 8 instead of 6 and we should probably use 4879 * dword accesses to them. This applies to the following PCI Device IDs, as 4880 * found in volume 1 of the datasheet[2]: 4881 * 4882 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4883 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4884 * 4885 * N.B. This doesn't fix what lspci shows. 4886 * 4887 * The 100 series chipset specification update includes this as errata #23[3]. 4888 * 4889 * The 200 series chipset (Union Point) has the same bug according to the 4890 * specification update (Intel 200 Series Chipset Family Platform Controller 4891 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4892 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4893 * chipset include: 4894 * 4895 * 0xa290-0xa29f PCI Express Root port #{0-16} 4896 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4897 * 4898 * Mobile chipsets are also affected, 7th & 8th Generation 4899 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4900 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4901 * Processor Family I/O for U Quad Core Platforms Specification Update, 4902 * August 2017, Revision 002, Document#: 334660-002)[6] 4903 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4904 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4905 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4906 * 4907 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4908 * 4909 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4910 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4911 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4912 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4913 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4914 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4915 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4916 */ 4917 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4918 { 4919 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4920 return false; 4921 4922 switch (dev->device) { 4923 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4924 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4925 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4926 return true; 4927 } 4928 4929 return false; 4930 } 4931 4932 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4933 4934 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4935 { 4936 int pos; 4937 u32 cap, ctrl; 4938 4939 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4940 return -ENOTTY; 4941 4942 pos = dev->acs_cap; 4943 if (!pos) 4944 return -ENOTTY; 4945 4946 /* see pci_acs_flags_enabled() */ 4947 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4948 acs_flags &= (cap | PCI_ACS_EC); 4949 4950 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4951 4952 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4953 } 4954 4955 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4956 { 4957 /* 4958 * SV, TB, and UF are not relevant to multifunction endpoints. 4959 * 4960 * Multifunction devices are only required to implement RR, CR, and DT 4961 * in their ACS capability if they support peer-to-peer transactions. 4962 * Devices matching this quirk have been verified by the vendor to not 4963 * perform peer-to-peer with other functions, allowing us to mask out 4964 * these bits as if they were unimplemented in the ACS capability. 4965 */ 4966 return pci_acs_ctrl_enabled(acs_flags, 4967 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4968 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4969 } 4970 4971 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 4972 { 4973 /* 4974 * Intel RCiEP's are required to allow p2p only on translated 4975 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 4976 * "Root-Complex Peer to Peer Considerations". 4977 */ 4978 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 4979 return -ENOTTY; 4980 4981 return pci_acs_ctrl_enabled(acs_flags, 4982 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4983 } 4984 4985 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 4986 { 4987 /* 4988 * iProc PAXB Root Ports don't advertise an ACS capability, but 4989 * they do not allow peer-to-peer transactions between Root Ports. 4990 * Allow each Root Port to be in a separate IOMMU group by masking 4991 * SV/RR/CR/UF bits. 4992 */ 4993 return pci_acs_ctrl_enabled(acs_flags, 4994 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4995 } 4996 4997 /* 4998 * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on 4999 * multi-function devices, the hardware isolates the functions by 5000 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and 5001 * PCI_ACS_CR were set. 5002 * SFxxx 1G NICs(em). 5003 * RP1000/RP2000 10G NICs(sp). 5004 * FF5xxx 40G/25G/10G NICs(aml). 5005 */ 5006 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 5007 { 5008 switch (dev->device) { 5009 case 0x0100 ... 0x010F: /* EM */ 5010 case 0x1001: case 0x2001: /* SP */ 5011 case 0x5010: case 0x5025: case 0x5040: /* AML */ 5012 case 0x5110: case 0x5125: case 0x5140: /* AML */ 5013 return pci_acs_ctrl_enabled(acs_flags, 5014 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5015 } 5016 5017 return false; 5018 } 5019 5020 static const struct pci_dev_acs_enabled { 5021 u16 vendor; 5022 u16 device; 5023 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 5024 } pci_dev_acs_enabled[] = { 5025 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 5026 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 5027 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 5028 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 5029 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 5030 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 5031 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 5032 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 5033 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 5034 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 5035 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 5036 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 5037 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 5038 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 5039 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 5040 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 5041 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 5042 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 5043 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 5044 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 5045 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 5046 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 5047 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5048 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5049 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5050 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5051 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5052 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5053 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5054 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5055 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5056 /* 82580 */ 5057 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5058 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5059 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5060 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5061 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5062 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5063 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5064 /* 82576 */ 5065 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5066 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5067 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5068 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5069 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5070 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5071 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5072 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5073 /* 82575 */ 5074 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5075 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5076 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5077 /* I350 */ 5078 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5079 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5080 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5081 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5082 /* 82571 (Quads omitted due to non-ACS switch) */ 5083 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5084 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5085 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5086 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5087 /* I219 */ 5088 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5089 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5090 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5091 /* QCOM QDF2xxx root ports */ 5092 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5093 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5094 /* QCOM SA8775P root port */ 5095 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5096 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5097 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5098 /* Intel PCH root ports */ 5099 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5100 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5101 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5102 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5103 /* Cavium ThunderX */ 5104 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5105 /* Cavium multi-function devices */ 5106 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5107 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5108 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5109 /* APM X-Gene */ 5110 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5111 /* Ampere Computing */ 5112 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5113 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5114 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5115 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5116 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5117 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5118 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5119 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5120 /* Broadcom multi-function device */ 5121 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5122 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5123 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5124 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5125 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs }, 5126 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs }, 5127 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs }, 5128 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs }, 5129 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5130 /* Amazon Annapurna Labs */ 5131 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5132 /* Zhaoxin multi-function devices */ 5133 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5134 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5135 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5136 /* NXP root ports, xx=16, 12, or 08 cores */ 5137 /* LX2xx0A : without security features + CAN-FD */ 5138 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5139 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5140 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5141 /* LX2xx0C : security features + CAN-FD */ 5142 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5143 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5144 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5145 /* LX2xx0E : security features + CAN */ 5146 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5147 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5148 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5149 /* LX2xx0N : without security features + CAN */ 5150 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5151 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5152 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5153 /* LX2xx2A : without security features + CAN-FD */ 5154 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5155 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5156 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5157 /* LX2xx2C : security features + CAN-FD */ 5158 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5159 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5160 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5161 /* LX2xx2E : security features + CAN */ 5162 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5163 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5164 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5165 /* LX2xx2N : without security features + CAN */ 5166 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5167 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5168 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5169 /* Zhaoxin Root/Downstream Ports */ 5170 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5171 /* Wangxun nics */ 5172 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5173 { 0 } 5174 }; 5175 5176 /* 5177 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5178 * @dev: PCI device 5179 * @acs_flags: Bitmask of desired ACS controls 5180 * 5181 * Returns: 5182 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5183 * device provides the desired controls 5184 * 0: Device does not provide all the desired controls 5185 * >0: Device provides all the controls in @acs_flags 5186 */ 5187 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5188 { 5189 const struct pci_dev_acs_enabled *i; 5190 int ret; 5191 5192 /* 5193 * Allow devices that do not expose standard PCIe ACS capabilities 5194 * or control to indicate their support here. Multi-function express 5195 * devices which do not allow internal peer-to-peer between functions, 5196 * but do not implement PCIe ACS may wish to return true here. 5197 */ 5198 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5199 if ((i->vendor == dev->vendor || 5200 i->vendor == (u16)PCI_ANY_ID) && 5201 (i->device == dev->device || 5202 i->device == (u16)PCI_ANY_ID)) { 5203 ret = i->acs_enabled(dev, acs_flags); 5204 if (ret >= 0) 5205 return ret; 5206 } 5207 } 5208 5209 return -ENOTTY; 5210 } 5211 5212 /* Config space offset of Root Complex Base Address register */ 5213 #define INTEL_LPC_RCBA_REG 0xf0 5214 /* 31:14 RCBA address */ 5215 #define INTEL_LPC_RCBA_MASK 0xffffc000 5216 /* RCBA Enable */ 5217 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5218 5219 /* Backbone Scratch Pad Register */ 5220 #define INTEL_BSPR_REG 0x1104 5221 /* Backbone Peer Non-Posted Disable */ 5222 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5223 /* Backbone Peer Posted Disable */ 5224 #define INTEL_BSPR_REG_BPPD (1 << 9) 5225 5226 /* Upstream Peer Decode Configuration Register */ 5227 #define INTEL_UPDCR_REG 0x1014 5228 /* 5:0 Peer Decode Enable bits */ 5229 #define INTEL_UPDCR_REG_MASK 0x3f 5230 5231 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5232 { 5233 u32 rcba, bspr, updcr; 5234 void __iomem *rcba_mem; 5235 5236 /* 5237 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5238 * are D28:F* and therefore get probed before LPC, thus we can't 5239 * use pci_get_slot()/pci_read_config_dword() here. 5240 */ 5241 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5242 INTEL_LPC_RCBA_REG, &rcba); 5243 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5244 return -EINVAL; 5245 5246 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5247 PAGE_ALIGN(INTEL_UPDCR_REG)); 5248 if (!rcba_mem) 5249 return -ENOMEM; 5250 5251 /* 5252 * The BSPR can disallow peer cycles, but it's set by soft strap and 5253 * therefore read-only. If both posted and non-posted peer cycles are 5254 * disallowed, we're ok. If either are allowed, then we need to use 5255 * the UPDCR to disable peer decodes for each port. This provides the 5256 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5257 */ 5258 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5259 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5260 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5261 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5262 if (updcr & INTEL_UPDCR_REG_MASK) { 5263 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5264 updcr &= ~INTEL_UPDCR_REG_MASK; 5265 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5266 } 5267 } 5268 5269 iounmap(rcba_mem); 5270 return 0; 5271 } 5272 5273 /* Miscellaneous Port Configuration register */ 5274 #define INTEL_MPC_REG 0xd8 5275 /* MPC: Invalid Receive Bus Number Check Enable */ 5276 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5277 5278 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5279 { 5280 u32 mpc; 5281 5282 /* 5283 * When enabled, the IRBNCE bit of the MPC register enables the 5284 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5285 * ensures that requester IDs fall within the bus number range 5286 * of the bridge. Enable if not already. 5287 */ 5288 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5289 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5290 pci_info(dev, "Enabling MPC IRBNCE\n"); 5291 mpc |= INTEL_MPC_REG_IRBNCE; 5292 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5293 } 5294 } 5295 5296 /* 5297 * Currently this quirk does the equivalent of 5298 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5299 * 5300 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5301 * if dev->external_facing || dev->untrusted 5302 */ 5303 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5304 { 5305 if (!pci_quirk_intel_pch_acs_match(dev)) 5306 return -ENOTTY; 5307 5308 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5309 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5310 return 0; 5311 } 5312 5313 pci_quirk_enable_intel_rp_mpc_acs(dev); 5314 5315 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5316 5317 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5318 5319 return 0; 5320 } 5321 5322 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5323 { 5324 int pos; 5325 u32 cap, ctrl; 5326 5327 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5328 return -ENOTTY; 5329 5330 pos = dev->acs_cap; 5331 if (!pos) 5332 return -ENOTTY; 5333 5334 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5335 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5336 5337 ctrl |= (cap & PCI_ACS_SV); 5338 ctrl |= (cap & PCI_ACS_RR); 5339 ctrl |= (cap & PCI_ACS_CR); 5340 ctrl |= (cap & PCI_ACS_UF); 5341 5342 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5343 ctrl |= (cap & PCI_ACS_TB); 5344 5345 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5346 5347 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5348 5349 return 0; 5350 } 5351 5352 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5353 { 5354 int pos; 5355 u32 cap, ctrl; 5356 5357 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5358 return -ENOTTY; 5359 5360 pos = dev->acs_cap; 5361 if (!pos) 5362 return -ENOTTY; 5363 5364 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5365 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5366 5367 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5368 5369 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5370 5371 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5372 5373 return 0; 5374 } 5375 5376 static const struct pci_dev_acs_ops { 5377 u16 vendor; 5378 u16 device; 5379 int (*enable_acs)(struct pci_dev *dev); 5380 int (*disable_acs_redir)(struct pci_dev *dev); 5381 } pci_dev_acs_ops[] = { 5382 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5383 .enable_acs = pci_quirk_enable_intel_pch_acs, 5384 }, 5385 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5386 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5387 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5388 }, 5389 }; 5390 5391 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5392 { 5393 const struct pci_dev_acs_ops *p; 5394 int i, ret; 5395 5396 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5397 p = &pci_dev_acs_ops[i]; 5398 if ((p->vendor == dev->vendor || 5399 p->vendor == (u16)PCI_ANY_ID) && 5400 (p->device == dev->device || 5401 p->device == (u16)PCI_ANY_ID) && 5402 p->enable_acs) { 5403 ret = p->enable_acs(dev); 5404 if (ret >= 0) 5405 return ret; 5406 } 5407 } 5408 5409 return -ENOTTY; 5410 } 5411 5412 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5413 { 5414 const struct pci_dev_acs_ops *p; 5415 int i, ret; 5416 5417 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5418 p = &pci_dev_acs_ops[i]; 5419 if ((p->vendor == dev->vendor || 5420 p->vendor == (u16)PCI_ANY_ID) && 5421 (p->device == dev->device || 5422 p->device == (u16)PCI_ANY_ID) && 5423 p->disable_acs_redir) { 5424 ret = p->disable_acs_redir(dev); 5425 if (ret >= 0) 5426 return ret; 5427 } 5428 } 5429 5430 return -ENOTTY; 5431 } 5432 5433 /* 5434 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5435 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5436 * Next Capability pointer in the MSI Capability Structure should point to 5437 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5438 * the list. 5439 */ 5440 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5441 { 5442 int pos, i = 0, ret; 5443 u8 next_cap; 5444 u16 reg16, *cap; 5445 struct pci_cap_saved_state *state; 5446 5447 /* Bail if the hardware bug is fixed */ 5448 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5449 return; 5450 5451 /* Bail if MSI Capability Structure is not found for some reason */ 5452 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5453 if (!pos) 5454 return; 5455 5456 /* 5457 * Bail if Next Capability pointer in the MSI Capability Structure 5458 * is not the expected incorrect 0x00. 5459 */ 5460 pci_read_config_byte(pdev, pos + 1, &next_cap); 5461 if (next_cap) 5462 return; 5463 5464 /* 5465 * PCIe Capability Structure is expected to be at 0x50 and should 5466 * terminate the list (Next Capability pointer is 0x00). Verify 5467 * Capability Id and Next Capability pointer is as expected. 5468 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5469 * to correctly set kernel data structures which have already been 5470 * set incorrectly due to the hardware bug. 5471 */ 5472 pos = 0x50; 5473 pci_read_config_word(pdev, pos, ®16); 5474 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5475 u32 status; 5476 #ifndef PCI_EXP_SAVE_REGS 5477 #define PCI_EXP_SAVE_REGS 7 5478 #endif 5479 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5480 5481 pdev->pcie_cap = pos; 5482 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5483 pdev->pcie_flags_reg = reg16; 5484 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5485 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5486 5487 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5488 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5489 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5490 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5491 5492 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5493 return; 5494 5495 /* Save PCIe cap */ 5496 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5497 if (!state) 5498 return; 5499 5500 state->cap.cap_nr = PCI_CAP_ID_EXP; 5501 state->cap.cap_extended = 0; 5502 state->cap.size = size; 5503 cap = (u16 *)&state->cap.data[0]; 5504 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5505 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5506 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5507 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5508 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5509 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5510 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5511 hlist_add_head(&state->next, &pdev->saved_cap_space); 5512 } 5513 } 5514 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5515 5516 /* 5517 * FLR may cause the following to devices to hang: 5518 * 5519 * AMD Starship/Matisse HD Audio Controller 0x1487 5520 * AMD Starship USB 3.0 Host Controller 0x148c 5521 * AMD Matisse USB 3.0 Host Controller 0x149c 5522 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5523 * Intel 82579V Gigabit Ethernet Controller 0x1503 5524 * 5525 */ 5526 static void quirk_no_flr(struct pci_dev *dev) 5527 { 5528 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5529 } 5530 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5531 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5532 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5533 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5534 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5535 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5536 5537 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5538 static void quirk_no_flr_snet(struct pci_dev *dev) 5539 { 5540 if (dev->revision == 0x1) 5541 quirk_no_flr(dev); 5542 } 5543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5544 5545 static void quirk_no_ext_tags(struct pci_dev *pdev) 5546 { 5547 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5548 5549 if (!bridge) 5550 return; 5551 5552 bridge->no_ext_tags = 1; 5553 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5554 5555 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5556 } 5557 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); 5558 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5562 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5563 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5565 5566 #ifdef CONFIG_PCI_ATS 5567 static void quirk_no_ats(struct pci_dev *pdev) 5568 { 5569 pci_info(pdev, "disabling ATS\n"); 5570 pdev->ats_cap = 0; 5571 } 5572 5573 /* 5574 * Some devices require additional driver setup to enable ATS. Don't use 5575 * ATS for those devices as ATS will be enabled before the driver has had a 5576 * chance to load and configure the device. 5577 */ 5578 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5579 { 5580 if (pdev->device == 0x15d8) { 5581 if (pdev->revision == 0xcf && 5582 pdev->subsystem_vendor == 0xea50 && 5583 (pdev->subsystem_device == 0xce19 || 5584 pdev->subsystem_device == 0xcc10 || 5585 pdev->subsystem_device == 0xcc08)) 5586 quirk_no_ats(pdev); 5587 } else { 5588 quirk_no_ats(pdev); 5589 } 5590 } 5591 5592 /* AMD Stoney platform GPU */ 5593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5594 /* AMD Iceland dGPU */ 5595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5596 /* AMD Navi10 dGPU */ 5597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5605 /* AMD Navi14 dGPU */ 5606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5610 /* AMD Raven platform iGPU */ 5611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5612 5613 /* 5614 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5615 * in ATS Invalidate Request message body. Disable ATS for those devices. 5616 */ 5617 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5618 { 5619 if (pdev->revision < 0x20) 5620 quirk_no_ats(pdev); 5621 } 5622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5631 #endif /* CONFIG_PCI_ATS */ 5632 5633 /* Freescale PCIe doesn't support MSI in RC mode */ 5634 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5635 { 5636 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5637 pdev->no_msi = 1; 5638 } 5639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5640 5641 /* 5642 * Although not allowed by the spec, some multi-function devices have 5643 * dependencies of one function (consumer) on another (supplier). For the 5644 * consumer to work in D0, the supplier must also be in D0. Create a 5645 * device link from the consumer to the supplier to enforce this 5646 * dependency. Runtime PM is allowed by default on the consumer to prevent 5647 * it from permanently keeping the supplier awake. 5648 */ 5649 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5650 unsigned int supplier, unsigned int class, 5651 unsigned int class_shift) 5652 { 5653 struct pci_dev *supplier_pdev; 5654 5655 if (PCI_FUNC(pdev->devfn) != consumer) 5656 return; 5657 5658 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5659 pdev->bus->number, 5660 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5661 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5662 pci_dev_put(supplier_pdev); 5663 return; 5664 } 5665 5666 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5667 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5668 pci_info(pdev, "D0 power state depends on %s\n", 5669 pci_name(supplier_pdev)); 5670 else 5671 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5672 pci_name(supplier_pdev)); 5673 5674 pm_runtime_allow(&pdev->dev); 5675 pci_dev_put(supplier_pdev); 5676 } 5677 5678 /* 5679 * Create device link for GPUs with integrated HDA controller for streaming 5680 * audio to attached displays. 5681 */ 5682 static void quirk_gpu_hda(struct pci_dev *hda) 5683 { 5684 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5685 } 5686 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5687 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5688 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5689 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5690 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5691 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5692 5693 /* 5694 * Create device link for GPUs with integrated USB xHCI Host 5695 * controller to VGA. 5696 */ 5697 static void quirk_gpu_usb(struct pci_dev *usb) 5698 { 5699 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5700 } 5701 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5702 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5703 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5704 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5705 5706 /* 5707 * Create device link for GPUs with integrated Type-C UCSI controller 5708 * to VGA. Currently there is no class code defined for UCSI device over PCI 5709 * so using UNKNOWN class for now and it will be updated when UCSI 5710 * over PCI gets a class code. 5711 */ 5712 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5713 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5714 { 5715 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5716 } 5717 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5718 PCI_CLASS_SERIAL_UNKNOWN, 8, 5719 quirk_gpu_usb_typec_ucsi); 5720 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5721 PCI_CLASS_SERIAL_UNKNOWN, 8, 5722 quirk_gpu_usb_typec_ucsi); 5723 5724 /* 5725 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5726 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5727 */ 5728 static void quirk_nvidia_hda(struct pci_dev *gpu) 5729 { 5730 u8 hdr_type; 5731 u32 val; 5732 5733 /* There was no integrated HDA controller before MCP89 */ 5734 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5735 return; 5736 5737 /* Bit 25 at offset 0x488 enables the HDA controller */ 5738 pci_read_config_dword(gpu, 0x488, &val); 5739 if (val & BIT(25)) 5740 return; 5741 5742 pci_info(gpu, "Enabling HDA controller\n"); 5743 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5744 5745 /* The GPU becomes a multi-function device when the HDA is enabled */ 5746 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5747 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 5748 } 5749 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5750 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5751 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5752 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5753 5754 /* 5755 * Some IDT switches incorrectly flag an ACS Source Validation error on 5756 * completions for config read requests even though PCIe r4.0, sec 5757 * 6.12.1.1, says that completions are never affected by ACS Source 5758 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5759 * 5760 * Item #36 - Downstream port applies ACS Source Validation to Completions 5761 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5762 * completions are never affected by ACS Source Validation. However, 5763 * completions received by a downstream port of the PCIe switch from a 5764 * device that has not yet captured a PCIe bus number are incorrectly 5765 * dropped by ACS Source Validation by the switch downstream port. 5766 * 5767 * The workaround suggested by IDT is to issue a config write to the 5768 * downstream device before issuing the first config read. This allows the 5769 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5770 * sec 2.2.9), thus avoiding the ACS error on the completion. 5771 * 5772 * However, we don't know when the device is ready to accept the config 5773 * write, so we do config reads until we receive a non-Config Request Retry 5774 * Status, then do the config write. 5775 * 5776 * To avoid hitting the erratum when doing the config reads, we disable ACS 5777 * SV around this process. 5778 */ 5779 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5780 { 5781 int pos; 5782 u16 ctrl = 0; 5783 bool found; 5784 struct pci_dev *bridge = bus->self; 5785 5786 pos = bridge->acs_cap; 5787 5788 /* Disable ACS SV before initial config reads */ 5789 if (pos) { 5790 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5791 if (ctrl & PCI_ACS_SV) 5792 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5793 ctrl & ~PCI_ACS_SV); 5794 } 5795 5796 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5797 5798 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5799 if (found) 5800 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5801 5802 /* Re-enable ACS_SV if it was previously enabled */ 5803 if (ctrl & PCI_ACS_SV) 5804 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5805 5806 return found; 5807 } 5808 5809 /* 5810 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5811 * NT endpoints via the internal switch fabric. These IDs replace the 5812 * originating Requester ID TLPs which access host memory on peer NTB 5813 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5814 * to permit access when the IOMMU is turned on. 5815 */ 5816 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5817 { 5818 void __iomem *mmio; 5819 struct ntb_info_regs __iomem *mmio_ntb; 5820 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5821 u64 partition_map; 5822 u8 partition; 5823 int pp; 5824 5825 if (pci_enable_device(pdev)) { 5826 pci_err(pdev, "Cannot enable Switchtec device\n"); 5827 return; 5828 } 5829 5830 mmio = pci_iomap(pdev, 0, 0); 5831 if (mmio == NULL) { 5832 pci_disable_device(pdev); 5833 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5834 return; 5835 } 5836 5837 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5838 5839 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5840 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5841 5842 partition = ioread8(&mmio_ntb->partition_id); 5843 5844 partition_map = ioread32(&mmio_ntb->ep_map); 5845 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5846 partition_map &= ~(1ULL << partition); 5847 5848 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5849 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5850 u32 table_sz = 0; 5851 int te; 5852 5853 if (!(partition_map & (1ULL << pp))) 5854 continue; 5855 5856 pci_dbg(pdev, "Processing partition %d\n", pp); 5857 5858 mmio_peer_ctrl = &mmio_ctrl[pp]; 5859 5860 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5861 if (!table_sz) { 5862 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5863 continue; 5864 } 5865 5866 if (table_sz > 512) { 5867 pci_warn(pdev, 5868 "Invalid Switchtec partition %d table_sz %d\n", 5869 pp, table_sz); 5870 continue; 5871 } 5872 5873 for (te = 0; te < table_sz; te++) { 5874 u32 rid_entry; 5875 u8 devfn; 5876 5877 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5878 devfn = (rid_entry >> 1) & 0xFF; 5879 pci_dbg(pdev, 5880 "Aliasing Partition %d Proxy ID %02x.%d\n", 5881 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5882 pci_add_dma_alias(pdev, devfn, 1); 5883 } 5884 } 5885 5886 pci_iounmap(pdev, mmio); 5887 pci_disable_device(pdev); 5888 } 5889 #define SWITCHTEC_QUIRK(vid) \ 5890 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5891 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5892 5893 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5894 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5895 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5896 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5897 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5898 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5899 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5900 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5901 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5902 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5903 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5904 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5905 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5906 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5907 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5908 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5909 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5910 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5911 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5912 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5913 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5914 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5915 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5916 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5917 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5918 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5919 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5920 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5921 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5922 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5923 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5924 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5925 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5926 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5927 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5928 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5929 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5930 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5931 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5932 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5933 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5934 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5935 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5936 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5937 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5938 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5939 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5940 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 5941 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 5942 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 5943 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 5944 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 5945 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 5946 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 5947 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 5948 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 5949 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 5950 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 5951 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 5952 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 5953 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 5954 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 5955 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 5956 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 5957 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 5958 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 5959 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 5960 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 5961 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 5962 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 5963 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 5964 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 5965 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 5966 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 5967 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 5968 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 5969 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 5970 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 5971 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 5972 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 5973 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 5974 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 5975 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 5976 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 5977 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 5978 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 5979 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 5980 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 5981 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 5982 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 5983 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 5984 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 5985 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 5986 5987 /* 5988 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 5989 * These IDs are used to forward responses to the originator on the other 5990 * side of the NTB. Alias all possible IDs to the NTB to permit access when 5991 * the IOMMU is turned on. 5992 */ 5993 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 5994 { 5995 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 5996 /* PLX NTB may use all 256 devfns */ 5997 pci_add_dma_alias(pdev, 0, 256); 5998 } 5999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 6000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 6001 6002 /* 6003 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 6004 * not always reset the secondary Nvidia GPU between reboots if the system 6005 * is configured to use Hybrid Graphics mode. This results in the GPU 6006 * being left in whatever state it was in during the *previous* boot, which 6007 * causes spurious interrupts from the GPU, which in turn causes us to 6008 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 6009 * this also completely breaks nouveau. 6010 * 6011 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 6012 * clean state and fixes all these issues. 6013 * 6014 * When the machine is configured in Dedicated display mode, the issue 6015 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 6016 * mode, so we can detect that and avoid resetting it. 6017 */ 6018 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 6019 { 6020 void __iomem *map; 6021 int ret; 6022 6023 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 6024 pdev->subsystem_device != 0x222e || 6025 !pci_reset_supported(pdev)) 6026 return; 6027 6028 if (pci_enable_device_mem(pdev)) 6029 return; 6030 6031 /* 6032 * Based on nvkm_device_ctor() in 6033 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 6034 */ 6035 map = pci_iomap(pdev, 0, 0x23000); 6036 if (!map) { 6037 pci_err(pdev, "Can't map MMIO space\n"); 6038 goto out_disable; 6039 } 6040 6041 /* 6042 * Make sure the GPU looks like it's been POSTed before resetting 6043 * it. 6044 */ 6045 if (ioread32(map + 0x2240c) & 0x2) { 6046 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 6047 ret = pci_reset_bus(pdev); 6048 if (ret < 0) 6049 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 6050 } 6051 6052 iounmap(map); 6053 out_disable: 6054 pci_disable_device(pdev); 6055 } 6056 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6057 PCI_CLASS_DISPLAY_VGA, 8, 6058 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6059 6060 /* 6061 * Device [1b21:2142] 6062 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6063 */ 6064 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6065 { 6066 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6067 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6068 } 6069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6070 6071 /* 6072 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6073 * 6074 * These devices advertise PME# support in all power states but don't 6075 * reliably assert it. 6076 * 6077 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6078 * says "The MSI Function is not implemented on this device" in chapters 6079 * 7.3.27, 7.3.29-7.3.31. 6080 */ 6081 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6082 { 6083 #ifdef CONFIG_PCI_MSI 6084 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6085 dev->no_msi = 1; 6086 #endif 6087 pci_info(dev, "PME# is unreliable, disabling it\n"); 6088 dev->pme_support = 0; 6089 } 6090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6092 6093 static void apex_pci_fixup_class(struct pci_dev *pdev) 6094 { 6095 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6096 } 6097 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6098 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6099 6100 /* 6101 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6102 * ACS P2P Request Redirect is not functional 6103 * 6104 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6105 * between upstream and downstream ports, packets are queued in an internal 6106 * buffer until CPLD packet. The workaround is to use the switch in store and 6107 * forward mode. 6108 */ 6109 #define PI7C9X2Gxxx_MODE_REG 0x74 6110 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6111 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6112 { 6113 struct pci_dev *upstream; 6114 u16 val; 6115 6116 /* Downstream ports only */ 6117 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6118 return; 6119 6120 /* Check for ACS P2P Request Redirect use */ 6121 if (!pdev->acs_cap) 6122 return; 6123 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6124 if (!(val & PCI_ACS_RR)) 6125 return; 6126 6127 upstream = pci_upstream_bridge(pdev); 6128 if (!upstream) 6129 return; 6130 6131 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6132 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6133 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6134 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6135 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6136 } 6137 } 6138 /* 6139 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6140 * ACS configuration changes or switch mode is reset 6141 */ 6142 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6143 pci_fixup_pericom_acs_store_forward); 6144 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6145 pci_fixup_pericom_acs_store_forward); 6146 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6147 pci_fixup_pericom_acs_store_forward); 6148 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6149 pci_fixup_pericom_acs_store_forward); 6150 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6151 pci_fixup_pericom_acs_store_forward); 6152 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6153 pci_fixup_pericom_acs_store_forward); 6154 6155 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6156 { 6157 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6158 } 6159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6160 6161 static void rom_bar_overlap_defect(struct pci_dev *dev) 6162 { 6163 pci_info(dev, "working around ROM BAR overlap defect\n"); 6164 dev->rom_bar_overlap = 1; 6165 } 6166 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6167 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6168 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6169 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6170 6171 #ifdef CONFIG_PCIEASPM 6172 /* 6173 * Several Intel DG2 graphics devices advertise that they can only tolerate 6174 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6175 * from being enabled. But in fact these devices can tolerate unlimited 6176 * latency. Override their Device Capabilities value to allow ASPM L1 to 6177 * be enabled. 6178 */ 6179 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6180 { 6181 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6182 6183 if (l1_lat < 7) { 6184 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6185 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6186 l1_lat); 6187 } 6188 } 6189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6191 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6192 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6193 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6194 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6195 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6196 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6201 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6204 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6215 #endif 6216 6217 #ifdef CONFIG_PCIE_DPC 6218 /* 6219 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6220 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6221 * Ports. 6222 */ 6223 static void dpc_log_size(struct pci_dev *dev) 6224 { 6225 u16 dpc, val; 6226 6227 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6228 if (!dpc) 6229 return; 6230 6231 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6232 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6233 return; 6234 6235 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6236 pci_info(dev, "Overriding RP PIO Log Size to 4\n"); 6237 dev->dpc_rp_log_size = 4; 6238 } 6239 } 6240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6249 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6251 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); 6257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); 6258 #endif 6259 6260 /* 6261 * For a PCI device with multiple downstream devices, its driver may use 6262 * a flattened device tree to describe the downstream devices. 6263 * To overlay the flattened device tree, the PCI device and all its ancestor 6264 * devices need to have device tree nodes on system base device tree. Thus, 6265 * before driver probing, it might need to add a device tree node as the final 6266 * fixup. 6267 */ 6268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); 6272 6273 /* 6274 * Devices known to require a longer delay before first config space access 6275 * after reset recovery or resume from D3cold: 6276 * 6277 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6278 */ 6279 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6280 { 6281 pdev->d3cold_delay = 1000; 6282 } 6283 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6284 6285 #ifdef CONFIG_PCIEAER 6286 static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) 6287 { 6288 struct pci_dev *parent = pci_upstream_bridge(pdev); 6289 u32 val; 6290 6291 if (!parent || !parent->aer_cap) 6292 return; 6293 6294 pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", 6295 pci_name(pdev)); 6296 6297 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); 6298 val |= PCI_ERR_COR_REP_TIMER; 6299 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); 6300 } 6301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); 6302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); 6303 #endif 6304