1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * The bridge optimization stuff has been removed. If you really 11 * have a silly BIOS which is unable to set your host bridge right, 12 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 13 */ 14 15 #include <linux/config.h> 16 #include <linux/types.h> 17 #include <linux/kernel.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/acpi.h> 22 #include "pci.h" 23 24 /* Deal with broken BIOS'es that neglect to enable passive release, 25 which can cause problems in combination with the 82441FX/PPro MTRRs */ 26 static void __devinit quirk_passive_release(struct pci_dev *dev) 27 { 28 struct pci_dev *d = NULL; 29 unsigned char dlc; 30 31 /* We have to make sure a particular bit is set in the PIIX3 32 ISA bridge, so we have to go out and find it. */ 33 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 34 pci_read_config_byte(d, 0x82, &dlc); 35 if (!(dlc & 1<<1)) { 36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 37 dlc |= 1<<1; 38 pci_write_config_byte(d, 0x82, dlc); 39 } 40 } 41 } 42 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 43 44 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 45 but VIA don't answer queries. If you happen to have good contacts at VIA 46 ask them for me please -- Alan 47 48 This appears to be BIOS not version dependent. So presumably there is a 49 chipset level fix */ 50 int isa_dma_bridge_buggy; /* Exported */ 51 52 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 53 { 54 if (!isa_dma_bridge_buggy) { 55 isa_dma_bridge_buggy=1; 56 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 57 } 58 } 59 /* 60 * Its not totally clear which chipsets are the problematic ones 61 * We know 82C586 and 82C596 variants are affected. 62 */ 63 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 70 71 int pci_pci_problems; 72 73 /* 74 * Chipsets where PCI->PCI transfers vanish or hang 75 */ 76 static void __devinit quirk_nopcipci(struct pci_dev *dev) 77 { 78 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 79 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 80 pci_pci_problems |= PCIPCI_FAIL; 81 } 82 } 83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 85 86 /* 87 * Triton requires workarounds to be used by the drivers 88 */ 89 static void __devinit quirk_triton(struct pci_dev *dev) 90 { 91 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 92 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 93 pci_pci_problems |= PCIPCI_TRITON; 94 } 95 } 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 100 101 /* 102 * VIA Apollo KT133 needs PCI latency patch 103 * Made according to a windows driver based patch by George E. Breese 104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 106 * the info on which Mr Breese based his work. 107 * 108 * Updated based on further information from the site and also on 109 * information provided by VIA 110 */ 111 static void __devinit quirk_vialatency(struct pci_dev *dev) 112 { 113 struct pci_dev *p; 114 u8 rev; 115 u8 busarb; 116 /* Ok we have a potential problem chipset here. Now see if we have 117 a buggy southbridge */ 118 119 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 120 if (p!=NULL) { 121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 123 /* Check for buggy part revisions */ 124 if (rev < 0x40 || rev > 0x42) 125 goto exit; 126 } else { 127 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 128 if (p==NULL) /* No problem parts */ 129 goto exit; 130 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 131 /* Check for buggy part revisions */ 132 if (rev < 0x10 || rev > 0x12) 133 goto exit; 134 } 135 136 /* 137 * Ok we have the problem. Now set the PCI master grant to 138 * occur every master grant. The apparent bug is that under high 139 * PCI load (quite common in Linux of course) you can get data 140 * loss when the CPU is held off the bus for 3 bus master requests 141 * This happens to include the IDE controllers.... 142 * 143 * VIA only apply this fix when an SB Live! is present but under 144 * both Linux and Windows this isnt enough, and we have seen 145 * corruption without SB Live! but with things like 3 UDMA IDE 146 * controllers. So we ignore that bit of the VIA recommendation.. 147 */ 148 149 pci_read_config_byte(dev, 0x76, &busarb); 150 /* Set bit 4 and bi 5 of byte 76 to 0x01 151 "Master priority rotation on every PCI master grant */ 152 busarb &= ~(1<<5); 153 busarb |= (1<<4); 154 pci_write_config_byte(dev, 0x76, busarb); 155 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 156 exit: 157 pci_dev_put(p); 158 } 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 162 163 /* 164 * VIA Apollo VP3 needs ETBF on BT848/878 165 */ 166 static void __devinit quirk_viaetbf(struct pci_dev *dev) 167 { 168 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 169 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 170 pci_pci_problems |= PCIPCI_VIAETBF; 171 } 172 } 173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 174 175 static void __devinit quirk_vsfx(struct pci_dev *dev) 176 { 177 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 178 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 179 pci_pci_problems |= PCIPCI_VSFX; 180 } 181 } 182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 183 184 /* 185 * Ali Magik requires workarounds to be used by the drivers 186 * that DMA to AGP space. Latency must be set to 0xA and triton 187 * workaround applied too 188 * [Info kindly provided by ALi] 189 */ 190 static void __init quirk_alimagik(struct pci_dev *dev) 191 { 192 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 193 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 194 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 195 } 196 } 197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 199 200 /* 201 * Natoma has some interesting boundary conditions with Zoran stuff 202 * at least 203 */ 204 static void __devinit quirk_natoma(struct pci_dev *dev) 205 { 206 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 208 pci_pci_problems |= PCIPCI_NATOMA; 209 } 210 } 211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 217 218 /* 219 * This chip can cause PCI parity errors if config register 0xA0 is read 220 * while DMAs are occurring. 221 */ 222 static void __devinit quirk_citrine(struct pci_dev *dev) 223 { 224 dev->cfg_size = 0xA0; 225 } 226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 227 228 /* 229 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 230 * If it's needed, re-allocate the region. 231 */ 232 static void __devinit quirk_s3_64M(struct pci_dev *dev) 233 { 234 struct resource *r = &dev->resource[0]; 235 236 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 237 r->start = 0; 238 r->end = 0x3ffffff; 239 } 240 } 241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 243 244 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr) 245 { 246 region &= ~(size-1); 247 if (region) { 248 struct pci_bus_region bus_region; 249 struct resource *res = dev->resource + nr; 250 251 res->name = pci_name(dev); 252 res->start = region; 253 res->end = region + size - 1; 254 res->flags = IORESOURCE_IO; 255 256 /* Convert from PCI bus to resource space. */ 257 bus_region.start = res->start; 258 bus_region.end = res->end; 259 pcibios_bus_to_resource(dev, res, &bus_region); 260 261 pci_claim_resource(dev, nr); 262 } 263 } 264 265 /* 266 * ATI Northbridge setups MCE the processor if you even 267 * read somewhere between 0x3b0->0x3bb or read 0x3d3 268 */ 269 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 270 { 271 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 272 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 273 request_region(0x3b0, 0x0C, "RadeonIGP"); 274 request_region(0x3d3, 0x01, "RadeonIGP"); 275 } 276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 277 278 /* 279 * Let's make the southbridge information explicit instead 280 * of having to worry about people probing the ACPI areas, 281 * for example.. (Yes, it happens, and if you read the wrong 282 * ACPI register it will put the machine to sleep with no 283 * way of waking it up again. Bummer). 284 * 285 * ALI M7101: Two IO regions pointed to by words at 286 * 0xE0 (64 bytes of ACPI registers) 287 * 0xE2 (32 bytes of SMB registers) 288 */ 289 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 290 { 291 u16 region; 292 293 pci_read_config_word(dev, 0xE0, ®ion); 294 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES); 295 pci_read_config_word(dev, 0xE2, ®ion); 296 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1); 297 } 298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 299 300 /* 301 * PIIX4 ACPI: Two IO regions pointed to by longwords at 302 * 0x40 (64 bytes of ACPI registers) 303 * 0x90 (32 bytes of SMB registers) 304 */ 305 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 306 { 307 u32 region; 308 309 pci_read_config_dword(dev, 0x40, ®ion); 310 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES); 311 pci_read_config_dword(dev, 0x90, ®ion); 312 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1); 313 } 314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 315 316 /* 317 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 318 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 319 * 0x58 (64 bytes of GPIO I/O space) 320 */ 321 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 322 { 323 u32 region; 324 325 pci_read_config_dword(dev, 0x40, ®ion); 326 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES); 327 328 pci_read_config_dword(dev, 0x58, ®ion); 329 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1); 330 } 331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 341 342 /* 343 * VIA ACPI: One IO region pointed to by longword at 344 * 0x48 or 0x20 (256 bytes of ACPI registers) 345 */ 346 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 347 { 348 u8 rev; 349 u32 region; 350 351 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 352 if (rev & 0x10) { 353 pci_read_config_dword(dev, 0x48, ®ion); 354 region &= PCI_BASE_ADDRESS_IO_MASK; 355 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES); 356 } 357 } 358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 359 360 /* 361 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 362 * 0x48 (256 bytes of ACPI registers) 363 * 0x70 (128 bytes of hardware monitoring register) 364 * 0x90 (16 bytes of SMB registers) 365 */ 366 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 367 { 368 u16 hm; 369 u32 smb; 370 371 quirk_vt82c586_acpi(dev); 372 373 pci_read_config_word(dev, 0x70, &hm); 374 hm &= PCI_BASE_ADDRESS_IO_MASK; 375 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1); 376 377 pci_read_config_dword(dev, 0x90, &smb); 378 smb &= PCI_BASE_ADDRESS_IO_MASK; 379 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2); 380 } 381 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 382 383 /* 384 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 385 * 0x88 (128 bytes of power management registers) 386 * 0xd0 (16 bytes of SMB registers) 387 */ 388 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 389 { 390 u16 pm, smb; 391 392 pci_read_config_word(dev, 0x88, &pm); 393 pm &= PCI_BASE_ADDRESS_IO_MASK; 394 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES); 395 396 pci_read_config_word(dev, 0xd0, &smb); 397 smb &= PCI_BASE_ADDRESS_IO_MASK; 398 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1); 399 } 400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 401 402 403 #ifdef CONFIG_X86_IO_APIC 404 405 #include <asm/io_apic.h> 406 407 /* 408 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 409 * devices to the external APIC. 410 * 411 * TODO: When we have device-specific interrupt routers, 412 * this code will go away from quirks. 413 */ 414 static void __devinit quirk_via_ioapic(struct pci_dev *dev) 415 { 416 u8 tmp; 417 418 if (nr_ioapics < 1) 419 tmp = 0; /* nothing routed to external APIC */ 420 else 421 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 422 423 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 424 tmp == 0 ? "Disa" : "Ena"); 425 426 /* Offset 0x58: External APIC IRQ output control */ 427 pci_write_config_byte (dev, 0x58, tmp); 428 } 429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 430 431 /* 432 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 433 * This leads to doubled level interrupt rates. 434 * Set this bit to get rid of cycle wastage. 435 * Otherwise uncritical. 436 */ 437 static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 438 { 439 u8 misc_control2; 440 #define BYPASS_APIC_DEASSERT 8 441 442 pci_read_config_byte(dev, 0x5B, &misc_control2); 443 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 444 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); 445 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 446 } 447 } 448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 449 450 /* 451 * The AMD io apic can hang the box when an apic irq is masked. 452 * We check all revs >= B0 (yet not in the pre production!) as the bug 453 * is currently marked NoFix 454 * 455 * We have multiple reports of hangs with this chipset that went away with 456 * noapic specified. For the moment we assume its the errata. We may be wrong 457 * of course. However the advice is demonstrably good even if so.. 458 */ 459 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 460 { 461 u8 rev; 462 463 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 464 if (rev >= 0x02) { 465 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n"); 466 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 467 } 468 } 469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 470 471 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 472 { 473 if (dev->devfn == 0 && dev->bus->number == 0) 474 sis_apic_bug = 1; 475 } 476 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 477 478 int pci_msi_quirk; 479 480 #define AMD8131_revA0 0x01 481 #define AMD8131_revB0 0x11 482 #define AMD8131_MISC 0x40 483 #define AMD8131_NIOAMODE_BIT 0 484 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) 485 { 486 unsigned char revid, tmp; 487 488 pci_msi_quirk = 1; 489 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 490 491 if (nr_ioapics == 0) 492 return; 493 494 pci_read_config_byte(dev, PCI_REVISION_ID, &revid); 495 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { 496 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 497 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 498 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 499 pci_write_config_byte( dev, AMD8131_MISC, tmp); 500 } 501 } 502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic ); 503 504 static void __init quirk_svw_msi(struct pci_dev *dev) 505 { 506 pci_msi_quirk = 1; 507 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 508 } 509 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi ); 510 #endif /* CONFIG_X86_IO_APIC */ 511 512 513 /* 514 * FIXME: it is questionable that quirk_via_acpi 515 * is needed. It shows up as an ISA bridge, and does not 516 * support the PCI_INTERRUPT_LINE register at all. Therefore 517 * it seems like setting the pci_dev's 'irq' to the 518 * value of the ACPI SCI interrupt is only done for convenience. 519 * -jgarzik 520 */ 521 static void __devinit quirk_via_acpi(struct pci_dev *d) 522 { 523 /* 524 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 525 */ 526 u8 irq; 527 pci_read_config_byte(d, 0x42, &irq); 528 irq &= 0xf; 529 if (irq && (irq != 2)) 530 d->irq = irq; 531 } 532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 534 535 /* 536 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip 537 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: 538 * when written, it makes an internal connection to the PIC. 539 * For these devices, this register is defined to be 4 bits wide. 540 * Normally this is fine. However for IO-APIC motherboards, or 541 * non-x86 architectures (yes Via exists on PPC among other places), 542 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get 543 * interrupts delivered properly. 544 */ 545 static void quirk_via_irq(struct pci_dev *dev) 546 { 547 u8 irq, new_irq; 548 549 new_irq = dev->irq & 0xf; 550 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 551 if (new_irq != irq) { 552 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n", 553 pci_name(dev), irq, new_irq); 554 udelay(15); /* unknown if delay really needed */ 555 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 556 } 557 } 558 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq); 559 560 /* 561 * PIIX3 USB: We have to disable USB interrupts that are 562 * hardwired to PIRQD# and may be shared with an 563 * external device. 564 * 565 * Legacy Support Register (LEGSUP): 566 * bit13: USB PIRQ Enable (USBPIRQDEN), 567 * bit4: Trap/SMI On IRQ Enable (USBSMIEN). 568 * 569 * We mask out all r/wc bits, too. 570 */ 571 static void __devinit quirk_piix3_usb(struct pci_dev *dev) 572 { 573 u16 legsup; 574 575 pci_read_config_word(dev, 0xc0, &legsup); 576 legsup &= 0x50ef; 577 pci_write_config_word(dev, 0xc0, legsup); 578 } 579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb ); 580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb ); 581 582 /* 583 * VIA VT82C598 has its device ID settable and many BIOSes 584 * set it to the ID of VT82C597 for backward compatibility. 585 * We need to switch it off to be able to recognize the real 586 * type of the chip. 587 */ 588 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 589 { 590 pci_write_config_byte(dev, 0xfc, 0); 591 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 592 } 593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 594 595 /* 596 * CardBus controllers have a legacy base address that enables them 597 * to respond as i82365 pcmcia controllers. We don't want them to 598 * do this even if the Linux CardBus driver is not loaded, because 599 * the Linux i82365 driver does not (and should not) handle CardBus. 600 */ 601 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) 602 { 603 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 604 return; 605 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 606 } 607 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 608 609 /* 610 * Following the PCI ordering rules is optional on the AMD762. I'm not 611 * sure what the designers were smoking but let's not inhale... 612 * 613 * To be fair to AMD, it follows the spec by default, its BIOS people 614 * who turn it off! 615 */ 616 static void __devinit quirk_amd_ordering(struct pci_dev *dev) 617 { 618 u32 pcic; 619 pci_read_config_dword(dev, 0x4C, &pcic); 620 if ((pcic&6)!=6) { 621 pcic |= 6; 622 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 623 pci_write_config_dword(dev, 0x4C, pcic); 624 pci_read_config_dword(dev, 0x84, &pcic); 625 pcic |= (1<<23); /* Required in this mode */ 626 pci_write_config_dword(dev, 0x84, pcic); 627 } 628 } 629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 630 631 /* 632 * DreamWorks provided workaround for Dunord I-3000 problem 633 * 634 * This card decodes and responds to addresses not apparently 635 * assigned to it. We force a larger allocation to ensure that 636 * nothing gets put too close to it. 637 */ 638 static void __devinit quirk_dunord ( struct pci_dev * dev ) 639 { 640 struct resource *r = &dev->resource [1]; 641 r->start = 0; 642 r->end = 0xffffff; 643 } 644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 645 646 /* 647 * i82380FB mobile docking controller: its PCI-to-PCI bridge 648 * is subtractive decoding (transparent), and does indicate this 649 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 650 * instead of 0x01. 651 */ 652 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 653 { 654 dev->transparent = 1; 655 } 656 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 658 659 /* 660 * Common misconfiguration of the MediaGX/Geode PCI master that will 661 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 662 * datasheets found at http://www.national.com/ds/GX for info on what 663 * these bits do. <christer@weinigel.se> 664 */ 665 static void __init quirk_mediagx_master(struct pci_dev *dev) 666 { 667 u8 reg; 668 pci_read_config_byte(dev, 0x41, ®); 669 if (reg & 2) { 670 reg &= ~2; 671 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 672 pci_write_config_byte(dev, 0x41, reg); 673 } 674 } 675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 676 677 /* 678 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers 679 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and 680 * secondary channels respectively). If the device reports Compatible mode 681 * but does use BAR0-3 for address decoding, we assume that firmware has 682 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374). 683 * Exceptions (if they exist) must be handled in chip/architecture specific 684 * fixups. 685 * 686 * Note: for non x86 people. You may need an arch specific quirk to handle 687 * moving IDE devices to native mode as well. Some plug in card devices power 688 * up in compatible mode and assume the BIOS will adjust them. 689 * 690 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as 691 * we do now ? We don't want is pci_enable_device to come along 692 * and assign new resources. Both approaches work for that. 693 */ 694 static void __devinit quirk_ide_bases(struct pci_dev *dev) 695 { 696 struct resource *res; 697 int first_bar = 2, last_bar = 0; 698 699 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 700 return; 701 702 res = &dev->resource[0]; 703 704 /* primary channel: ProgIf bit 0, BAR0, BAR1 */ 705 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { 706 res[0].start = res[0].end = res[0].flags = 0; 707 res[1].start = res[1].end = res[1].flags = 0; 708 first_bar = 0; 709 last_bar = 1; 710 } 711 712 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */ 713 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { 714 res[2].start = res[2].end = res[2].flags = 0; 715 res[3].start = res[3].end = res[3].flags = 0; 716 last_bar = 3; 717 } 718 719 if (!last_bar) 720 return; 721 722 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n", 723 first_bar, last_bar, pci_name(dev)); 724 } 725 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases); 726 727 /* 728 * Ensure C0 rev restreaming is off. This is normally done by 729 * the BIOS but in the odd case it is not the results are corruption 730 * hence the presence of a Linux check 731 */ 732 static void __init quirk_disable_pxb(struct pci_dev *pdev) 733 { 734 u16 config; 735 u8 rev; 736 737 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 738 if (rev != 0x04) /* Only C0 requires this */ 739 return; 740 pci_read_config_word(pdev, 0x40, &config); 741 if (config & (1<<6)) { 742 config &= ~(1<<6); 743 pci_write_config_word(pdev, 0x40, config); 744 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 745 } 746 } 747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 748 749 750 /* 751 * Serverworks CSB5 IDE does not fully support native mode 752 */ 753 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 754 { 755 u8 prog; 756 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 757 if (prog & 5) { 758 prog &= ~5; 759 pdev->class &= ~5; 760 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 761 /* need to re-assign BARs for compat mode */ 762 quirk_ide_bases(pdev); 763 } 764 } 765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 766 767 /* 768 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 769 */ 770 static void __init quirk_ide_samemode(struct pci_dev *pdev) 771 { 772 u8 prog; 773 774 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 775 776 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 777 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 778 prog &= ~5; 779 pdev->class &= ~5; 780 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 781 /* need to re-assign BARs for compat mode */ 782 quirk_ide_bases(pdev); 783 } 784 } 785 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 786 787 /* This was originally an Alpha specific thing, but it really fits here. 788 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 789 */ 790 static void __init quirk_eisa_bridge(struct pci_dev *dev) 791 { 792 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 793 } 794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 795 796 /* 797 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 798 * is not activated. The myth is that Asus said that they do not want the 799 * users to be irritated by just another PCI Device in the Win98 device 800 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 801 * package 2.7.0 for details) 802 * 803 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 804 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 805 * becomes necessary to do this tweak in two steps -- I've chosen the Host 806 * bridge as trigger. 807 */ 808 static int __initdata asus_hides_smbus = 0; 809 810 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 811 { 812 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 813 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 814 switch(dev->subsystem_device) { 815 case 0x8025: /* P4B-LX */ 816 case 0x8070: /* P4B */ 817 case 0x8088: /* P4B533 */ 818 case 0x1626: /* L3C notebook */ 819 asus_hides_smbus = 1; 820 } 821 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 822 switch(dev->subsystem_device) { 823 case 0x80b1: /* P4GE-V */ 824 case 0x80b2: /* P4PE */ 825 case 0x8093: /* P4B533-V */ 826 asus_hides_smbus = 1; 827 } 828 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 829 switch(dev->subsystem_device) { 830 case 0x8030: /* P4T533 */ 831 asus_hides_smbus = 1; 832 } 833 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 834 switch (dev->subsystem_device) { 835 case 0x8070: /* P4G8X Deluxe */ 836 asus_hides_smbus = 1; 837 } 838 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 839 switch (dev->subsystem_device) { 840 case 0x1751: /* M2N notebook */ 841 case 0x1821: /* M5N notebook */ 842 asus_hides_smbus = 1; 843 } 844 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 845 switch (dev->subsystem_device) { 846 case 0x184b: /* W1N notebook */ 847 case 0x186a: /* M6Ne notebook */ 848 asus_hides_smbus = 1; 849 } 850 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 851 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 852 switch(dev->subsystem_device) { 853 case 0x088C: /* HP Compaq nc8000 */ 854 case 0x0890: /* HP Compaq nc6000 */ 855 asus_hides_smbus = 1; 856 } 857 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 858 switch (dev->subsystem_device) { 859 case 0x12bc: /* HP D330L */ 860 asus_hides_smbus = 1; 861 } 862 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { 863 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 864 switch(dev->subsystem_device) { 865 case 0x0001: /* Toshiba Satellite A40 */ 866 asus_hides_smbus = 1; 867 } 868 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 869 switch(dev->subsystem_device) { 870 case 0x0001: /* Toshiba Tecra M2 */ 871 asus_hides_smbus = 1; 872 } 873 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 874 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 875 switch(dev->subsystem_device) { 876 case 0xC00C: /* Samsung P35 notebook */ 877 asus_hides_smbus = 1; 878 } 879 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 880 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 881 switch(dev->subsystem_device) { 882 case 0x0058: /* Compaq Evo N620c */ 883 asus_hides_smbus = 1; 884 } 885 } 886 } 887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 894 895 static void __init asus_hides_smbus_lpc(struct pci_dev *dev) 896 { 897 u16 val; 898 899 if (likely(!asus_hides_smbus)) 900 return; 901 902 pci_read_config_word(dev, 0xF2, &val); 903 if (val & 0x8) { 904 pci_write_config_word(dev, 0xF2, val & (~0x8)); 905 pci_read_config_word(dev, 0xF2, &val); 906 if (val & 0x8) 907 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 908 else 909 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 910 } 911 } 912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 917 918 /* 919 * SiS 96x south bridge: BIOS typically hides SMBus device... 920 */ 921 static void __init quirk_sis_96x_smbus(struct pci_dev *dev) 922 { 923 u8 val = 0; 924 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 925 pci_read_config_byte(dev, 0x77, &val); 926 pci_write_config_byte(dev, 0x77, val & ~0x10); 927 pci_read_config_byte(dev, 0x77, &val); 928 } 929 930 931 #define UHCI_USBLEGSUP 0xc0 /* legacy support */ 932 #define UHCI_USBCMD 0 /* command register */ 933 #define UHCI_USBSTS 2 /* status register */ 934 #define UHCI_USBINTR 4 /* interrupt register */ 935 #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 936 #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 937 #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */ 938 #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */ 939 #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */ 940 941 #define OHCI_CONTROL 0x04 942 #define OHCI_CMDSTATUS 0x08 943 #define OHCI_INTRSTATUS 0x0c 944 #define OHCI_INTRENABLE 0x10 945 #define OHCI_INTRDISABLE 0x14 946 #define OHCI_OCR (1 << 3) /* ownership change request */ 947 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 948 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 949 950 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 951 #define EHCI_USBCMD 0 /* command register */ 952 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 953 #define EHCI_USBSTS 4 /* status register */ 954 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 955 #define EHCI_USBINTR 8 /* interrupt register */ 956 #define EHCI_USBLEGSUP 0 /* legacy support register */ 957 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 958 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 959 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 960 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 961 962 int usb_early_handoff __devinitdata = 0; 963 static int __init usb_handoff_early(char *str) 964 { 965 usb_early_handoff = 1; 966 return 0; 967 } 968 __setup("usb-handoff", usb_handoff_early); 969 970 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev) 971 { 972 unsigned long base = 0; 973 int wait_time, delta; 974 u16 val, sts; 975 int i; 976 977 for (i = 0; i < PCI_ROM_RESOURCE; i++) 978 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 979 base = pci_resource_start(pdev, i); 980 break; 981 } 982 983 if (!base) 984 return; 985 986 /* 987 * stop controller 988 */ 989 sts = inw(base + UHCI_USBSTS); 990 val = inw(base + UHCI_USBCMD); 991 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE); 992 outw(val, base + UHCI_USBCMD); 993 994 /* 995 * wait while it stops if it was running 996 */ 997 if ((sts & UHCI_USBSTS_HALTED) == 0) 998 { 999 wait_time = 1000; 1000 delta = 100; 1001 1002 do { 1003 outw(0x1f, base + UHCI_USBSTS); 1004 udelay(delta); 1005 wait_time -= delta; 1006 val = inw(base + UHCI_USBSTS); 1007 if (val & UHCI_USBSTS_HALTED) 1008 break; 1009 } while (wait_time > 0); 1010 } 1011 1012 /* 1013 * disable interrupts & legacy support 1014 */ 1015 outw(0, base + UHCI_USBINTR); 1016 outw(0x1f, base + UHCI_USBSTS); 1017 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val); 1018 if (val & 0xbf) 1019 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT); 1020 1021 } 1022 1023 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) 1024 { 1025 void __iomem *base; 1026 int wait_time; 1027 1028 base = ioremap_nocache(pci_resource_start(pdev, 0), 1029 pci_resource_len(pdev, 0)); 1030 if (base == NULL) return; 1031 1032 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 1033 wait_time = 500; /* 0.5 seconds */ 1034 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 1035 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 1036 while (wait_time > 0 && 1037 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 1038 wait_time -= 10; 1039 msleep(10); 1040 } 1041 } 1042 1043 /* 1044 * disable interrupts 1045 */ 1046 writel(~(u32)0, base + OHCI_INTRDISABLE); 1047 writel(~(u32)0, base + OHCI_INTRSTATUS); 1048 1049 iounmap(base); 1050 } 1051 1052 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) 1053 { 1054 int wait_time, delta; 1055 void __iomem *base, *op_reg_base; 1056 u32 hcc_params, val, temp; 1057 u8 cap_length; 1058 1059 base = ioremap_nocache(pci_resource_start(pdev, 0), 1060 pci_resource_len(pdev, 0)); 1061 if (base == NULL) return; 1062 1063 cap_length = readb(base); 1064 op_reg_base = base + cap_length; 1065 hcc_params = readl(base + EHCI_HCC_PARAMS); 1066 hcc_params = (hcc_params >> 8) & 0xff; 1067 if (hcc_params) { 1068 pci_read_config_dword(pdev, 1069 hcc_params + EHCI_USBLEGSUP, 1070 &val); 1071 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) { 1072 /* 1073 * Ok, BIOS is in smm mode, try to hand off... 1074 */ 1075 pci_read_config_dword(pdev, 1076 hcc_params + EHCI_USBLEGCTLSTS, 1077 &temp); 1078 pci_write_config_dword(pdev, 1079 hcc_params + EHCI_USBLEGCTLSTS, 1080 temp | EHCI_USBLEGCTLSTS_SOOE); 1081 val |= EHCI_USBLEGSUP_OS; 1082 pci_write_config_dword(pdev, 1083 hcc_params + EHCI_USBLEGSUP, 1084 val); 1085 1086 wait_time = 500; 1087 do { 1088 msleep(10); 1089 wait_time -= 10; 1090 pci_read_config_dword(pdev, 1091 hcc_params + EHCI_USBLEGSUP, 1092 &val); 1093 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS)); 1094 if (!wait_time) { 1095 /* 1096 * well, possibly buggy BIOS... 1097 */ 1098 printk(KERN_WARNING "EHCI early BIOS handoff " 1099 "failed (BIOS bug ?)\n"); 1100 pci_write_config_dword(pdev, 1101 hcc_params + EHCI_USBLEGSUP, 1102 EHCI_USBLEGSUP_OS); 1103 pci_write_config_dword(pdev, 1104 hcc_params + EHCI_USBLEGCTLSTS, 1105 0); 1106 } 1107 } 1108 } 1109 1110 /* 1111 * halt EHCI & disable its interrupts in any case 1112 */ 1113 val = readl(op_reg_base + EHCI_USBSTS); 1114 if ((val & EHCI_USBSTS_HALTED) == 0) { 1115 val = readl(op_reg_base + EHCI_USBCMD); 1116 val &= ~EHCI_USBCMD_RUN; 1117 writel(val, op_reg_base + EHCI_USBCMD); 1118 1119 wait_time = 2000; 1120 delta = 100; 1121 do { 1122 writel(0x3f, op_reg_base + EHCI_USBSTS); 1123 udelay(delta); 1124 wait_time -= delta; 1125 val = readl(op_reg_base + EHCI_USBSTS); 1126 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 1127 break; 1128 } 1129 } while (wait_time > 0); 1130 } 1131 writel(0, op_reg_base + EHCI_USBINTR); 1132 writel(0x3f, op_reg_base + EHCI_USBSTS); 1133 1134 iounmap(base); 1135 1136 return; 1137 } 1138 1139 1140 1141 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev) 1142 { 1143 if (!usb_early_handoff) 1144 return; 1145 1146 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */ 1147 quirk_usb_handoff_uhci(pdev); 1148 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */ 1149 quirk_usb_handoff_ohci(pdev); 1150 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */ 1151 quirk_usb_disable_ehci(pdev); 1152 } 1153 1154 return; 1155 } 1156 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff); 1157 1158 /* 1159 * ... This is further complicated by the fact that some SiS96x south 1160 * bridges pretend to be 85C503/5513 instead. In that case see if we 1161 * spotted a compatible north bridge to make sure. 1162 * (pci_find_device doesn't work yet) 1163 * 1164 * We can also enable the sis96x bit in the discovery register.. 1165 */ 1166 static int __devinitdata sis_96x_compatible = 0; 1167 1168 #define SIS_DETECT_REGISTER 0x40 1169 1170 static void __init quirk_sis_503(struct pci_dev *dev) 1171 { 1172 u8 reg; 1173 u16 devid; 1174 1175 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1176 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1177 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1178 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1179 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1180 return; 1181 } 1182 1183 /* Make people aware that we changed the config.. */ 1184 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible); 1185 1186 /* 1187 * Ok, it now shows up as a 96x.. The 96x quirks are after 1188 * the 503 quirk in the quirk table, so they'll automatically 1189 * run and enable things like the SMBus device 1190 */ 1191 dev->device = devid; 1192 } 1193 1194 static void __init quirk_sis_96x_compatible(struct pci_dev *dev) 1195 { 1196 sis_96x_compatible = 1; 1197 } 1198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible ); 1199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible ); 1200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible ); 1201 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible ); 1202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible ); 1203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible ); 1204 1205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1206 1207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1211 1212 #ifdef CONFIG_X86_IO_APIC 1213 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1214 { 1215 int i; 1216 1217 if ((pdev->class >> 8) != 0xff00) 1218 return; 1219 1220 /* the first BAR is the location of the IO APIC...we must 1221 * not touch this (and it's already covered by the fixmap), so 1222 * forcibly insert it into the resource tree */ 1223 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1224 insert_resource(&iomem_resource, &pdev->resource[0]); 1225 1226 /* The next five BARs all seem to be rubbish, so just clean 1227 * them out */ 1228 for (i=1; i < 6; i++) { 1229 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1230 } 1231 1232 } 1233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1234 #endif 1235 1236 #ifdef CONFIG_SCSI_SATA 1237 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) 1238 { 1239 u8 prog, comb, tmp; 1240 int ich = 0; 1241 1242 /* 1243 * Narrow down to Intel SATA PCI devices. 1244 */ 1245 switch (pdev->device) { 1246 /* PCI ids taken from drivers/scsi/ata_piix.c */ 1247 case 0x24d1: 1248 case 0x24df: 1249 case 0x25a3: 1250 case 0x25b0: 1251 ich = 5; 1252 break; 1253 case 0x2651: 1254 case 0x2652: 1255 case 0x2653: 1256 case 0x2680: /* ESB2 */ 1257 ich = 6; 1258 break; 1259 case 0x27c0: 1260 case 0x27c4: 1261 ich = 7; 1262 break; 1263 default: 1264 /* we do not handle this PCI device */ 1265 return; 1266 } 1267 1268 /* 1269 * Read combined mode register. 1270 */ 1271 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ 1272 1273 if (ich == 5) { 1274 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ 1275 if (tmp == 0x4) /* bits 10x */ 1276 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1277 else if (tmp == 0x6) /* bits 11x */ 1278 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1279 else 1280 return; /* not in combined mode */ 1281 } else { 1282 WARN_ON((ich != 6) && (ich != 7)); 1283 tmp &= 0x3; /* interesting bits 1:0 */ 1284 if (tmp & (1 << 0)) 1285 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1286 else if (tmp & (1 << 1)) 1287 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1288 else 1289 return; /* not in combined mode */ 1290 } 1291 1292 /* 1293 * Read programming interface register. 1294 * (Tells us if it's legacy or native mode) 1295 */ 1296 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1297 1298 /* if SATA port is in native mode, we're ok. */ 1299 if (prog & comb) 1300 return; 1301 1302 /* SATA port is in legacy mode. Reserve port so that 1303 * IDE driver does not attempt to use it. If request_region 1304 * fails, it will be obvious at boot time, so we don't bother 1305 * checking return values. 1306 */ 1307 if (comb == (1 << 0)) 1308 request_region(0x1f0, 8, "libata"); /* port 0 */ 1309 else 1310 request_region(0x170, 8, "libata"); /* port 1 */ 1311 } 1312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); 1313 #endif /* CONFIG_SCSI_SATA */ 1314 1315 1316 int pcie_mch_quirk; 1317 1318 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1319 { 1320 pcie_mch_quirk = 1; 1321 } 1322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1325 1326 1327 /* 1328 * It's possible for the MSI to get corrupted if shpc and acpi 1329 * are used together on certain PXH-based systems. 1330 */ 1331 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1332 { 1333 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), 1334 PCI_CAP_ID_MSI); 1335 dev->no_msi = 1; 1336 1337 printk(KERN_WARNING "PCI: PXH quirk detected, " 1338 "disabling MSI for SHPC device\n"); 1339 } 1340 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1341 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1342 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1343 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1344 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1345 1346 1347 static void __devinit quirk_netmos(struct pci_dev *dev) 1348 { 1349 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1350 unsigned int num_serial = dev->subsystem_device & 0xf; 1351 1352 /* 1353 * These Netmos parts are multiport serial devices with optional 1354 * parallel ports. Even when parallel ports are present, they 1355 * are identified as class SERIAL, which means the serial driver 1356 * will claim them. To prevent this, mark them as class OTHER. 1357 * These combo devices should be claimed by parport_serial. 1358 * 1359 * The subdevice ID is of the form 0x00PS, where <P> is the number 1360 * of parallel ports and <S> is the number of serial ports. 1361 */ 1362 switch (dev->device) { 1363 case PCI_DEVICE_ID_NETMOS_9735: 1364 case PCI_DEVICE_ID_NETMOS_9745: 1365 case PCI_DEVICE_ID_NETMOS_9835: 1366 case PCI_DEVICE_ID_NETMOS_9845: 1367 case PCI_DEVICE_ID_NETMOS_9855: 1368 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1369 num_parallel) { 1370 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1371 "%u serial); changing class SERIAL to OTHER " 1372 "(use parport_serial)\n", 1373 dev->device, num_parallel, num_serial); 1374 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1375 (dev->class & 0xff); 1376 } 1377 } 1378 } 1379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1380 1381 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1382 { 1383 while (f < end) { 1384 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1385 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1386 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1387 f->hook(dev); 1388 } 1389 f++; 1390 } 1391 } 1392 1393 extern struct pci_fixup __start_pci_fixups_early[]; 1394 extern struct pci_fixup __end_pci_fixups_early[]; 1395 extern struct pci_fixup __start_pci_fixups_header[]; 1396 extern struct pci_fixup __end_pci_fixups_header[]; 1397 extern struct pci_fixup __start_pci_fixups_final[]; 1398 extern struct pci_fixup __end_pci_fixups_final[]; 1399 extern struct pci_fixup __start_pci_fixups_enable[]; 1400 extern struct pci_fixup __end_pci_fixups_enable[]; 1401 1402 1403 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 1404 { 1405 struct pci_fixup *start, *end; 1406 1407 switch(pass) { 1408 case pci_fixup_early: 1409 start = __start_pci_fixups_early; 1410 end = __end_pci_fixups_early; 1411 break; 1412 1413 case pci_fixup_header: 1414 start = __start_pci_fixups_header; 1415 end = __end_pci_fixups_header; 1416 break; 1417 1418 case pci_fixup_final: 1419 start = __start_pci_fixups_final; 1420 end = __end_pci_fixups_final; 1421 break; 1422 1423 case pci_fixup_enable: 1424 start = __start_pci_fixups_enable; 1425 end = __end_pci_fixups_enable; 1426 break; 1427 1428 default: 1429 /* stupid compiler warning, you would think with an enum... */ 1430 return; 1431 } 1432 pci_do_fixups(dev, start, end); 1433 } 1434 1435 EXPORT_SYMBOL(pcie_mch_quirk); 1436 #ifdef CONFIG_HOTPLUG 1437 EXPORT_SYMBOL(pci_fixup_device); 1438 #endif 1439