1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/align.h> 17 #include <linux/bitfield.h> 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/export.h> 21 #include <linux/pci.h> 22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 23 #include <linux/init.h> 24 #include <linux/iommu.h> 25 #include <linux/delay.h> 26 #include <linux/acpi.h> 27 #include <linux/dmi.h> 28 #include <linux/ioport.h> 29 #include <linux/sched.h> 30 #include <linux/ktime.h> 31 #include <linux/mm.h> 32 #include <linux/nvme.h> 33 #include <linux/platform_data/x86/apple.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/sizes.h> 36 #include <linux/suspend.h> 37 #include <linux/switchtec.h> 38 #include "pci.h" 39 40 static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta) 41 { 42 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) 43 return true; 44 45 return lnksta & PCI_EXP_LNKSTA_LBMS; 46 } 47 48 /* 49 * Retrain the link of a downstream PCIe port by hand if necessary. 50 * 51 * This is needed at least where a downstream port of the ASMedia ASM2824 52 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 53 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 54 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 55 * board. 56 * 57 * In such a configuration the switches are supposed to negotiate the link 58 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 59 * continues switching between the two speeds indefinitely and the data 60 * link layer never reaches the active state, with link training reported 61 * repeatedly active ~84% of the time. Forcing the target link speed to 62 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 63 * each other correctly however. And more interestingly retraining with a 64 * higher target link speed afterwards lets the two successfully negotiate 65 * 5.0GT/s. 66 * 67 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 68 * Link Active status bit and in the failed link training scenario it will 69 * be off along with the Link Bandwidth Management Status indicating that 70 * hardware has changed the link speed or width in an attempt to correct 71 * unreliable link operation. For a port that has been left unconnected 72 * both bits will be clear. So use this information to detect the problem 73 * rather than polling the Link Training bit and watching out for flips or 74 * at least the active status. 75 * 76 * Since the exact nature of the problem isn't known and in principle this 77 * could trigger where an ASM2824 device is downstream rather upstream, 78 * apply this erratum workaround to any downstream ports as long as they 79 * support Link Active reporting and have the Link Control 2 register. 80 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 81 * request a retrain and check the result. 82 * 83 * If this turns out successful, or where a 2.5GT/s speed restriction has 84 * been previously arranged by the firmware and the port reports its link 85 * already being up, lift the restriction, in a hope it is safe to do so, 86 * letting the devices negotiate a higher speed. 87 * 88 * Otherwise revert the speed to the original setting and request a retrain 89 * again to remove any residual state, ignoring the result as it's supposed 90 * to fail anyway. 91 * 92 * Return 0 if the link has been successfully retrained. Return an error 93 * if retraining was not needed or we attempted a retrain and it failed. 94 */ 95 int pcie_failed_link_retrain(struct pci_dev *dev) 96 { 97 u16 lnksta, lnkctl2, oldlnkctl2; 98 enum pci_bus_speed speed_cap; 99 int ret = -ENOTTY; 100 101 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 102 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 103 return ret; 104 105 speed_cap = pcie_get_speed_cap(dev); 106 if (speed_cap <= PCIE_SPEED_2_5GT) 107 return ret; 108 109 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 110 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2); 111 if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) { 112 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 113 ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false); 114 if (ret) 115 goto err; 116 } 117 118 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 119 if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT) { 120 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 121 ret = pcie_set_target_speed(dev, speed_cap, false); 122 if (ret) 123 goto err; 124 } 125 126 return ret; 127 err: 128 pci_info(dev, "retraining failed\n"); 129 pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), true); 130 return ret; 131 } 132 133 static ktime_t fixup_debug_start(struct pci_dev *dev, 134 void (*fn)(struct pci_dev *dev)) 135 { 136 if (initcall_debug) 137 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 138 139 return ktime_get(); 140 } 141 142 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 143 void (*fn)(struct pci_dev *dev)) 144 { 145 ktime_t delta, rettime; 146 unsigned long long duration; 147 148 rettime = ktime_get(); 149 delta = ktime_sub(rettime, calltime); 150 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 151 if (initcall_debug || duration > 10000) 152 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 153 } 154 155 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 156 struct pci_fixup *end) 157 { 158 ktime_t calltime; 159 160 for (; f < end; f++) 161 if ((f->class == (u32) (dev->class >> f->class_shift) || 162 f->class == (u32) PCI_ANY_ID) && 163 (f->vendor == dev->vendor || 164 f->vendor == (u16) PCI_ANY_ID) && 165 (f->device == dev->device || 166 f->device == (u16) PCI_ANY_ID)) { 167 void (*hook)(struct pci_dev *dev); 168 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 169 hook = offset_to_ptr(&f->hook_offset); 170 #else 171 hook = f->hook; 172 #endif 173 calltime = fixup_debug_start(dev, hook); 174 hook(dev); 175 fixup_debug_report(dev, calltime, hook); 176 } 177 } 178 179 extern struct pci_fixup __start_pci_fixups_early[]; 180 extern struct pci_fixup __end_pci_fixups_early[]; 181 extern struct pci_fixup __start_pci_fixups_header[]; 182 extern struct pci_fixup __end_pci_fixups_header[]; 183 extern struct pci_fixup __start_pci_fixups_final[]; 184 extern struct pci_fixup __end_pci_fixups_final[]; 185 extern struct pci_fixup __start_pci_fixups_enable[]; 186 extern struct pci_fixup __end_pci_fixups_enable[]; 187 extern struct pci_fixup __start_pci_fixups_resume[]; 188 extern struct pci_fixup __end_pci_fixups_resume[]; 189 extern struct pci_fixup __start_pci_fixups_resume_early[]; 190 extern struct pci_fixup __end_pci_fixups_resume_early[]; 191 extern struct pci_fixup __start_pci_fixups_suspend[]; 192 extern struct pci_fixup __end_pci_fixups_suspend[]; 193 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 194 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 195 196 static bool pci_apply_fixup_final_quirks; 197 198 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 199 { 200 struct pci_fixup *start, *end; 201 202 switch (pass) { 203 case pci_fixup_early: 204 start = __start_pci_fixups_early; 205 end = __end_pci_fixups_early; 206 break; 207 208 case pci_fixup_header: 209 start = __start_pci_fixups_header; 210 end = __end_pci_fixups_header; 211 break; 212 213 case pci_fixup_final: 214 if (!pci_apply_fixup_final_quirks) 215 return; 216 start = __start_pci_fixups_final; 217 end = __end_pci_fixups_final; 218 break; 219 220 case pci_fixup_enable: 221 start = __start_pci_fixups_enable; 222 end = __end_pci_fixups_enable; 223 break; 224 225 case pci_fixup_resume: 226 start = __start_pci_fixups_resume; 227 end = __end_pci_fixups_resume; 228 break; 229 230 case pci_fixup_resume_early: 231 start = __start_pci_fixups_resume_early; 232 end = __end_pci_fixups_resume_early; 233 break; 234 235 case pci_fixup_suspend: 236 start = __start_pci_fixups_suspend; 237 end = __end_pci_fixups_suspend; 238 break; 239 240 case pci_fixup_suspend_late: 241 start = __start_pci_fixups_suspend_late; 242 end = __end_pci_fixups_suspend_late; 243 break; 244 245 default: 246 /* stupid compiler warning, you would think with an enum... */ 247 return; 248 } 249 pci_do_fixups(dev, start, end); 250 } 251 EXPORT_SYMBOL(pci_fixup_device); 252 253 static int __init pci_apply_final_quirks(void) 254 { 255 struct pci_dev *dev = NULL; 256 u8 cls = 0; 257 u8 tmp; 258 259 if (pci_cache_line_size) 260 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 261 262 pci_apply_fixup_final_quirks = true; 263 for_each_pci_dev(dev) { 264 pci_fixup_device(pci_fixup_final, dev); 265 /* 266 * If arch hasn't set it explicitly yet, use the CLS 267 * value shared by all PCI devices. If there's a 268 * mismatch, fall back to the default value. 269 */ 270 if (!pci_cache_line_size) { 271 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 272 if (!cls) 273 cls = tmp; 274 if (!tmp || cls == tmp) 275 continue; 276 277 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 278 cls << 2, tmp << 2, 279 pci_dfl_cache_line_size << 2); 280 pci_cache_line_size = pci_dfl_cache_line_size; 281 } 282 } 283 284 if (!pci_cache_line_size) { 285 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 286 pci_dfl_cache_line_size << 2); 287 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 288 } 289 290 return 0; 291 } 292 fs_initcall_sync(pci_apply_final_quirks); 293 294 /* 295 * Decoding should be disabled for a PCI device during BAR sizing to avoid 296 * conflict. But doing so may cause problems on host bridge and perhaps other 297 * key system devices. For devices that need to have mmio decoding always-on, 298 * we need to set the dev->mmio_always_on bit. 299 */ 300 static void quirk_mmio_always_on(struct pci_dev *dev) 301 { 302 dev->mmio_always_on = 1; 303 } 304 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 305 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 306 307 /* 308 * The Mellanox Tavor device gives false positive parity errors. Disable 309 * parity error reporting. 310 */ 311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 313 314 /* 315 * Deal with broken BIOSes that neglect to enable passive release, 316 * which can cause problems in combination with the 82441FX/PPro MTRRs 317 */ 318 static void quirk_passive_release(struct pci_dev *dev) 319 { 320 struct pci_dev *d = NULL; 321 unsigned char dlc; 322 323 /* 324 * We have to make sure a particular bit is set in the PIIX3 325 * ISA bridge, so we have to go out and find it. 326 */ 327 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 328 pci_read_config_byte(d, 0x82, &dlc); 329 if (!(dlc & 1<<1)) { 330 pci_info(d, "PIIX3: Enabling Passive Release\n"); 331 dlc |= 1<<1; 332 pci_write_config_byte(d, 0x82, dlc); 333 } 334 } 335 } 336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 337 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 338 339 #ifdef CONFIG_X86_32 340 /* 341 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 342 * workaround but VIA don't answer queries. If you happen to have good 343 * contacts at VIA ask them for me please -- Alan 344 * 345 * This appears to be BIOS not version dependent. So presumably there is a 346 * chipset level fix. 347 */ 348 static void quirk_isa_dma_hangs(struct pci_dev *dev) 349 { 350 if (!isa_dma_bridge_buggy) { 351 isa_dma_bridge_buggy = 1; 352 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 353 } 354 } 355 /* 356 * It's not totally clear which chipsets are the problematic ones. We know 357 * 82C586 and 82C596 variants are affected. 358 */ 359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 362 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 363 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 364 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 365 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 366 #endif 367 368 #ifdef CONFIG_HAS_IOPORT 369 /* 370 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 371 * for some HT machines to use C4 w/o hanging. 372 */ 373 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 374 { 375 u32 pmbase; 376 u16 pm1a; 377 378 pci_read_config_dword(dev, 0x40, &pmbase); 379 pmbase = pmbase & 0xff80; 380 pm1a = inw(pmbase); 381 382 if (pm1a & 0x10) { 383 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 384 outw(0x10, pmbase); 385 } 386 } 387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 388 #endif 389 390 /* Chipsets where PCI->PCI transfers vanish or hang */ 391 static void quirk_nopcipci(struct pci_dev *dev) 392 { 393 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 394 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 395 pci_pci_problems |= PCIPCI_FAIL; 396 } 397 } 398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 400 401 static void quirk_nopciamd(struct pci_dev *dev) 402 { 403 u8 rev; 404 pci_read_config_byte(dev, 0x08, &rev); 405 if (rev == 0x13) { 406 /* Erratum 24 */ 407 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 408 pci_pci_problems |= PCIAGP_FAIL; 409 } 410 } 411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 412 413 /* Triton requires workarounds to be used by the drivers */ 414 static void quirk_triton(struct pci_dev *dev) 415 { 416 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 417 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 418 pci_pci_problems |= PCIPCI_TRITON; 419 } 420 } 421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 425 426 /* 427 * VIA Apollo KT133 needs PCI latency patch 428 * Made according to a Windows driver-based patch by George E. Breese; 429 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 430 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 431 * which Mr Breese based his work. 432 * 433 * Updated based on further information from the site and also on 434 * information provided by VIA 435 */ 436 static void quirk_vialatency(struct pci_dev *dev) 437 { 438 struct pci_dev *p; 439 u8 busarb; 440 441 /* 442 * Ok, we have a potential problem chipset here. Now see if we have 443 * a buggy southbridge. 444 */ 445 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 446 if (p != NULL) { 447 448 /* 449 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 450 * thanks Dan Hollis. 451 * Check for buggy part revisions 452 */ 453 if (p->revision < 0x40 || p->revision > 0x42) 454 goto exit; 455 } else { 456 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 457 if (p == NULL) /* No problem parts */ 458 goto exit; 459 460 /* Check for buggy part revisions */ 461 if (p->revision < 0x10 || p->revision > 0x12) 462 goto exit; 463 } 464 465 /* 466 * Ok we have the problem. Now set the PCI master grant to occur 467 * every master grant. The apparent bug is that under high PCI load 468 * (quite common in Linux of course) you can get data loss when the 469 * CPU is held off the bus for 3 bus master requests. This happens 470 * to include the IDE controllers.... 471 * 472 * VIA only apply this fix when an SB Live! is present but under 473 * both Linux and Windows this isn't enough, and we have seen 474 * corruption without SB Live! but with things like 3 UDMA IDE 475 * controllers. So we ignore that bit of the VIA recommendation.. 476 */ 477 pci_read_config_byte(dev, 0x76, &busarb); 478 479 /* 480 * Set bit 4 and bit 5 of byte 76 to 0x01 481 * "Master priority rotation on every PCI master grant" 482 */ 483 busarb &= ~(1<<5); 484 busarb |= (1<<4); 485 pci_write_config_byte(dev, 0x76, busarb); 486 pci_info(dev, "Applying VIA southbridge workaround\n"); 487 exit: 488 pci_dev_put(p); 489 } 490 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 491 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 492 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 493 /* Must restore this on a resume from RAM */ 494 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 495 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 496 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 497 498 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 499 static void quirk_viaetbf(struct pci_dev *dev) 500 { 501 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 502 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 503 pci_pci_problems |= PCIPCI_VIAETBF; 504 } 505 } 506 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 507 508 static void quirk_vsfx(struct pci_dev *dev) 509 { 510 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 511 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 512 pci_pci_problems |= PCIPCI_VSFX; 513 } 514 } 515 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 516 517 /* 518 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 519 * space. Latency must be set to 0xA and Triton workaround applied too. 520 * [Info kindly provided by ALi] 521 */ 522 static void quirk_alimagik(struct pci_dev *dev) 523 { 524 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 525 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 526 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 527 } 528 } 529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 531 532 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 533 static void quirk_natoma(struct pci_dev *dev) 534 { 535 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 536 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 537 pci_pci_problems |= PCIPCI_NATOMA; 538 } 539 } 540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 546 547 /* 548 * This chip can cause PCI parity errors if config register 0xA0 is read 549 * while DMAs are occurring. 550 */ 551 static void quirk_citrine(struct pci_dev *dev) 552 { 553 dev->cfg_size = 0xA0; 554 } 555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 556 557 /* 558 * This chip can cause bus lockups if config addresses above 0x600 559 * are read or written. 560 */ 561 static void quirk_nfp6000(struct pci_dev *dev) 562 { 563 dev->cfg_size = 0x600; 564 } 565 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 566 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 567 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 569 570 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 571 static void quirk_extend_bar_to_page(struct pci_dev *dev) 572 { 573 int i; 574 575 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 576 struct resource *r = &dev->resource[i]; 577 const char *r_name = pci_resource_name(dev, i); 578 579 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 580 resource_set_range(r, 0, PAGE_SIZE); 581 r->flags |= IORESOURCE_UNSET; 582 pci_info(dev, "%s %pR: expanded to page size\n", 583 r_name, r); 584 } 585 } 586 } 587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 588 589 /* 590 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 591 * If it's needed, re-allocate the region. 592 */ 593 static void quirk_s3_64M(struct pci_dev *dev) 594 { 595 struct resource *r = &dev->resource[0]; 596 597 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) { 598 r->flags |= IORESOURCE_UNSET; 599 resource_set_range(r, 0, SZ_64M); 600 } 601 } 602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 604 605 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 606 const char *name) 607 { 608 u32 region; 609 struct pci_bus_region bus_region; 610 struct resource *res = pci_resource_n(dev, pos); 611 const char *res_name = pci_resource_name(dev, pos); 612 613 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 614 615 if (!region) 616 return; 617 618 res->name = pci_name(dev); 619 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 620 res->flags |= 621 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 622 region &= ~(size - 1); 623 624 /* Convert from PCI bus to resource space */ 625 bus_region.start = region; 626 bus_region.end = region + size - 1; 627 pcibios_bus_to_resource(dev->bus, res, &bus_region); 628 629 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name); 630 } 631 632 /* 633 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 634 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 635 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 636 * (which conflicts w/ BAR1's memory range). 637 * 638 * CS553x's ISA PCI BARs may also be read-only (ref: 639 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 640 */ 641 static void quirk_cs5536_vsa(struct pci_dev *dev) 642 { 643 static char *name = "CS5536 ISA bridge"; 644 645 if (pci_resource_len(dev, 0) != 8) { 646 quirk_io(dev, 0, 8, name); /* SMB */ 647 quirk_io(dev, 1, 256, name); /* GPIO */ 648 quirk_io(dev, 2, 64, name); /* MFGPT */ 649 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 650 name); 651 } 652 } 653 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 654 655 static void quirk_io_region(struct pci_dev *dev, int port, 656 unsigned int size, int nr, const char *name) 657 { 658 u16 region; 659 struct pci_bus_region bus_region; 660 struct resource *res = pci_resource_n(dev, nr); 661 662 pci_read_config_word(dev, port, ®ion); 663 region &= ~(size - 1); 664 665 if (!region) 666 return; 667 668 res->name = pci_name(dev); 669 res->flags = IORESOURCE_IO; 670 671 /* Convert from PCI bus to resource space */ 672 bus_region.start = region; 673 bus_region.end = region + size - 1; 674 pcibios_bus_to_resource(dev->bus, res, &bus_region); 675 676 /* 677 * "res" is typically a bridge window resource that's not being 678 * used for a bridge window, so it's just a place to stash this 679 * non-standard resource. Printing "nr" or pci_resource_name() of 680 * it doesn't really make sense. 681 */ 682 if (!pci_claim_resource(dev, nr)) 683 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 684 } 685 686 /* 687 * ATI Northbridge setups MCE the processor if you even read somewhere 688 * between 0x3b0->0x3bb or read 0x3d3 689 */ 690 static void quirk_ati_exploding_mce(struct pci_dev *dev) 691 { 692 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 693 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 694 request_region(0x3b0, 0x0C, "RadeonIGP"); 695 request_region(0x3d3, 0x01, "RadeonIGP"); 696 } 697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 698 699 /* 700 * In the AMD NL platform, this device ([1022:7912]) has a class code of 701 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 702 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 703 * 704 * But the dwc3 driver is a more specific driver for this device, and we'd 705 * prefer to use it instead of xhci. To prevent xhci from claiming the 706 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 707 * defines as "USB device (not host controller)". The dwc3 driver can then 708 * claim it based on its Vendor and Device ID. 709 */ 710 static void quirk_amd_dwc_class(struct pci_dev *pdev) 711 { 712 u32 class = pdev->class; 713 714 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 715 /* Use "USB Device (not host controller)" class */ 716 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 717 pci_info(pdev, 718 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 719 class, pdev->class); 720 } 721 } 722 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 723 quirk_amd_dwc_class); 724 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 725 quirk_amd_dwc_class); 726 727 /* 728 * Synopsys USB 3.x host HAPS platform has a class code of 729 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 730 * devices should use dwc3-haps driver. Change these devices' class code to 731 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 732 * them. 733 */ 734 static void quirk_synopsys_haps(struct pci_dev *pdev) 735 { 736 u32 class = pdev->class; 737 738 switch (pdev->device) { 739 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 740 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 741 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 742 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 743 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 744 class, pdev->class); 745 break; 746 } 747 } 748 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 749 PCI_CLASS_SERIAL_USB_XHCI, 0, 750 quirk_synopsys_haps); 751 752 /* 753 * Let's make the southbridge information explicit instead of having to 754 * worry about people probing the ACPI areas, for example.. (Yes, it 755 * happens, and if you read the wrong ACPI register it will put the machine 756 * to sleep with no way of waking it up again. Bummer). 757 * 758 * ALI M7101: Two IO regions pointed to by words at 759 * 0xE0 (64 bytes of ACPI registers) 760 * 0xE2 (32 bytes of SMB registers) 761 */ 762 static void quirk_ali7101_acpi(struct pci_dev *dev) 763 { 764 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 765 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 766 } 767 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 768 769 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 770 { 771 u32 devres; 772 u32 mask, size, base; 773 774 pci_read_config_dword(dev, port, &devres); 775 if ((devres & enable) != enable) 776 return; 777 mask = (devres >> 16) & 15; 778 base = devres & 0xffff; 779 size = 16; 780 for (;;) { 781 unsigned int bit = size >> 1; 782 if ((bit & mask) == bit) 783 break; 784 size = bit; 785 } 786 /* 787 * For now we only print it out. Eventually we'll want to 788 * reserve it (at least if it's in the 0x1000+ range), but 789 * let's get enough confirmation reports first. 790 */ 791 base &= -size; 792 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 793 } 794 795 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 796 { 797 u32 devres; 798 u32 mask, size, base; 799 800 pci_read_config_dword(dev, port, &devres); 801 if ((devres & enable) != enable) 802 return; 803 base = devres & 0xffff0000; 804 mask = (devres & 0x3f) << 16; 805 size = 128 << 16; 806 for (;;) { 807 unsigned int bit = size >> 1; 808 if ((bit & mask) == bit) 809 break; 810 size = bit; 811 } 812 813 /* 814 * For now we only print it out. Eventually we'll want to 815 * reserve it, but let's get enough confirmation reports first. 816 */ 817 base &= -size; 818 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 819 } 820 821 /* 822 * PIIX4 ACPI: Two IO regions pointed to by longwords at 823 * 0x40 (64 bytes of ACPI registers) 824 * 0x90 (16 bytes of SMB registers) 825 * and a few strange programmable PIIX4 device resources. 826 */ 827 static void quirk_piix4_acpi(struct pci_dev *dev) 828 { 829 u32 res_a; 830 831 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 832 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 833 834 /* Device resource A has enables for some of the other ones */ 835 pci_read_config_dword(dev, 0x5c, &res_a); 836 837 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 838 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 839 840 /* Device resource D is just bitfields for static resources */ 841 842 /* Device 12 enabled? */ 843 if (res_a & (1 << 29)) { 844 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 845 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 846 } 847 /* Device 13 enabled? */ 848 if (res_a & (1 << 30)) { 849 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 850 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 851 } 852 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 853 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 854 } 855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 857 858 #define ICH_PMBASE 0x40 859 #define ICH_ACPI_CNTL 0x44 860 #define ICH4_ACPI_EN 0x10 861 #define ICH6_ACPI_EN 0x80 862 #define ICH4_GPIOBASE 0x58 863 #define ICH4_GPIO_CNTL 0x5c 864 #define ICH4_GPIO_EN 0x10 865 #define ICH6_GPIOBASE 0x48 866 #define ICH6_GPIO_CNTL 0x4c 867 #define ICH6_GPIO_EN 0x10 868 869 /* 870 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 871 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 872 * 0x58 (64 bytes of GPIO I/O space) 873 */ 874 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 875 { 876 u8 enable; 877 878 /* 879 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 880 * with low legacy (and fixed) ports. We don't know the decoding 881 * priority and can't tell whether the legacy device or the one created 882 * here is really at that address. This happens on boards with broken 883 * BIOSes. 884 */ 885 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 886 if (enable & ICH4_ACPI_EN) 887 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 888 "ICH4 ACPI/GPIO/TCO"); 889 890 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 891 if (enable & ICH4_GPIO_EN) 892 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 893 "ICH4 GPIO"); 894 } 895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 905 906 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 907 { 908 u8 enable; 909 910 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 911 if (enable & ICH6_ACPI_EN) 912 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 913 "ICH6 ACPI/GPIO/TCO"); 914 915 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 916 if (enable & ICH6_GPIO_EN) 917 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 918 "ICH6 GPIO"); 919 } 920 921 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 922 const char *name, int dynsize) 923 { 924 u32 val; 925 u32 size, base; 926 927 pci_read_config_dword(dev, reg, &val); 928 929 /* Enabled? */ 930 if (!(val & 1)) 931 return; 932 base = val & 0xfffc; 933 if (dynsize) { 934 /* 935 * This is not correct. It is 16, 32 or 64 bytes depending on 936 * register D31:F0:ADh bits 5:4. 937 * 938 * But this gets us at least _part_ of it. 939 */ 940 size = 16; 941 } else { 942 size = 128; 943 } 944 base &= ~(size-1); 945 946 /* 947 * Just print it out for now. We should reserve it after more 948 * debugging. 949 */ 950 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 951 } 952 953 static void quirk_ich6_lpc(struct pci_dev *dev) 954 { 955 /* Shared ACPI/GPIO decode with all ICH6+ */ 956 ich6_lpc_acpi_gpio(dev); 957 958 /* ICH6-specific generic IO decode */ 959 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 960 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 961 } 962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 963 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 964 965 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 966 const char *name) 967 { 968 u32 val; 969 u32 mask, base; 970 971 pci_read_config_dword(dev, reg, &val); 972 973 /* Enabled? */ 974 if (!(val & 1)) 975 return; 976 977 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 978 base = val & 0xfffc; 979 mask = (val >> 16) & 0xfc; 980 mask |= 3; 981 982 /* 983 * Just print it out for now. We should reserve it after more 984 * debugging. 985 */ 986 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 987 } 988 989 /* ICH7-10 has the same common LPC generic IO decode registers */ 990 static void quirk_ich7_lpc(struct pci_dev *dev) 991 { 992 /* We share the common ACPI/GPIO decode with ICH6 */ 993 ich6_lpc_acpi_gpio(dev); 994 995 /* And have 4 ICH7+ generic decodes */ 996 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 997 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 998 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 999 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 1000 } 1001 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 1002 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 1003 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 1004 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 1005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 1006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 1007 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 1008 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 1009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 1010 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 1011 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1012 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1014 1015 /* 1016 * VIA ACPI: One IO region pointed to by longword at 1017 * 0x48 or 0x20 (256 bytes of ACPI registers) 1018 */ 1019 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1020 { 1021 if (dev->revision & 0x10) 1022 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1023 "vt82c586 ACPI"); 1024 } 1025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1026 1027 /* 1028 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1029 * 0x48 (256 bytes of ACPI registers) 1030 * 0x70 (128 bytes of hardware monitoring register) 1031 * 0x90 (16 bytes of SMB registers) 1032 */ 1033 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1034 { 1035 quirk_vt82c586_acpi(dev); 1036 1037 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1038 "vt82c686 HW-mon"); 1039 1040 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1041 } 1042 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1043 1044 /* 1045 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1046 * 0x88 (128 bytes of power management registers) 1047 * 0xd0 (16 bytes of SMB registers) 1048 */ 1049 static void quirk_vt8235_acpi(struct pci_dev *dev) 1050 { 1051 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1052 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1053 } 1054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1055 1056 /* 1057 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1058 * back-to-back: Disable fast back-to-back on the secondary bus segment 1059 */ 1060 static void quirk_xio2000a(struct pci_dev *dev) 1061 { 1062 struct pci_dev *pdev; 1063 u16 command; 1064 1065 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1066 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1067 pci_read_config_word(pdev, PCI_COMMAND, &command); 1068 if (command & PCI_COMMAND_FAST_BACK) 1069 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1070 } 1071 } 1072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1073 quirk_xio2000a); 1074 1075 #ifdef CONFIG_X86_IO_APIC 1076 1077 #include <asm/io_apic.h> 1078 1079 /* 1080 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1081 * devices to the external APIC. 1082 * 1083 * TODO: When we have device-specific interrupt routers, this code will go 1084 * away from quirks. 1085 */ 1086 static void quirk_via_ioapic(struct pci_dev *dev) 1087 { 1088 u8 tmp; 1089 1090 if (nr_ioapics < 1) 1091 tmp = 0; /* nothing routed to external APIC */ 1092 else 1093 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1094 1095 pci_info(dev, "%s VIA external APIC routing\n", 1096 tmp ? "Enabling" : "Disabling"); 1097 1098 /* Offset 0x58: External APIC IRQ output control */ 1099 pci_write_config_byte(dev, 0x58, tmp); 1100 } 1101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1102 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1103 1104 /* 1105 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1106 * This leads to doubled level interrupt rates. 1107 * Set this bit to get rid of cycle wastage. 1108 * Otherwise uncritical. 1109 */ 1110 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1111 { 1112 u8 misc_control2; 1113 #define BYPASS_APIC_DEASSERT 8 1114 1115 pci_read_config_byte(dev, 0x5B, &misc_control2); 1116 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1117 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1118 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1119 } 1120 } 1121 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1122 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1123 1124 /* 1125 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1126 * We check all revs >= B0 (yet not in the pre production!) as the bug 1127 * is currently marked NoFix 1128 * 1129 * We have multiple reports of hangs with this chipset that went away with 1130 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1131 * of course. However the advice is demonstrably good even if so. 1132 */ 1133 static void quirk_amd_ioapic(struct pci_dev *dev) 1134 { 1135 if (dev->revision >= 0x02) { 1136 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1137 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1138 } 1139 } 1140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1141 #endif /* CONFIG_X86_IO_APIC */ 1142 1143 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1144 1145 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1146 { 1147 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1148 if (dev->subsystem_device == 0xa118) 1149 dev->sriov->link = dev->devfn; 1150 } 1151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1152 #endif 1153 1154 /* 1155 * Some settings of MMRBC can lead to data corruption so block changes. 1156 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1157 */ 1158 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1159 { 1160 if (dev->subordinate && dev->revision <= 0x12) { 1161 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1162 dev->revision); 1163 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1164 } 1165 } 1166 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1167 1168 /* 1169 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1170 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1171 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1172 * of the ACPI SCI interrupt is only done for convenience. 1173 * -jgarzik 1174 */ 1175 static void quirk_via_acpi(struct pci_dev *d) 1176 { 1177 u8 irq; 1178 1179 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1180 pci_read_config_byte(d, 0x42, &irq); 1181 irq &= 0xf; 1182 if (irq && (irq != 2)) 1183 d->irq = irq; 1184 } 1185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1187 1188 /* VIA bridges which have VLink */ 1189 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1190 1191 static void quirk_via_bridge(struct pci_dev *dev) 1192 { 1193 /* See what bridge we have and find the device ranges */ 1194 switch (dev->device) { 1195 case PCI_DEVICE_ID_VIA_82C686: 1196 /* 1197 * The VT82C686 is special; it attaches to PCI and can have 1198 * any device number. All its subdevices are functions of 1199 * that single device. 1200 */ 1201 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1202 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1203 break; 1204 case PCI_DEVICE_ID_VIA_8237: 1205 case PCI_DEVICE_ID_VIA_8237A: 1206 via_vlink_dev_lo = 15; 1207 break; 1208 case PCI_DEVICE_ID_VIA_8235: 1209 via_vlink_dev_lo = 16; 1210 break; 1211 case PCI_DEVICE_ID_VIA_8231: 1212 case PCI_DEVICE_ID_VIA_8233_0: 1213 case PCI_DEVICE_ID_VIA_8233A: 1214 case PCI_DEVICE_ID_VIA_8233C_0: 1215 via_vlink_dev_lo = 17; 1216 break; 1217 } 1218 } 1219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1221 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1227 1228 /* 1229 * quirk_via_vlink - VIA VLink IRQ number update 1230 * @dev: PCI device 1231 * 1232 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1233 * the IRQ line register which usually is not relevant for PCI cards, is 1234 * actually written so that interrupts get sent to the right place. 1235 * 1236 * We only do this on systems where a VIA south bridge was detected, and 1237 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1238 */ 1239 static void quirk_via_vlink(struct pci_dev *dev) 1240 { 1241 u8 irq, new_irq; 1242 1243 /* Check if we have VLink at all */ 1244 if (via_vlink_dev_lo == -1) 1245 return; 1246 1247 new_irq = dev->irq; 1248 1249 /* Don't quirk interrupts outside the legacy IRQ range */ 1250 if (!new_irq || new_irq > 15) 1251 return; 1252 1253 /* Internal device ? */ 1254 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1255 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1256 return; 1257 1258 /* 1259 * This is an internal VLink device on a PIC interrupt. The BIOS 1260 * ought to have set this but may not have, so we redo it. 1261 */ 1262 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1263 if (new_irq != irq) { 1264 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1265 irq, new_irq); 1266 udelay(15); /* unknown if delay really needed */ 1267 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1268 } 1269 } 1270 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1271 1272 /* 1273 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1274 * of VT82C597 for backward compatibility. We need to switch it off to be 1275 * able to recognize the real type of the chip. 1276 */ 1277 static void quirk_vt82c598_id(struct pci_dev *dev) 1278 { 1279 pci_write_config_byte(dev, 0xfc, 0); 1280 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1281 } 1282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1283 1284 /* 1285 * CardBus controllers have a legacy base address that enables them to 1286 * respond as i82365 PCMCIA controllers. We don't want them to do this. 1287 */ 1288 static void quirk_cardbus_legacy(struct pci_dev *dev) 1289 { 1290 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1291 } 1292 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1293 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1294 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1295 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1296 1297 /* 1298 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1299 * what the designers were smoking but let's not inhale... 1300 * 1301 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1302 * turn it off! 1303 */ 1304 static void quirk_amd_ordering(struct pci_dev *dev) 1305 { 1306 u32 pcic; 1307 pci_read_config_dword(dev, 0x4C, &pcic); 1308 if ((pcic & 6) != 6) { 1309 pcic |= 6; 1310 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1311 pci_write_config_dword(dev, 0x4C, pcic); 1312 pci_read_config_dword(dev, 0x84, &pcic); 1313 pcic |= (1 << 23); /* Required in this mode */ 1314 pci_write_config_dword(dev, 0x84, pcic); 1315 } 1316 } 1317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1318 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1319 1320 /* 1321 * DreamWorks-provided workaround for Dunord I-3000 problem 1322 * 1323 * This card decodes and responds to addresses not apparently assigned to 1324 * it. We force a larger allocation to ensure that nothing gets put too 1325 * close to it. 1326 */ 1327 static void quirk_dunord(struct pci_dev *dev) 1328 { 1329 struct resource *r = &dev->resource[1]; 1330 1331 r->flags |= IORESOURCE_UNSET; 1332 resource_set_range(r, 0, SZ_16M); 1333 } 1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1335 1336 /* 1337 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1338 * decoding (transparent), and does indicate this in the ProgIf. 1339 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1340 */ 1341 static void quirk_transparent_bridge(struct pci_dev *dev) 1342 { 1343 dev->transparent = 1; 1344 } 1345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1347 1348 /* 1349 * Enabling Link Bandwidth Management Interrupts (BW notifications) can cause 1350 * boot hangs on P45. 1351 */ 1352 static void quirk_p45_bw_notifications(struct pci_dev *dev) 1353 { 1354 dev->no_bw_notif = 1; 1355 } 1356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e21, quirk_p45_bw_notifications); 1357 1358 /* 1359 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1360 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1361 * found at http://www.national.com/analog for info on what these bits do. 1362 * <christer@weinigel.se> 1363 */ 1364 static void quirk_mediagx_master(struct pci_dev *dev) 1365 { 1366 u8 reg; 1367 1368 pci_read_config_byte(dev, 0x41, ®); 1369 if (reg & 2) { 1370 reg &= ~2; 1371 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1372 reg); 1373 pci_write_config_byte(dev, 0x41, reg); 1374 } 1375 } 1376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1377 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1378 1379 /* 1380 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1381 * in the odd case it is not the results are corruption hence the presence 1382 * of a Linux check. 1383 */ 1384 static void quirk_disable_pxb(struct pci_dev *pdev) 1385 { 1386 u16 config; 1387 1388 if (pdev->revision != 0x04) /* Only C0 requires this */ 1389 return; 1390 pci_read_config_word(pdev, 0x40, &config); 1391 if (config & (1<<6)) { 1392 config &= ~(1<<6); 1393 pci_write_config_word(pdev, 0x40, config); 1394 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1395 } 1396 } 1397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1398 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1399 1400 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1401 { 1402 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1403 u8 tmp; 1404 1405 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1406 if (tmp == 0x01) { 1407 pci_read_config_byte(pdev, 0x40, &tmp); 1408 pci_write_config_byte(pdev, 0x40, tmp|1); 1409 pci_write_config_byte(pdev, 0x9, 1); 1410 pci_write_config_byte(pdev, 0xa, 6); 1411 pci_write_config_byte(pdev, 0x40, tmp); 1412 1413 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1414 pci_info(pdev, "set SATA to AHCI mode\n"); 1415 } 1416 } 1417 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1418 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1420 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1422 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1425 1426 /* Serverworks CSB5 IDE does not fully support native mode */ 1427 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1428 { 1429 u8 prog; 1430 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1431 if (prog & 5) { 1432 prog &= ~5; 1433 pdev->class &= ~5; 1434 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1435 /* PCI layer will sort out resources */ 1436 } 1437 } 1438 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1439 1440 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1441 static void quirk_ide_samemode(struct pci_dev *pdev) 1442 { 1443 u8 prog; 1444 1445 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1446 1447 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1448 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1449 prog &= ~5; 1450 pdev->class &= ~5; 1451 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1452 } 1453 } 1454 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1455 1456 /* Some ATA devices break if put into D3 */ 1457 static void quirk_no_ata_d3(struct pci_dev *pdev) 1458 { 1459 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1460 } 1461 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1462 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1463 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1464 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1465 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1466 /* ALi loses some register settings that we cannot then restore */ 1467 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1468 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1469 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1470 occur when mode detecting */ 1471 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1472 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1473 1474 /* 1475 * This was originally an Alpha-specific thing, but it really fits here. 1476 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1477 */ 1478 static void quirk_eisa_bridge(struct pci_dev *dev) 1479 { 1480 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1481 } 1482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1483 1484 /* 1485 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1486 * is not activated. The myth is that Asus said that they do not want the 1487 * users to be irritated by just another PCI Device in the Win98 device 1488 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1489 * package 2.7.0 for details) 1490 * 1491 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1492 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1493 * becomes necessary to do this tweak in two steps -- the chosen trigger 1494 * is either the Host bridge (preferred) or on-board VGA controller. 1495 * 1496 * Note that we used to unhide the SMBus that way on Toshiba laptops 1497 * (Satellite A40 and Tecra M2) but then found that the thermal management 1498 * was done by SMM code, which could cause unsynchronized concurrent 1499 * accesses to the SMBus registers, with potentially bad effects. Thus you 1500 * should be very careful when adding new entries: if SMM is accessing the 1501 * Intel SMBus, this is a very good reason to leave it hidden. 1502 * 1503 * Likewise, many recent laptops use ACPI for thermal management. If the 1504 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1505 * natively, and keeping the SMBus hidden is the right thing to do. If you 1506 * are about to add an entry in the table below, please first disassemble 1507 * the DSDT and double-check that there is no code accessing the SMBus. 1508 */ 1509 static int asus_hides_smbus; 1510 1511 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1512 { 1513 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1514 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1515 switch (dev->subsystem_device) { 1516 case 0x8025: /* P4B-LX */ 1517 case 0x8070: /* P4B */ 1518 case 0x8088: /* P4B533 */ 1519 case 0x1626: /* L3C notebook */ 1520 asus_hides_smbus = 1; 1521 } 1522 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1523 switch (dev->subsystem_device) { 1524 case 0x80b1: /* P4GE-V */ 1525 case 0x80b2: /* P4PE */ 1526 case 0x8093: /* P4B533-V */ 1527 asus_hides_smbus = 1; 1528 } 1529 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1530 switch (dev->subsystem_device) { 1531 case 0x8030: /* P4T533 */ 1532 asus_hides_smbus = 1; 1533 } 1534 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1535 switch (dev->subsystem_device) { 1536 case 0x8070: /* P4G8X Deluxe */ 1537 asus_hides_smbus = 1; 1538 } 1539 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1540 switch (dev->subsystem_device) { 1541 case 0x80c9: /* PU-DLS */ 1542 asus_hides_smbus = 1; 1543 } 1544 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1545 switch (dev->subsystem_device) { 1546 case 0x1751: /* M2N notebook */ 1547 case 0x1821: /* M5N notebook */ 1548 case 0x1897: /* A6L notebook */ 1549 asus_hides_smbus = 1; 1550 } 1551 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1552 switch (dev->subsystem_device) { 1553 case 0x184b: /* W1N notebook */ 1554 case 0x186a: /* M6Ne notebook */ 1555 asus_hides_smbus = 1; 1556 } 1557 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1558 switch (dev->subsystem_device) { 1559 case 0x80f2: /* P4P800-X */ 1560 asus_hides_smbus = 1; 1561 } 1562 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1563 switch (dev->subsystem_device) { 1564 case 0x1882: /* M6V notebook */ 1565 case 0x1977: /* A6VA notebook */ 1566 asus_hides_smbus = 1; 1567 } 1568 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1569 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1570 switch (dev->subsystem_device) { 1571 case 0x088C: /* HP Compaq nc8000 */ 1572 case 0x0890: /* HP Compaq nc6000 */ 1573 asus_hides_smbus = 1; 1574 } 1575 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1576 switch (dev->subsystem_device) { 1577 case 0x12bc: /* HP D330L */ 1578 case 0x12bd: /* HP D530 */ 1579 case 0x006a: /* HP Compaq nx9500 */ 1580 asus_hides_smbus = 1; 1581 } 1582 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1583 switch (dev->subsystem_device) { 1584 case 0x12bf: /* HP xw4100 */ 1585 asus_hides_smbus = 1; 1586 } 1587 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1588 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1589 switch (dev->subsystem_device) { 1590 case 0xC00C: /* Samsung P35 notebook */ 1591 asus_hides_smbus = 1; 1592 } 1593 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1594 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1595 switch (dev->subsystem_device) { 1596 case 0x0058: /* Compaq Evo N620c */ 1597 asus_hides_smbus = 1; 1598 } 1599 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1600 switch (dev->subsystem_device) { 1601 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1602 /* Motherboard doesn't have Host bridge 1603 * subvendor/subdevice IDs, therefore checking 1604 * its on-board VGA controller */ 1605 asus_hides_smbus = 1; 1606 } 1607 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1608 switch (dev->subsystem_device) { 1609 case 0x00b8: /* Compaq Evo D510 CMT */ 1610 case 0x00b9: /* Compaq Evo D510 SFF */ 1611 case 0x00ba: /* Compaq Evo D510 USDT */ 1612 /* Motherboard doesn't have Host bridge 1613 * subvendor/subdevice IDs and on-board VGA 1614 * controller is disabled if an AGP card is 1615 * inserted, therefore checking USB UHCI 1616 * Controller #1 */ 1617 asus_hides_smbus = 1; 1618 } 1619 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1620 switch (dev->subsystem_device) { 1621 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1622 /* Motherboard doesn't have host bridge 1623 * subvendor/subdevice IDs, therefore checking 1624 * its on-board VGA controller */ 1625 asus_hides_smbus = 1; 1626 } 1627 } 1628 } 1629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1630 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1639 1640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1643 1644 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1645 { 1646 u16 val; 1647 1648 if (likely(!asus_hides_smbus)) 1649 return; 1650 1651 pci_read_config_word(dev, 0xF2, &val); 1652 if (val & 0x8) { 1653 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1654 pci_read_config_word(dev, 0xF2, &val); 1655 if (val & 0x8) 1656 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1657 val); 1658 else 1659 pci_info(dev, "Enabled i801 SMBus device\n"); 1660 } 1661 } 1662 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1663 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1664 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1668 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1669 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1670 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1671 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1672 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1673 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1674 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1675 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1676 1677 /* It appears we just have one such device. If not, we have a warning */ 1678 static void __iomem *asus_rcba_base; 1679 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1680 { 1681 u32 rcba; 1682 1683 if (likely(!asus_hides_smbus)) 1684 return; 1685 WARN_ON(asus_rcba_base); 1686 1687 pci_read_config_dword(dev, 0xF0, &rcba); 1688 /* use bits 31:14, 16 kB aligned */ 1689 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1690 if (asus_rcba_base == NULL) 1691 return; 1692 } 1693 1694 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1695 { 1696 u32 val; 1697 1698 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1699 return; 1700 1701 /* read the Function Disable register, dword mode only */ 1702 val = readl(asus_rcba_base + 0x3418); 1703 1704 /* enable the SMBus device */ 1705 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1706 } 1707 1708 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1709 { 1710 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1711 return; 1712 1713 iounmap(asus_rcba_base); 1714 asus_rcba_base = NULL; 1715 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1716 } 1717 1718 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1719 { 1720 asus_hides_smbus_lpc_ich6_suspend(dev); 1721 asus_hides_smbus_lpc_ich6_resume_early(dev); 1722 asus_hides_smbus_lpc_ich6_resume(dev); 1723 } 1724 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1725 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1726 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1727 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1728 1729 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1730 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1731 { 1732 u8 val = 0; 1733 pci_read_config_byte(dev, 0x77, &val); 1734 if (val & 0x10) { 1735 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1736 pci_write_config_byte(dev, 0x77, val & ~0x10); 1737 } 1738 } 1739 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1740 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1741 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1742 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1743 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1744 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1745 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1746 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1747 1748 /* 1749 * ... This is further complicated by the fact that some SiS96x south 1750 * bridges pretend to be 85C503/5513 instead. In that case see if we 1751 * spotted a compatible north bridge to make sure. 1752 * (pci_find_device() doesn't work yet) 1753 * 1754 * We can also enable the sis96x bit in the discovery register.. 1755 */ 1756 #define SIS_DETECT_REGISTER 0x40 1757 1758 static void quirk_sis_503(struct pci_dev *dev) 1759 { 1760 u8 reg; 1761 u16 devid; 1762 1763 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1764 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1765 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1766 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1767 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1768 return; 1769 } 1770 1771 /* 1772 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1773 * it has already been processed. (Depends on link order, which is 1774 * apparently not guaranteed) 1775 */ 1776 dev->device = devid; 1777 quirk_sis_96x_smbus(dev); 1778 } 1779 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1780 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1781 1782 /* 1783 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1784 * and MC97 modem controller are disabled when a second PCI soundcard is 1785 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1786 * -- bjd 1787 */ 1788 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1789 { 1790 u8 val; 1791 int asus_hides_ac97 = 0; 1792 1793 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1794 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1795 asus_hides_ac97 = 1; 1796 } 1797 1798 if (!asus_hides_ac97) 1799 return; 1800 1801 pci_read_config_byte(dev, 0x50, &val); 1802 if (val & 0xc0) { 1803 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1804 pci_read_config_byte(dev, 0x50, &val); 1805 if (val & 0xc0) 1806 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1807 val); 1808 else 1809 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1810 } 1811 } 1812 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1813 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1814 1815 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1816 1817 /* 1818 * If we are using libata we can drive this chip properly but must do this 1819 * early on to make the additional device appear during the PCI scanning. 1820 */ 1821 static void quirk_jmicron_ata(struct pci_dev *pdev) 1822 { 1823 u32 conf1, conf5, class; 1824 u8 hdr; 1825 1826 /* Only poke fn 0 */ 1827 if (PCI_FUNC(pdev->devfn)) 1828 return; 1829 1830 pci_read_config_dword(pdev, 0x40, &conf1); 1831 pci_read_config_dword(pdev, 0x80, &conf5); 1832 1833 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1834 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1835 1836 switch (pdev->device) { 1837 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1838 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1839 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1840 /* The controller should be in single function ahci mode */ 1841 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1842 break; 1843 1844 case PCI_DEVICE_ID_JMICRON_JMB365: 1845 case PCI_DEVICE_ID_JMICRON_JMB366: 1846 /* Redirect IDE second PATA port to the right spot */ 1847 conf5 |= (1 << 24); 1848 fallthrough; 1849 case PCI_DEVICE_ID_JMICRON_JMB361: 1850 case PCI_DEVICE_ID_JMICRON_JMB363: 1851 case PCI_DEVICE_ID_JMICRON_JMB369: 1852 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1853 /* Set the class codes correctly and then direct IDE 0 */ 1854 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1855 break; 1856 1857 case PCI_DEVICE_ID_JMICRON_JMB368: 1858 /* The controller should be in single function IDE mode */ 1859 conf1 |= 0x00C00000; /* Set 22, 23 */ 1860 break; 1861 } 1862 1863 pci_write_config_dword(pdev, 0x40, conf1); 1864 pci_write_config_dword(pdev, 0x80, conf5); 1865 1866 /* Update pdev accordingly */ 1867 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1868 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; 1869 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); 1870 1871 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1872 pdev->class = class >> 8; 1873 } 1874 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1875 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1876 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1877 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1878 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1879 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1880 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1881 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1882 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1883 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1884 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1885 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1886 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1887 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1888 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1889 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1890 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1891 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1892 1893 #endif 1894 1895 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1896 { 1897 if (dev->multifunction) { 1898 device_disable_async_suspend(&dev->dev); 1899 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1900 } 1901 } 1902 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1903 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1904 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1906 1907 #ifdef CONFIG_X86_IO_APIC 1908 static void quirk_alder_ioapic(struct pci_dev *pdev) 1909 { 1910 int i; 1911 1912 if ((pdev->class >> 8) != 0xff00) 1913 return; 1914 1915 /* 1916 * The first BAR is the location of the IO-APIC... we must 1917 * not touch this (and it's already covered by the fixmap), so 1918 * forcibly insert it into the resource tree. 1919 */ 1920 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1921 insert_resource(&iomem_resource, &pdev->resource[0]); 1922 1923 /* 1924 * The next five BARs all seem to be rubbish, so just clean 1925 * them out. 1926 */ 1927 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1928 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1929 } 1930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1931 #endif 1932 1933 static void quirk_no_msi(struct pci_dev *dev) 1934 { 1935 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1936 dev->no_msi = 1; 1937 } 1938 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1939 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1941 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1943 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1944 1945 static void quirk_pcie_mch(struct pci_dev *pdev) 1946 { 1947 pdev->no_msi = 1; 1948 } 1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1952 1953 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1954 1955 /* 1956 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1957 * actually on the AMBA bus. These fake PCI devices can support SVA via 1958 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1959 * 1960 * Normally stalling must not be enabled for PCI devices, since it would 1961 * break the PCI requirement for free-flowing writes and may lead to 1962 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1963 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1964 * even when a "PCI" device turns out to be a regular old SoC device 1965 * dressed up as a RCiEP and normal rules don't apply. 1966 */ 1967 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1968 { 1969 struct property_entry properties[] = { 1970 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1971 {}, 1972 }; 1973 1974 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1975 return; 1976 1977 pdev->pasid_no_tlp = 1; 1978 1979 /* 1980 * Set the dma-can-stall property on ACPI platforms. Device tree 1981 * can set it directly. 1982 */ 1983 if (!pdev->dev.of_node && 1984 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1985 pci_warn(pdev, "could not add stall property"); 1986 } 1987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 1988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 1989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 1990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 1991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 1992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 1993 1994 /* 1995 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1996 * together on certain PXH-based systems. 1997 */ 1998 static void quirk_pcie_pxh(struct pci_dev *dev) 1999 { 2000 dev->no_msi = 1; 2001 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 2002 } 2003 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 2004 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 2005 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 2006 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 2007 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 2008 2009 /* 2010 * Some Intel PCI Express chipsets have trouble with downstream device 2011 * power management. 2012 */ 2013 static void quirk_intel_pcie_pm(struct pci_dev *dev) 2014 { 2015 pci_pm_d3hot_delay = 120; 2016 dev->no_d1d2 = 1; 2017 } 2018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2039 2040 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2041 { 2042 if (dev->d3hot_delay >= delay) 2043 return; 2044 2045 dev->d3hot_delay = delay; 2046 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2047 dev->d3hot_delay); 2048 } 2049 2050 static void quirk_radeon_pm(struct pci_dev *dev) 2051 { 2052 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2053 dev->subsystem_device == 0x00e2) 2054 quirk_d3hot_delay(dev, 20); 2055 } 2056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2057 2058 /* 2059 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2060 * reset is performed too soon after transition to D0, extend d3hot_delay 2061 * to previous effective default for all NVIDIA HDA controllers. 2062 */ 2063 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2064 { 2065 quirk_d3hot_delay(dev, 20); 2066 } 2067 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2068 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2069 quirk_nvidia_hda_pm); 2070 2071 /* 2072 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2073 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2074 * 2075 * The kernel attempts to transition these devices to D3cold, but that seems 2076 * to be ineffective on the platforms in question; the PCI device appears to 2077 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2078 * extended delay in order to succeed. 2079 */ 2080 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2081 { 2082 quirk_d3hot_delay(dev, 20); 2083 } 2084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2087 2088 #ifdef CONFIG_X86_IO_APIC 2089 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2090 { 2091 noioapicreroute = 1; 2092 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2093 2094 return 0; 2095 } 2096 2097 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2098 /* 2099 * Systems to exclude from boot interrupt reroute quirks 2100 */ 2101 { 2102 .callback = dmi_disable_ioapicreroute, 2103 .ident = "ASUSTek Computer INC. M2N-LR", 2104 .matches = { 2105 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2106 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2107 }, 2108 }, 2109 {} 2110 }; 2111 2112 /* 2113 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2114 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2115 * that a PCI device's interrupt handler is installed on the boot interrupt 2116 * line instead. 2117 */ 2118 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2119 { 2120 dmi_check_system(boot_interrupt_dmi_table); 2121 if (noioapicquirk || noioapicreroute) 2122 return; 2123 2124 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2125 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2126 dev->vendor, dev->device); 2127 } 2128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2129 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2130 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2136 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2137 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2138 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2139 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2140 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2141 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2142 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2143 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2144 2145 /* 2146 * On some chipsets we can disable the generation of legacy INTx boot 2147 * interrupts. 2148 */ 2149 2150 /* 2151 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2152 * 300641-004US, section 5.7.3. 2153 * 2154 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2155 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2156 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2157 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2158 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2159 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2160 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2161 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2162 * Core IO on Xeon Scalable, see Intel order no 610950. 2163 */ 2164 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2165 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2166 2167 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2168 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2169 2170 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2171 { 2172 u16 pci_config_word; 2173 u32 pci_config_dword; 2174 2175 if (noioapicquirk) 2176 return; 2177 2178 switch (dev->device) { 2179 case PCI_DEVICE_ID_INTEL_ESB_10: 2180 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2181 &pci_config_word); 2182 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2183 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2184 pci_config_word); 2185 break; 2186 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2187 case 0x0e28: /* Xeon E5/E7 V2 */ 2188 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2189 case 0x6f28: /* Xeon D-1500 */ 2190 case 0x2034: /* Xeon Scalable Family */ 2191 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2192 &pci_config_dword); 2193 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2194 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2195 pci_config_dword); 2196 break; 2197 default: 2198 return; 2199 } 2200 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2201 dev->vendor, dev->device); 2202 } 2203 /* 2204 * Device 29 Func 5 Device IDs of IO-APIC 2205 * containing ABAR—APIC1 Alternate Base Address Register 2206 */ 2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2208 quirk_disable_intel_boot_interrupt); 2209 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2210 quirk_disable_intel_boot_interrupt); 2211 2212 /* 2213 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2214 * containing Coherent Interface Protocol Interrupt Control 2215 * 2216 * Device IDs obtained from volume 2 datasheets of commented 2217 * families above. 2218 */ 2219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2220 quirk_disable_intel_boot_interrupt); 2221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2222 quirk_disable_intel_boot_interrupt); 2223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2224 quirk_disable_intel_boot_interrupt); 2225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2226 quirk_disable_intel_boot_interrupt); 2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2228 quirk_disable_intel_boot_interrupt); 2229 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2230 quirk_disable_intel_boot_interrupt); 2231 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2232 quirk_disable_intel_boot_interrupt); 2233 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2234 quirk_disable_intel_boot_interrupt); 2235 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2236 quirk_disable_intel_boot_interrupt); 2237 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2238 quirk_disable_intel_boot_interrupt); 2239 2240 /* Disable boot interrupts on HT-1000 */ 2241 #define BC_HT1000_FEATURE_REG 0x64 2242 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2243 #define BC_HT1000_MAP_IDX 0xC00 2244 #define BC_HT1000_MAP_DATA 0xC01 2245 2246 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2247 { 2248 u32 pci_config_dword; 2249 u8 irq; 2250 2251 if (noioapicquirk) 2252 return; 2253 2254 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2255 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2256 BC_HT1000_PIC_REGS_ENABLE); 2257 2258 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2259 outb(irq, BC_HT1000_MAP_IDX); 2260 outb(0x00, BC_HT1000_MAP_DATA); 2261 } 2262 2263 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2264 2265 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2266 dev->vendor, dev->device); 2267 } 2268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2269 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2270 2271 /* Disable boot interrupts on AMD and ATI chipsets */ 2272 2273 /* 2274 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2275 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2276 * (due to an erratum). 2277 */ 2278 #define AMD_813X_MISC 0x40 2279 #define AMD_813X_NOIOAMODE (1<<0) 2280 #define AMD_813X_REV_B1 0x12 2281 #define AMD_813X_REV_B2 0x13 2282 2283 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2284 { 2285 u32 pci_config_dword; 2286 2287 if (noioapicquirk) 2288 return; 2289 if ((dev->revision == AMD_813X_REV_B1) || 2290 (dev->revision == AMD_813X_REV_B2)) 2291 return; 2292 2293 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2294 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2295 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2296 2297 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2298 dev->vendor, dev->device); 2299 } 2300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2301 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2303 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2304 2305 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2306 2307 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2308 { 2309 u16 pci_config_word; 2310 2311 if (noioapicquirk) 2312 return; 2313 2314 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2315 if (!pci_config_word) { 2316 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2317 dev->vendor, dev->device); 2318 return; 2319 } 2320 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2321 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2322 dev->vendor, dev->device); 2323 } 2324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2325 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2326 #endif /* CONFIG_X86_IO_APIC */ 2327 2328 /* 2329 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2330 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2331 * Re-allocate the region if needed... 2332 */ 2333 static void quirk_tc86c001_ide(struct pci_dev *dev) 2334 { 2335 struct resource *r = &dev->resource[0]; 2336 2337 if (r->start & 0x8) { 2338 r->flags |= IORESOURCE_UNSET; 2339 resource_set_range(r, 0, SZ_16); 2340 } 2341 } 2342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2343 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2344 quirk_tc86c001_ide); 2345 2346 /* 2347 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2348 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2349 * being read correctly if bit 7 of the base address is set. 2350 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2351 * Re-allocate the regions to a 256-byte boundary if necessary. 2352 */ 2353 static void quirk_plx_pci9050(struct pci_dev *dev) 2354 { 2355 unsigned int bar; 2356 2357 /* Fixed in revision 2 (PCI 9052). */ 2358 if (dev->revision >= 2) 2359 return; 2360 for (bar = 0; bar <= 1; bar++) 2361 if (pci_resource_len(dev, bar) == 0x80 && 2362 (pci_resource_start(dev, bar) & 0x80)) { 2363 struct resource *r = &dev->resource[bar]; 2364 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2365 bar); 2366 r->flags |= IORESOURCE_UNSET; 2367 resource_set_range(r, 0, SZ_256); 2368 } 2369 } 2370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2371 quirk_plx_pci9050); 2372 /* 2373 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2374 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2375 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2376 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2377 * 2378 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2379 * driver. 2380 */ 2381 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2382 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2383 2384 static void quirk_netmos(struct pci_dev *dev) 2385 { 2386 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2387 unsigned int num_serial = dev->subsystem_device & 0xf; 2388 2389 /* 2390 * These Netmos parts are multiport serial devices with optional 2391 * parallel ports. Even when parallel ports are present, they 2392 * are identified as class SERIAL, which means the serial driver 2393 * will claim them. To prevent this, mark them as class OTHER. 2394 * These combo devices should be claimed by parport_serial. 2395 * 2396 * The subdevice ID is of the form 0x00PS, where <P> is the number 2397 * of parallel ports and <S> is the number of serial ports. 2398 */ 2399 switch (dev->device) { 2400 case PCI_DEVICE_ID_NETMOS_9835: 2401 /* Well, this rule doesn't hold for the following 9835 device */ 2402 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2403 dev->subsystem_device == 0x0299) 2404 return; 2405 fallthrough; 2406 case PCI_DEVICE_ID_NETMOS_9735: 2407 case PCI_DEVICE_ID_NETMOS_9745: 2408 case PCI_DEVICE_ID_NETMOS_9845: 2409 case PCI_DEVICE_ID_NETMOS_9855: 2410 if (num_parallel) { 2411 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2412 dev->device, num_parallel, num_serial); 2413 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2414 (dev->class & 0xff); 2415 } 2416 } 2417 } 2418 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2419 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2420 2421 static void quirk_e100_interrupt(struct pci_dev *dev) 2422 { 2423 u16 command, pmcsr; 2424 u8 __iomem *csr; 2425 u8 cmd_hi; 2426 2427 switch (dev->device) { 2428 /* PCI IDs taken from drivers/net/e100.c */ 2429 case 0x1029: 2430 case 0x1030 ... 0x1034: 2431 case 0x1038 ... 0x103E: 2432 case 0x1050 ... 0x1057: 2433 case 0x1059: 2434 case 0x1064 ... 0x106B: 2435 case 0x1091 ... 0x1095: 2436 case 0x1209: 2437 case 0x1229: 2438 case 0x2449: 2439 case 0x2459: 2440 case 0x245D: 2441 case 0x27DC: 2442 break; 2443 default: 2444 return; 2445 } 2446 2447 /* 2448 * Some firmware hands off the e100 with interrupts enabled, 2449 * which can cause a flood of interrupts if packets are 2450 * received before the driver attaches to the device. So 2451 * disable all e100 interrupts here. The driver will 2452 * re-enable them when it's ready. 2453 */ 2454 pci_read_config_word(dev, PCI_COMMAND, &command); 2455 2456 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2457 return; 2458 2459 /* 2460 * Check that the device is in the D0 power state. If it's not, 2461 * there is no point to look any further. 2462 */ 2463 if (dev->pm_cap) { 2464 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2465 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2466 return; 2467 } 2468 2469 /* Convert from PCI bus to resource space. */ 2470 csr = ioremap(pci_resource_start(dev, 0), 8); 2471 if (!csr) { 2472 pci_warn(dev, "Can't map e100 registers\n"); 2473 return; 2474 } 2475 2476 cmd_hi = readb(csr + 3); 2477 if (cmd_hi == 0) { 2478 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2479 writeb(1, csr + 3); 2480 } 2481 2482 iounmap(csr); 2483 } 2484 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2485 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2486 2487 /* 2488 * The 82575 and 82598 may experience data corruption issues when transitioning 2489 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2490 */ 2491 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2492 { 2493 pcie_aspm_remove_cap(dev, PCI_EXP_LNKCAP_ASPM_L0S); 2494 } 2495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2509 2510 /* Realtek RTS525A generates a Replay Timer Timeout storm when L0s is enabled. */ 2511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x525a, quirk_disable_aspm_l0s); 2512 2513 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2514 { 2515 pcie_aspm_remove_cap(dev, 2516 PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1); 2517 } 2518 2519 /* 2520 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2521 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2522 * disable both L0s and L1 for now to be safe. 2523 */ 2524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1); 2526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1); 2527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1); 2528 2529 /* 2530 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2531 * Link bit cleared after starting the link retrain process to allow this 2532 * process to finish. 2533 * 2534 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2535 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2536 */ 2537 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2538 { 2539 dev->clear_retrain_link = 1; 2540 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2541 } 2542 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2544 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2545 2546 static void fixup_rev1_53c810(struct pci_dev *dev) 2547 { 2548 u32 class = dev->class; 2549 2550 /* 2551 * rev 1 ncr53c810 chips don't set the class at all which means 2552 * they don't get their resources remapped. Fix that here. 2553 */ 2554 if (class) 2555 return; 2556 2557 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2558 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2559 class, dev->class); 2560 } 2561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2562 2563 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2564 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2565 { 2566 u16 en1k; 2567 2568 pci_read_config_word(dev, 0x40, &en1k); 2569 2570 if (en1k & 0x200) { 2571 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2572 dev->io_window_1k = 1; 2573 } 2574 } 2575 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2576 2577 /* 2578 * Under some circumstances, AER is not linked with extended capabilities. 2579 * Force it to be linked by setting the corresponding control bit in the 2580 * config space. 2581 */ 2582 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2583 { 2584 uint8_t b; 2585 2586 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2587 if (!(b & 0x20)) { 2588 pci_write_config_byte(dev, 0xf41, b | 0x20); 2589 pci_info(dev, "Linking AER extended capability\n"); 2590 } 2591 } 2592 } 2593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2594 quirk_nvidia_ck804_pcie_aer_ext_cap); 2595 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2596 quirk_nvidia_ck804_pcie_aer_ext_cap); 2597 2598 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2599 { 2600 /* 2601 * Disable PCI Bus Parking and PCI Master read caching on CX700 2602 * which causes unspecified timing errors with a VT6212L on the PCI 2603 * bus leading to USB2.0 packet loss. 2604 * 2605 * This quirk is only enabled if a second (on the external PCI bus) 2606 * VT6212L is found -- the CX700 core itself also contains a USB 2607 * host controller with the same PCI ID as the VT6212L. 2608 */ 2609 2610 /* Count VT6212L instances */ 2611 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2612 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2613 uint8_t b; 2614 2615 /* 2616 * p should contain the first (internal) VT6212L -- see if we have 2617 * an external one by searching again. 2618 */ 2619 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2620 if (!p) 2621 return; 2622 pci_dev_put(p); 2623 2624 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2625 if (b & 0x40) { 2626 /* Turn off PCI Bus Parking */ 2627 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2628 2629 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2630 } 2631 } 2632 2633 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2634 if (b != 0) { 2635 /* Turn off PCI Master read caching */ 2636 pci_write_config_byte(dev, 0x72, 0x0); 2637 2638 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2639 pci_write_config_byte(dev, 0x75, 0x1); 2640 2641 /* Disable "Read FIFO Timer" */ 2642 pci_write_config_byte(dev, 0x77, 0x0); 2643 2644 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2645 } 2646 } 2647 } 2648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2649 2650 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2651 { 2652 u32 rev; 2653 2654 pci_read_config_dword(dev, 0xf4, &rev); 2655 2656 /* Only CAP the MRRS if the device is a 5719 A0 */ 2657 if (rev == 0x05719000) { 2658 int readrq = pcie_get_readrq(dev); 2659 if (readrq > 2048) 2660 pcie_set_readrq(dev, 2048); 2661 } 2662 } 2663 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2664 PCI_DEVICE_ID_TIGON3_5719, 2665 quirk_brcm_5719_limit_mrrs); 2666 2667 /* 2668 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2669 * hide device 6 which configures the overflow device access containing the 2670 * DRBs - this is where we expose device 6. 2671 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2672 */ 2673 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2674 { 2675 u8 reg; 2676 2677 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2678 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2679 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2680 } 2681 } 2682 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2683 quirk_unhide_mch_dev6); 2684 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2685 quirk_unhide_mch_dev6); 2686 2687 #ifdef CONFIG_PCI_MSI 2688 /* 2689 * Some chipsets do not support MSI. We cannot easily rely on setting 2690 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2691 * other buses controlled by the chipset even if Linux is not aware of it. 2692 * Instead of setting the flag on all buses in the machine, simply disable 2693 * MSI globally. 2694 */ 2695 static void quirk_disable_all_msi(struct pci_dev *dev) 2696 { 2697 pci_no_msi(); 2698 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2699 } 2700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2709 2710 /* Disable MSI on chipsets that are known to not support it */ 2711 static void quirk_disable_msi(struct pci_dev *dev) 2712 { 2713 if (dev->subordinate) { 2714 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2715 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2716 } 2717 } 2718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); 2722 2723 /* 2724 * The APC bridge device in AMD 780 family northbridges has some random 2725 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2726 * we use the possible vendor/device IDs of the host bridge for the 2727 * declared quirk, and search for the APC bridge by slot number. 2728 */ 2729 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2730 { 2731 struct pci_dev *apc_bridge; 2732 2733 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2734 if (apc_bridge) { 2735 if (apc_bridge->device == 0x9602) 2736 quirk_disable_msi(apc_bridge); 2737 pci_dev_put(apc_bridge); 2738 } 2739 } 2740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2742 2743 /* 2744 * Go through the list of HyperTransport capabilities and return 1 if a HT 2745 * MSI capability is found and enabled. 2746 */ 2747 static int msi_ht_cap_enabled(struct pci_dev *dev) 2748 { 2749 int pos, ttl = PCI_FIND_CAP_TTL; 2750 2751 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2752 while (pos && ttl--) { 2753 u8 flags; 2754 2755 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2756 &flags) == 0) { 2757 pci_info(dev, "Found %s HT MSI Mapping\n", 2758 flags & HT_MSI_FLAGS_ENABLE ? 2759 "enabled" : "disabled"); 2760 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2761 } 2762 2763 pos = pci_find_next_ht_capability(dev, pos, 2764 HT_CAPTYPE_MSI_MAPPING); 2765 } 2766 return 0; 2767 } 2768 2769 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2770 static void quirk_msi_ht_cap(struct pci_dev *dev) 2771 { 2772 if (!msi_ht_cap_enabled(dev)) 2773 quirk_disable_msi(dev); 2774 } 2775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2776 quirk_msi_ht_cap); 2777 2778 /* 2779 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2780 * if the MSI capability is set in any of these mappings. 2781 */ 2782 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2783 { 2784 struct pci_dev *pdev; 2785 2786 /* 2787 * Check HT MSI cap on this chipset and the root one. A single one 2788 * having MSI is enough to be sure that MSI is supported. 2789 */ 2790 pdev = pci_get_slot(dev->bus, 0); 2791 if (!pdev) 2792 return; 2793 if (!msi_ht_cap_enabled(pdev)) 2794 quirk_msi_ht_cap(dev); 2795 pci_dev_put(pdev); 2796 } 2797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2798 quirk_nvidia_ck804_msi_ht_cap); 2799 2800 /* Force enable MSI mapping capability on HT bridges */ 2801 static void ht_enable_msi_mapping(struct pci_dev *dev) 2802 { 2803 int pos, ttl = PCI_FIND_CAP_TTL; 2804 2805 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2806 while (pos && ttl--) { 2807 u8 flags; 2808 2809 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2810 &flags) == 0) { 2811 pci_info(dev, "Enabling HT MSI Mapping\n"); 2812 2813 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2814 flags | HT_MSI_FLAGS_ENABLE); 2815 } 2816 pos = pci_find_next_ht_capability(dev, pos, 2817 HT_CAPTYPE_MSI_MAPPING); 2818 } 2819 } 2820 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2821 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2822 ht_enable_msi_mapping); 2823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2824 ht_enable_msi_mapping); 2825 2826 /* 2827 * The P5N32-SLI motherboards from Asus have a problem with MSI 2828 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2829 * also affects other devices. As for now, turn off MSI for this device. 2830 */ 2831 static void nvenet_msi_disable(struct pci_dev *dev) 2832 { 2833 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2834 2835 if (board_name && 2836 (strstr(board_name, "P5N32-SLI PREMIUM") || 2837 strstr(board_name, "P5N32-E SLI"))) { 2838 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2839 dev->no_msi = 1; 2840 } 2841 } 2842 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2843 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2844 nvenet_msi_disable); 2845 2846 /* 2847 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2848 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2849 * interrupts for PME and AER events; instead only INTx interrupts are 2850 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2851 * for other events, since PCIe specification doesn't support using a mix of 2852 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2853 * service drivers registering their respective ISRs for MSIs. 2854 */ 2855 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2856 { 2857 dev->no_msi = 1; 2858 } 2859 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2860 PCI_CLASS_BRIDGE_PCI, 8, 2861 pci_quirk_nvidia_tegra_disable_rp_msi); 2862 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2863 PCI_CLASS_BRIDGE_PCI, 8, 2864 pci_quirk_nvidia_tegra_disable_rp_msi); 2865 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2866 PCI_CLASS_BRIDGE_PCI, 8, 2867 pci_quirk_nvidia_tegra_disable_rp_msi); 2868 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2869 PCI_CLASS_BRIDGE_PCI, 8, 2870 pci_quirk_nvidia_tegra_disable_rp_msi); 2871 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2872 PCI_CLASS_BRIDGE_PCI, 8, 2873 pci_quirk_nvidia_tegra_disable_rp_msi); 2874 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2875 PCI_CLASS_BRIDGE_PCI, 8, 2876 pci_quirk_nvidia_tegra_disable_rp_msi); 2877 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2878 PCI_CLASS_BRIDGE_PCI, 8, 2879 pci_quirk_nvidia_tegra_disable_rp_msi); 2880 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2881 PCI_CLASS_BRIDGE_PCI, 8, 2882 pci_quirk_nvidia_tegra_disable_rp_msi); 2883 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2884 PCI_CLASS_BRIDGE_PCI, 8, 2885 pci_quirk_nvidia_tegra_disable_rp_msi); 2886 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2887 PCI_CLASS_BRIDGE_PCI, 8, 2888 pci_quirk_nvidia_tegra_disable_rp_msi); 2889 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2890 PCI_CLASS_BRIDGE_PCI, 8, 2891 pci_quirk_nvidia_tegra_disable_rp_msi); 2892 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2893 PCI_CLASS_BRIDGE_PCI, 8, 2894 pci_quirk_nvidia_tegra_disable_rp_msi); 2895 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2896 PCI_CLASS_BRIDGE_PCI, 8, 2897 pci_quirk_nvidia_tegra_disable_rp_msi); 2898 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2899 PCI_CLASS_BRIDGE_PCI, 8, 2900 pci_quirk_nvidia_tegra_disable_rp_msi); 2901 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2902 PCI_CLASS_BRIDGE_PCI, 8, 2903 pci_quirk_nvidia_tegra_disable_rp_msi); 2904 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2905 PCI_CLASS_BRIDGE_PCI, 8, 2906 pci_quirk_nvidia_tegra_disable_rp_msi); 2907 2908 /* 2909 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2910 * config register. This register controls the routing of legacy 2911 * interrupts from devices that route through the MCP55. If this register 2912 * is misprogrammed, interrupts are only sent to the BSP, unlike 2913 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2914 * having this register set properly prevents kdump from booting up 2915 * properly, so let's make sure that we have it set correctly. 2916 * Note that this is an undocumented register. 2917 */ 2918 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2919 { 2920 u32 cfg; 2921 2922 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2923 return; 2924 2925 pci_read_config_dword(dev, 0x74, &cfg); 2926 2927 if (cfg & ((1 << 2) | (1 << 15))) { 2928 pr_info("Rewriting IRQ routing register on MCP55\n"); 2929 cfg &= ~((1 << 2) | (1 << 15)); 2930 pci_write_config_dword(dev, 0x74, cfg); 2931 } 2932 } 2933 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2934 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2935 nvbridge_check_legacy_irq_routing); 2936 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2937 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2938 nvbridge_check_legacy_irq_routing); 2939 2940 static int ht_check_msi_mapping(struct pci_dev *dev) 2941 { 2942 int pos, ttl = PCI_FIND_CAP_TTL; 2943 int found = 0; 2944 2945 /* Check if there is HT MSI cap or enabled on this device */ 2946 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2947 while (pos && ttl--) { 2948 u8 flags; 2949 2950 if (found < 1) 2951 found = 1; 2952 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2953 &flags) == 0) { 2954 if (flags & HT_MSI_FLAGS_ENABLE) { 2955 if (found < 2) { 2956 found = 2; 2957 break; 2958 } 2959 } 2960 } 2961 pos = pci_find_next_ht_capability(dev, pos, 2962 HT_CAPTYPE_MSI_MAPPING); 2963 } 2964 2965 return found; 2966 } 2967 2968 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2969 { 2970 struct pci_dev *dev; 2971 int pos; 2972 int i, dev_no; 2973 int found = 0; 2974 2975 dev_no = host_bridge->devfn >> 3; 2976 for (i = dev_no + 1; i < 0x20; i++) { 2977 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2978 if (!dev) 2979 continue; 2980 2981 /* found next host bridge? */ 2982 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2983 if (pos != 0) { 2984 pci_dev_put(dev); 2985 break; 2986 } 2987 2988 if (ht_check_msi_mapping(dev)) { 2989 found = 1; 2990 pci_dev_put(dev); 2991 break; 2992 } 2993 pci_dev_put(dev); 2994 } 2995 2996 return found; 2997 } 2998 2999 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 3000 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 3001 3002 static int is_end_of_ht_chain(struct pci_dev *dev) 3003 { 3004 int pos, ctrl_off; 3005 int end = 0; 3006 u16 flags, ctrl; 3007 3008 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3009 3010 if (!pos) 3011 goto out; 3012 3013 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 3014 3015 ctrl_off = ((flags >> 10) & 1) ? 3016 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 3017 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 3018 3019 if (ctrl & (1 << 6)) 3020 end = 1; 3021 3022 out: 3023 return end; 3024 } 3025 3026 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3027 { 3028 struct pci_dev *host_bridge; 3029 int pos; 3030 int i, dev_no; 3031 int found = 0; 3032 3033 dev_no = dev->devfn >> 3; 3034 for (i = dev_no; i >= 0; i--) { 3035 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3036 if (!host_bridge) 3037 continue; 3038 3039 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3040 if (pos != 0) { 3041 found = 1; 3042 break; 3043 } 3044 pci_dev_put(host_bridge); 3045 } 3046 3047 if (!found) 3048 return; 3049 3050 /* don't enable end_device/host_bridge with leaf directly here */ 3051 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3052 host_bridge_with_leaf(host_bridge)) 3053 goto out; 3054 3055 /* root did that ! */ 3056 if (msi_ht_cap_enabled(host_bridge)) 3057 goto out; 3058 3059 ht_enable_msi_mapping(dev); 3060 3061 out: 3062 pci_dev_put(host_bridge); 3063 } 3064 3065 static void ht_disable_msi_mapping(struct pci_dev *dev) 3066 { 3067 int pos, ttl = PCI_FIND_CAP_TTL; 3068 3069 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3070 while (pos && ttl--) { 3071 u8 flags; 3072 3073 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3074 &flags) == 0) { 3075 pci_info(dev, "Disabling HT MSI Mapping\n"); 3076 3077 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3078 flags & ~HT_MSI_FLAGS_ENABLE); 3079 } 3080 pos = pci_find_next_ht_capability(dev, pos, 3081 HT_CAPTYPE_MSI_MAPPING); 3082 } 3083 } 3084 3085 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3086 { 3087 struct pci_dev *host_bridge; 3088 int pos; 3089 int found; 3090 3091 if (!pci_msi_enabled()) 3092 return; 3093 3094 /* check if there is HT MSI cap or enabled on this device */ 3095 found = ht_check_msi_mapping(dev); 3096 3097 /* no HT MSI CAP */ 3098 if (found == 0) 3099 return; 3100 3101 /* 3102 * HT MSI mapping should be disabled on devices that are below 3103 * a non-HyperTransport host bridge. Locate the host bridge. 3104 */ 3105 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3106 PCI_DEVFN(0, 0)); 3107 if (host_bridge == NULL) { 3108 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3109 return; 3110 } 3111 3112 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3113 if (pos != 0) { 3114 /* Host bridge is to HT */ 3115 if (found == 1) { 3116 /* it is not enabled, try to enable it */ 3117 if (all) 3118 ht_enable_msi_mapping(dev); 3119 else 3120 nv_ht_enable_msi_mapping(dev); 3121 } 3122 goto out; 3123 } 3124 3125 /* HT MSI is not enabled */ 3126 if (found == 1) 3127 goto out; 3128 3129 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3130 ht_disable_msi_mapping(dev); 3131 3132 out: 3133 pci_dev_put(host_bridge); 3134 } 3135 3136 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3137 { 3138 return __nv_msi_ht_cap_quirk(dev, 1); 3139 } 3140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3141 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3142 3143 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3144 { 3145 return __nv_msi_ht_cap_quirk(dev, 0); 3146 } 3147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3148 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3149 3150 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3151 { 3152 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3153 } 3154 3155 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3156 { 3157 struct pci_dev *p; 3158 3159 /* 3160 * SB700 MSI issue will be fixed at HW level from revision A21; 3161 * we need check PCI REVISION ID of SMBus controller to get SB700 3162 * revision. 3163 */ 3164 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3165 NULL); 3166 if (!p) 3167 return; 3168 3169 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3170 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3171 pci_dev_put(p); 3172 } 3173 3174 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3175 { 3176 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3177 if (dev->revision < 0x18) { 3178 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3179 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3180 } 3181 } 3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3183 PCI_DEVICE_ID_TIGON3_5780, 3184 quirk_msi_intx_disable_bug); 3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3186 PCI_DEVICE_ID_TIGON3_5780S, 3187 quirk_msi_intx_disable_bug); 3188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3189 PCI_DEVICE_ID_TIGON3_5714, 3190 quirk_msi_intx_disable_bug); 3191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3192 PCI_DEVICE_ID_TIGON3_5714S, 3193 quirk_msi_intx_disable_bug); 3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3195 PCI_DEVICE_ID_TIGON3_5715, 3196 quirk_msi_intx_disable_bug); 3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3198 PCI_DEVICE_ID_TIGON3_5715S, 3199 quirk_msi_intx_disable_bug); 3200 3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3202 quirk_msi_intx_disable_ati_bug); 3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3204 quirk_msi_intx_disable_ati_bug); 3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3206 quirk_msi_intx_disable_ati_bug); 3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3208 quirk_msi_intx_disable_ati_bug); 3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3210 quirk_msi_intx_disable_ati_bug); 3211 3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3213 quirk_msi_intx_disable_bug); 3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3215 quirk_msi_intx_disable_bug); 3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3217 quirk_msi_intx_disable_bug); 3218 3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3220 quirk_msi_intx_disable_bug); 3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3222 quirk_msi_intx_disable_bug); 3223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3224 quirk_msi_intx_disable_bug); 3225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3226 quirk_msi_intx_disable_bug); 3227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3228 quirk_msi_intx_disable_bug); 3229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3230 quirk_msi_intx_disable_bug); 3231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3232 quirk_msi_intx_disable_qca_bug); 3233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3234 quirk_msi_intx_disable_qca_bug); 3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3236 quirk_msi_intx_disable_qca_bug); 3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3238 quirk_msi_intx_disable_qca_bug); 3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3240 quirk_msi_intx_disable_qca_bug); 3241 3242 /* 3243 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3244 * should be disabled on platforms where the device (mistakenly) advertises it. 3245 * 3246 * Notice that this quirk also disables MSI (which may work, but hasn't been 3247 * tested), since currently there is no standard way to disable only MSI-X. 3248 * 3249 * The 0031 device id is reused for other non Root Port device types, 3250 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3251 */ 3252 static void quirk_al_msi_disable(struct pci_dev *dev) 3253 { 3254 dev->no_msi = 1; 3255 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3256 } 3257 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3258 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3259 #endif /* CONFIG_PCI_MSI */ 3260 3261 /* 3262 * Allow manual resource allocation for PCI hotplug bridges via 3263 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3264 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3265 * allocate resources when hotplug device is inserted and PCI bus is 3266 * rescanned. 3267 */ 3268 static void quirk_hotplug_bridge(struct pci_dev *dev) 3269 { 3270 dev->is_hotplug_bridge = 1; 3271 } 3272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3273 3274 /* 3275 * This is a quirk for the Ricoh MMC controller found as a part of some 3276 * multifunction chips. 3277 * 3278 * This is very similar and based on the ricoh_mmc driver written by 3279 * Philip Langdale. Thank you for these magic sequences. 3280 * 3281 * These chips implement the four main memory card controllers (SD, MMC, 3282 * MS, xD) and one or both of CardBus or FireWire. 3283 * 3284 * It happens that they implement SD and MMC support as separate 3285 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3286 * cards but the chip detects MMC cards in hardware and directs them to the 3287 * MMC controller - so the SDHCI driver never sees them. 3288 * 3289 * To get around this, we must disable the useless MMC controller. At that 3290 * point, the SDHCI controller will start seeing them. It seems to be the 3291 * case that the relevant PCI registers to deactivate the MMC controller 3292 * live on PCI function 0, which might be the CardBus controller or the 3293 * FireWire controller, depending on the particular chip in question 3294 * 3295 * This has to be done early, because as soon as we disable the MMC controller 3296 * other PCI functions shift up one level, e.g. function #2 becomes function 3297 * #1, and this will confuse the PCI core. 3298 */ 3299 #ifdef CONFIG_MMC_RICOH_MMC 3300 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3301 { 3302 u8 write_enable; 3303 u8 write_target; 3304 u8 disable; 3305 3306 /* 3307 * Disable via CardBus interface 3308 * 3309 * This must be done via function #0 3310 */ 3311 if (PCI_FUNC(dev->devfn)) 3312 return; 3313 3314 pci_read_config_byte(dev, 0xB7, &disable); 3315 if (disable & 0x02) 3316 return; 3317 3318 pci_read_config_byte(dev, 0x8E, &write_enable); 3319 pci_write_config_byte(dev, 0x8E, 0xAA); 3320 pci_read_config_byte(dev, 0x8D, &write_target); 3321 pci_write_config_byte(dev, 0x8D, 0xB7); 3322 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3323 pci_write_config_byte(dev, 0x8E, write_enable); 3324 pci_write_config_byte(dev, 0x8D, write_target); 3325 3326 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3327 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3328 } 3329 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3330 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3331 3332 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3333 { 3334 u8 write_enable; 3335 u8 disable; 3336 3337 /* 3338 * Disable via FireWire interface 3339 * 3340 * This must be done via function #0 3341 */ 3342 if (PCI_FUNC(dev->devfn)) 3343 return; 3344 /* 3345 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3346 * certain types of SD/MMC cards. Lowering the SD base clock 3347 * frequency from 200Mhz to 50Mhz fixes this issue. 3348 * 3349 * 0x150 - SD2.0 mode enable for changing base clock 3350 * frequency to 50Mhz 3351 * 0xe1 - Base clock frequency 3352 * 0x32 - 50Mhz new clock frequency 3353 * 0xf9 - Key register for 0x150 3354 * 0xfc - key register for 0xe1 3355 */ 3356 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3357 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3358 pci_write_config_byte(dev, 0xf9, 0xfc); 3359 pci_write_config_byte(dev, 0x150, 0x10); 3360 pci_write_config_byte(dev, 0xf9, 0x00); 3361 pci_write_config_byte(dev, 0xfc, 0x01); 3362 pci_write_config_byte(dev, 0xe1, 0x32); 3363 pci_write_config_byte(dev, 0xfc, 0x00); 3364 3365 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3366 } 3367 3368 pci_read_config_byte(dev, 0xCB, &disable); 3369 3370 if (disable & 0x02) 3371 return; 3372 3373 pci_read_config_byte(dev, 0xCA, &write_enable); 3374 pci_write_config_byte(dev, 0xCA, 0x57); 3375 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3376 pci_write_config_byte(dev, 0xCA, write_enable); 3377 3378 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3379 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3380 3381 } 3382 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3383 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3384 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3385 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3386 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3387 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3388 #endif /*CONFIG_MMC_RICOH_MMC*/ 3389 3390 #ifdef CONFIG_DMAR_TABLE 3391 #define VTUNCERRMSK_REG 0x1ac 3392 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3393 /* 3394 * This is a quirk for masking VT-d spec-defined errors to platform error 3395 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3396 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3397 * on the RAS config settings of the platform) when a VT-d fault happens. 3398 * The resulting SMI caused the system to hang. 3399 * 3400 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3401 * need to report the same error through other channels. 3402 */ 3403 static void vtd_mask_spec_errors(struct pci_dev *dev) 3404 { 3405 u32 word; 3406 3407 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3408 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3409 } 3410 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3411 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3412 #endif 3413 3414 static void fixup_ti816x_class(struct pci_dev *dev) 3415 { 3416 u32 class = dev->class; 3417 3418 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3419 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3420 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3421 class, dev->class); 3422 } 3423 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3424 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3425 3426 /* 3427 * Some PCIe devices do not work reliably with the claimed maximum 3428 * payload size supported. 3429 */ 3430 static void fixup_mpss_256(struct pci_dev *dev) 3431 { 3432 dev->pcie_mpss = 1; /* 256 bytes */ 3433 } 3434 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3435 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3436 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3437 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3438 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3439 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3440 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3441 3442 /* 3443 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3444 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3445 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3446 * until all of the devices are discovered and buses walked, read completion 3447 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3448 * it is possible to hotplug a device with MPS of 256B. 3449 */ 3450 static void quirk_intel_mc_errata(struct pci_dev *dev) 3451 { 3452 int err; 3453 u16 rcc; 3454 3455 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3456 pcie_bus_config == PCIE_BUS_DEFAULT) 3457 return; 3458 3459 /* 3460 * Intel erratum specifies bits to change but does not say what 3461 * they are. Keeping them magical until such time as the registers 3462 * and values can be explained. 3463 */ 3464 err = pci_read_config_word(dev, 0x48, &rcc); 3465 if (err) { 3466 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3467 return; 3468 } 3469 3470 if (!(rcc & (1 << 10))) 3471 return; 3472 3473 rcc &= ~(1 << 10); 3474 3475 err = pci_write_config_word(dev, 0x48, rcc); 3476 if (err) { 3477 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3478 return; 3479 } 3480 3481 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3482 } 3483 /* Intel 5000 series memory controllers and ports 2-7 */ 3484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3498 /* Intel 5100 series memory controllers and ports 2-7 */ 3499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3510 3511 /* 3512 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3513 * To work around this, query the size it should be configured to by the 3514 * device and modify the resource end to correspond to this new size. 3515 */ 3516 static void quirk_intel_ntb(struct pci_dev *dev) 3517 { 3518 int rc; 3519 u8 val; 3520 3521 rc = pci_read_config_byte(dev, 0x00D0, &val); 3522 if (rc) 3523 return; 3524 3525 resource_set_size(&dev->resource[2], (resource_size_t)1 << val); 3526 3527 rc = pci_read_config_byte(dev, 0x00D1, &val); 3528 if (rc) 3529 return; 3530 3531 resource_set_size(&dev->resource[4], (resource_size_t)1 << val); 3532 } 3533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3535 3536 /* 3537 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3538 * though no one is handling them (e.g., if the i915 driver is never 3539 * loaded). Additionally the interrupt destination is not set up properly 3540 * and the interrupt ends up -somewhere-. 3541 * 3542 * These spurious interrupts are "sticky" and the kernel disables the 3543 * (shared) interrupt line after 100,000+ generated interrupts. 3544 * 3545 * Fix it by disabling the still enabled interrupts. This resolves crashes 3546 * often seen on monitor unplug. 3547 */ 3548 #define I915_DEIER_REG 0x4400c 3549 static void disable_igfx_irq(struct pci_dev *dev) 3550 { 3551 void __iomem *regs = pci_iomap(dev, 0, 0); 3552 if (regs == NULL) { 3553 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3554 return; 3555 } 3556 3557 /* Check if any interrupt line is still enabled */ 3558 if (readl(regs + I915_DEIER_REG) != 0) { 3559 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3560 3561 writel(0, regs + I915_DEIER_REG); 3562 } 3563 3564 pci_iounmap(dev, regs); 3565 } 3566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3573 3574 /* 3575 * PCI devices which are on Intel chips can skip the 10ms delay 3576 * before entering D3 mode. 3577 */ 3578 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3579 { 3580 dev->d3hot_delay = 0; 3581 } 3582 /* C600 Series devices do not need 10ms d3hot_delay */ 3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3586 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3598 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3608 3609 /* 3610 * Some devices may pass our check in pci_intx_mask_supported() if 3611 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3612 * support this feature. 3613 */ 3614 static void quirk_broken_intx_masking(struct pci_dev *dev) 3615 { 3616 dev->broken_intx_masking = 1; 3617 } 3618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3619 quirk_broken_intx_masking); 3620 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3621 quirk_broken_intx_masking); 3622 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3623 quirk_broken_intx_masking); 3624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, 3625 quirk_broken_intx_masking); 3626 3627 /* 3628 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3629 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3630 * 3631 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3632 */ 3633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3634 quirk_broken_intx_masking); 3635 3636 /* 3637 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3638 * DisINTx can be set but the interrupt status bit is non-functional. 3639 */ 3640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3656 3657 static u16 mellanox_broken_intx_devs[] = { 3658 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3659 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3660 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3661 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3662 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3663 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3664 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3665 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3666 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3667 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3668 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3669 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3670 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3671 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3672 }; 3673 3674 #define CONNECTX_4_CURR_MAX_MINOR 99 3675 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3676 3677 /* 3678 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3679 * If so, don't mark it as broken. 3680 * FW minor > 99 means older FW version format and no INTx masking support. 3681 * FW minor < 14 means new FW version format and no INTx masking support. 3682 */ 3683 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3684 { 3685 __be32 __iomem *fw_ver; 3686 u16 fw_major; 3687 u16 fw_minor; 3688 u16 fw_subminor; 3689 u32 fw_maj_min; 3690 u32 fw_sub_min; 3691 int i; 3692 3693 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3694 if (pdev->device == mellanox_broken_intx_devs[i]) { 3695 pdev->broken_intx_masking = 1; 3696 return; 3697 } 3698 } 3699 3700 /* 3701 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3702 * support so shouldn't be checked further 3703 */ 3704 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3705 return; 3706 3707 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3708 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3709 return; 3710 3711 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3712 if (pci_enable_device_mem(pdev)) { 3713 pci_warn(pdev, "Can't enable device memory\n"); 3714 return; 3715 } 3716 3717 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3718 if (!fw_ver) { 3719 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3720 goto out; 3721 } 3722 3723 /* Reading from resource space should be 32b aligned */ 3724 fw_maj_min = ioread32be(fw_ver); 3725 fw_sub_min = ioread32be(fw_ver + 1); 3726 fw_major = fw_maj_min & 0xffff; 3727 fw_minor = fw_maj_min >> 16; 3728 fw_subminor = fw_sub_min & 0xffff; 3729 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3730 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3731 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3732 fw_major, fw_minor, fw_subminor, pdev->device == 3733 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3734 pdev->broken_intx_masking = 1; 3735 } 3736 3737 iounmap(fw_ver); 3738 3739 out: 3740 pci_disable_device(pdev); 3741 } 3742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3743 mellanox_check_broken_intx_masking); 3744 3745 static void quirk_no_bus_reset(struct pci_dev *dev) 3746 { 3747 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3748 } 3749 3750 /* 3751 * After asserting Secondary Bus Reset to downstream devices via a GB10 3752 * Root Port, the link may not retrain correctly. 3753 * https://lore.kernel.org/r/20251113084441.2124737-1-Johnny-CC.Chang@mediatek.com 3754 */ 3755 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22CE, quirk_no_bus_reset); 3756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22D0, quirk_no_bus_reset); 3757 3758 /* 3759 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3760 * prevented for those affected devices. 3761 */ 3762 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3763 { 3764 if ((dev->device & 0xffc0) == 0x2340) 3765 quirk_no_bus_reset(dev); 3766 } 3767 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3768 quirk_nvidia_no_bus_reset); 3769 3770 /* 3771 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3772 * The device will throw a Link Down error on AER-capable systems and 3773 * regardless of AER, config space of the device is never accessible again 3774 * and typically causes the system to hang or reset when access is attempted. 3775 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3776 */ 3777 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3778 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3779 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3780 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3781 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3782 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3783 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1103, quirk_no_bus_reset); /* WCN6855 */ 3784 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1107, quirk_no_bus_reset); /* WCN7850 */ 3785 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x0308, quirk_no_bus_reset); /* SDX62/SDX65 */ 3786 3787 /* 3788 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3789 * reset when used with certain child devices. After the reset, config 3790 * accesses to the child may fail. 3791 */ 3792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3793 3794 /* 3795 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3796 * automatically disables LTSSM when Secondary Bus Reset is received and 3797 * the device stops working. Prevent bus reset for these devices. With 3798 * this change, the device can be assigned to VMs with VFIO, but it will 3799 * leak state between VMs. Reference 3800 * https://e2e.ti.com/support/processors/f/791/t/954382 3801 */ 3802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3803 3804 /* 3805 * Reports from users making use of PCI device assignment with ASM1164 3806 * controllers indicate an issue with bus reset where the device fails to 3807 * retrain. The issue appears more common in configurations with multiple 3808 * controllers. The device does indicate PM reset support (NoSoftRst-), 3809 * therefore this still leaves a viable reset method. 3810 * https://forum.proxmox.com/threads/problems-with-pcie-passthrough-with-two-identical-devices.149003/ 3811 */ 3812 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1164, quirk_no_bus_reset); 3813 3814 static void quirk_no_pm_reset(struct pci_dev *dev) 3815 { 3816 /* 3817 * We can't do a bus reset on root bus devices, but an ineffective 3818 * PM reset may be better than nothing. 3819 */ 3820 if (!pci_is_root_bus(dev->bus)) 3821 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3822 } 3823 3824 /* 3825 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3826 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3827 * to have no effect on the device: it retains the framebuffer contents and 3828 * monitor sync. Advertising this support makes other layers, like VFIO, 3829 * assume pci_reset_function() is viable for this device. Mark it as 3830 * unavailable to skip it when testing reset methods. 3831 */ 3832 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3833 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3834 3835 /* 3836 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3837 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3838 * any effect on the device: It continues to be operational and network ports 3839 * remain up. Advertising this support makes it seem as if a PM reset is viable 3840 * for these devices. Mark it as unavailable to skip it when testing reset 3841 * methods. 3842 */ 3843 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3844 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3845 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3847 3848 /* 3849 * Thunderbolt controllers with broken MSI hotplug signaling: 3850 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3851 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3852 */ 3853 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3854 { 3855 if (pdev->is_pciehp && 3856 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3857 pdev->revision <= 1)) 3858 pdev->no_msi = 1; 3859 } 3860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3861 quirk_thunderbolt_hotplug_msi); 3862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3863 quirk_thunderbolt_hotplug_msi); 3864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3865 quirk_thunderbolt_hotplug_msi); 3866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3867 quirk_thunderbolt_hotplug_msi); 3868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3869 quirk_thunderbolt_hotplug_msi); 3870 3871 #ifdef CONFIG_ACPI 3872 /* 3873 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3874 * 3875 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3876 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3877 * be present after resume if a device was plugged in before suspend. 3878 * 3879 * The Thunderbolt controller consists of a PCIe switch with downstream 3880 * bridges leading to the NHI and to the tunnel PCI bridges. 3881 * 3882 * This quirk cuts power to the whole chip. Therefore we have to apply it 3883 * during suspend_noirq of the upstream bridge. 3884 * 3885 * Power is automagically restored before resume. No action is needed. 3886 */ 3887 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3888 { 3889 acpi_handle bridge, SXIO, SXFP, SXLV; 3890 3891 if (!x86_apple_machine) 3892 return; 3893 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3894 return; 3895 3896 /* 3897 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3898 * We don't know how to turn it back on again, but firmware does, 3899 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3900 * firmware. 3901 */ 3902 if (!pm_suspend_via_firmware()) 3903 return; 3904 3905 bridge = ACPI_HANDLE(&dev->dev); 3906 if (!bridge) 3907 return; 3908 3909 /* 3910 * SXIO and SXLV are present only on machines requiring this quirk. 3911 * Thunderbolt bridges in external devices might have the same 3912 * device ID as those on the host, but they will not have the 3913 * associated ACPI methods. This implicitly checks that we are at 3914 * the right bridge. 3915 */ 3916 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3917 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3918 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3919 return; 3920 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3921 3922 /* magic sequence */ 3923 acpi_execute_simple_method(SXIO, NULL, 1); 3924 acpi_execute_simple_method(SXFP, NULL, 0); 3925 msleep(300); 3926 acpi_execute_simple_method(SXLV, NULL, 0); 3927 acpi_execute_simple_method(SXIO, NULL, 0); 3928 acpi_execute_simple_method(SXLV, NULL, 0); 3929 } 3930 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3931 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3932 quirk_apple_poweroff_thunderbolt); 3933 #endif 3934 3935 /* 3936 * Following are device-specific reset methods which can be used to 3937 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3938 * not available. 3939 */ 3940 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3941 { 3942 /* 3943 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3944 * 3945 * The 82599 supports FLR on VFs, but FLR support is reported only 3946 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3947 * Thus we must call pcie_flr() directly without first checking if it is 3948 * supported. 3949 */ 3950 if (!probe) 3951 pcie_flr(dev); 3952 return 0; 3953 } 3954 3955 #define SOUTH_CHICKEN2 0xc2004 3956 #define PCH_PP_STATUS 0xc7200 3957 #define PCH_PP_CONTROL 0xc7204 3958 #define MSG_CTL 0x45010 3959 #define NSDE_PWR_STATE 0xd0100 3960 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3961 3962 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3963 { 3964 void __iomem *mmio_base; 3965 unsigned long timeout; 3966 u32 val; 3967 3968 if (probe) 3969 return 0; 3970 3971 mmio_base = pci_iomap(dev, 0, 0); 3972 if (!mmio_base) 3973 return -ENOMEM; 3974 3975 iowrite32(0x00000002, mmio_base + MSG_CTL); 3976 3977 /* 3978 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3979 * driver loaded sets the right bits. However, this's a reset and 3980 * the bits have been set by i915 previously, so we clobber 3981 * SOUTH_CHICKEN2 register directly here. 3982 */ 3983 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3984 3985 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3986 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3987 3988 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3989 do { 3990 val = ioread32(mmio_base + PCH_PP_STATUS); 3991 if ((val & 0xb0000000) == 0) 3992 goto reset_complete; 3993 msleep(10); 3994 } while (time_before(jiffies, timeout)); 3995 pci_warn(dev, "timeout during reset\n"); 3996 3997 reset_complete: 3998 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3999 4000 pci_iounmap(dev, mmio_base); 4001 return 0; 4002 } 4003 4004 /* Device-specific reset method for Chelsio T4-based adapters */ 4005 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 4006 { 4007 u16 old_command; 4008 u16 msix_flags; 4009 4010 /* 4011 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 4012 * that we have no device-specific reset method. 4013 */ 4014 if ((dev->device & 0xf000) != 0x4000) 4015 return -ENOTTY; 4016 4017 /* 4018 * If this is the "probe" phase, return 0 indicating that we can 4019 * reset this device. 4020 */ 4021 if (probe) 4022 return 0; 4023 4024 /* 4025 * T4 can wedge if there are DMAs in flight within the chip and Bus 4026 * Master has been disabled. We need to have it on till the Function 4027 * Level Reset completes. (BUS_MASTER is disabled in 4028 * pci_reset_function()). 4029 */ 4030 pci_read_config_word(dev, PCI_COMMAND, &old_command); 4031 pci_write_config_word(dev, PCI_COMMAND, 4032 old_command | PCI_COMMAND_MASTER); 4033 4034 /* 4035 * Perform the actual device function reset, saving and restoring 4036 * configuration information around the reset. 4037 */ 4038 pci_save_state(dev); 4039 4040 /* 4041 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 4042 * are disabled when an MSI-X interrupt message needs to be delivered. 4043 * So we briefly re-enable MSI-X interrupts for the duration of the 4044 * FLR. The pci_restore_state() below will restore the original 4045 * MSI-X state. 4046 */ 4047 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 4048 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 4049 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 4050 msix_flags | 4051 PCI_MSIX_FLAGS_ENABLE | 4052 PCI_MSIX_FLAGS_MASKALL); 4053 4054 pcie_flr(dev); 4055 4056 /* 4057 * Restore the configuration information (BAR values, etc.) including 4058 * the original PCI Configuration Space Command word, and return 4059 * success. 4060 */ 4061 pci_restore_state(dev); 4062 pci_write_config_word(dev, PCI_COMMAND, old_command); 4063 return 0; 4064 } 4065 4066 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4067 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4068 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4069 4070 /* 4071 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4072 * FLR where config space reads from the device return -1. We seem to be 4073 * able to avoid this condition if we disable the NVMe controller prior to 4074 * FLR. This quirk is generic for any NVMe class device requiring similar 4075 * assistance to quiesce the device prior to FLR. 4076 * 4077 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4078 * Revision 1.0e: 4079 * Chapter 2: Required and optional PCI config registers 4080 * Chapter 3: NVMe control registers 4081 * Chapter 7.3: Reset behavior 4082 */ 4083 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4084 { 4085 void __iomem *bar; 4086 u16 cmd; 4087 u32 cfg; 4088 4089 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4090 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4091 return -ENOTTY; 4092 4093 if (probe) 4094 return 0; 4095 4096 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4097 if (!bar) 4098 return -ENOTTY; 4099 4100 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4101 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4102 4103 cfg = readl(bar + NVME_REG_CC); 4104 4105 /* Disable controller if enabled */ 4106 if (cfg & NVME_CC_ENABLE) { 4107 u32 cap = readl(bar + NVME_REG_CAP); 4108 unsigned long timeout; 4109 4110 /* 4111 * Per nvme_disable_ctrl() skip shutdown notification as it 4112 * could complete commands to the admin queue. We only intend 4113 * to quiesce the device before reset. 4114 */ 4115 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4116 4117 writel(cfg, bar + NVME_REG_CC); 4118 4119 /* 4120 * Some controllers require an additional delay here, see 4121 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4122 * supported by this quirk. 4123 */ 4124 4125 /* Cap register provides max timeout in 500ms increments */ 4126 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4127 4128 for (;;) { 4129 u32 status = readl(bar + NVME_REG_CSTS); 4130 4131 /* Ready status becomes zero on disable complete */ 4132 if (!(status & NVME_CSTS_RDY)) 4133 break; 4134 4135 msleep(100); 4136 4137 if (time_after(jiffies, timeout)) { 4138 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4139 break; 4140 } 4141 } 4142 } 4143 4144 pci_iounmap(dev, bar); 4145 4146 pcie_flr(dev); 4147 4148 return 0; 4149 } 4150 4151 /* 4152 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4153 * timeout waiting for ready status to change after NVMe enable if the driver 4154 * starts interacting with the device too soon after FLR. A 250ms delay after 4155 * FLR has heuristically proven to produce reliably working results for device 4156 * assignment cases. 4157 */ 4158 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4159 { 4160 if (probe) 4161 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4162 4163 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4164 4165 msleep(250); 4166 4167 return 0; 4168 } 4169 4170 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4171 #define HINIC_VF_FLR_TYPE 0x1000 4172 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4173 #define HINIC_VF_OP 0xE80 4174 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4175 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4176 4177 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4178 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4179 { 4180 unsigned long timeout; 4181 void __iomem *bar; 4182 u32 val; 4183 4184 if (probe) 4185 return 0; 4186 4187 bar = pci_iomap(pdev, 0, 0); 4188 if (!bar) 4189 return -ENOTTY; 4190 4191 /* Get and check firmware capabilities */ 4192 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4193 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4194 pci_iounmap(pdev, bar); 4195 return -ENOTTY; 4196 } 4197 4198 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4199 val = ioread32be(bar + HINIC_VF_OP); 4200 val = val | HINIC_VF_FLR_PROC_BIT; 4201 iowrite32be(val, bar + HINIC_VF_OP); 4202 4203 pcie_flr(pdev); 4204 4205 /* 4206 * The device must recapture its Bus and Device Numbers after FLR 4207 * in order generate Completions. Issue a config write to let the 4208 * device capture this information. 4209 */ 4210 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4211 4212 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4213 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4214 do { 4215 val = ioread32be(bar + HINIC_VF_OP); 4216 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4217 goto reset_complete; 4218 msleep(20); 4219 } while (time_before(jiffies, timeout)); 4220 4221 val = ioread32be(bar + HINIC_VF_OP); 4222 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4223 goto reset_complete; 4224 4225 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4226 4227 reset_complete: 4228 pci_iounmap(pdev, bar); 4229 4230 return 0; 4231 } 4232 4233 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4234 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4235 reset_intel_82599_sfp_virtfn }, 4236 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4237 reset_ivb_igd }, 4238 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4239 reset_ivb_igd }, 4240 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4241 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4242 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4243 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4244 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4245 reset_chelsio_generic_dev }, 4246 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4247 reset_hinic_vf_dev }, 4248 { 0 } 4249 }; 4250 4251 static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, 4252 const struct pci_dev_reset_methods *i) 4253 { 4254 int ret; 4255 4256 ret = pci_dev_reset_iommu_prepare(dev); 4257 if (ret) { 4258 pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); 4259 return ret; 4260 } 4261 4262 ret = i->reset(dev, probe); 4263 pci_dev_reset_iommu_done(dev); 4264 return ret; 4265 } 4266 4267 /* 4268 * These device-specific reset methods are here rather than in a driver 4269 * because when a host assigns a device to a guest VM, the host may need 4270 * to reset the device but probably doesn't have a driver for it. 4271 */ 4272 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4273 { 4274 const struct pci_dev_reset_methods *i; 4275 4276 for (i = pci_dev_reset_methods; i->reset; i++) { 4277 if ((i->vendor == dev->vendor || 4278 i->vendor == (u16)PCI_ANY_ID) && 4279 (i->device == dev->device || 4280 i->device == (u16)PCI_ANY_ID)) 4281 return __pci_dev_specific_reset(dev, probe, i); 4282 } 4283 4284 return -ENOTTY; 4285 } 4286 4287 static void quirk_dma_func0_alias(struct pci_dev *dev) 4288 { 4289 if (PCI_FUNC(dev->devfn) != 0) 4290 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4291 } 4292 4293 /* 4294 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4295 * 4296 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4297 */ 4298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4300 4301 /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ 4302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); 4303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); 4304 4305 static void quirk_dma_func1_alias(struct pci_dev *dev) 4306 { 4307 if (PCI_FUNC(dev->devfn) != 1) 4308 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4309 } 4310 4311 /* 4312 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4313 * SKUs function 1 is present and is a legacy IDE controller, in other 4314 * SKUs this function is not present, making this a ghost requester. 4315 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4316 */ 4317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4318 quirk_dma_func1_alias); 4319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4320 quirk_dma_func1_alias); 4321 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4323 quirk_dma_func1_alias); 4324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4325 quirk_dma_func1_alias); 4326 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4328 quirk_dma_func1_alias); 4329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4330 quirk_dma_func1_alias); 4331 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4333 quirk_dma_func1_alias); 4334 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4336 quirk_dma_func1_alias); 4337 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4339 quirk_dma_func1_alias); 4340 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4342 quirk_dma_func1_alias); 4343 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4345 quirk_dma_func1_alias); 4346 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4348 quirk_dma_func1_alias); 4349 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4351 quirk_dma_func1_alias); 4352 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4354 quirk_dma_func1_alias); 4355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4356 quirk_dma_func1_alias); 4357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4358 quirk_dma_func1_alias); 4359 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4360 quirk_dma_func1_alias); 4361 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4363 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4364 quirk_dma_func1_alias); 4365 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4366 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4367 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4368 quirk_dma_func1_alias); 4369 4370 /* 4371 * Some devices DMA with the wrong devfn, not just the wrong function. 4372 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4373 * the alias is "fixed" and independent of the device devfn. 4374 * 4375 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4376 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4377 * single device on the secondary bus. In reality, the single exposed 4378 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4379 * that provides a bridge to the internal bus of the I/O processor. The 4380 * controller supports private devices, which can be hidden from PCI config 4381 * space. In the case of the Adaptec 3405, a private device at 01.0 4382 * appears to be the DMA engine, which therefore needs to become a DMA 4383 * alias for the device. 4384 */ 4385 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4386 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4387 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4388 .driver_data = PCI_DEVFN(1, 0) }, 4389 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4390 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4391 .driver_data = PCI_DEVFN(1, 0) }, 4392 { 0 } 4393 }; 4394 4395 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4396 { 4397 const struct pci_device_id *id; 4398 4399 id = pci_match_id(fixed_dma_alias_tbl, dev); 4400 if (id) 4401 pci_add_dma_alias(dev, id->driver_data, 1); 4402 } 4403 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4404 4405 /* 4406 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4407 * using the wrong DMA alias for the device. Some of these devices can be 4408 * used as either forward or reverse bridges, so we need to test whether the 4409 * device is operating in the correct mode. We could probably apply this 4410 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4411 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4412 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4413 */ 4414 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4415 { 4416 if (!pci_is_root_bus(pdev->bus) && 4417 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4418 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4419 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4420 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4421 } 4422 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4424 quirk_use_pcie_bridge_dma_alias); 4425 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4426 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4427 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4428 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4429 /* ITE 8893 has the same problem as the 8892 */ 4430 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4431 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4432 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4433 4434 /* 4435 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4436 * be added as aliases to the DMA device in order to allow buffer access 4437 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4438 * programmed in the EEPROM. 4439 */ 4440 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4441 { 4442 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4443 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4444 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4445 } 4446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4448 4449 /* 4450 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4451 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4452 * 4453 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4454 * when IOMMU is enabled. These aliases allow computational unit access to 4455 * host memory. These aliases mark the whole VCA device as one IOMMU 4456 * group. 4457 * 4458 * All possible slot numbers (0x20) are used, since we are unable to tell 4459 * what slot is used on other side. This quirk is intended for both host 4460 * and computational unit sides. The VCA devices have up to five functions 4461 * (four for DMA channels and one additional). 4462 */ 4463 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4464 { 4465 const unsigned int num_pci_slots = 0x20; 4466 unsigned int slot; 4467 4468 for (slot = 0; slot < num_pci_slots; slot++) 4469 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4470 } 4471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4476 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4477 4478 /* 4479 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4480 * associated not at the root bus, but at a bridge below. This quirk avoids 4481 * generating invalid DMA aliases. 4482 */ 4483 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4484 { 4485 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4486 } 4487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4488 quirk_bridge_cavm_thrx2_pcie_root); 4489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4490 quirk_bridge_cavm_thrx2_pcie_root); 4491 4492 /* 4493 * AST1150 doesn't use a real PCI bus and always forwards the requester ID 4494 * from downstream devices. 4495 */ 4496 static void quirk_aspeed_pci_bridge_no_alias(struct pci_dev *pdev) 4497 { 4498 pdev->dev_flags |= PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS; 4499 } 4500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASPEED, 0x1150, quirk_aspeed_pci_bridge_no_alias); 4501 4502 /* 4503 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4504 * class code. Fix it. 4505 */ 4506 static void quirk_tw686x_class(struct pci_dev *pdev) 4507 { 4508 u32 class = pdev->class; 4509 4510 /* Use "Multimedia controller" class */ 4511 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4512 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4513 class, pdev->class); 4514 } 4515 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4516 quirk_tw686x_class); 4517 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4518 quirk_tw686x_class); 4519 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4520 quirk_tw686x_class); 4521 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4522 quirk_tw686x_class); 4523 4524 /* 4525 * Some devices have problems with Transaction Layer Packets with the Relaxed 4526 * Ordering Attribute set. Such devices should mark themselves and other 4527 * device drivers should check before sending TLPs with RO set. 4528 */ 4529 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4530 { 4531 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4532 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4533 } 4534 4535 /* 4536 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4537 * Complex have a Flow Control Credit issue which can cause performance 4538 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4539 */ 4540 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4541 quirk_relaxedordering_disable); 4542 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4543 quirk_relaxedordering_disable); 4544 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4545 quirk_relaxedordering_disable); 4546 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4547 quirk_relaxedordering_disable); 4548 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4549 quirk_relaxedordering_disable); 4550 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4551 quirk_relaxedordering_disable); 4552 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4553 quirk_relaxedordering_disable); 4554 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4555 quirk_relaxedordering_disable); 4556 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4557 quirk_relaxedordering_disable); 4558 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4559 quirk_relaxedordering_disable); 4560 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4561 quirk_relaxedordering_disable); 4562 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4563 quirk_relaxedordering_disable); 4564 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4565 quirk_relaxedordering_disable); 4566 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4567 quirk_relaxedordering_disable); 4568 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4569 quirk_relaxedordering_disable); 4570 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4571 quirk_relaxedordering_disable); 4572 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4573 quirk_relaxedordering_disable); 4574 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4575 quirk_relaxedordering_disable); 4576 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4577 quirk_relaxedordering_disable); 4578 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4579 quirk_relaxedordering_disable); 4580 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4581 quirk_relaxedordering_disable); 4582 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4583 quirk_relaxedordering_disable); 4584 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4585 quirk_relaxedordering_disable); 4586 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4587 quirk_relaxedordering_disable); 4588 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4589 quirk_relaxedordering_disable); 4590 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4591 quirk_relaxedordering_disable); 4592 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4593 quirk_relaxedordering_disable); 4594 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4595 quirk_relaxedordering_disable); 4596 4597 /* 4598 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4599 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4600 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4601 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4602 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4603 * November 10, 2010). As a result, on this platform we can't use Relaxed 4604 * Ordering for Upstream TLPs. 4605 */ 4606 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4607 quirk_relaxedordering_disable); 4608 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4609 quirk_relaxedordering_disable); 4610 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4611 quirk_relaxedordering_disable); 4612 4613 /* 4614 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4615 * values for the Attribute as were supplied in the header of the 4616 * corresponding Request, except as explicitly allowed when IDO is used." 4617 * 4618 * If a non-compliant device generates a completion with a different 4619 * attribute than the request, the receiver may accept it (which itself 4620 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4621 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4622 * device access timeout. 4623 * 4624 * If the non-compliant device generates completions with zero attributes 4625 * (instead of copying the attributes from the request), we can work around 4626 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4627 * upstream devices so they always generate requests with zero attributes. 4628 * 4629 * This affects other devices under the same Root Port, but since these 4630 * attributes are performance hints, there should be no functional problem. 4631 * 4632 * Note that Configuration Space accesses are never supposed to have TLP 4633 * Attributes, so we're safe waiting till after any Configuration Space 4634 * accesses to do the Root Port fixup. 4635 */ 4636 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4637 { 4638 struct pci_dev *root_port = pcie_find_root_port(pdev); 4639 4640 if (!root_port) { 4641 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4642 return; 4643 } 4644 4645 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4646 dev_name(&pdev->dev)); 4647 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL, 4648 PCI_EXP_DEVCTL_RELAX_EN | 4649 PCI_EXP_DEVCTL_NOSNOOP_EN); 4650 } 4651 4652 /* 4653 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4654 * Completion it generates. 4655 */ 4656 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4657 { 4658 /* 4659 * This mask/compare operation selects for Physical Function 4 on a 4660 * T5. We only need to fix up the Root Port once for any of the 4661 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4662 * 0x54xx so we use that one. 4663 */ 4664 if ((pdev->device & 0xff00) == 0x5400) 4665 quirk_disable_root_port_attributes(pdev); 4666 } 4667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4668 quirk_chelsio_T5_disable_root_port_attributes); 4669 4670 /* 4671 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4672 * by a device 4673 * @acs_ctrl_req: Bitmask of desired ACS controls 4674 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4675 * the hardware design 4676 * 4677 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4678 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4679 * caller desires. Return 0 otherwise. 4680 */ 4681 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4682 { 4683 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4684 return 1; 4685 return 0; 4686 } 4687 4688 /* 4689 * AMD has indicated that the devices below do not support peer-to-peer 4690 * in any system where they are found in the southbridge with an AMD 4691 * IOMMU in the system. Multifunction devices that do not support 4692 * peer-to-peer between functions can claim to support a subset of ACS. 4693 * Such devices effectively enable request redirect (RR) and completion 4694 * redirect (CR) since all transactions are redirected to the upstream 4695 * root complex. 4696 * 4697 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4698 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4699 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4700 * 4701 * 1002:4385 SBx00 SMBus Controller 4702 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4703 * 1002:4383 SBx00 Azalia (Intel HDA) 4704 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4705 * 1002:4384 SBx00 PCI to PCI Bridge 4706 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4707 * 4708 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4709 * 4710 * 1022:780f [AMD] FCH PCI Bridge 4711 * 1022:7809 [AMD] FCH USB OHCI Controller 4712 */ 4713 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4714 { 4715 #ifdef CONFIG_ACPI 4716 struct acpi_table_header *header = NULL; 4717 acpi_status status; 4718 4719 /* Targeting multifunction devices on the SB (appears on root bus) */ 4720 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4721 return -ENODEV; 4722 4723 /* The IVRS table describes the AMD IOMMU */ 4724 status = acpi_get_table("IVRS", 0, &header); 4725 if (ACPI_FAILURE(status)) 4726 return -ENODEV; 4727 4728 acpi_put_table(header); 4729 4730 /* Filter out flags not applicable to multifunction */ 4731 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4732 4733 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4734 #else 4735 return -ENODEV; 4736 #endif 4737 } 4738 4739 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4740 { 4741 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4742 return false; 4743 4744 switch (dev->device) { 4745 /* 4746 * Effectively selects all downstream ports for whole ThunderX1 4747 * (which represents 8 SoCs). 4748 */ 4749 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4750 case 0xaf84: /* ThunderX2 */ 4751 case 0xb884: /* ThunderX3 */ 4752 return true; 4753 default: 4754 return false; 4755 } 4756 } 4757 4758 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4759 { 4760 if (!pci_quirk_cavium_acs_match(dev)) 4761 return -ENOTTY; 4762 4763 /* 4764 * Cavium Root Ports don't advertise an ACS capability. However, 4765 * the RTL internally implements similar protection as if ACS had 4766 * Source Validation, Request Redirection, Completion Redirection, 4767 * and Upstream Forwarding features enabled. Assert that the 4768 * hardware implements and enables equivalent ACS functionality for 4769 * these flags. 4770 */ 4771 return pci_acs_ctrl_enabled(acs_flags, 4772 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4773 } 4774 4775 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4776 { 4777 /* 4778 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4779 * transactions with others, allowing masking out these bits as if they 4780 * were unimplemented in the ACS capability. 4781 */ 4782 return pci_acs_ctrl_enabled(acs_flags, 4783 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4784 } 4785 4786 /* 4787 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4788 * But the implementation could block peer-to-peer transactions between them 4789 * and provide ACS-like functionality. 4790 */ 4791 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4792 { 4793 if (!pci_is_pcie(dev) || 4794 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4795 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4796 return -ENOTTY; 4797 4798 /* 4799 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4800 * implement ACS capability in accordance with the PCIe Spec. 4801 */ 4802 switch (dev->device) { 4803 case 0x0710 ... 0x071e: 4804 case 0x0721: 4805 case 0x0723 ... 0x0752: 4806 return pci_acs_ctrl_enabled(acs_flags, 4807 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4808 } 4809 4810 return false; 4811 } 4812 4813 /* 4814 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4815 * transactions and validate bus numbers in requests, but do not provide an 4816 * actual PCIe ACS capability. This is the list of device IDs known to fall 4817 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4818 */ 4819 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4820 /* Ibexpeak PCH */ 4821 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4822 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4823 /* Cougarpoint PCH */ 4824 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4825 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4826 /* Pantherpoint PCH */ 4827 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4828 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4829 /* Lynxpoint-H PCH */ 4830 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4831 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4832 /* Lynxpoint-LP PCH */ 4833 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4834 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4835 /* Wildcat PCH */ 4836 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4837 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4838 /* Patsburg (X79) PCH */ 4839 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4840 /* Wellsburg (X99) PCH */ 4841 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4842 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4843 /* Lynx Point (9 series) PCH */ 4844 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4845 }; 4846 4847 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4848 { 4849 int i; 4850 4851 /* Filter out a few obvious non-matches first */ 4852 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4853 return false; 4854 4855 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4856 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4857 return true; 4858 4859 return false; 4860 } 4861 4862 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4863 { 4864 if (!pci_quirk_intel_pch_acs_match(dev)) 4865 return -ENOTTY; 4866 4867 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4868 return pci_acs_ctrl_enabled(acs_flags, 4869 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4870 4871 return pci_acs_ctrl_enabled(acs_flags, 0); 4872 } 4873 4874 /* 4875 * These QCOM Root Ports do provide ACS-like features to disable peer 4876 * transactions and validate bus numbers in requests, but do not provide an 4877 * actual PCIe ACS capability. Hardware supports source validation but it 4878 * will report the issue as Completer Abort instead of ACS Violation. 4879 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4880 * Complex with unique segment numbers. It is not possible for one Root 4881 * Port to pass traffic to another Root Port. All PCIe transactions are 4882 * terminated inside the Root Port. 4883 */ 4884 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4885 { 4886 return pci_acs_ctrl_enabled(acs_flags, 4887 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4888 } 4889 4890 /* 4891 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4892 * number and does provide isolation features to disable peer transactions 4893 * and validate bus numbers in requests, but does not provide an ACS 4894 * capability. 4895 */ 4896 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4897 { 4898 return pci_acs_ctrl_enabled(acs_flags, 4899 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4900 } 4901 4902 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4903 { 4904 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4905 return -ENOTTY; 4906 4907 /* 4908 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4909 * but do include ACS-like functionality. The hardware doesn't support 4910 * peer-to-peer transactions via the root port and each has a unique 4911 * segment number. 4912 * 4913 * Additionally, the root ports cannot send traffic to each other. 4914 */ 4915 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4916 4917 return acs_flags ? 0 : 1; 4918 } 4919 4920 /* 4921 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4922 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4923 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4924 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4925 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4926 * control register is at offset 8 instead of 6 and we should probably use 4927 * dword accesses to them. This applies to the following PCI Device IDs, as 4928 * found in volume 1 of the datasheet[2]: 4929 * 4930 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4931 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4932 * 4933 * N.B. This doesn't fix what lspci shows. 4934 * 4935 * The 100 series chipset specification update includes this as errata #23[3]. 4936 * 4937 * The 200 series chipset (Union Point) has the same bug according to the 4938 * specification update (Intel 200 Series Chipset Family Platform Controller 4939 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4940 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4941 * chipset include: 4942 * 4943 * 0xa290-0xa29f PCI Express Root port #{0-16} 4944 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4945 * 4946 * Mobile chipsets are also affected, 7th & 8th Generation 4947 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4948 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4949 * Processor Family I/O for U Quad Core Platforms Specification Update, 4950 * August 2017, Revision 002, Document#: 334660-002)[6] 4951 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4952 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4953 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4954 * 4955 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4956 * 4957 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4958 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4959 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4960 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4961 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4962 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4963 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4964 */ 4965 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4966 { 4967 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4968 return false; 4969 4970 switch (dev->device) { 4971 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4972 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4973 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4974 return true; 4975 } 4976 4977 return false; 4978 } 4979 4980 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4981 4982 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4983 { 4984 int pos; 4985 u32 cap, ctrl; 4986 4987 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4988 return -ENOTTY; 4989 4990 pos = dev->acs_cap; 4991 if (!pos) 4992 return -ENOTTY; 4993 4994 /* see pci_acs_flags_enabled() */ 4995 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4996 acs_flags &= (cap | PCI_ACS_EC); 4997 4998 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4999 5000 return pci_acs_ctrl_enabled(acs_flags, ctrl); 5001 } 5002 5003 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 5004 { 5005 /* 5006 * SV, TB, and UF are not relevant to multifunction endpoints. 5007 * 5008 * Multifunction devices are only required to implement RR, CR, and DT 5009 * in their ACS capability if they support peer-to-peer transactions. 5010 * Devices matching this quirk have been verified by the vendor to not 5011 * perform peer-to-peer with other functions, allowing us to mask out 5012 * these bits as if they were unimplemented in the ACS capability. 5013 */ 5014 return pci_acs_ctrl_enabled(acs_flags, 5015 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 5016 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 5017 } 5018 5019 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 5020 { 5021 /* 5022 * Intel RCiEP's are required to allow p2p only on translated 5023 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 5024 * "Root-Complex Peer to Peer Considerations". 5025 */ 5026 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 5027 return -ENOTTY; 5028 5029 return pci_acs_ctrl_enabled(acs_flags, 5030 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5031 } 5032 5033 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 5034 { 5035 /* 5036 * iProc PAXB Root Ports don't advertise an ACS capability, but 5037 * they do not allow peer-to-peer transactions between Root Ports. 5038 * Allow each Root Port to be in a separate IOMMU group by masking 5039 * SV/RR/CR/UF bits. 5040 */ 5041 return pci_acs_ctrl_enabled(acs_flags, 5042 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5043 } 5044 5045 static int pci_quirk_loongson_acs(struct pci_dev *dev, u16 acs_flags) 5046 { 5047 /* 5048 * Loongson PCIe Root Ports don't advertise an ACS capability, but 5049 * they do not allow peer-to-peer transactions between Root Ports. 5050 * Allow each Root Port to be in a separate IOMMU group by masking 5051 * SV/RR/CR/UF bits. 5052 */ 5053 return pci_acs_ctrl_enabled(acs_flags, 5054 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5055 } 5056 5057 /* 5058 * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on 5059 * multi-function devices, the hardware isolates the functions by 5060 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and 5061 * PCI_ACS_CR were set. 5062 * SFxxx 1G NICs(em). 5063 * RP1000/RP2000 10G NICs(sp). 5064 * FF5xxx 40G/25G/10G NICs(aml). 5065 */ 5066 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 5067 { 5068 switch (dev->device) { 5069 case 0x0100 ... 0x010F: /* EM */ 5070 case 0x1001: case 0x2001: /* SP */ 5071 case 0x5010: case 0x5025: case 0x5040: /* AML */ 5072 case 0x5110: case 0x5125: case 0x5140: /* AML */ 5073 return pci_acs_ctrl_enabled(acs_flags, 5074 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5075 } 5076 5077 return false; 5078 } 5079 5080 static const struct pci_dev_acs_enabled { 5081 u16 vendor; 5082 u16 device; 5083 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 5084 } pci_dev_acs_enabled[] = { 5085 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 5086 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 5087 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 5088 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 5089 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 5090 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 5091 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 5092 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 5093 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 5094 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 5095 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 5096 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 5097 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 5098 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 5099 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 5100 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 5101 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 5102 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 5103 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 5104 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 5105 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 5106 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 5107 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5108 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5109 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5110 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5111 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5112 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5113 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5114 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5115 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5116 /* 82580 */ 5117 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5118 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5119 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5120 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5121 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5122 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5123 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5124 /* 82576 */ 5125 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5126 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5127 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5128 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5129 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5130 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5131 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5132 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5133 /* 82575 */ 5134 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5135 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5136 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5137 /* I350 */ 5138 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5139 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5140 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5141 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5142 /* 82571 (Quads omitted due to non-ACS switch) */ 5143 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5144 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5145 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5146 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5147 /* I219 */ 5148 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5149 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5150 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5151 /* QCOM QDF2xxx root ports */ 5152 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5153 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5154 /* QCOM SA8775P root port */ 5155 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5156 /* QCOM Hamoa root port */ 5157 { PCI_VENDOR_ID_QCOM, 0x0111, pci_quirk_qcom_rp_acs }, 5158 /* QCOM Glymur root port */ 5159 { PCI_VENDOR_ID_QCOM, 0x0120, pci_quirk_qcom_rp_acs }, 5160 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5161 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5162 /* Intel PCH root ports */ 5163 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5164 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5165 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5166 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5167 /* Cavium ThunderX */ 5168 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5169 /* Cavium multi-function devices */ 5170 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5171 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5172 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5173 /* APM X-Gene */ 5174 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5175 /* Ampere Computing */ 5176 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5177 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5178 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5179 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5180 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5181 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5182 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5183 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5184 /* Broadcom multi-function device */ 5185 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5186 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5187 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5188 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5189 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs }, 5190 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs }, 5191 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs }, 5192 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs }, 5193 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5194 /* Loongson PCIe Root Ports */ 5195 { PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs }, 5196 { PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs }, 5197 { PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs }, 5198 { PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs }, 5199 { PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs }, 5200 { PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs }, 5201 { PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs }, 5202 { PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs }, 5203 { PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs }, 5204 { PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs }, 5205 /* Amazon Annapurna Labs */ 5206 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5207 /* Zhaoxin multi-function devices */ 5208 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5209 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5210 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5211 /* NXP root ports, xx=16, 12, or 08 cores */ 5212 /* LX2xx0A : without security features + CAN-FD */ 5213 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5214 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5215 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5216 /* LX2xx0C : security features + CAN-FD */ 5217 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5218 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5219 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5220 /* LX2xx0E : security features + CAN */ 5221 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5222 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5223 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5224 /* LX2xx0N : without security features + CAN */ 5225 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5226 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5227 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5228 /* LX2xx2A : without security features + CAN-FD */ 5229 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5230 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5231 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5232 /* LX2xx2C : security features + CAN-FD */ 5233 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5234 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5235 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5236 /* LX2xx2E : security features + CAN */ 5237 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5238 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5239 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5240 /* LX2xx2N : without security features + CAN */ 5241 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5242 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5243 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5244 /* Zhaoxin Root/Downstream Ports */ 5245 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5246 /* Wangxun nics */ 5247 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5248 { 0 } 5249 }; 5250 5251 /* 5252 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5253 * @dev: PCI device 5254 * @acs_flags: Bitmask of desired ACS controls 5255 * 5256 * Returns: 5257 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5258 * device provides the desired controls 5259 * 0: Device does not provide all the desired controls 5260 * >0: Device provides all the controls in @acs_flags 5261 */ 5262 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5263 { 5264 const struct pci_dev_acs_enabled *i; 5265 int ret; 5266 5267 /* 5268 * Allow devices that do not expose standard PCIe ACS capabilities 5269 * or control to indicate their support here. Multi-function express 5270 * devices which do not allow internal peer-to-peer between functions, 5271 * but do not implement PCIe ACS may wish to return true here. 5272 */ 5273 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5274 if ((i->vendor == dev->vendor || 5275 i->vendor == (u16)PCI_ANY_ID) && 5276 (i->device == dev->device || 5277 i->device == (u16)PCI_ANY_ID)) { 5278 ret = i->acs_enabled(dev, acs_flags); 5279 if (ret >= 0) 5280 return ret; 5281 } 5282 } 5283 5284 return -ENOTTY; 5285 } 5286 5287 /* Config space offset of Root Complex Base Address register */ 5288 #define INTEL_LPC_RCBA_REG 0xf0 5289 /* 31:14 RCBA address */ 5290 #define INTEL_LPC_RCBA_MASK 0xffffc000 5291 /* RCBA Enable */ 5292 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5293 5294 /* Backbone Scratch Pad Register */ 5295 #define INTEL_BSPR_REG 0x1104 5296 /* Backbone Peer Non-Posted Disable */ 5297 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5298 /* Backbone Peer Posted Disable */ 5299 #define INTEL_BSPR_REG_BPPD (1 << 9) 5300 5301 /* Upstream Peer Decode Configuration Register */ 5302 #define INTEL_UPDCR_REG 0x1014 5303 /* 5:0 Peer Decode Enable bits */ 5304 #define INTEL_UPDCR_REG_MASK 0x3f 5305 5306 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5307 { 5308 u32 rcba, bspr, updcr; 5309 void __iomem *rcba_mem; 5310 5311 /* 5312 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5313 * are D28:F* and therefore get probed before LPC, thus we can't 5314 * use pci_get_slot()/pci_read_config_dword() here. 5315 */ 5316 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5317 INTEL_LPC_RCBA_REG, &rcba); 5318 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5319 return -EINVAL; 5320 5321 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5322 PAGE_ALIGN(INTEL_UPDCR_REG)); 5323 if (!rcba_mem) 5324 return -ENOMEM; 5325 5326 /* 5327 * The BSPR can disallow peer cycles, but it's set by soft strap and 5328 * therefore read-only. If both posted and non-posted peer cycles are 5329 * disallowed, we're ok. If either are allowed, then we need to use 5330 * the UPDCR to disable peer decodes for each port. This provides the 5331 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5332 */ 5333 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5334 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5335 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5336 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5337 if (updcr & INTEL_UPDCR_REG_MASK) { 5338 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5339 updcr &= ~INTEL_UPDCR_REG_MASK; 5340 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5341 } 5342 } 5343 5344 iounmap(rcba_mem); 5345 return 0; 5346 } 5347 5348 /* Miscellaneous Port Configuration register */ 5349 #define INTEL_MPC_REG 0xd8 5350 /* MPC: Invalid Receive Bus Number Check Enable */ 5351 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5352 5353 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5354 { 5355 u32 mpc; 5356 5357 /* 5358 * When enabled, the IRBNCE bit of the MPC register enables the 5359 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5360 * ensures that requester IDs fall within the bus number range 5361 * of the bridge. Enable if not already. 5362 */ 5363 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5364 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5365 pci_info(dev, "Enabling MPC IRBNCE\n"); 5366 mpc |= INTEL_MPC_REG_IRBNCE; 5367 pci_write_config_dword(dev, INTEL_MPC_REG, mpc); 5368 } 5369 } 5370 5371 /* 5372 * Currently this quirk does the equivalent of 5373 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5374 * 5375 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5376 * if dev->external_facing || dev->untrusted 5377 */ 5378 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5379 { 5380 if (!pci_quirk_intel_pch_acs_match(dev)) 5381 return -ENOTTY; 5382 5383 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5384 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5385 return 0; 5386 } 5387 5388 pci_quirk_enable_intel_rp_mpc_acs(dev); 5389 5390 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5391 5392 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5393 5394 return 0; 5395 } 5396 5397 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5398 { 5399 int pos; 5400 u32 cap, ctrl; 5401 5402 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5403 return -ENOTTY; 5404 5405 pos = dev->acs_cap; 5406 if (!pos) 5407 return -ENOTTY; 5408 5409 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5410 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5411 5412 ctrl |= (cap & PCI_ACS_SV); 5413 ctrl |= (cap & PCI_ACS_RR); 5414 ctrl |= (cap & PCI_ACS_CR); 5415 ctrl |= (cap & PCI_ACS_UF); 5416 5417 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5418 ctrl |= (cap & PCI_ACS_TB); 5419 5420 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5421 5422 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5423 5424 return 0; 5425 } 5426 5427 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5428 { 5429 int pos; 5430 u32 cap, ctrl; 5431 5432 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5433 return -ENOTTY; 5434 5435 pos = dev->acs_cap; 5436 if (!pos) 5437 return -ENOTTY; 5438 5439 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5440 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5441 5442 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5443 5444 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5445 5446 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5447 5448 return 0; 5449 } 5450 5451 static const struct pci_dev_acs_ops { 5452 u16 vendor; 5453 u16 device; 5454 int (*enable_acs)(struct pci_dev *dev); 5455 int (*disable_acs_redir)(struct pci_dev *dev); 5456 } pci_dev_acs_ops[] = { 5457 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5458 .enable_acs = pci_quirk_enable_intel_pch_acs, 5459 }, 5460 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5461 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5462 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5463 }, 5464 }; 5465 5466 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5467 { 5468 const struct pci_dev_acs_ops *p; 5469 int i, ret; 5470 5471 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5472 p = &pci_dev_acs_ops[i]; 5473 if ((p->vendor == dev->vendor || 5474 p->vendor == (u16)PCI_ANY_ID) && 5475 (p->device == dev->device || 5476 p->device == (u16)PCI_ANY_ID) && 5477 p->enable_acs) { 5478 ret = p->enable_acs(dev); 5479 if (ret >= 0) 5480 return ret; 5481 } 5482 } 5483 5484 return -ENOTTY; 5485 } 5486 5487 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5488 { 5489 const struct pci_dev_acs_ops *p; 5490 int i, ret; 5491 5492 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5493 p = &pci_dev_acs_ops[i]; 5494 if ((p->vendor == dev->vendor || 5495 p->vendor == (u16)PCI_ANY_ID) && 5496 (p->device == dev->device || 5497 p->device == (u16)PCI_ANY_ID) && 5498 p->disable_acs_redir) { 5499 ret = p->disable_acs_redir(dev); 5500 if (ret >= 0) 5501 return ret; 5502 } 5503 } 5504 5505 return -ENOTTY; 5506 } 5507 5508 /* 5509 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5510 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5511 * Next Capability pointer in the MSI Capability Structure should point to 5512 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5513 * the list. 5514 */ 5515 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5516 { 5517 int pos, i = 0, ret; 5518 u8 next_cap; 5519 u16 reg16, *cap; 5520 struct pci_cap_saved_state *state; 5521 5522 /* Bail if the hardware bug is fixed */ 5523 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5524 return; 5525 5526 /* Bail if MSI Capability Structure is not found for some reason */ 5527 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5528 if (!pos) 5529 return; 5530 5531 /* 5532 * Bail if Next Capability pointer in the MSI Capability Structure 5533 * is not the expected incorrect 0x00. 5534 */ 5535 pci_read_config_byte(pdev, pos + 1, &next_cap); 5536 if (next_cap) 5537 return; 5538 5539 /* 5540 * PCIe Capability Structure is expected to be at 0x50 and should 5541 * terminate the list (Next Capability pointer is 0x00). Verify 5542 * Capability Id and Next Capability pointer is as expected. 5543 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5544 * to correctly set kernel data structures which have already been 5545 * set incorrectly due to the hardware bug. 5546 */ 5547 pos = 0x50; 5548 pci_read_config_word(pdev, pos, ®16); 5549 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5550 u32 status; 5551 #ifndef PCI_EXP_SAVE_REGS 5552 #define PCI_EXP_SAVE_REGS 7 5553 #endif 5554 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5555 5556 pdev->pcie_cap = pos; 5557 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5558 pdev->pcie_flags_reg = reg16; 5559 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5560 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5561 5562 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5563 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5564 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5565 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5566 5567 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5568 return; 5569 5570 /* Save PCIe cap */ 5571 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5572 if (!state) 5573 return; 5574 5575 state->cap.cap_nr = PCI_CAP_ID_EXP; 5576 state->cap.cap_extended = 0; 5577 state->cap.size = size; 5578 cap = (u16 *)&state->cap.data[0]; 5579 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5580 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5581 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5582 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5583 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5584 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5585 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5586 hlist_add_head(&state->next, &pdev->saved_cap_space); 5587 } 5588 } 5589 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5590 5591 /* 5592 * FLR may cause the following to devices to hang: 5593 * 5594 * AMD Starship/Matisse HD Audio Controller 0x1487 5595 * AMD Starship USB 3.0 Host Controller 0x148c 5596 * AMD Matisse USB 3.0 Host Controller 0x149c 5597 * AMD Neural Processing Unit 0x1502 0x17f0 5598 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5599 * Intel 82579V Gigabit Ethernet Controller 0x1503 5600 * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter 5601 * Mediatek MT7925 802.11be PCI Express Wireless Network Adapter 5602 */ 5603 static void quirk_no_flr(struct pci_dev *dev) 5604 { 5605 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5606 } 5607 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5608 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5609 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5610 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5611 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1502, quirk_no_flr); 5612 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x17f0, quirk_no_flr); 5613 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5614 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5615 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr); 5616 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x7925, quirk_no_flr); 5617 5618 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5619 static void quirk_no_flr_snet(struct pci_dev *dev) 5620 { 5621 if (dev->revision == 0x1) 5622 quirk_no_flr(dev); 5623 } 5624 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5625 5626 static void quirk_no_ext_tags(struct pci_dev *pdev) 5627 { 5628 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5629 5630 if (!bridge) 5631 return; 5632 5633 bridge->no_ext_tags = 1; 5634 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5635 5636 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5637 } 5638 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); 5639 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1005, quirk_no_ext_tags); 5640 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5641 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5642 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5643 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5644 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5645 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5646 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5647 5648 #ifdef CONFIG_PCI_ATS 5649 static void quirk_no_ats(struct pci_dev *pdev) 5650 { 5651 pci_info(pdev, "disabling ATS\n"); 5652 pdev->ats_cap = 0; 5653 } 5654 5655 /* 5656 * Some devices require additional driver setup to enable ATS. Don't use 5657 * ATS for those devices as ATS will be enabled before the driver has had a 5658 * chance to load and configure the device. 5659 */ 5660 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5661 { 5662 if (pdev->device == 0x15d8) { 5663 if (pdev->revision == 0xcf && 5664 pdev->subsystem_vendor == 0xea50 && 5665 (pdev->subsystem_device == 0xce19 || 5666 pdev->subsystem_device == 0xcc10 || 5667 pdev->subsystem_device == 0xcc08)) 5668 quirk_no_ats(pdev); 5669 } else { 5670 quirk_no_ats(pdev); 5671 } 5672 } 5673 5674 /* AMD Stoney platform GPU */ 5675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5676 /* AMD Iceland dGPU */ 5677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5678 /* AMD Navi10 dGPU */ 5679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5687 /* AMD Navi14 dGPU */ 5688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5692 /* AMD Raven platform iGPU */ 5693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5694 5695 /* 5696 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5697 * in ATS Invalidate Request message body. Disable ATS for those devices. 5698 */ 5699 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5700 { 5701 if (pdev->revision < 0x20) 5702 quirk_no_ats(pdev); 5703 } 5704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5712 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5713 5714 static bool quirk_nvidia_gpu_ats_required(struct pci_dev *pdev) 5715 { 5716 switch (pdev->device) { 5717 case 0x2e00 ... 0x2e3f: /* GB20B */ 5718 return true; 5719 } 5720 return false; 5721 } 5722 5723 static const struct pci_dev_ats_required { 5724 u16 vendor; 5725 u16 device; 5726 bool (*ats_required)(struct pci_dev *dev); 5727 } pci_dev_ats_required[] = { 5728 /* NVIDIA GPUs */ 5729 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, quirk_nvidia_gpu_ats_required }, 5730 /* NVIDIA CX10 Family NVlink-C2C */ 5731 { PCI_VENDOR_ID_MELLANOX, 0x2101, NULL }, 5732 { 0 } 5733 }; 5734 5735 /* 5736 * Some NVIDIA devices do not implement CXL config space, but present as PCIe 5737 * devices that can issue CXL-like cache operations like CXL.cache. Thus, they 5738 * require ATS to obtain host physical addresses, like pci_cxl_ats_required(). 5739 */ 5740 bool pci_dev_specific_ats_required(struct pci_dev *pdev) 5741 { 5742 const struct pci_dev_ats_required *i; 5743 5744 for (i = pci_dev_ats_required; i->vendor; i++) { 5745 if (i->vendor != pdev->vendor) 5746 continue; 5747 if (i->ats_required && i->ats_required(pdev)) 5748 return true; 5749 if (!i->ats_required && i->device == pdev->device) 5750 return true; 5751 } 5752 5753 return false; 5754 } 5755 #endif /* CONFIG_PCI_ATS */ 5756 5757 /* Freescale PCIe doesn't support MSI in RC mode */ 5758 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5759 { 5760 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5761 pdev->no_msi = 1; 5762 } 5763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5764 5765 /* 5766 * Although not allowed by the spec, some multi-function devices have 5767 * dependencies of one function (consumer) on another (supplier). For the 5768 * consumer to work in D0, the supplier must also be in D0. Create a 5769 * device link from the consumer to the supplier to enforce this 5770 * dependency. Runtime PM is allowed by default on the consumer to prevent 5771 * it from permanently keeping the supplier awake. 5772 */ 5773 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5774 unsigned int supplier, unsigned int class, 5775 unsigned int class_shift) 5776 { 5777 struct pci_dev *supplier_pdev; 5778 5779 if (PCI_FUNC(pdev->devfn) != consumer) 5780 return; 5781 5782 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5783 pdev->bus->number, 5784 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5785 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5786 pci_dev_put(supplier_pdev); 5787 return; 5788 } 5789 5790 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5791 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5792 pci_info(pdev, "D0 power state depends on %s\n", 5793 pci_name(supplier_pdev)); 5794 else 5795 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5796 pci_name(supplier_pdev)); 5797 5798 pm_runtime_allow(&pdev->dev); 5799 pci_dev_put(supplier_pdev); 5800 } 5801 5802 /* 5803 * Create device link for GPUs with integrated HDA controller for streaming 5804 * audio to attached displays. 5805 */ 5806 static void quirk_gpu_hda(struct pci_dev *hda) 5807 { 5808 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5809 } 5810 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5811 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5812 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5813 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5814 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5815 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5816 5817 /* 5818 * Create device link for GPUs with integrated USB xHCI Host 5819 * controller to VGA. 5820 */ 5821 static void quirk_gpu_usb(struct pci_dev *usb) 5822 { 5823 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5824 } 5825 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5826 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5827 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5828 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5829 5830 /* 5831 * Create device link for GPUs with integrated Type-C UCSI controller 5832 * to VGA. Currently there is no class code defined for UCSI device over PCI 5833 * so using UNKNOWN class for now and it will be updated when UCSI 5834 * over PCI gets a class code. 5835 */ 5836 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5837 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5838 { 5839 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5840 } 5841 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5842 PCI_CLASS_SERIAL_UNKNOWN, 8, 5843 quirk_gpu_usb_typec_ucsi); 5844 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5845 PCI_CLASS_SERIAL_UNKNOWN, 8, 5846 quirk_gpu_usb_typec_ucsi); 5847 5848 /* 5849 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5850 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5851 */ 5852 static void quirk_nvidia_hda(struct pci_dev *gpu) 5853 { 5854 u8 hdr_type; 5855 u32 val; 5856 5857 /* There was no integrated HDA controller before MCP89 */ 5858 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5859 return; 5860 5861 /* Bit 25 at offset 0x488 enables the HDA controller */ 5862 pci_read_config_dword(gpu, 0x488, &val); 5863 if (val & BIT(25)) 5864 return; 5865 5866 pci_info(gpu, "Enabling HDA controller\n"); 5867 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5868 5869 /* The GPU becomes a multi-function device when the HDA is enabled */ 5870 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5871 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 5872 } 5873 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5874 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5875 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5876 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5877 5878 /* 5879 * Some IDT switches incorrectly flag an ACS Source Validation error on 5880 * completions for config read requests even though PCIe r7.0, sec 5881 * 6.12.1.1, says that completions are never affected by ACS Source 5882 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5883 * 5884 * Item #36 - Downstream port applies ACS Source Validation to Completions 5885 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5886 * completions are never affected by ACS Source Validation. However, 5887 * completions received by a downstream port of the PCIe switch from a 5888 * device that has not yet captured a PCIe bus number are incorrectly 5889 * dropped by ACS Source Validation by the switch downstream port. 5890 * 5891 * The workaround suggested by IDT is to issue a config write to the 5892 * downstream device before issuing the first config read. This allows the 5893 * downstream device to capture its bus and device numbers (see PCIe r7.0, 5894 * sec 2.2.9.1), thus avoiding the ACS error on the completion. 5895 * 5896 * However, we don't know when the device is ready to accept the config 5897 * write, and the issue affects resets of the switch as well as enumeration, 5898 * so disable use of ACS SV for these devices altogether. 5899 */ 5900 void pci_disable_broken_acs_cap(struct pci_dev *pdev) 5901 { 5902 if (pdev->vendor == PCI_VENDOR_ID_IDT && 5903 (pdev->device == 0x80b5 || pdev->device == 0x8090)) { 5904 pci_info(pdev, "Disabling broken ACS SV; downstream device isolation reduced\n"); 5905 pdev->acs_capabilities &= ~PCI_ACS_SV; 5906 } 5907 } 5908 5909 /* 5910 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5911 * NT endpoints via the internal switch fabric. These IDs replace the 5912 * originating Requester ID TLPs which access host memory on peer NTB 5913 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5914 * to permit access when the IOMMU is turned on. 5915 */ 5916 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5917 { 5918 void __iomem *mmio; 5919 struct ntb_info_regs __iomem *mmio_ntb; 5920 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5921 u64 partition_map; 5922 u8 partition; 5923 int pp; 5924 5925 if (pci_enable_device(pdev)) { 5926 pci_err(pdev, "Cannot enable Switchtec device\n"); 5927 return; 5928 } 5929 5930 mmio = pci_iomap(pdev, 0, 0); 5931 if (mmio == NULL) { 5932 pci_disable_device(pdev); 5933 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5934 return; 5935 } 5936 5937 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5938 5939 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5940 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5941 5942 partition = ioread8(&mmio_ntb->partition_id); 5943 5944 partition_map = ioread32(&mmio_ntb->ep_map); 5945 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5946 partition_map &= ~(1ULL << partition); 5947 5948 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5949 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5950 u32 table_sz = 0; 5951 int te; 5952 5953 if (!(partition_map & (1ULL << pp))) 5954 continue; 5955 5956 pci_dbg(pdev, "Processing partition %d\n", pp); 5957 5958 mmio_peer_ctrl = &mmio_ctrl[pp]; 5959 5960 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5961 if (!table_sz) { 5962 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5963 continue; 5964 } 5965 5966 if (table_sz > 512) { 5967 pci_warn(pdev, 5968 "Invalid Switchtec partition %d table_sz %d\n", 5969 pp, table_sz); 5970 continue; 5971 } 5972 5973 for (te = 0; te < table_sz; te++) { 5974 u32 rid_entry; 5975 u8 devfn; 5976 5977 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5978 devfn = (rid_entry >> 1) & 0xFF; 5979 pci_dbg(pdev, 5980 "Aliasing Partition %d Proxy ID %02x.%d\n", 5981 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5982 pci_add_dma_alias(pdev, devfn, 1); 5983 } 5984 } 5985 5986 pci_iounmap(pdev, mmio); 5987 pci_disable_device(pdev); 5988 } 5989 #define SWITCHTEC_QUIRK(vid) \ 5990 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5991 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5992 5993 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5994 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5995 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5996 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5997 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5998 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5999 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 6000 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 6001 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 6002 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 6003 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 6004 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 6005 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 6006 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 6007 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 6008 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 6009 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 6010 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 6011 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 6012 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 6013 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 6014 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 6015 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 6016 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 6017 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 6018 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 6019 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 6020 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 6021 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 6022 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 6023 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 6024 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 6025 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 6026 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 6027 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 6028 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 6029 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 6030 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 6031 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 6032 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 6033 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 6034 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 6035 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 6036 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 6037 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 6038 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 6039 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 6040 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 6041 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 6042 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 6043 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 6044 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 6045 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 6046 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 6047 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 6048 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 6049 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 6050 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 6051 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 6052 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 6053 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 6054 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 6055 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 6056 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 6057 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 6058 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 6059 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 6060 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 6061 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 6062 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 6063 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 6064 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 6065 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 6066 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 6067 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 6068 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 6069 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 6070 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 6071 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 6072 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 6073 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 6074 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 6075 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 6076 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 6077 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 6078 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 6079 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 6080 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 6081 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 6082 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 6083 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 6084 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 6085 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 6086 6087 #define SWITCHTEC_PCI100X_QUIRK(vid) \ 6088 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_EFAR, vid, \ 6089 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 6090 SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */ 6091 SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */ 6092 SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */ 6093 SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */ 6094 SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */ 6095 SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */ 6096 SWITCHTEC_PCI100X_QUIRK(0x1008); /* PCI1008XG4 */ 6097 6098 6099 /* 6100 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 6101 * These IDs are used to forward responses to the originator on the other 6102 * side of the NTB. Alias all possible IDs to the NTB to permit access when 6103 * the IOMMU is turned on. 6104 */ 6105 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 6106 { 6107 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 6108 /* PLX NTB may use all 256 devfns */ 6109 pci_add_dma_alias(pdev, 0, 256); 6110 } 6111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 6112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 6113 6114 /* 6115 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 6116 * not always reset the secondary Nvidia GPU between reboots if the system 6117 * is configured to use Hybrid Graphics mode. This results in the GPU 6118 * being left in whatever state it was in during the *previous* boot, which 6119 * causes spurious interrupts from the GPU, which in turn causes us to 6120 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 6121 * this also completely breaks nouveau. 6122 * 6123 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 6124 * clean state and fixes all these issues. 6125 * 6126 * When the machine is configured in Dedicated display mode, the issue 6127 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 6128 * mode, so we can detect that and avoid resetting it. 6129 */ 6130 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 6131 { 6132 void __iomem *map; 6133 int ret; 6134 6135 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 6136 pdev->subsystem_device != 0x222e || 6137 !pci_reset_supported(pdev)) 6138 return; 6139 6140 if (pci_enable_device_mem(pdev)) 6141 return; 6142 6143 /* 6144 * Based on nvkm_device_ctor() in 6145 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 6146 */ 6147 map = pci_iomap(pdev, 0, 0x23000); 6148 if (!map) { 6149 pci_err(pdev, "Can't map MMIO space\n"); 6150 goto out_disable; 6151 } 6152 6153 /* 6154 * Make sure the GPU looks like it's been POSTed before resetting 6155 * it. 6156 */ 6157 if (ioread32(map + 0x2240c) & 0x2) { 6158 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 6159 ret = pci_reset_bus(pdev); 6160 if (ret < 0) 6161 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 6162 } 6163 6164 iounmap(map); 6165 out_disable: 6166 pci_disable_device(pdev); 6167 } 6168 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6169 PCI_CLASS_DISPLAY_VGA, 8, 6170 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6171 6172 /* 6173 * Device [1b21:2142] 6174 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6175 */ 6176 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6177 { 6178 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6179 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6180 } 6181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6182 6183 /* 6184 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6185 * 6186 * These devices advertise PME# support in all power states but don't 6187 * reliably assert it. 6188 * 6189 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6190 * says "The MSI Function is not implemented on this device" in chapters 6191 * 7.3.27, 7.3.29-7.3.31. 6192 */ 6193 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6194 { 6195 #ifdef CONFIG_PCI_MSI 6196 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6197 dev->no_msi = 1; 6198 #endif 6199 pci_info(dev, "PME# is unreliable, disabling it\n"); 6200 dev->pme_support = 0; 6201 } 6202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6204 6205 static void apex_pci_fixup_class(struct pci_dev *pdev) 6206 { 6207 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6208 } 6209 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6210 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6211 6212 /* 6213 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6214 * ACS P2P Request Redirect is not functional 6215 * 6216 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6217 * between upstream and downstream ports, packets are queued in an internal 6218 * buffer until CPLD packet. The workaround is to use the switch in store and 6219 * forward mode. 6220 */ 6221 #define PI7C9X2Gxxx_MODE_REG 0x74 6222 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6223 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6224 { 6225 struct pci_dev *upstream; 6226 u16 val; 6227 6228 /* Downstream ports only */ 6229 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6230 return; 6231 6232 /* Check for ACS P2P Request Redirect use */ 6233 if (!pdev->acs_cap) 6234 return; 6235 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6236 if (!(val & PCI_ACS_RR)) 6237 return; 6238 6239 upstream = pci_upstream_bridge(pdev); 6240 if (!upstream) 6241 return; 6242 6243 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6244 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6245 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6246 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6247 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6248 } 6249 } 6250 /* 6251 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6252 * ACS configuration changes or switch mode is reset 6253 */ 6254 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6255 pci_fixup_pericom_acs_store_forward); 6256 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6257 pci_fixup_pericom_acs_store_forward); 6258 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6259 pci_fixup_pericom_acs_store_forward); 6260 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6261 pci_fixup_pericom_acs_store_forward); 6262 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6263 pci_fixup_pericom_acs_store_forward); 6264 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6265 pci_fixup_pericom_acs_store_forward); 6266 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0xb404, 6267 pci_fixup_pericom_acs_store_forward); 6268 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0xb404, 6269 pci_fixup_pericom_acs_store_forward); 6270 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2608, 6271 pci_fixup_pericom_acs_store_forward); 6272 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2608, 6273 pci_fixup_pericom_acs_store_forward); 6274 6275 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6276 { 6277 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6278 } 6279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6280 6281 static void rom_bar_overlap_defect(struct pci_dev *dev) 6282 { 6283 pci_info(dev, "working around ROM BAR overlap defect\n"); 6284 dev->rom_bar_overlap = 1; 6285 } 6286 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6287 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6288 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6289 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6290 6291 #ifdef CONFIG_PCIEASPM 6292 /* 6293 * Several Intel DG2 graphics devices advertise that they can only tolerate 6294 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6295 * from being enabled. But in fact these devices can tolerate unlimited 6296 * latency. Override their Device Capabilities value to allow ASPM L1 to 6297 * be enabled. 6298 */ 6299 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6300 { 6301 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6302 6303 if (l1_lat < 7) { 6304 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6305 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6306 l1_lat); 6307 } 6308 } 6309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6335 #endif 6336 6337 #ifdef CONFIG_PCIE_DPC 6338 /* 6339 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6340 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6341 * Ports. 6342 */ 6343 static void dpc_log_size(struct pci_dev *dev) 6344 { 6345 u16 dpc, val; 6346 6347 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6348 if (!dpc) 6349 return; 6350 6351 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6352 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6353 return; 6354 6355 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6356 pci_info(dev, "Overriding RP PIO Log Size to %d\n", 6357 PCIE_STD_NUM_TLP_HEADERLOG); 6358 dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG; 6359 } 6360 } 6361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size); 6378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); 6379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); 6380 #endif 6381 6382 /* 6383 * For a PCI device with multiple downstream devices, its driver may use 6384 * a flattened device tree to describe the downstream devices. 6385 * To overlay the flattened device tree, the PCI device and all its ancestor 6386 * devices need to have device tree nodes on system base device tree. Thus, 6387 * before driver probing, it might need to add a device tree node as the final 6388 * fixup. 6389 */ 6390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); 6394 6395 /* 6396 * Devices known to require a longer delay before first config space access 6397 * after reset recovery or resume from D3cold: 6398 * 6399 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6400 */ 6401 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6402 { 6403 pdev->d3cold_delay = 1000; 6404 } 6405 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6406 6407 #ifdef CONFIG_PCIEAER 6408 static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) 6409 { 6410 struct pci_dev *parent = pci_upstream_bridge(pdev); 6411 u32 val; 6412 6413 if (!parent || !parent->aer_cap) 6414 return; 6415 6416 pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", 6417 pci_name(pdev)); 6418 6419 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); 6420 val |= PCI_ERR_COR_REP_TIMER; 6421 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); 6422 } 6423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); 6424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); 6425 #endif 6426