1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/acpi.h> 24 #include "pci.h" 25 26 /* The Mellanox Tavor device gives false positive parity errors 27 * Mark this device with a broken_parity_status, to allow 28 * PCI scanning code to "skip" this now blacklisted device. 29 */ 30 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 31 { 32 dev->broken_parity_status = 1; /* This device gives false positives */ 33 } 34 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 36 37 /* Deal with broken BIOS'es that neglect to enable passive release, 38 which can cause problems in combination with the 82441FX/PPro MTRRs */ 39 static void __devinit quirk_passive_release(struct pci_dev *dev) 40 { 41 struct pci_dev *d = NULL; 42 unsigned char dlc; 43 44 /* We have to make sure a particular bit is set in the PIIX3 45 ISA bridge, so we have to go out and find it. */ 46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 47 pci_read_config_byte(d, 0x82, &dlc); 48 if (!(dlc & 1<<1)) { 49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 50 dlc |= 1<<1; 51 pci_write_config_byte(d, 0x82, dlc); 52 } 53 } 54 } 55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 56 57 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 58 but VIA don't answer queries. If you happen to have good contacts at VIA 59 ask them for me please -- Alan 60 61 This appears to be BIOS not version dependent. So presumably there is a 62 chipset level fix */ 63 int isa_dma_bridge_buggy; /* Exported */ 64 65 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 66 { 67 if (!isa_dma_bridge_buggy) { 68 isa_dma_bridge_buggy=1; 69 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 70 } 71 } 72 /* 73 * Its not totally clear which chipsets are the problematic ones 74 * We know 82C586 and 82C596 variants are affected. 75 */ 76 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 77 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 78 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 83 84 int pci_pci_problems; 85 86 /* 87 * Chipsets where PCI->PCI transfers vanish or hang 88 */ 89 static void __devinit quirk_nopcipci(struct pci_dev *dev) 90 { 91 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 92 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 93 pci_pci_problems |= PCIPCI_FAIL; 94 } 95 } 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 98 99 /* 100 * Triton requires workarounds to be used by the drivers 101 */ 102 static void __devinit quirk_triton(struct pci_dev *dev) 103 { 104 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 105 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 106 pci_pci_problems |= PCIPCI_TRITON; 107 } 108 } 109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 113 114 /* 115 * VIA Apollo KT133 needs PCI latency patch 116 * Made according to a windows driver based patch by George E. Breese 117 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 118 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 119 * the info on which Mr Breese based his work. 120 * 121 * Updated based on further information from the site and also on 122 * information provided by VIA 123 */ 124 static void __devinit quirk_vialatency(struct pci_dev *dev) 125 { 126 struct pci_dev *p; 127 u8 rev; 128 u8 busarb; 129 /* Ok we have a potential problem chipset here. Now see if we have 130 a buggy southbridge */ 131 132 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 133 if (p!=NULL) { 134 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 135 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 136 /* Check for buggy part revisions */ 137 if (rev < 0x40 || rev > 0x42) 138 goto exit; 139 } else { 140 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 141 if (p==NULL) /* No problem parts */ 142 goto exit; 143 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 144 /* Check for buggy part revisions */ 145 if (rev < 0x10 || rev > 0x12) 146 goto exit; 147 } 148 149 /* 150 * Ok we have the problem. Now set the PCI master grant to 151 * occur every master grant. The apparent bug is that under high 152 * PCI load (quite common in Linux of course) you can get data 153 * loss when the CPU is held off the bus for 3 bus master requests 154 * This happens to include the IDE controllers.... 155 * 156 * VIA only apply this fix when an SB Live! is present but under 157 * both Linux and Windows this isnt enough, and we have seen 158 * corruption without SB Live! but with things like 3 UDMA IDE 159 * controllers. So we ignore that bit of the VIA recommendation.. 160 */ 161 162 pci_read_config_byte(dev, 0x76, &busarb); 163 /* Set bit 4 and bi 5 of byte 76 to 0x01 164 "Master priority rotation on every PCI master grant */ 165 busarb &= ~(1<<5); 166 busarb |= (1<<4); 167 pci_write_config_byte(dev, 0x76, busarb); 168 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 169 exit: 170 pci_dev_put(p); 171 } 172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 175 176 /* 177 * VIA Apollo VP3 needs ETBF on BT848/878 178 */ 179 static void __devinit quirk_viaetbf(struct pci_dev *dev) 180 { 181 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 182 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 183 pci_pci_problems |= PCIPCI_VIAETBF; 184 } 185 } 186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 187 188 static void __devinit quirk_vsfx(struct pci_dev *dev) 189 { 190 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 191 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 192 pci_pci_problems |= PCIPCI_VSFX; 193 } 194 } 195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 196 197 /* 198 * Ali Magik requires workarounds to be used by the drivers 199 * that DMA to AGP space. Latency must be set to 0xA and triton 200 * workaround applied too 201 * [Info kindly provided by ALi] 202 */ 203 static void __init quirk_alimagik(struct pci_dev *dev) 204 { 205 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 206 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 207 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 208 } 209 } 210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 212 213 /* 214 * Natoma has some interesting boundary conditions with Zoran stuff 215 * at least 216 */ 217 static void __devinit quirk_natoma(struct pci_dev *dev) 218 { 219 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 220 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 221 pci_pci_problems |= PCIPCI_NATOMA; 222 } 223 } 224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 230 231 /* 232 * This chip can cause PCI parity errors if config register 0xA0 is read 233 * while DMAs are occurring. 234 */ 235 static void __devinit quirk_citrine(struct pci_dev *dev) 236 { 237 dev->cfg_size = 0xA0; 238 } 239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 240 241 /* 242 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 243 * If it's needed, re-allocate the region. 244 */ 245 static void __devinit quirk_s3_64M(struct pci_dev *dev) 246 { 247 struct resource *r = &dev->resource[0]; 248 249 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 250 r->start = 0; 251 r->end = 0x3ffffff; 252 } 253 } 254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 256 257 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 258 unsigned size, int nr, const char *name) 259 { 260 region &= ~(size-1); 261 if (region) { 262 struct pci_bus_region bus_region; 263 struct resource *res = dev->resource + nr; 264 265 res->name = pci_name(dev); 266 res->start = region; 267 res->end = region + size - 1; 268 res->flags = IORESOURCE_IO; 269 270 /* Convert from PCI bus to resource space. */ 271 bus_region.start = res->start; 272 bus_region.end = res->end; 273 pcibios_bus_to_resource(dev, res, &bus_region); 274 275 pci_claim_resource(dev, nr); 276 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 277 } 278 } 279 280 /* 281 * ATI Northbridge setups MCE the processor if you even 282 * read somewhere between 0x3b0->0x3bb or read 0x3d3 283 */ 284 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 285 { 286 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 287 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 288 request_region(0x3b0, 0x0C, "RadeonIGP"); 289 request_region(0x3d3, 0x01, "RadeonIGP"); 290 } 291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 292 293 /* 294 * Let's make the southbridge information explicit instead 295 * of having to worry about people probing the ACPI areas, 296 * for example.. (Yes, it happens, and if you read the wrong 297 * ACPI register it will put the machine to sleep with no 298 * way of waking it up again. Bummer). 299 * 300 * ALI M7101: Two IO regions pointed to by words at 301 * 0xE0 (64 bytes of ACPI registers) 302 * 0xE2 (32 bytes of SMB registers) 303 */ 304 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 305 { 306 u16 region; 307 308 pci_read_config_word(dev, 0xE0, ®ion); 309 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 310 pci_read_config_word(dev, 0xE2, ®ion); 311 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 312 } 313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 314 315 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 316 { 317 u32 devres; 318 u32 mask, size, base; 319 320 pci_read_config_dword(dev, port, &devres); 321 if ((devres & enable) != enable) 322 return; 323 mask = (devres >> 16) & 15; 324 base = devres & 0xffff; 325 size = 16; 326 for (;;) { 327 unsigned bit = size >> 1; 328 if ((bit & mask) == bit) 329 break; 330 size = bit; 331 } 332 /* 333 * For now we only print it out. Eventually we'll want to 334 * reserve it (at least if it's in the 0x1000+ range), but 335 * let's get enough confirmation reports first. 336 */ 337 base &= -size; 338 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); 339 } 340 341 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 342 { 343 u32 devres; 344 u32 mask, size, base; 345 346 pci_read_config_dword(dev, port, &devres); 347 if ((devres & enable) != enable) 348 return; 349 base = devres & 0xffff0000; 350 mask = (devres & 0x3f) << 16; 351 size = 128 << 16; 352 for (;;) { 353 unsigned bit = size >> 1; 354 if ((bit & mask) == bit) 355 break; 356 size = bit; 357 } 358 /* 359 * For now we only print it out. Eventually we'll want to 360 * reserve it, but let's get enough confirmation reports first. 361 */ 362 base &= -size; 363 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); 364 } 365 366 /* 367 * PIIX4 ACPI: Two IO regions pointed to by longwords at 368 * 0x40 (64 bytes of ACPI registers) 369 * 0x90 (16 bytes of SMB registers) 370 * and a few strange programmable PIIX4 device resources. 371 */ 372 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 373 { 374 u32 region, res_a; 375 376 pci_read_config_dword(dev, 0x40, ®ion); 377 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 378 pci_read_config_dword(dev, 0x90, ®ion); 379 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 380 381 /* Device resource A has enables for some of the other ones */ 382 pci_read_config_dword(dev, 0x5c, &res_a); 383 384 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 385 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 386 387 /* Device resource D is just bitfields for static resources */ 388 389 /* Device 12 enabled? */ 390 if (res_a & (1 << 29)) { 391 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 392 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 393 } 394 /* Device 13 enabled? */ 395 if (res_a & (1 << 30)) { 396 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 397 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 398 } 399 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 400 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 401 } 402 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 403 404 /* 405 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 406 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 407 * 0x58 (64 bytes of GPIO I/O space) 408 */ 409 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 410 { 411 u32 region; 412 413 pci_read_config_dword(dev, 0x40, ®ion); 414 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); 415 416 pci_read_config_dword(dev, 0x58, ®ion); 417 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 418 } 419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 428 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 429 430 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) 431 { 432 u32 region; 433 434 pci_read_config_dword(dev, 0x40, ®ion); 435 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); 436 437 pci_read_config_dword(dev, 0x48, ®ion); 438 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 439 } 440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); 441 442 /* 443 * VIA ACPI: One IO region pointed to by longword at 444 * 0x48 or 0x20 (256 bytes of ACPI registers) 445 */ 446 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 447 { 448 u8 rev; 449 u32 region; 450 451 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 452 if (rev & 0x10) { 453 pci_read_config_dword(dev, 0x48, ®ion); 454 region &= PCI_BASE_ADDRESS_IO_MASK; 455 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 456 } 457 } 458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 459 460 /* 461 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 462 * 0x48 (256 bytes of ACPI registers) 463 * 0x70 (128 bytes of hardware monitoring register) 464 * 0x90 (16 bytes of SMB registers) 465 */ 466 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 467 { 468 u16 hm; 469 u32 smb; 470 471 quirk_vt82c586_acpi(dev); 472 473 pci_read_config_word(dev, 0x70, &hm); 474 hm &= PCI_BASE_ADDRESS_IO_MASK; 475 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 476 477 pci_read_config_dword(dev, 0x90, &smb); 478 smb &= PCI_BASE_ADDRESS_IO_MASK; 479 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 480 } 481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 482 483 /* 484 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 485 * 0x88 (128 bytes of power management registers) 486 * 0xd0 (16 bytes of SMB registers) 487 */ 488 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 489 { 490 u16 pm, smb; 491 492 pci_read_config_word(dev, 0x88, &pm); 493 pm &= PCI_BASE_ADDRESS_IO_MASK; 494 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 495 496 pci_read_config_word(dev, 0xd0, &smb); 497 smb &= PCI_BASE_ADDRESS_IO_MASK; 498 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 499 } 500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 501 502 503 #ifdef CONFIG_X86_IO_APIC 504 505 #include <asm/io_apic.h> 506 507 /* 508 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 509 * devices to the external APIC. 510 * 511 * TODO: When we have device-specific interrupt routers, 512 * this code will go away from quirks. 513 */ 514 static void __devinit quirk_via_ioapic(struct pci_dev *dev) 515 { 516 u8 tmp; 517 518 if (nr_ioapics < 1) 519 tmp = 0; /* nothing routed to external APIC */ 520 else 521 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 522 523 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 524 tmp == 0 ? "Disa" : "Ena"); 525 526 /* Offset 0x58: External APIC IRQ output control */ 527 pci_write_config_byte (dev, 0x58, tmp); 528 } 529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 530 531 /* 532 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 533 * This leads to doubled level interrupt rates. 534 * Set this bit to get rid of cycle wastage. 535 * Otherwise uncritical. 536 */ 537 static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 538 { 539 u8 misc_control2; 540 #define BYPASS_APIC_DEASSERT 8 541 542 pci_read_config_byte(dev, 0x5B, &misc_control2); 543 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 544 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); 545 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 546 } 547 } 548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 549 550 /* 551 * The AMD io apic can hang the box when an apic irq is masked. 552 * We check all revs >= B0 (yet not in the pre production!) as the bug 553 * is currently marked NoFix 554 * 555 * We have multiple reports of hangs with this chipset that went away with 556 * noapic specified. For the moment we assume its the errata. We may be wrong 557 * of course. However the advice is demonstrably good even if so.. 558 */ 559 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 560 { 561 u8 rev; 562 563 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 564 if (rev >= 0x02) { 565 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n"); 566 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 567 } 568 } 569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 570 571 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 572 { 573 if (dev->devfn == 0 && dev->bus->number == 0) 574 sis_apic_bug = 1; 575 } 576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 577 578 int pci_msi_quirk; 579 580 #define AMD8131_revA0 0x01 581 #define AMD8131_revB0 0x11 582 #define AMD8131_MISC 0x40 583 #define AMD8131_NIOAMODE_BIT 0 584 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) 585 { 586 unsigned char revid, tmp; 587 588 if (dev->subordinate) { 589 printk(KERN_WARNING "PCI: MSI quirk detected. " 590 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n"); 591 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 592 } 593 594 if (nr_ioapics == 0) 595 return; 596 597 pci_read_config_byte(dev, PCI_REVISION_ID, &revid); 598 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { 599 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 600 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 601 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 602 pci_write_config_byte( dev, AMD8131_MISC, tmp); 603 } 604 } 605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); 606 607 static void __init quirk_svw_msi(struct pci_dev *dev) 608 { 609 pci_msi_quirk = 1; 610 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 611 } 612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi ); 613 #endif /* CONFIG_X86_IO_APIC */ 614 615 616 /* 617 * FIXME: it is questionable that quirk_via_acpi 618 * is needed. It shows up as an ISA bridge, and does not 619 * support the PCI_INTERRUPT_LINE register at all. Therefore 620 * it seems like setting the pci_dev's 'irq' to the 621 * value of the ACPI SCI interrupt is only done for convenience. 622 * -jgarzik 623 */ 624 static void __devinit quirk_via_acpi(struct pci_dev *d) 625 { 626 /* 627 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 628 */ 629 u8 irq; 630 pci_read_config_byte(d, 0x42, &irq); 631 irq &= 0xf; 632 if (irq && (irq != 2)) 633 d->irq = irq; 634 } 635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 637 638 /* 639 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip 640 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: 641 * when written, it makes an internal connection to the PIC. 642 * For these devices, this register is defined to be 4 bits wide. 643 * Normally this is fine. However for IO-APIC motherboards, or 644 * non-x86 architectures (yes Via exists on PPC among other places), 645 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get 646 * interrupts delivered properly. 647 * 648 * Some of the on-chip devices are actually '586 devices' so they are 649 * listed here. 650 */ 651 static void quirk_via_irq(struct pci_dev *dev) 652 { 653 u8 irq, new_irq; 654 655 new_irq = dev->irq & 0xf; 656 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 657 if (new_irq != irq) { 658 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n", 659 pci_name(dev), irq, new_irq); 660 udelay(15); /* unknown if delay really needed */ 661 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 662 } 663 } 664 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq); 665 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq); 666 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq); 667 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq); 668 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq); 669 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq); 670 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq); 671 672 /* 673 * VIA VT82C598 has its device ID settable and many BIOSes 674 * set it to the ID of VT82C597 for backward compatibility. 675 * We need to switch it off to be able to recognize the real 676 * type of the chip. 677 */ 678 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 679 { 680 pci_write_config_byte(dev, 0xfc, 0); 681 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 682 } 683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 684 685 /* 686 * CardBus controllers have a legacy base address that enables them 687 * to respond as i82365 pcmcia controllers. We don't want them to 688 * do this even if the Linux CardBus driver is not loaded, because 689 * the Linux i82365 driver does not (and should not) handle CardBus. 690 */ 691 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) 692 { 693 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 694 return; 695 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 696 } 697 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 698 699 /* 700 * Following the PCI ordering rules is optional on the AMD762. I'm not 701 * sure what the designers were smoking but let's not inhale... 702 * 703 * To be fair to AMD, it follows the spec by default, its BIOS people 704 * who turn it off! 705 */ 706 static void __devinit quirk_amd_ordering(struct pci_dev *dev) 707 { 708 u32 pcic; 709 pci_read_config_dword(dev, 0x4C, &pcic); 710 if ((pcic&6)!=6) { 711 pcic |= 6; 712 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 713 pci_write_config_dword(dev, 0x4C, pcic); 714 pci_read_config_dword(dev, 0x84, &pcic); 715 pcic |= (1<<23); /* Required in this mode */ 716 pci_write_config_dword(dev, 0x84, pcic); 717 } 718 } 719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 720 721 /* 722 * DreamWorks provided workaround for Dunord I-3000 problem 723 * 724 * This card decodes and responds to addresses not apparently 725 * assigned to it. We force a larger allocation to ensure that 726 * nothing gets put too close to it. 727 */ 728 static void __devinit quirk_dunord ( struct pci_dev * dev ) 729 { 730 struct resource *r = &dev->resource [1]; 731 r->start = 0; 732 r->end = 0xffffff; 733 } 734 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 735 736 /* 737 * i82380FB mobile docking controller: its PCI-to-PCI bridge 738 * is subtractive decoding (transparent), and does indicate this 739 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 740 * instead of 0x01. 741 */ 742 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 743 { 744 dev->transparent = 1; 745 } 746 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 748 749 /* 750 * Common misconfiguration of the MediaGX/Geode PCI master that will 751 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 752 * datasheets found at http://www.national.com/ds/GX for info on what 753 * these bits do. <christer@weinigel.se> 754 */ 755 static void __init quirk_mediagx_master(struct pci_dev *dev) 756 { 757 u8 reg; 758 pci_read_config_byte(dev, 0x41, ®); 759 if (reg & 2) { 760 reg &= ~2; 761 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 762 pci_write_config_byte(dev, 0x41, reg); 763 } 764 } 765 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 766 767 /* 768 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers 769 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and 770 * secondary channels respectively). If the device reports Compatible mode 771 * but does use BAR0-3 for address decoding, we assume that firmware has 772 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374). 773 * Exceptions (if they exist) must be handled in chip/architecture specific 774 * fixups. 775 * 776 * Note: for non x86 people. You may need an arch specific quirk to handle 777 * moving IDE devices to native mode as well. Some plug in card devices power 778 * up in compatible mode and assume the BIOS will adjust them. 779 * 780 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as 781 * we do now ? We don't want is pci_enable_device to come along 782 * and assign new resources. Both approaches work for that. 783 */ 784 static void __devinit quirk_ide_bases(struct pci_dev *dev) 785 { 786 struct resource *res; 787 int first_bar = 2, last_bar = 0; 788 789 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 790 return; 791 792 res = &dev->resource[0]; 793 794 /* primary channel: ProgIf bit 0, BAR0, BAR1 */ 795 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { 796 res[0].start = res[0].end = res[0].flags = 0; 797 res[1].start = res[1].end = res[1].flags = 0; 798 first_bar = 0; 799 last_bar = 1; 800 } 801 802 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */ 803 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { 804 res[2].start = res[2].end = res[2].flags = 0; 805 res[3].start = res[3].end = res[3].flags = 0; 806 last_bar = 3; 807 } 808 809 if (!last_bar) 810 return; 811 812 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n", 813 first_bar, last_bar, pci_name(dev)); 814 } 815 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases); 816 817 /* 818 * Ensure C0 rev restreaming is off. This is normally done by 819 * the BIOS but in the odd case it is not the results are corruption 820 * hence the presence of a Linux check 821 */ 822 static void __init quirk_disable_pxb(struct pci_dev *pdev) 823 { 824 u16 config; 825 u8 rev; 826 827 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 828 if (rev != 0x04) /* Only C0 requires this */ 829 return; 830 pci_read_config_word(pdev, 0x40, &config); 831 if (config & (1<<6)) { 832 config &= ~(1<<6); 833 pci_write_config_word(pdev, 0x40, config); 834 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 835 } 836 } 837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 838 839 840 /* 841 * Serverworks CSB5 IDE does not fully support native mode 842 */ 843 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 844 { 845 u8 prog; 846 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 847 if (prog & 5) { 848 prog &= ~5; 849 pdev->class &= ~5; 850 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 851 /* need to re-assign BARs for compat mode */ 852 quirk_ide_bases(pdev); 853 } 854 } 855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 856 857 /* 858 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 859 */ 860 static void __init quirk_ide_samemode(struct pci_dev *pdev) 861 { 862 u8 prog; 863 864 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 865 866 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 867 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 868 prog &= ~5; 869 pdev->class &= ~5; 870 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 871 /* need to re-assign BARs for compat mode */ 872 quirk_ide_bases(pdev); 873 } 874 } 875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 876 877 /* This was originally an Alpha specific thing, but it really fits here. 878 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 879 */ 880 static void __init quirk_eisa_bridge(struct pci_dev *dev) 881 { 882 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 883 } 884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 885 886 /* 887 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled 888 * when a PCI-Soundcard is added. The BIOS only gives Options 889 * "Disabled" and "AUTO". This Quirk Sets the corresponding 890 * Register-Value to enable the Soundcard. 891 * 892 * FIXME: Presently this quirk will run on anything that has an 8237 893 * which isn't correct, we need to check DMI tables or something in 894 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it 895 * runs everywhere at present we suppress the printk output in most 896 * irrelevant cases. 897 */ 898 static void __init k8t_sound_hostbridge(struct pci_dev *dev) 899 { 900 unsigned char val; 901 902 pci_read_config_byte(dev, 0x50, &val); 903 if (val == 0x88 || val == 0xc8) { 904 /* Assume it's probably a MSI-K8T-Neo2Fir */ 905 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n"); 906 pci_write_config_byte(dev, 0x50, val & (~0x40)); 907 908 /* Verify the Change for Status output */ 909 pci_read_config_byte(dev, 0x50, &val); 910 if (val & 0x40) 911 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n"); 912 else 913 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n"); 914 } 915 } 916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge); 917 918 #ifndef CONFIG_ACPI_SLEEP 919 /* 920 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 921 * is not activated. The myth is that Asus said that they do not want the 922 * users to be irritated by just another PCI Device in the Win98 device 923 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 924 * package 2.7.0 for details) 925 * 926 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 927 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 928 * becomes necessary to do this tweak in two steps -- I've chosen the Host 929 * bridge as trigger. 930 * 931 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram 932 * will cause thermal management to break down, and causing machine to 933 * overheat. 934 */ 935 static int __initdata asus_hides_smbus; 936 937 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 938 { 939 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 940 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 941 switch(dev->subsystem_device) { 942 case 0x8025: /* P4B-LX */ 943 case 0x8070: /* P4B */ 944 case 0x8088: /* P4B533 */ 945 case 0x1626: /* L3C notebook */ 946 asus_hides_smbus = 1; 947 } 948 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 949 switch(dev->subsystem_device) { 950 case 0x80b1: /* P4GE-V */ 951 case 0x80b2: /* P4PE */ 952 case 0x8093: /* P4B533-V */ 953 asus_hides_smbus = 1; 954 } 955 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 956 switch(dev->subsystem_device) { 957 case 0x8030: /* P4T533 */ 958 asus_hides_smbus = 1; 959 } 960 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 961 switch (dev->subsystem_device) { 962 case 0x8070: /* P4G8X Deluxe */ 963 asus_hides_smbus = 1; 964 } 965 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 966 switch (dev->subsystem_device) { 967 case 0x1751: /* M2N notebook */ 968 case 0x1821: /* M5N notebook */ 969 asus_hides_smbus = 1; 970 } 971 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 972 switch (dev->subsystem_device) { 973 case 0x184b: /* W1N notebook */ 974 case 0x186a: /* M6Ne notebook */ 975 asus_hides_smbus = 1; 976 } 977 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { 978 switch (dev->subsystem_device) { 979 case 0x1882: /* M6V notebook */ 980 case 0x1977: /* A6VA notebook */ 981 asus_hides_smbus = 1; 982 } 983 } 984 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 985 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 986 switch(dev->subsystem_device) { 987 case 0x088C: /* HP Compaq nc8000 */ 988 case 0x0890: /* HP Compaq nc6000 */ 989 asus_hides_smbus = 1; 990 } 991 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 992 switch (dev->subsystem_device) { 993 case 0x12bc: /* HP D330L */ 994 case 0x12bd: /* HP D530 */ 995 asus_hides_smbus = 1; 996 } 997 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { 998 switch (dev->subsystem_device) { 999 case 0x099c: /* HP Compaq nx6110 */ 1000 asus_hides_smbus = 1; 1001 } 1002 } 1003 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { 1004 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1005 switch(dev->subsystem_device) { 1006 case 0x0001: /* Toshiba Satellite A40 */ 1007 asus_hides_smbus = 1; 1008 } 1009 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1010 switch(dev->subsystem_device) { 1011 case 0x0001: /* Toshiba Tecra M2 */ 1012 asus_hides_smbus = 1; 1013 } 1014 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1015 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1016 switch(dev->subsystem_device) { 1017 case 0xC00C: /* Samsung P35 notebook */ 1018 asus_hides_smbus = 1; 1019 } 1020 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1021 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1022 switch(dev->subsystem_device) { 1023 case 0x0058: /* Compaq Evo N620c */ 1024 asus_hides_smbus = 1; 1025 } 1026 } 1027 } 1028 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 1029 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 1030 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 1031 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 1032 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 1033 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 1034 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 1035 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); 1036 1037 static void __init asus_hides_smbus_lpc(struct pci_dev *dev) 1038 { 1039 u16 val; 1040 1041 if (likely(!asus_hides_smbus)) 1042 return; 1043 1044 pci_read_config_word(dev, 0xF2, &val); 1045 if (val & 0x8) { 1046 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1047 pci_read_config_word(dev, 0xF2, &val); 1048 if (val & 0x8) 1049 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1050 else 1051 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 1052 } 1053 } 1054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc ); 1060 1061 static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1062 { 1063 u32 val, rcba; 1064 void __iomem *base; 1065 1066 if (likely(!asus_hides_smbus)) 1067 return; 1068 pci_read_config_dword(dev, 0xF0, &rcba); 1069 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ 1070 if (base == NULL) return; 1071 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ 1072 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ 1073 iounmap(base); 1074 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); 1075 } 1076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1077 1078 #endif 1079 1080 /* 1081 * SiS 96x south bridge: BIOS typically hides SMBus device... 1082 */ 1083 static void __init quirk_sis_96x_smbus(struct pci_dev *dev) 1084 { 1085 u8 val = 0; 1086 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 1087 pci_read_config_byte(dev, 0x77, &val); 1088 pci_write_config_byte(dev, 0x77, val & ~0x10); 1089 pci_read_config_byte(dev, 0x77, &val); 1090 } 1091 1092 /* 1093 * ... This is further complicated by the fact that some SiS96x south 1094 * bridges pretend to be 85C503/5513 instead. In that case see if we 1095 * spotted a compatible north bridge to make sure. 1096 * (pci_find_device doesn't work yet) 1097 * 1098 * We can also enable the sis96x bit in the discovery register.. 1099 */ 1100 static int __devinitdata sis_96x_compatible = 0; 1101 1102 #define SIS_DETECT_REGISTER 0x40 1103 1104 static void __init quirk_sis_503(struct pci_dev *dev) 1105 { 1106 u8 reg; 1107 u16 devid; 1108 1109 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1110 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1111 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1112 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1113 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1114 return; 1115 } 1116 1117 /* Make people aware that we changed the config.. */ 1118 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible); 1119 1120 /* 1121 * Ok, it now shows up as a 96x.. The 96x quirks are after 1122 * the 503 quirk in the quirk table, so they'll automatically 1123 * run and enable things like the SMBus device 1124 */ 1125 dev->device = devid; 1126 } 1127 1128 static void __init quirk_sis_96x_compatible(struct pci_dev *dev) 1129 { 1130 sis_96x_compatible = 1; 1131 } 1132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible ); 1133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible ); 1134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible ); 1135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible ); 1136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible ); 1137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible ); 1138 1139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1140 /* 1141 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1142 * and MC97 modem controller are disabled when a second PCI soundcard is 1143 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1144 * -- bjd 1145 */ 1146 static void __init asus_hides_ac97_lpc(struct pci_dev *dev) 1147 { 1148 u8 val; 1149 int asus_hides_ac97 = 0; 1150 1151 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1152 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1153 asus_hides_ac97 = 1; 1154 } 1155 1156 if (!asus_hides_ac97) 1157 return; 1158 1159 pci_read_config_byte(dev, 0x50, &val); 1160 if (val & 0xc0) { 1161 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1162 pci_read_config_byte(dev, 0x50, &val); 1163 if (val & 0xc0) 1164 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1165 else 1166 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); 1167 } 1168 } 1169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); 1170 1171 1172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1176 1177 #ifdef CONFIG_X86_IO_APIC 1178 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1179 { 1180 int i; 1181 1182 if ((pdev->class >> 8) != 0xff00) 1183 return; 1184 1185 /* the first BAR is the location of the IO APIC...we must 1186 * not touch this (and it's already covered by the fixmap), so 1187 * forcibly insert it into the resource tree */ 1188 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1189 insert_resource(&iomem_resource, &pdev->resource[0]); 1190 1191 /* The next five BARs all seem to be rubbish, so just clean 1192 * them out */ 1193 for (i=1; i < 6; i++) { 1194 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1195 } 1196 1197 } 1198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1199 #endif 1200 1201 enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 }; 1202 /* Defaults to combined */ 1203 static enum ide_combined_type combined_mode; 1204 1205 static int __init combined_setup(char *str) 1206 { 1207 if (!strncmp(str, "ide", 3)) 1208 combined_mode = IDE; 1209 else if (!strncmp(str, "libata", 6)) 1210 combined_mode = LIBATA; 1211 else /* "combined" or anything else defaults to old behavior */ 1212 combined_mode = COMBINED; 1213 1214 return 1; 1215 } 1216 __setup("combined_mode=", combined_setup); 1217 1218 #ifdef CONFIG_SCSI_SATA_INTEL_COMBINED 1219 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) 1220 { 1221 u8 prog, comb, tmp; 1222 int ich = 0; 1223 1224 /* 1225 * Narrow down to Intel SATA PCI devices. 1226 */ 1227 switch (pdev->device) { 1228 /* PCI ids taken from drivers/scsi/ata_piix.c */ 1229 case 0x24d1: 1230 case 0x24df: 1231 case 0x25a3: 1232 case 0x25b0: 1233 ich = 5; 1234 break; 1235 case 0x2651: 1236 case 0x2652: 1237 case 0x2653: 1238 case 0x2680: /* ESB2 */ 1239 ich = 6; 1240 break; 1241 case 0x27c0: 1242 case 0x27c4: 1243 ich = 7; 1244 break; 1245 case 0x2828: /* ICH8M */ 1246 ich = 8; 1247 break; 1248 default: 1249 /* we do not handle this PCI device */ 1250 return; 1251 } 1252 1253 /* 1254 * Read combined mode register. 1255 */ 1256 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ 1257 1258 if (ich == 5) { 1259 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ 1260 if (tmp == 0x4) /* bits 10x */ 1261 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1262 else if (tmp == 0x6) /* bits 11x */ 1263 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1264 else 1265 return; /* not in combined mode */ 1266 } else { 1267 WARN_ON((ich != 6) && (ich != 7) && (ich != 8)); 1268 tmp &= 0x3; /* interesting bits 1:0 */ 1269 if (tmp & (1 << 0)) 1270 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1271 else if (tmp & (1 << 1)) 1272 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1273 else 1274 return; /* not in combined mode */ 1275 } 1276 1277 /* 1278 * Read programming interface register. 1279 * (Tells us if it's legacy or native mode) 1280 */ 1281 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1282 1283 /* if SATA port is in native mode, we're ok. */ 1284 if (prog & comb) 1285 return; 1286 1287 /* Don't reserve any so the IDE driver can get them (but only if 1288 * combined_mode=ide). 1289 */ 1290 if (combined_mode == IDE) 1291 return; 1292 1293 /* Grab them both for libata if combined_mode=libata. */ 1294 if (combined_mode == LIBATA) { 1295 request_region(0x1f0, 8, "libata"); /* port 0 */ 1296 request_region(0x170, 8, "libata"); /* port 1 */ 1297 return; 1298 } 1299 1300 /* SATA port is in legacy mode. Reserve port so that 1301 * IDE driver does not attempt to use it. If request_region 1302 * fails, it will be obvious at boot time, so we don't bother 1303 * checking return values. 1304 */ 1305 if (comb == (1 << 0)) 1306 request_region(0x1f0, 8, "libata"); /* port 0 */ 1307 else 1308 request_region(0x170, 8, "libata"); /* port 1 */ 1309 } 1310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); 1311 #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */ 1312 1313 1314 int pcie_mch_quirk; 1315 1316 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1317 { 1318 pcie_mch_quirk = 1; 1319 } 1320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1323 1324 1325 /* 1326 * It's possible for the MSI to get corrupted if shpc and acpi 1327 * are used together on certain PXH-based systems. 1328 */ 1329 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1330 { 1331 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), 1332 PCI_CAP_ID_MSI); 1333 dev->no_msi = 1; 1334 1335 printk(KERN_WARNING "PCI: PXH quirk detected, " 1336 "disabling MSI for SHPC device\n"); 1337 } 1338 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1339 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1340 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1341 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1342 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1343 1344 1345 /* 1346 * Fixup the cardbus bridges on the IBM Dock II docking station 1347 */ 1348 static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev) 1349 { 1350 u32 val; 1351 1352 /* 1353 * tie the 2 interrupt pins to INTA, and configure the 1354 * multifunction routing register to handle this. 1355 */ 1356 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) && 1357 (dev->subsystem_device == 0x0148)) { 1358 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge " 1359 "applying quirk\n"); 1360 pci_read_config_dword(dev, 0x8c, &val); 1361 val = ((val & 0xffffff00) | 0x1002); 1362 pci_write_config_dword(dev, 0x8c, val); 1363 pci_read_config_dword(dev, 0x80, &val); 1364 val = ((val & 0x00ffff00) | 0x2864c077); 1365 pci_write_config_dword(dev, 0x80, val); 1366 } 1367 } 1368 1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, 1370 quirk_ibm_dock2_cardbus); 1371 1372 static void __devinit quirk_netmos(struct pci_dev *dev) 1373 { 1374 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1375 unsigned int num_serial = dev->subsystem_device & 0xf; 1376 1377 /* 1378 * These Netmos parts are multiport serial devices with optional 1379 * parallel ports. Even when parallel ports are present, they 1380 * are identified as class SERIAL, which means the serial driver 1381 * will claim them. To prevent this, mark them as class OTHER. 1382 * These combo devices should be claimed by parport_serial. 1383 * 1384 * The subdevice ID is of the form 0x00PS, where <P> is the number 1385 * of parallel ports and <S> is the number of serial ports. 1386 */ 1387 switch (dev->device) { 1388 case PCI_DEVICE_ID_NETMOS_9735: 1389 case PCI_DEVICE_ID_NETMOS_9745: 1390 case PCI_DEVICE_ID_NETMOS_9835: 1391 case PCI_DEVICE_ID_NETMOS_9845: 1392 case PCI_DEVICE_ID_NETMOS_9855: 1393 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1394 num_parallel) { 1395 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1396 "%u serial); changing class SERIAL to OTHER " 1397 "(use parport_serial)\n", 1398 dev->device, num_parallel, num_serial); 1399 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1400 (dev->class & 0xff); 1401 } 1402 } 1403 } 1404 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1405 1406 1407 static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1408 { 1409 /* rev 1 ncr53c810 chips don't set the class at all which means 1410 * they don't get their resources remapped. Fix that here. 1411 */ 1412 1413 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1414 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); 1415 dev->class = PCI_CLASS_STORAGE_SCSI; 1416 } 1417 } 1418 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1419 1420 1421 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1422 { 1423 while (f < end) { 1424 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1425 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1426 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1427 f->hook(dev); 1428 } 1429 f++; 1430 } 1431 } 1432 1433 extern struct pci_fixup __start_pci_fixups_early[]; 1434 extern struct pci_fixup __end_pci_fixups_early[]; 1435 extern struct pci_fixup __start_pci_fixups_header[]; 1436 extern struct pci_fixup __end_pci_fixups_header[]; 1437 extern struct pci_fixup __start_pci_fixups_final[]; 1438 extern struct pci_fixup __end_pci_fixups_final[]; 1439 extern struct pci_fixup __start_pci_fixups_enable[]; 1440 extern struct pci_fixup __end_pci_fixups_enable[]; 1441 1442 1443 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 1444 { 1445 struct pci_fixup *start, *end; 1446 1447 switch(pass) { 1448 case pci_fixup_early: 1449 start = __start_pci_fixups_early; 1450 end = __end_pci_fixups_early; 1451 break; 1452 1453 case pci_fixup_header: 1454 start = __start_pci_fixups_header; 1455 end = __end_pci_fixups_header; 1456 break; 1457 1458 case pci_fixup_final: 1459 start = __start_pci_fixups_final; 1460 end = __end_pci_fixups_final; 1461 break; 1462 1463 case pci_fixup_enable: 1464 start = __start_pci_fixups_enable; 1465 end = __end_pci_fixups_enable; 1466 break; 1467 1468 default: 1469 /* stupid compiler warning, you would think with an enum... */ 1470 return; 1471 } 1472 pci_do_fixups(dev, start, end); 1473 } 1474 1475 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1476 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1477 { 1478 u16 en1k; 1479 u8 io_base_lo, io_limit_lo; 1480 unsigned long base, limit; 1481 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1482 1483 pci_read_config_word(dev, 0x40, &en1k); 1484 1485 if (en1k & 0x200) { 1486 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); 1487 1488 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1489 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1490 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1491 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1492 1493 if (base <= limit) { 1494 res->start = base; 1495 res->end = limit + 0x3ff; 1496 } 1497 } 1498 } 1499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1500 1501 /* Under some circumstances, AER is not linked with extended capabilities. 1502 * Force it to be linked by setting the corresponding control bit in the 1503 * config space. 1504 */ 1505 static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1506 { 1507 uint8_t b; 1508 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1509 if (!(b & 0x20)) { 1510 pci_write_config_byte(dev, 0xf41, b | 0x20); 1511 printk(KERN_INFO 1512 "PCI: Linking AER extended capability on %s\n", 1513 pci_name(dev)); 1514 } 1515 } 1516 } 1517 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1518 quirk_nvidia_ck804_pcie_aer_ext_cap); 1519 1520 EXPORT_SYMBOL(pcie_mch_quirk); 1521 #ifdef CONFIG_HOTPLUG 1522 EXPORT_SYMBOL(pci_fixup_device); 1523 #endif 1524