1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * The bridge optimization stuff has been removed. If you really 11 * have a silly BIOS which is unable to set your host bridge right, 12 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 13 */ 14 15 #include <linux/config.h> 16 #include <linux/types.h> 17 #include <linux/kernel.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/acpi.h> 22 #include "pci.h" 23 24 /* Deal with broken BIOS'es that neglect to enable passive release, 25 which can cause problems in combination with the 82441FX/PPro MTRRs */ 26 static void __devinit quirk_passive_release(struct pci_dev *dev) 27 { 28 struct pci_dev *d = NULL; 29 unsigned char dlc; 30 31 /* We have to make sure a particular bit is set in the PIIX3 32 ISA bridge, so we have to go out and find it. */ 33 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 34 pci_read_config_byte(d, 0x82, &dlc); 35 if (!(dlc & 1<<1)) { 36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 37 dlc |= 1<<1; 38 pci_write_config_byte(d, 0x82, dlc); 39 } 40 } 41 } 42 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 43 44 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 45 but VIA don't answer queries. If you happen to have good contacts at VIA 46 ask them for me please -- Alan 47 48 This appears to be BIOS not version dependent. So presumably there is a 49 chipset level fix */ 50 int isa_dma_bridge_buggy; /* Exported */ 51 52 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 53 { 54 if (!isa_dma_bridge_buggy) { 55 isa_dma_bridge_buggy=1; 56 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 57 } 58 } 59 /* 60 * Its not totally clear which chipsets are the problematic ones 61 * We know 82C586 and 82C596 variants are affected. 62 */ 63 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 70 71 int pci_pci_problems; 72 73 /* 74 * Chipsets where PCI->PCI transfers vanish or hang 75 */ 76 static void __devinit quirk_nopcipci(struct pci_dev *dev) 77 { 78 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 79 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 80 pci_pci_problems |= PCIPCI_FAIL; 81 } 82 } 83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 85 86 /* 87 * Triton requires workarounds to be used by the drivers 88 */ 89 static void __devinit quirk_triton(struct pci_dev *dev) 90 { 91 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 92 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 93 pci_pci_problems |= PCIPCI_TRITON; 94 } 95 } 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 100 101 /* 102 * VIA Apollo KT133 needs PCI latency patch 103 * Made according to a windows driver based patch by George E. Breese 104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 106 * the info on which Mr Breese based his work. 107 * 108 * Updated based on further information from the site and also on 109 * information provided by VIA 110 */ 111 static void __devinit quirk_vialatency(struct pci_dev *dev) 112 { 113 struct pci_dev *p; 114 u8 rev; 115 u8 busarb; 116 /* Ok we have a potential problem chipset here. Now see if we have 117 a buggy southbridge */ 118 119 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 120 if (p!=NULL) { 121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 123 /* Check for buggy part revisions */ 124 if (rev < 0x40 || rev > 0x42) 125 goto exit; 126 } else { 127 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 128 if (p==NULL) /* No problem parts */ 129 goto exit; 130 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 131 /* Check for buggy part revisions */ 132 if (rev < 0x10 || rev > 0x12) 133 goto exit; 134 } 135 136 /* 137 * Ok we have the problem. Now set the PCI master grant to 138 * occur every master grant. The apparent bug is that under high 139 * PCI load (quite common in Linux of course) you can get data 140 * loss when the CPU is held off the bus for 3 bus master requests 141 * This happens to include the IDE controllers.... 142 * 143 * VIA only apply this fix when an SB Live! is present but under 144 * both Linux and Windows this isnt enough, and we have seen 145 * corruption without SB Live! but with things like 3 UDMA IDE 146 * controllers. So we ignore that bit of the VIA recommendation.. 147 */ 148 149 pci_read_config_byte(dev, 0x76, &busarb); 150 /* Set bit 4 and bi 5 of byte 76 to 0x01 151 "Master priority rotation on every PCI master grant */ 152 busarb &= ~(1<<5); 153 busarb |= (1<<4); 154 pci_write_config_byte(dev, 0x76, busarb); 155 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 156 exit: 157 pci_dev_put(p); 158 } 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 162 163 /* 164 * VIA Apollo VP3 needs ETBF on BT848/878 165 */ 166 static void __devinit quirk_viaetbf(struct pci_dev *dev) 167 { 168 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 169 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 170 pci_pci_problems |= PCIPCI_VIAETBF; 171 } 172 } 173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 174 175 static void __devinit quirk_vsfx(struct pci_dev *dev) 176 { 177 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 178 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 179 pci_pci_problems |= PCIPCI_VSFX; 180 } 181 } 182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 183 184 /* 185 * Ali Magik requires workarounds to be used by the drivers 186 * that DMA to AGP space. Latency must be set to 0xA and triton 187 * workaround applied too 188 * [Info kindly provided by ALi] 189 */ 190 static void __init quirk_alimagik(struct pci_dev *dev) 191 { 192 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 193 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 194 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 195 } 196 } 197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 199 200 /* 201 * Natoma has some interesting boundary conditions with Zoran stuff 202 * at least 203 */ 204 static void __devinit quirk_natoma(struct pci_dev *dev) 205 { 206 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 208 pci_pci_problems |= PCIPCI_NATOMA; 209 } 210 } 211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 217 218 /* 219 * This chip can cause PCI parity errors if config register 0xA0 is read 220 * while DMAs are occurring. 221 */ 222 static void __devinit quirk_citrine(struct pci_dev *dev) 223 { 224 dev->cfg_size = 0xA0; 225 } 226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 227 228 /* 229 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 230 * If it's needed, re-allocate the region. 231 */ 232 static void __devinit quirk_s3_64M(struct pci_dev *dev) 233 { 234 struct resource *r = &dev->resource[0]; 235 236 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 237 r->start = 0; 238 r->end = 0x3ffffff; 239 } 240 } 241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 243 244 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr) 245 { 246 region &= ~(size-1); 247 if (region) { 248 struct resource *res = dev->resource + nr; 249 250 res->name = pci_name(dev); 251 res->start = region; 252 res->end = region + size - 1; 253 res->flags = IORESOURCE_IO; 254 pci_claim_resource(dev, nr); 255 } 256 } 257 258 /* 259 * ATI Northbridge setups MCE the processor if you even 260 * read somewhere between 0x3b0->0x3bb or read 0x3d3 261 */ 262 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 263 { 264 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 265 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 266 request_region(0x3b0, 0x0C, "RadeonIGP"); 267 request_region(0x3d3, 0x01, "RadeonIGP"); 268 } 269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 270 271 /* 272 * Let's make the southbridge information explicit instead 273 * of having to worry about people probing the ACPI areas, 274 * for example.. (Yes, it happens, and if you read the wrong 275 * ACPI register it will put the machine to sleep with no 276 * way of waking it up again. Bummer). 277 * 278 * ALI M7101: Two IO regions pointed to by words at 279 * 0xE0 (64 bytes of ACPI registers) 280 * 0xE2 (32 bytes of SMB registers) 281 */ 282 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 283 { 284 u16 region; 285 286 pci_read_config_word(dev, 0xE0, ®ion); 287 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES); 288 pci_read_config_word(dev, 0xE2, ®ion); 289 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1); 290 } 291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 292 293 /* 294 * PIIX4 ACPI: Two IO regions pointed to by longwords at 295 * 0x40 (64 bytes of ACPI registers) 296 * 0x90 (32 bytes of SMB registers) 297 */ 298 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 299 { 300 u32 region; 301 302 pci_read_config_dword(dev, 0x40, ®ion); 303 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES); 304 pci_read_config_dword(dev, 0x90, ®ion); 305 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1); 306 } 307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 308 309 /* 310 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 311 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 312 * 0x58 (64 bytes of GPIO I/O space) 313 */ 314 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 315 { 316 u32 region; 317 318 pci_read_config_dword(dev, 0x40, ®ion); 319 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES); 320 321 pci_read_config_dword(dev, 0x58, ®ion); 322 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1); 323 } 324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 334 335 /* 336 * VIA ACPI: One IO region pointed to by longword at 337 * 0x48 or 0x20 (256 bytes of ACPI registers) 338 */ 339 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 340 { 341 u8 rev; 342 u32 region; 343 344 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 345 if (rev & 0x10) { 346 pci_read_config_dword(dev, 0x48, ®ion); 347 region &= PCI_BASE_ADDRESS_IO_MASK; 348 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES); 349 } 350 } 351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 352 353 /* 354 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 355 * 0x48 (256 bytes of ACPI registers) 356 * 0x70 (128 bytes of hardware monitoring register) 357 * 0x90 (16 bytes of SMB registers) 358 */ 359 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 360 { 361 u16 hm; 362 u32 smb; 363 364 quirk_vt82c586_acpi(dev); 365 366 pci_read_config_word(dev, 0x70, &hm); 367 hm &= PCI_BASE_ADDRESS_IO_MASK; 368 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1); 369 370 pci_read_config_dword(dev, 0x90, &smb); 371 smb &= PCI_BASE_ADDRESS_IO_MASK; 372 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2); 373 } 374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 375 376 /* 377 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 378 * 0x88 (128 bytes of power management registers) 379 * 0xd0 (16 bytes of SMB registers) 380 */ 381 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 382 { 383 u16 pm, smb; 384 385 pci_read_config_word(dev, 0x88, &pm); 386 pm &= PCI_BASE_ADDRESS_IO_MASK; 387 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES); 388 389 pci_read_config_word(dev, 0xd0, &smb); 390 smb &= PCI_BASE_ADDRESS_IO_MASK; 391 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1); 392 } 393 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 394 395 396 #ifdef CONFIG_X86_IO_APIC 397 398 #include <asm/io_apic.h> 399 400 /* 401 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 402 * devices to the external APIC. 403 * 404 * TODO: When we have device-specific interrupt routers, 405 * this code will go away from quirks. 406 */ 407 static void __devinit quirk_via_ioapic(struct pci_dev *dev) 408 { 409 u8 tmp; 410 411 if (nr_ioapics < 1) 412 tmp = 0; /* nothing routed to external APIC */ 413 else 414 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 415 416 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 417 tmp == 0 ? "Disa" : "Ena"); 418 419 /* Offset 0x58: External APIC IRQ output control */ 420 pci_write_config_byte (dev, 0x58, tmp); 421 } 422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 423 424 /* 425 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 426 * This leads to doubled level interrupt rates. 427 * Set this bit to get rid of cycle wastage. 428 * Otherwise uncritical. 429 */ 430 static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 431 { 432 u8 misc_control2; 433 #define BYPASS_APIC_DEASSERT 8 434 435 pci_read_config_byte(dev, 0x5B, &misc_control2); 436 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 437 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); 438 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 439 } 440 } 441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 442 443 /* 444 * The AMD io apic can hang the box when an apic irq is masked. 445 * We check all revs >= B0 (yet not in the pre production!) as the bug 446 * is currently marked NoFix 447 * 448 * We have multiple reports of hangs with this chipset that went away with 449 * noapic specified. For the moment we assume its the errata. We may be wrong 450 * of course. However the advice is demonstrably good even if so.. 451 */ 452 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 453 { 454 u8 rev; 455 456 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 457 if (rev >= 0x02) { 458 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n"); 459 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 460 } 461 } 462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 463 464 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 465 { 466 if (dev->devfn == 0 && dev->bus->number == 0) 467 sis_apic_bug = 1; 468 } 469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 470 471 int pci_msi_quirk; 472 473 #define AMD8131_revA0 0x01 474 #define AMD8131_revB0 0x11 475 #define AMD8131_MISC 0x40 476 #define AMD8131_NIOAMODE_BIT 0 477 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) 478 { 479 unsigned char revid, tmp; 480 481 pci_msi_quirk = 1; 482 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 483 484 if (nr_ioapics == 0) 485 return; 486 487 pci_read_config_byte(dev, PCI_REVISION_ID, &revid); 488 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { 489 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 490 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 491 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 492 pci_write_config_byte( dev, AMD8131_MISC, tmp); 493 } 494 } 495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic ); 496 497 static void __init quirk_svw_msi(struct pci_dev *dev) 498 { 499 pci_msi_quirk = 1; 500 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 501 } 502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi ); 503 #endif /* CONFIG_X86_IO_APIC */ 504 505 506 /* 507 * FIXME: it is questionable that quirk_via_acpi 508 * is needed. It shows up as an ISA bridge, and does not 509 * support the PCI_INTERRUPT_LINE register at all. Therefore 510 * it seems like setting the pci_dev's 'irq' to the 511 * value of the ACPI SCI interrupt is only done for convenience. 512 * -jgarzik 513 */ 514 static void __devinit quirk_via_acpi(struct pci_dev *d) 515 { 516 /* 517 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 518 */ 519 u8 irq; 520 pci_read_config_byte(d, 0x42, &irq); 521 irq &= 0xf; 522 if (irq && (irq != 2)) 523 d->irq = irq; 524 } 525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 527 528 /* 529 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip 530 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: 531 * when written, it makes an internal connection to the PIC. 532 * For these devices, this register is defined to be 4 bits wide. 533 * Normally this is fine. However for IO-APIC motherboards, or 534 * non-x86 architectures (yes Via exists on PPC among other places), 535 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get 536 * interrupts delivered properly. 537 */ 538 static void quirk_via_irq(struct pci_dev *dev) 539 { 540 u8 irq, new_irq; 541 542 new_irq = dev->irq & 0xf; 543 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 544 if (new_irq != irq) { 545 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n", 546 pci_name(dev), irq, new_irq); 547 udelay(15); /* unknown if delay really needed */ 548 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 549 } 550 } 551 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq); 552 553 /* 554 * PIIX3 USB: We have to disable USB interrupts that are 555 * hardwired to PIRQD# and may be shared with an 556 * external device. 557 * 558 * Legacy Support Register (LEGSUP): 559 * bit13: USB PIRQ Enable (USBPIRQDEN), 560 * bit4: Trap/SMI On IRQ Enable (USBSMIEN). 561 * 562 * We mask out all r/wc bits, too. 563 */ 564 static void __devinit quirk_piix3_usb(struct pci_dev *dev) 565 { 566 u16 legsup; 567 568 pci_read_config_word(dev, 0xc0, &legsup); 569 legsup &= 0x50ef; 570 pci_write_config_word(dev, 0xc0, legsup); 571 } 572 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb ); 573 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb ); 574 575 /* 576 * VIA VT82C598 has its device ID settable and many BIOSes 577 * set it to the ID of VT82C597 for backward compatibility. 578 * We need to switch it off to be able to recognize the real 579 * type of the chip. 580 */ 581 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 582 { 583 pci_write_config_byte(dev, 0xfc, 0); 584 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 585 } 586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 587 588 /* 589 * CardBus controllers have a legacy base address that enables them 590 * to respond as i82365 pcmcia controllers. We don't want them to 591 * do this even if the Linux CardBus driver is not loaded, because 592 * the Linux i82365 driver does not (and should not) handle CardBus. 593 */ 594 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) 595 { 596 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 597 return; 598 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 599 } 600 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 601 602 /* 603 * Following the PCI ordering rules is optional on the AMD762. I'm not 604 * sure what the designers were smoking but let's not inhale... 605 * 606 * To be fair to AMD, it follows the spec by default, its BIOS people 607 * who turn it off! 608 */ 609 static void __devinit quirk_amd_ordering(struct pci_dev *dev) 610 { 611 u32 pcic; 612 pci_read_config_dword(dev, 0x4C, &pcic); 613 if ((pcic&6)!=6) { 614 pcic |= 6; 615 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 616 pci_write_config_dword(dev, 0x4C, pcic); 617 pci_read_config_dword(dev, 0x84, &pcic); 618 pcic |= (1<<23); /* Required in this mode */ 619 pci_write_config_dword(dev, 0x84, pcic); 620 } 621 } 622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 623 624 /* 625 * DreamWorks provided workaround for Dunord I-3000 problem 626 * 627 * This card decodes and responds to addresses not apparently 628 * assigned to it. We force a larger allocation to ensure that 629 * nothing gets put too close to it. 630 */ 631 static void __devinit quirk_dunord ( struct pci_dev * dev ) 632 { 633 struct resource *r = &dev->resource [1]; 634 r->start = 0; 635 r->end = 0xffffff; 636 } 637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 638 639 /* 640 * i82380FB mobile docking controller: its PCI-to-PCI bridge 641 * is subtractive decoding (transparent), and does indicate this 642 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 643 * instead of 0x01. 644 */ 645 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 646 { 647 dev->transparent = 1; 648 } 649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 651 652 /* 653 * Common misconfiguration of the MediaGX/Geode PCI master that will 654 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 655 * datasheets found at http://www.national.com/ds/GX for info on what 656 * these bits do. <christer@weinigel.se> 657 */ 658 static void __init quirk_mediagx_master(struct pci_dev *dev) 659 { 660 u8 reg; 661 pci_read_config_byte(dev, 0x41, ®); 662 if (reg & 2) { 663 reg &= ~2; 664 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 665 pci_write_config_byte(dev, 0x41, reg); 666 } 667 } 668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 669 670 /* 671 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers 672 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and 673 * secondary channels respectively). If the device reports Compatible mode 674 * but does use BAR0-3 for address decoding, we assume that firmware has 675 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374). 676 * Exceptions (if they exist) must be handled in chip/architecture specific 677 * fixups. 678 * 679 * Note: for non x86 people. You may need an arch specific quirk to handle 680 * moving IDE devices to native mode as well. Some plug in card devices power 681 * up in compatible mode and assume the BIOS will adjust them. 682 * 683 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as 684 * we do now ? We don't want is pci_enable_device to come along 685 * and assign new resources. Both approaches work for that. 686 */ 687 static void __devinit quirk_ide_bases(struct pci_dev *dev) 688 { 689 struct resource *res; 690 int first_bar = 2, last_bar = 0; 691 692 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 693 return; 694 695 res = &dev->resource[0]; 696 697 /* primary channel: ProgIf bit 0, BAR0, BAR1 */ 698 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { 699 res[0].start = res[0].end = res[0].flags = 0; 700 res[1].start = res[1].end = res[1].flags = 0; 701 first_bar = 0; 702 last_bar = 1; 703 } 704 705 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */ 706 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { 707 res[2].start = res[2].end = res[2].flags = 0; 708 res[3].start = res[3].end = res[3].flags = 0; 709 last_bar = 3; 710 } 711 712 if (!last_bar) 713 return; 714 715 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n", 716 first_bar, last_bar, pci_name(dev)); 717 } 718 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases); 719 720 /* 721 * Ensure C0 rev restreaming is off. This is normally done by 722 * the BIOS but in the odd case it is not the results are corruption 723 * hence the presence of a Linux check 724 */ 725 static void __init quirk_disable_pxb(struct pci_dev *pdev) 726 { 727 u16 config; 728 u8 rev; 729 730 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 731 if (rev != 0x04) /* Only C0 requires this */ 732 return; 733 pci_read_config_word(pdev, 0x40, &config); 734 if (config & (1<<6)) { 735 config &= ~(1<<6); 736 pci_write_config_word(pdev, 0x40, config); 737 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 738 } 739 } 740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 741 742 743 /* 744 * Serverworks CSB5 IDE does not fully support native mode 745 */ 746 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 747 { 748 u8 prog; 749 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 750 if (prog & 5) { 751 prog &= ~5; 752 pdev->class &= ~5; 753 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 754 /* need to re-assign BARs for compat mode */ 755 quirk_ide_bases(pdev); 756 } 757 } 758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 759 760 /* 761 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 762 */ 763 static void __init quirk_ide_samemode(struct pci_dev *pdev) 764 { 765 u8 prog; 766 767 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 768 769 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 770 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 771 prog &= ~5; 772 pdev->class &= ~5; 773 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 774 /* need to re-assign BARs for compat mode */ 775 quirk_ide_bases(pdev); 776 } 777 } 778 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 779 780 /* This was originally an Alpha specific thing, but it really fits here. 781 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 782 */ 783 static void __init quirk_eisa_bridge(struct pci_dev *dev) 784 { 785 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 786 } 787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 788 789 /* 790 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 791 * is not activated. The myth is that Asus said that they do not want the 792 * users to be irritated by just another PCI Device in the Win98 device 793 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 794 * package 2.7.0 for details) 795 * 796 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 797 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 798 * becomes necessary to do this tweak in two steps -- I've chosen the Host 799 * bridge as trigger. 800 */ 801 static int __initdata asus_hides_smbus = 0; 802 803 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 804 { 805 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 806 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 807 switch(dev->subsystem_device) { 808 case 0x8025: /* P4B-LX */ 809 case 0x8070: /* P4B */ 810 case 0x8088: /* P4B533 */ 811 case 0x1626: /* L3C notebook */ 812 asus_hides_smbus = 1; 813 } 814 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 815 switch(dev->subsystem_device) { 816 case 0x80b1: /* P4GE-V */ 817 case 0x80b2: /* P4PE */ 818 case 0x8093: /* P4B533-V */ 819 asus_hides_smbus = 1; 820 } 821 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 822 switch(dev->subsystem_device) { 823 case 0x8030: /* P4T533 */ 824 asus_hides_smbus = 1; 825 } 826 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 827 switch (dev->subsystem_device) { 828 case 0x8070: /* P4G8X Deluxe */ 829 asus_hides_smbus = 1; 830 } 831 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 832 switch (dev->subsystem_device) { 833 case 0x1751: /* M2N notebook */ 834 case 0x1821: /* M5N notebook */ 835 asus_hides_smbus = 1; 836 } 837 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 838 switch (dev->subsystem_device) { 839 case 0x184b: /* W1N notebook */ 840 case 0x186a: /* M6Ne notebook */ 841 asus_hides_smbus = 1; 842 } 843 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 844 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 845 switch(dev->subsystem_device) { 846 case 0x088C: /* HP Compaq nc8000 */ 847 case 0x0890: /* HP Compaq nc6000 */ 848 asus_hides_smbus = 1; 849 } 850 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 851 switch (dev->subsystem_device) { 852 case 0x12bc: /* HP D330L */ 853 asus_hides_smbus = 1; 854 } 855 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { 856 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 857 switch(dev->subsystem_device) { 858 case 0x0001: /* Toshiba Satellite A40 */ 859 asus_hides_smbus = 1; 860 } 861 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 862 switch(dev->subsystem_device) { 863 case 0x0001: /* Toshiba Tecra M2 */ 864 asus_hides_smbus = 1; 865 } 866 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 867 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 868 switch(dev->subsystem_device) { 869 case 0xC00C: /* Samsung P35 notebook */ 870 asus_hides_smbus = 1; 871 } 872 } 873 } 874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 881 882 static void __init asus_hides_smbus_lpc(struct pci_dev *dev) 883 { 884 u16 val; 885 886 if (likely(!asus_hides_smbus)) 887 return; 888 889 pci_read_config_word(dev, 0xF2, &val); 890 if (val & 0x8) { 891 pci_write_config_word(dev, 0xF2, val & (~0x8)); 892 pci_read_config_word(dev, 0xF2, &val); 893 if (val & 0x8) 894 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 895 else 896 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 897 } 898 } 899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 904 905 /* 906 * SiS 96x south bridge: BIOS typically hides SMBus device... 907 */ 908 static void __init quirk_sis_96x_smbus(struct pci_dev *dev) 909 { 910 u8 val = 0; 911 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 912 pci_read_config_byte(dev, 0x77, &val); 913 pci_write_config_byte(dev, 0x77, val & ~0x10); 914 pci_read_config_byte(dev, 0x77, &val); 915 } 916 917 918 #define UHCI_USBLEGSUP 0xc0 /* legacy support */ 919 #define UHCI_USBCMD 0 /* command register */ 920 #define UHCI_USBSTS 2 /* status register */ 921 #define UHCI_USBINTR 4 /* interrupt register */ 922 #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 923 #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 924 #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */ 925 #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */ 926 #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */ 927 928 #define OHCI_CONTROL 0x04 929 #define OHCI_CMDSTATUS 0x08 930 #define OHCI_INTRSTATUS 0x0c 931 #define OHCI_INTRENABLE 0x10 932 #define OHCI_INTRDISABLE 0x14 933 #define OHCI_OCR (1 << 3) /* ownership change request */ 934 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 935 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 936 937 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 938 #define EHCI_USBCMD 0 /* command register */ 939 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 940 #define EHCI_USBSTS 4 /* status register */ 941 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 942 #define EHCI_USBINTR 8 /* interrupt register */ 943 #define EHCI_USBLEGSUP 0 /* legacy support register */ 944 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 945 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 946 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 947 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 948 949 int usb_early_handoff __devinitdata = 0; 950 static int __init usb_handoff_early(char *str) 951 { 952 usb_early_handoff = 1; 953 return 0; 954 } 955 __setup("usb-handoff", usb_handoff_early); 956 957 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev) 958 { 959 unsigned long base = 0; 960 int wait_time, delta; 961 u16 val, sts; 962 int i; 963 964 for (i = 0; i < PCI_ROM_RESOURCE; i++) 965 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 966 base = pci_resource_start(pdev, i); 967 break; 968 } 969 970 if (!base) 971 return; 972 973 /* 974 * stop controller 975 */ 976 sts = inw(base + UHCI_USBSTS); 977 val = inw(base + UHCI_USBCMD); 978 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE); 979 outw(val, base + UHCI_USBCMD); 980 981 /* 982 * wait while it stops if it was running 983 */ 984 if ((sts & UHCI_USBSTS_HALTED) == 0) 985 { 986 wait_time = 1000; 987 delta = 100; 988 989 do { 990 outw(0x1f, base + UHCI_USBSTS); 991 udelay(delta); 992 wait_time -= delta; 993 val = inw(base + UHCI_USBSTS); 994 if (val & UHCI_USBSTS_HALTED) 995 break; 996 } while (wait_time > 0); 997 } 998 999 /* 1000 * disable interrupts & legacy support 1001 */ 1002 outw(0, base + UHCI_USBINTR); 1003 outw(0x1f, base + UHCI_USBSTS); 1004 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val); 1005 if (val & 0xbf) 1006 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT); 1007 1008 } 1009 1010 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) 1011 { 1012 void __iomem *base; 1013 int wait_time; 1014 1015 base = ioremap_nocache(pci_resource_start(pdev, 0), 1016 pci_resource_len(pdev, 0)); 1017 if (base == NULL) return; 1018 1019 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 1020 wait_time = 500; /* 0.5 seconds */ 1021 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 1022 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 1023 while (wait_time > 0 && 1024 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 1025 wait_time -= 10; 1026 msleep(10); 1027 } 1028 } 1029 1030 /* 1031 * disable interrupts 1032 */ 1033 writel(~(u32)0, base + OHCI_INTRDISABLE); 1034 writel(~(u32)0, base + OHCI_INTRSTATUS); 1035 1036 iounmap(base); 1037 } 1038 1039 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) 1040 { 1041 int wait_time, delta; 1042 void __iomem *base, *op_reg_base; 1043 u32 hcc_params, val, temp; 1044 u8 cap_length; 1045 1046 base = ioremap_nocache(pci_resource_start(pdev, 0), 1047 pci_resource_len(pdev, 0)); 1048 if (base == NULL) return; 1049 1050 cap_length = readb(base); 1051 op_reg_base = base + cap_length; 1052 hcc_params = readl(base + EHCI_HCC_PARAMS); 1053 hcc_params = (hcc_params >> 8) & 0xff; 1054 if (hcc_params) { 1055 pci_read_config_dword(pdev, 1056 hcc_params + EHCI_USBLEGSUP, 1057 &val); 1058 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) { 1059 /* 1060 * Ok, BIOS is in smm mode, try to hand off... 1061 */ 1062 pci_read_config_dword(pdev, 1063 hcc_params + EHCI_USBLEGCTLSTS, 1064 &temp); 1065 pci_write_config_dword(pdev, 1066 hcc_params + EHCI_USBLEGCTLSTS, 1067 temp | EHCI_USBLEGCTLSTS_SOOE); 1068 val |= EHCI_USBLEGSUP_OS; 1069 pci_write_config_dword(pdev, 1070 hcc_params + EHCI_USBLEGSUP, 1071 val); 1072 1073 wait_time = 500; 1074 do { 1075 msleep(10); 1076 wait_time -= 10; 1077 pci_read_config_dword(pdev, 1078 hcc_params + EHCI_USBLEGSUP, 1079 &val); 1080 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS)); 1081 if (!wait_time) { 1082 /* 1083 * well, possibly buggy BIOS... 1084 */ 1085 printk(KERN_WARNING "EHCI early BIOS handoff " 1086 "failed (BIOS bug ?)\n"); 1087 pci_write_config_dword(pdev, 1088 hcc_params + EHCI_USBLEGSUP, 1089 EHCI_USBLEGSUP_OS); 1090 pci_write_config_dword(pdev, 1091 hcc_params + EHCI_USBLEGCTLSTS, 1092 0); 1093 } 1094 } 1095 } 1096 1097 /* 1098 * halt EHCI & disable its interrupts in any case 1099 */ 1100 val = readl(op_reg_base + EHCI_USBSTS); 1101 if ((val & EHCI_USBSTS_HALTED) == 0) { 1102 val = readl(op_reg_base + EHCI_USBCMD); 1103 val &= ~EHCI_USBCMD_RUN; 1104 writel(val, op_reg_base + EHCI_USBCMD); 1105 1106 wait_time = 2000; 1107 delta = 100; 1108 do { 1109 writel(0x3f, op_reg_base + EHCI_USBSTS); 1110 udelay(delta); 1111 wait_time -= delta; 1112 val = readl(op_reg_base + EHCI_USBSTS); 1113 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 1114 break; 1115 } 1116 } while (wait_time > 0); 1117 } 1118 writel(0, op_reg_base + EHCI_USBINTR); 1119 writel(0x3f, op_reg_base + EHCI_USBSTS); 1120 1121 iounmap(base); 1122 1123 return; 1124 } 1125 1126 1127 1128 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev) 1129 { 1130 if (!usb_early_handoff) 1131 return; 1132 1133 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */ 1134 quirk_usb_handoff_uhci(pdev); 1135 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */ 1136 quirk_usb_handoff_ohci(pdev); 1137 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */ 1138 quirk_usb_disable_ehci(pdev); 1139 } 1140 1141 return; 1142 } 1143 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff); 1144 1145 /* 1146 * ... This is further complicated by the fact that some SiS96x south 1147 * bridges pretend to be 85C503/5513 instead. In that case see if we 1148 * spotted a compatible north bridge to make sure. 1149 * (pci_find_device doesn't work yet) 1150 * 1151 * We can also enable the sis96x bit in the discovery register.. 1152 */ 1153 static int __devinitdata sis_96x_compatible = 0; 1154 1155 #define SIS_DETECT_REGISTER 0x40 1156 1157 static void __init quirk_sis_503(struct pci_dev *dev) 1158 { 1159 u8 reg; 1160 u16 devid; 1161 1162 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1163 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1164 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1165 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1166 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1167 return; 1168 } 1169 1170 /* Make people aware that we changed the config.. */ 1171 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible); 1172 1173 /* 1174 * Ok, it now shows up as a 96x.. The 96x quirks are after 1175 * the 503 quirk in the quirk table, so they'll automatically 1176 * run and enable things like the SMBus device 1177 */ 1178 dev->device = devid; 1179 } 1180 1181 static void __init quirk_sis_96x_compatible(struct pci_dev *dev) 1182 { 1183 sis_96x_compatible = 1; 1184 } 1185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible ); 1186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible ); 1187 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible ); 1188 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible ); 1189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible ); 1190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible ); 1191 1192 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1193 1194 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1195 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1196 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1198 1199 #ifdef CONFIG_X86_IO_APIC 1200 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1201 { 1202 int i; 1203 1204 if ((pdev->class >> 8) != 0xff00) 1205 return; 1206 1207 /* the first BAR is the location of the IO APIC...we must 1208 * not touch this (and it's already covered by the fixmap), so 1209 * forcibly insert it into the resource tree */ 1210 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1211 insert_resource(&iomem_resource, &pdev->resource[0]); 1212 1213 /* The next five BARs all seem to be rubbish, so just clean 1214 * them out */ 1215 for (i=1; i < 6; i++) { 1216 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1217 } 1218 1219 } 1220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1221 #endif 1222 1223 #ifdef CONFIG_SCSI_SATA 1224 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) 1225 { 1226 u8 prog, comb, tmp; 1227 int ich = 0; 1228 1229 /* 1230 * Narrow down to Intel SATA PCI devices. 1231 */ 1232 switch (pdev->device) { 1233 /* PCI ids taken from drivers/scsi/ata_piix.c */ 1234 case 0x24d1: 1235 case 0x24df: 1236 case 0x25a3: 1237 case 0x25b0: 1238 ich = 5; 1239 break; 1240 case 0x2651: 1241 case 0x2652: 1242 case 0x2653: 1243 case 0x2680: /* ESB2 */ 1244 ich = 6; 1245 break; 1246 case 0x27c0: 1247 case 0x27c4: 1248 ich = 7; 1249 break; 1250 default: 1251 /* we do not handle this PCI device */ 1252 return; 1253 } 1254 1255 /* 1256 * Read combined mode register. 1257 */ 1258 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ 1259 1260 if (ich == 5) { 1261 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ 1262 if (tmp == 0x4) /* bits 10x */ 1263 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1264 else if (tmp == 0x6) /* bits 11x */ 1265 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1266 else 1267 return; /* not in combined mode */ 1268 } else { 1269 WARN_ON((ich != 6) && (ich != 7)); 1270 tmp &= 0x3; /* interesting bits 1:0 */ 1271 if (tmp & (1 << 0)) 1272 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1273 else if (tmp & (1 << 1)) 1274 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1275 else 1276 return; /* not in combined mode */ 1277 } 1278 1279 /* 1280 * Read programming interface register. 1281 * (Tells us if it's legacy or native mode) 1282 */ 1283 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1284 1285 /* if SATA port is in native mode, we're ok. */ 1286 if (prog & comb) 1287 return; 1288 1289 /* SATA port is in legacy mode. Reserve port so that 1290 * IDE driver does not attempt to use it. If request_region 1291 * fails, it will be obvious at boot time, so we don't bother 1292 * checking return values. 1293 */ 1294 if (comb == (1 << 0)) 1295 request_region(0x1f0, 8, "libata"); /* port 0 */ 1296 else 1297 request_region(0x170, 8, "libata"); /* port 1 */ 1298 } 1299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); 1300 #endif /* CONFIG_SCSI_SATA */ 1301 1302 1303 int pcie_mch_quirk; 1304 1305 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1306 { 1307 pcie_mch_quirk = 1; 1308 } 1309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1312 1313 1314 /* 1315 * It's possible for the MSI to get corrupted if shpc and acpi 1316 * are used together on certain PXH-based systems. 1317 */ 1318 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1319 { 1320 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), 1321 PCI_CAP_ID_MSI); 1322 dev->no_msi = 1; 1323 1324 printk(KERN_WARNING "PCI: PXH quirk detected, " 1325 "disabling MSI for SHPC device\n"); 1326 } 1327 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1328 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1329 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1330 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1331 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1332 1333 1334 static void __devinit quirk_netmos(struct pci_dev *dev) 1335 { 1336 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1337 unsigned int num_serial = dev->subsystem_device & 0xf; 1338 1339 /* 1340 * These Netmos parts are multiport serial devices with optional 1341 * parallel ports. Even when parallel ports are present, they 1342 * are identified as class SERIAL, which means the serial driver 1343 * will claim them. To prevent this, mark them as class OTHER. 1344 * These combo devices should be claimed by parport_serial. 1345 * 1346 * The subdevice ID is of the form 0x00PS, where <P> is the number 1347 * of parallel ports and <S> is the number of serial ports. 1348 */ 1349 switch (dev->device) { 1350 case PCI_DEVICE_ID_NETMOS_9735: 1351 case PCI_DEVICE_ID_NETMOS_9745: 1352 case PCI_DEVICE_ID_NETMOS_9835: 1353 case PCI_DEVICE_ID_NETMOS_9845: 1354 case PCI_DEVICE_ID_NETMOS_9855: 1355 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1356 num_parallel) { 1357 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1358 "%u serial); changing class SERIAL to OTHER " 1359 "(use parport_serial)\n", 1360 dev->device, num_parallel, num_serial); 1361 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1362 (dev->class & 0xff); 1363 } 1364 } 1365 } 1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1367 1368 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1369 { 1370 while (f < end) { 1371 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1372 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1373 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1374 f->hook(dev); 1375 } 1376 f++; 1377 } 1378 } 1379 1380 extern struct pci_fixup __start_pci_fixups_early[]; 1381 extern struct pci_fixup __end_pci_fixups_early[]; 1382 extern struct pci_fixup __start_pci_fixups_header[]; 1383 extern struct pci_fixup __end_pci_fixups_header[]; 1384 extern struct pci_fixup __start_pci_fixups_final[]; 1385 extern struct pci_fixup __end_pci_fixups_final[]; 1386 extern struct pci_fixup __start_pci_fixups_enable[]; 1387 extern struct pci_fixup __end_pci_fixups_enable[]; 1388 1389 1390 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 1391 { 1392 struct pci_fixup *start, *end; 1393 1394 switch(pass) { 1395 case pci_fixup_early: 1396 start = __start_pci_fixups_early; 1397 end = __end_pci_fixups_early; 1398 break; 1399 1400 case pci_fixup_header: 1401 start = __start_pci_fixups_header; 1402 end = __end_pci_fixups_header; 1403 break; 1404 1405 case pci_fixup_final: 1406 start = __start_pci_fixups_final; 1407 end = __end_pci_fixups_final; 1408 break; 1409 1410 case pci_fixup_enable: 1411 start = __start_pci_fixups_enable; 1412 end = __end_pci_fixups_enable; 1413 break; 1414 1415 default: 1416 /* stupid compiler warning, you would think with an enum... */ 1417 return; 1418 } 1419 pci_do_fixups(dev, start, end); 1420 } 1421 1422 EXPORT_SYMBOL(pcie_mch_quirk); 1423 #ifdef CONFIG_HOTPLUG 1424 EXPORT_SYMBOL(pci_fixup_device); 1425 #endif 1426