xref: /linux/drivers/pci/proc.c (revision 905e46acd3272d04566fec49afbd7ad9e2ed9ae3)
1 /*
2  *	Procfs interface for the PCI bus.
3  *
4  *	Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
5  */
6 
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/proc_fs.h>
12 #include <linux/seq_file.h>
13 #include <linux/capability.h>
14 #include <linux/uaccess.h>
15 #include <asm/byteorder.h>
16 #include "pci.h"
17 
18 static int proc_initialized;	/* = 0 */
19 
20 static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
21 {
22 	struct pci_dev *dev = PDE_DATA(file_inode(file));
23 	return fixed_size_llseek(file, off, whence, dev->cfg_size);
24 }
25 
26 static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
27 				 size_t nbytes, loff_t *ppos)
28 {
29 	struct pci_dev *dev = PDE_DATA(file_inode(file));
30 	unsigned int pos = *ppos;
31 	unsigned int cnt, size;
32 
33 	/*
34 	 * Normal users can read only the standardized portion of the
35 	 * configuration space as several chips lock up when trying to read
36 	 * undefined locations (think of Intel PIIX4 as a typical example).
37 	 */
38 
39 	if (capable(CAP_SYS_ADMIN))
40 		size = dev->cfg_size;
41 	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
42 		size = 128;
43 	else
44 		size = 64;
45 
46 	if (pos >= size)
47 		return 0;
48 	if (nbytes >= size)
49 		nbytes = size;
50 	if (pos + nbytes > size)
51 		nbytes = size - pos;
52 	cnt = nbytes;
53 
54 	if (!access_ok(VERIFY_WRITE, buf, cnt))
55 		return -EINVAL;
56 
57 	pci_config_pm_runtime_get(dev);
58 
59 	if ((pos & 1) && cnt) {
60 		unsigned char val;
61 		pci_user_read_config_byte(dev, pos, &val);
62 		__put_user(val, buf);
63 		buf++;
64 		pos++;
65 		cnt--;
66 	}
67 
68 	if ((pos & 3) && cnt > 2) {
69 		unsigned short val;
70 		pci_user_read_config_word(dev, pos, &val);
71 		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
72 		buf += 2;
73 		pos += 2;
74 		cnt -= 2;
75 	}
76 
77 	while (cnt >= 4) {
78 		unsigned int val;
79 		pci_user_read_config_dword(dev, pos, &val);
80 		__put_user(cpu_to_le32(val), (__le32 __user *) buf);
81 		buf += 4;
82 		pos += 4;
83 		cnt -= 4;
84 	}
85 
86 	if (cnt >= 2) {
87 		unsigned short val;
88 		pci_user_read_config_word(dev, pos, &val);
89 		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
90 		buf += 2;
91 		pos += 2;
92 		cnt -= 2;
93 	}
94 
95 	if (cnt) {
96 		unsigned char val;
97 		pci_user_read_config_byte(dev, pos, &val);
98 		__put_user(val, buf);
99 		buf++;
100 		pos++;
101 		cnt--;
102 	}
103 
104 	pci_config_pm_runtime_put(dev);
105 
106 	*ppos = pos;
107 	return nbytes;
108 }
109 
110 static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
111 				  size_t nbytes, loff_t *ppos)
112 {
113 	struct inode *ino = file_inode(file);
114 	struct pci_dev *dev = PDE_DATA(ino);
115 	int pos = *ppos;
116 	int size = dev->cfg_size;
117 	int cnt;
118 
119 	if (pos >= size)
120 		return 0;
121 	if (nbytes >= size)
122 		nbytes = size;
123 	if (pos + nbytes > size)
124 		nbytes = size - pos;
125 	cnt = nbytes;
126 
127 	if (!access_ok(VERIFY_READ, buf, cnt))
128 		return -EINVAL;
129 
130 	pci_config_pm_runtime_get(dev);
131 
132 	if ((pos & 1) && cnt) {
133 		unsigned char val;
134 		__get_user(val, buf);
135 		pci_user_write_config_byte(dev, pos, val);
136 		buf++;
137 		pos++;
138 		cnt--;
139 	}
140 
141 	if ((pos & 3) && cnt > 2) {
142 		__le16 val;
143 		__get_user(val, (__le16 __user *) buf);
144 		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
145 		buf += 2;
146 		pos += 2;
147 		cnt -= 2;
148 	}
149 
150 	while (cnt >= 4) {
151 		__le32 val;
152 		__get_user(val, (__le32 __user *) buf);
153 		pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
154 		buf += 4;
155 		pos += 4;
156 		cnt -= 4;
157 	}
158 
159 	if (cnt >= 2) {
160 		__le16 val;
161 		__get_user(val, (__le16 __user *) buf);
162 		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
163 		buf += 2;
164 		pos += 2;
165 		cnt -= 2;
166 	}
167 
168 	if (cnt) {
169 		unsigned char val;
170 		__get_user(val, buf);
171 		pci_user_write_config_byte(dev, pos, val);
172 		buf++;
173 		pos++;
174 		cnt--;
175 	}
176 
177 	pci_config_pm_runtime_put(dev);
178 
179 	*ppos = pos;
180 	i_size_write(ino, dev->cfg_size);
181 	return nbytes;
182 }
183 
184 struct pci_filp_private {
185 	enum pci_mmap_state mmap_state;
186 	int write_combine;
187 };
188 
189 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
190 			       unsigned long arg)
191 {
192 	struct pci_dev *dev = PDE_DATA(file_inode(file));
193 #ifdef HAVE_PCI_MMAP
194 	struct pci_filp_private *fpriv = file->private_data;
195 #endif /* HAVE_PCI_MMAP */
196 	int ret = 0;
197 
198 	switch (cmd) {
199 	case PCIIOC_CONTROLLER:
200 		ret = pci_domain_nr(dev->bus);
201 		break;
202 
203 #ifdef HAVE_PCI_MMAP
204 	case PCIIOC_MMAP_IS_IO:
205 		if (!arch_can_pci_mmap_io())
206 			return -EINVAL;
207 		fpriv->mmap_state = pci_mmap_io;
208 		break;
209 
210 	case PCIIOC_MMAP_IS_MEM:
211 		fpriv->mmap_state = pci_mmap_mem;
212 		break;
213 
214 	case PCIIOC_WRITE_COMBINE:
215 		if (arch_can_pci_mmap_wc()) {
216 			if (arg)
217 				fpriv->write_combine = 1;
218 			else
219 				fpriv->write_combine = 0;
220 			break;
221 		}
222 		/* If arch decided it can't, fall through... */
223 #endif /* HAVE_PCI_MMAP */
224 	default:
225 		ret = -EINVAL;
226 		break;
227 	}
228 
229 	return ret;
230 }
231 
232 #ifdef HAVE_PCI_MMAP
233 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
234 {
235 	struct pci_dev *dev = PDE_DATA(file_inode(file));
236 	struct pci_filp_private *fpriv = file->private_data;
237 	int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;
238 
239 	if (!capable(CAP_SYS_RAWIO))
240 		return -EPERM;
241 
242 	if (fpriv->mmap_state == pci_mmap_io) {
243 		if (!arch_can_pci_mmap_io())
244 			return -EINVAL;
245 		res_bit = IORESOURCE_IO;
246 	}
247 
248 	/* Make sure the caller is mapping a real resource for this device */
249 	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
250 		if (dev->resource[i].flags & res_bit &&
251 		    pci_mmap_fits(dev, i, vma,  PCI_MMAP_PROCFS))
252 			break;
253 	}
254 
255 	if (i >= PCI_ROM_RESOURCE)
256 		return -ENODEV;
257 
258 	if (fpriv->mmap_state == pci_mmap_mem &&
259 	    fpriv->write_combine) {
260 		if (dev->resource[i].flags & IORESOURCE_PREFETCH)
261 			write_combine = 1;
262 		else
263 			return -EINVAL;
264 	}
265 	ret = pci_mmap_page_range(dev, i, vma,
266 				  fpriv->mmap_state, write_combine);
267 	if (ret < 0)
268 		return ret;
269 
270 	return 0;
271 }
272 
273 static int proc_bus_pci_open(struct inode *inode, struct file *file)
274 {
275 	struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
276 
277 	if (!fpriv)
278 		return -ENOMEM;
279 
280 	fpriv->mmap_state = pci_mmap_io;
281 	fpriv->write_combine = 0;
282 
283 	file->private_data = fpriv;
284 
285 	return 0;
286 }
287 
288 static int proc_bus_pci_release(struct inode *inode, struct file *file)
289 {
290 	kfree(file->private_data);
291 	file->private_data = NULL;
292 
293 	return 0;
294 }
295 #endif /* HAVE_PCI_MMAP */
296 
297 static const struct file_operations proc_bus_pci_operations = {
298 	.owner		= THIS_MODULE,
299 	.llseek		= proc_bus_pci_lseek,
300 	.read		= proc_bus_pci_read,
301 	.write		= proc_bus_pci_write,
302 	.unlocked_ioctl	= proc_bus_pci_ioctl,
303 	.compat_ioctl	= proc_bus_pci_ioctl,
304 #ifdef HAVE_PCI_MMAP
305 	.open		= proc_bus_pci_open,
306 	.release	= proc_bus_pci_release,
307 	.mmap		= proc_bus_pci_mmap,
308 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
309 	.get_unmapped_area = get_pci_unmapped_area,
310 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
311 #endif /* HAVE_PCI_MMAP */
312 };
313 
314 /* iterator */
315 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
316 {
317 	struct pci_dev *dev = NULL;
318 	loff_t n = *pos;
319 
320 	for_each_pci_dev(dev) {
321 		if (!n--)
322 			break;
323 	}
324 	return dev;
325 }
326 
327 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
328 {
329 	struct pci_dev *dev = v;
330 
331 	(*pos)++;
332 	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
333 	return dev;
334 }
335 
336 static void pci_seq_stop(struct seq_file *m, void *v)
337 {
338 	if (v) {
339 		struct pci_dev *dev = v;
340 		pci_dev_put(dev);
341 	}
342 }
343 
344 static int show_device(struct seq_file *m, void *v)
345 {
346 	const struct pci_dev *dev = v;
347 	const struct pci_driver *drv;
348 	int i;
349 
350 	if (dev == NULL)
351 		return 0;
352 
353 	drv = pci_dev_driver(dev);
354 	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
355 			dev->bus->number,
356 			dev->devfn,
357 			dev->vendor,
358 			dev->device,
359 			dev->irq);
360 
361 	/* only print standard and ROM resources to preserve compatibility */
362 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
363 		resource_size_t start, end;
364 		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
365 		seq_printf(m, "\t%16llx",
366 			(unsigned long long)(start |
367 			(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
368 	}
369 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
370 		resource_size_t start, end;
371 		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
372 		seq_printf(m, "\t%16llx",
373 			dev->resource[i].start < dev->resource[i].end ?
374 			(unsigned long long)(end - start) + 1 : 0);
375 	}
376 	seq_putc(m, '\t');
377 	if (drv)
378 		seq_printf(m, "%s", drv->name);
379 	seq_putc(m, '\n');
380 	return 0;
381 }
382 
383 static const struct seq_operations proc_bus_pci_devices_op = {
384 	.start	= pci_seq_start,
385 	.next	= pci_seq_next,
386 	.stop	= pci_seq_stop,
387 	.show	= show_device
388 };
389 
390 static struct proc_dir_entry *proc_bus_pci_dir;
391 
392 int pci_proc_attach_device(struct pci_dev *dev)
393 {
394 	struct pci_bus *bus = dev->bus;
395 	struct proc_dir_entry *e;
396 	char name[16];
397 
398 	if (!proc_initialized)
399 		return -EACCES;
400 
401 	if (!bus->procdir) {
402 		if (pci_proc_domain(bus)) {
403 			sprintf(name, "%04x:%02x", pci_domain_nr(bus),
404 					bus->number);
405 		} else {
406 			sprintf(name, "%02x", bus->number);
407 		}
408 		bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
409 		if (!bus->procdir)
410 			return -ENOMEM;
411 	}
412 
413 	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
414 	e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
415 			     &proc_bus_pci_operations, dev);
416 	if (!e)
417 		return -ENOMEM;
418 	proc_set_size(e, dev->cfg_size);
419 	dev->procent = e;
420 
421 	return 0;
422 }
423 
424 int pci_proc_detach_device(struct pci_dev *dev)
425 {
426 	proc_remove(dev->procent);
427 	dev->procent = NULL;
428 	return 0;
429 }
430 
431 int pci_proc_detach_bus(struct pci_bus *bus)
432 {
433 	proc_remove(bus->procdir);
434 	return 0;
435 }
436 
437 static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
438 {
439 	return seq_open(file, &proc_bus_pci_devices_op);
440 }
441 
442 static const struct file_operations proc_bus_pci_dev_operations = {
443 	.owner		= THIS_MODULE,
444 	.open		= proc_bus_pci_dev_open,
445 	.read		= seq_read,
446 	.llseek		= seq_lseek,
447 	.release	= seq_release,
448 };
449 
450 static int __init pci_proc_init(void)
451 {
452 	struct pci_dev *dev = NULL;
453 	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
454 	proc_create("devices", 0, proc_bus_pci_dir,
455 		    &proc_bus_pci_dev_operations);
456 	proc_initialized = 1;
457 	for_each_pci_dev(dev)
458 		pci_proc_attach_device(dev);
459 
460 	return 0;
461 }
462 device_initcall(pci_proc_init);
463