1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_device.h> 12 #include <linux/of_pci.h> 13 #include <linux/pci_hotplug.h> 14 #include <linux/slab.h> 15 #include <linux/module.h> 16 #include <linux/cpumask.h> 17 #include <linux/aer.h> 18 #include <linux/acpi.h> 19 #include <linux/hypervisor.h> 20 #include <linux/irqdomain.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/bitfield.h> 23 #include "pci.h" 24 25 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 26 #define CARDBUS_RESERVE_BUSNR 3 27 28 static struct resource busn_resource = { 29 .name = "PCI busn", 30 .start = 0, 31 .end = 255, 32 .flags = IORESOURCE_BUS, 33 }; 34 35 /* Ugh. Need to stop exporting this to modules. */ 36 LIST_HEAD(pci_root_buses); 37 EXPORT_SYMBOL(pci_root_buses); 38 39 static LIST_HEAD(pci_domain_busn_res_list); 40 41 struct pci_domain_busn_res { 42 struct list_head list; 43 struct resource res; 44 int domain_nr; 45 }; 46 47 static struct resource *get_pci_domain_busn_res(int domain_nr) 48 { 49 struct pci_domain_busn_res *r; 50 51 list_for_each_entry(r, &pci_domain_busn_res_list, list) 52 if (r->domain_nr == domain_nr) 53 return &r->res; 54 55 r = kzalloc(sizeof(*r), GFP_KERNEL); 56 if (!r) 57 return NULL; 58 59 r->domain_nr = domain_nr; 60 r->res.start = 0; 61 r->res.end = 0xff; 62 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 63 64 list_add_tail(&r->list, &pci_domain_busn_res_list); 65 66 return &r->res; 67 } 68 69 /* 70 * Some device drivers need know if PCI is initiated. 71 * Basically, we think PCI is not initiated when there 72 * is no device to be found on the pci_bus_type. 73 */ 74 int no_pci_devices(void) 75 { 76 struct device *dev; 77 int no_devices; 78 79 dev = bus_find_next_device(&pci_bus_type, NULL); 80 no_devices = (dev == NULL); 81 put_device(dev); 82 return no_devices; 83 } 84 EXPORT_SYMBOL(no_pci_devices); 85 86 /* 87 * PCI Bus Class 88 */ 89 static void release_pcibus_dev(struct device *dev) 90 { 91 struct pci_bus *pci_bus = to_pci_bus(dev); 92 93 put_device(pci_bus->bridge); 94 pci_bus_remove_resources(pci_bus); 95 pci_release_bus_of_node(pci_bus); 96 kfree(pci_bus); 97 } 98 99 static struct class pcibus_class = { 100 .name = "pci_bus", 101 .dev_release = &release_pcibus_dev, 102 .dev_groups = pcibus_groups, 103 }; 104 105 static int __init pcibus_class_init(void) 106 { 107 return class_register(&pcibus_class); 108 } 109 postcore_initcall(pcibus_class_init); 110 111 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 112 { 113 u64 size = mask & maxbase; /* Find the significant bits */ 114 if (!size) 115 return 0; 116 117 /* 118 * Get the lowest of them to find the decode size, and from that 119 * the extent. 120 */ 121 size = size & ~(size-1); 122 123 /* 124 * base == maxbase can be valid only if the BAR has already been 125 * programmed with all 1s. 126 */ 127 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 128 return 0; 129 130 return size; 131 } 132 133 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 134 { 135 u32 mem_type; 136 unsigned long flags; 137 138 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 139 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 140 flags |= IORESOURCE_IO; 141 return flags; 142 } 143 144 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 145 flags |= IORESOURCE_MEM; 146 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 147 flags |= IORESOURCE_PREFETCH; 148 149 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 150 switch (mem_type) { 151 case PCI_BASE_ADDRESS_MEM_TYPE_32: 152 break; 153 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 154 /* 1M mem BAR treated as 32-bit BAR */ 155 break; 156 case PCI_BASE_ADDRESS_MEM_TYPE_64: 157 flags |= IORESOURCE_MEM_64; 158 break; 159 default: 160 /* mem unknown type treated as 32-bit BAR */ 161 break; 162 } 163 return flags; 164 } 165 166 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 167 168 /** 169 * __pci_read_base - Read a PCI BAR 170 * @dev: the PCI device 171 * @type: type of the BAR 172 * @res: resource buffer to be filled in 173 * @pos: BAR position in the config space 174 * 175 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 176 */ 177 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 178 struct resource *res, unsigned int pos) 179 { 180 u32 l = 0, sz = 0, mask; 181 u64 l64, sz64, mask64; 182 u16 orig_cmd; 183 struct pci_bus_region region, inverted_region; 184 185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 186 187 /* No printks while decoding is disabled! */ 188 if (!dev->mmio_always_on) { 189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 191 pci_write_config_word(dev, PCI_COMMAND, 192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 193 } 194 } 195 196 res->name = pci_name(dev); 197 198 pci_read_config_dword(dev, pos, &l); 199 pci_write_config_dword(dev, pos, l | mask); 200 pci_read_config_dword(dev, pos, &sz); 201 pci_write_config_dword(dev, pos, l); 202 203 /* 204 * All bits set in sz means the device isn't working properly. 205 * If the BAR isn't implemented, all bits must be 0. If it's a 206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 207 * 1 must be clear. 208 */ 209 if (PCI_POSSIBLE_ERROR(sz)) 210 sz = 0; 211 212 /* 213 * I don't know how l can have all bits set. Copied from old code. 214 * Maybe it fixes a bug on some ancient platform. 215 */ 216 if (PCI_POSSIBLE_ERROR(l)) 217 l = 0; 218 219 if (type == pci_bar_unknown) { 220 res->flags = decode_bar(dev, l); 221 res->flags |= IORESOURCE_SIZEALIGN; 222 if (res->flags & IORESOURCE_IO) { 223 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 226 } else { 227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 230 } 231 } else { 232 if (l & PCI_ROM_ADDRESS_ENABLE) 233 res->flags |= IORESOURCE_ROM_ENABLE; 234 l64 = l & PCI_ROM_ADDRESS_MASK; 235 sz64 = sz & PCI_ROM_ADDRESS_MASK; 236 mask64 = PCI_ROM_ADDRESS_MASK; 237 } 238 239 if (res->flags & IORESOURCE_MEM_64) { 240 pci_read_config_dword(dev, pos + 4, &l); 241 pci_write_config_dword(dev, pos + 4, ~0); 242 pci_read_config_dword(dev, pos + 4, &sz); 243 pci_write_config_dword(dev, pos + 4, l); 244 245 l64 |= ((u64)l << 32); 246 sz64 |= ((u64)sz << 32); 247 mask64 |= ((u64)~0 << 32); 248 } 249 250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 252 253 if (!sz64) 254 goto fail; 255 256 sz64 = pci_size(l64, sz64, mask64); 257 if (!sz64) { 258 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", 259 pos); 260 goto fail; 261 } 262 263 if (res->flags & IORESOURCE_MEM_64) { 264 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 265 && sz64 > 0x100000000ULL) { 266 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 267 res->start = 0; 268 res->end = 0; 269 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", 270 pos, (unsigned long long)sz64); 271 goto out; 272 } 273 274 if ((sizeof(pci_bus_addr_t) < 8) && l) { 275 /* Above 32-bit boundary; try to reallocate */ 276 res->flags |= IORESOURCE_UNSET; 277 res->start = 0; 278 res->end = sz64 - 1; 279 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", 280 pos, (unsigned long long)l64); 281 goto out; 282 } 283 } 284 285 region.start = l64; 286 region.end = l64 + sz64 - 1; 287 288 pcibios_bus_to_resource(dev->bus, res, ®ion); 289 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 290 291 /* 292 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 293 * the corresponding resource address (the physical address used by 294 * the CPU. Converting that resource address back to a bus address 295 * should yield the original BAR value: 296 * 297 * resource_to_bus(bus_to_resource(A)) == A 298 * 299 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 300 * be claimed by the device. 301 */ 302 if (inverted_region.start != region.start) { 303 res->flags |= IORESOURCE_UNSET; 304 res->start = 0; 305 res->end = region.end - region.start; 306 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", 307 pos, (unsigned long long)region.start); 308 } 309 310 goto out; 311 312 313 fail: 314 res->flags = 0; 315 out: 316 if (res->flags) 317 pci_info(dev, "reg 0x%x: %pR\n", pos, res); 318 319 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 320 } 321 322 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 323 { 324 unsigned int pos, reg; 325 326 if (dev->non_compliant_bars) 327 return; 328 329 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 330 if (dev->is_virtfn) 331 return; 332 333 for (pos = 0; pos < howmany; pos++) { 334 struct resource *res = &dev->resource[pos]; 335 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 336 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 337 } 338 339 if (rom) { 340 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 341 dev->rom_base_reg = rom; 342 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 343 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 344 __pci_read_base(dev, pci_bar_mem32, res, rom); 345 } 346 } 347 348 static void pci_read_bridge_windows(struct pci_dev *bridge) 349 { 350 u16 io; 351 u32 pmem, tmp; 352 353 pci_read_config_word(bridge, PCI_IO_BASE, &io); 354 if (!io) { 355 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 356 pci_read_config_word(bridge, PCI_IO_BASE, &io); 357 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 358 } 359 if (io) 360 bridge->io_window = 1; 361 362 /* 363 * DECchip 21050 pass 2 errata: the bridge may miss an address 364 * disconnect boundary by one PCI data phase. Workaround: do not 365 * use prefetching on this device. 366 */ 367 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 368 return; 369 370 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 371 if (!pmem) { 372 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 373 0xffe0fff0); 374 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 375 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 376 } 377 if (!pmem) 378 return; 379 380 bridge->pref_window = 1; 381 382 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 383 384 /* 385 * Bridge claims to have a 64-bit prefetchable memory 386 * window; verify that the upper bits are actually 387 * writable. 388 */ 389 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 390 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 391 0xffffffff); 392 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 393 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 394 if (tmp) 395 bridge->pref_64_window = 1; 396 } 397 } 398 399 static void pci_read_bridge_io(struct pci_bus *child) 400 { 401 struct pci_dev *dev = child->self; 402 u8 io_base_lo, io_limit_lo; 403 unsigned long io_mask, io_granularity, base, limit; 404 struct pci_bus_region region; 405 struct resource *res; 406 407 io_mask = PCI_IO_RANGE_MASK; 408 io_granularity = 0x1000; 409 if (dev->io_window_1k) { 410 /* Support 1K I/O space granularity */ 411 io_mask = PCI_IO_1K_RANGE_MASK; 412 io_granularity = 0x400; 413 } 414 415 res = child->resource[0]; 416 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 417 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 418 base = (io_base_lo & io_mask) << 8; 419 limit = (io_limit_lo & io_mask) << 8; 420 421 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 422 u16 io_base_hi, io_limit_hi; 423 424 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 425 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 426 base |= ((unsigned long) io_base_hi << 16); 427 limit |= ((unsigned long) io_limit_hi << 16); 428 } 429 430 if (base <= limit) { 431 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 432 region.start = base; 433 region.end = limit + io_granularity - 1; 434 pcibios_bus_to_resource(dev->bus, res, ®ion); 435 pci_info(dev, " bridge window %pR\n", res); 436 } 437 } 438 439 static void pci_read_bridge_mmio(struct pci_bus *child) 440 { 441 struct pci_dev *dev = child->self; 442 u16 mem_base_lo, mem_limit_lo; 443 unsigned long base, limit; 444 struct pci_bus_region region; 445 struct resource *res; 446 447 res = child->resource[1]; 448 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 449 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 450 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 451 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 452 if (base <= limit) { 453 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 454 region.start = base; 455 region.end = limit + 0xfffff; 456 pcibios_bus_to_resource(dev->bus, res, ®ion); 457 pci_info(dev, " bridge window %pR\n", res); 458 } 459 } 460 461 static void pci_read_bridge_mmio_pref(struct pci_bus *child) 462 { 463 struct pci_dev *dev = child->self; 464 u16 mem_base_lo, mem_limit_lo; 465 u64 base64, limit64; 466 pci_bus_addr_t base, limit; 467 struct pci_bus_region region; 468 struct resource *res; 469 470 res = child->resource[2]; 471 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 472 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 473 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 474 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 475 476 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 477 u32 mem_base_hi, mem_limit_hi; 478 479 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 480 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 481 482 /* 483 * Some bridges set the base > limit by default, and some 484 * (broken) BIOSes do not initialize them. If we find 485 * this, just assume they are not being used. 486 */ 487 if (mem_base_hi <= mem_limit_hi) { 488 base64 |= (u64) mem_base_hi << 32; 489 limit64 |= (u64) mem_limit_hi << 32; 490 } 491 } 492 493 base = (pci_bus_addr_t) base64; 494 limit = (pci_bus_addr_t) limit64; 495 496 if (base != base64) { 497 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 498 (unsigned long long) base64); 499 return; 500 } 501 502 if (base <= limit) { 503 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 504 IORESOURCE_MEM | IORESOURCE_PREFETCH; 505 if (res->flags & PCI_PREF_RANGE_TYPE_64) 506 res->flags |= IORESOURCE_MEM_64; 507 region.start = base; 508 region.end = limit + 0xfffff; 509 pcibios_bus_to_resource(dev->bus, res, ®ion); 510 pci_info(dev, " bridge window %pR\n", res); 511 } 512 } 513 514 void pci_read_bridge_bases(struct pci_bus *child) 515 { 516 struct pci_dev *dev = child->self; 517 struct resource *res; 518 int i; 519 520 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 521 return; 522 523 pci_info(dev, "PCI bridge to %pR%s\n", 524 &child->busn_res, 525 dev->transparent ? " (subtractive decode)" : ""); 526 527 pci_bus_remove_resources(child); 528 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 529 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 530 531 pci_read_bridge_io(child); 532 pci_read_bridge_mmio(child); 533 pci_read_bridge_mmio_pref(child); 534 535 if (dev->transparent) { 536 pci_bus_for_each_resource(child->parent, res, i) { 537 if (res && res->flags) { 538 pci_bus_add_resource(child, res, 539 PCI_SUBTRACTIVE_DECODE); 540 pci_info(dev, " bridge window %pR (subtractive decode)\n", 541 res); 542 } 543 } 544 } 545 } 546 547 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 548 { 549 struct pci_bus *b; 550 551 b = kzalloc(sizeof(*b), GFP_KERNEL); 552 if (!b) 553 return NULL; 554 555 INIT_LIST_HEAD(&b->node); 556 INIT_LIST_HEAD(&b->children); 557 INIT_LIST_HEAD(&b->devices); 558 INIT_LIST_HEAD(&b->slots); 559 INIT_LIST_HEAD(&b->resources); 560 b->max_bus_speed = PCI_SPEED_UNKNOWN; 561 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 562 #ifdef CONFIG_PCI_DOMAINS_GENERIC 563 if (parent) 564 b->domain_nr = parent->domain_nr; 565 #endif 566 return b; 567 } 568 569 static void pci_release_host_bridge_dev(struct device *dev) 570 { 571 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 572 573 if (bridge->release_fn) 574 bridge->release_fn(bridge); 575 576 pci_free_resource_list(&bridge->windows); 577 pci_free_resource_list(&bridge->dma_ranges); 578 kfree(bridge); 579 } 580 581 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 582 { 583 INIT_LIST_HEAD(&bridge->windows); 584 INIT_LIST_HEAD(&bridge->dma_ranges); 585 586 /* 587 * We assume we can manage these PCIe features. Some systems may 588 * reserve these for use by the platform itself, e.g., an ACPI BIOS 589 * may implement its own AER handling and use _OSC to prevent the 590 * OS from interfering. 591 */ 592 bridge->native_aer = 1; 593 bridge->native_pcie_hotplug = 1; 594 bridge->native_shpc_hotplug = 1; 595 bridge->native_pme = 1; 596 bridge->native_ltr = 1; 597 bridge->native_dpc = 1; 598 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 599 600 device_initialize(&bridge->dev); 601 } 602 603 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 604 { 605 struct pci_host_bridge *bridge; 606 607 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 608 if (!bridge) 609 return NULL; 610 611 pci_init_host_bridge(bridge); 612 bridge->dev.release = pci_release_host_bridge_dev; 613 614 return bridge; 615 } 616 EXPORT_SYMBOL(pci_alloc_host_bridge); 617 618 static void devm_pci_alloc_host_bridge_release(void *data) 619 { 620 pci_free_host_bridge(data); 621 } 622 623 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 624 size_t priv) 625 { 626 int ret; 627 struct pci_host_bridge *bridge; 628 629 bridge = pci_alloc_host_bridge(priv); 630 if (!bridge) 631 return NULL; 632 633 bridge->dev.parent = dev; 634 635 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 636 bridge); 637 if (ret) 638 return NULL; 639 640 ret = devm_of_pci_bridge_init(dev, bridge); 641 if (ret) 642 return NULL; 643 644 return bridge; 645 } 646 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 647 648 void pci_free_host_bridge(struct pci_host_bridge *bridge) 649 { 650 put_device(&bridge->dev); 651 } 652 EXPORT_SYMBOL(pci_free_host_bridge); 653 654 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 655 static const unsigned char pcix_bus_speed[] = { 656 PCI_SPEED_UNKNOWN, /* 0 */ 657 PCI_SPEED_66MHz_PCIX, /* 1 */ 658 PCI_SPEED_100MHz_PCIX, /* 2 */ 659 PCI_SPEED_133MHz_PCIX, /* 3 */ 660 PCI_SPEED_UNKNOWN, /* 4 */ 661 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 662 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 663 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 664 PCI_SPEED_UNKNOWN, /* 8 */ 665 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 666 PCI_SPEED_100MHz_PCIX_266, /* A */ 667 PCI_SPEED_133MHz_PCIX_266, /* B */ 668 PCI_SPEED_UNKNOWN, /* C */ 669 PCI_SPEED_66MHz_PCIX_533, /* D */ 670 PCI_SPEED_100MHz_PCIX_533, /* E */ 671 PCI_SPEED_133MHz_PCIX_533 /* F */ 672 }; 673 674 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 675 const unsigned char pcie_link_speed[] = { 676 PCI_SPEED_UNKNOWN, /* 0 */ 677 PCIE_SPEED_2_5GT, /* 1 */ 678 PCIE_SPEED_5_0GT, /* 2 */ 679 PCIE_SPEED_8_0GT, /* 3 */ 680 PCIE_SPEED_16_0GT, /* 4 */ 681 PCIE_SPEED_32_0GT, /* 5 */ 682 PCIE_SPEED_64_0GT, /* 6 */ 683 PCI_SPEED_UNKNOWN, /* 7 */ 684 PCI_SPEED_UNKNOWN, /* 8 */ 685 PCI_SPEED_UNKNOWN, /* 9 */ 686 PCI_SPEED_UNKNOWN, /* A */ 687 PCI_SPEED_UNKNOWN, /* B */ 688 PCI_SPEED_UNKNOWN, /* C */ 689 PCI_SPEED_UNKNOWN, /* D */ 690 PCI_SPEED_UNKNOWN, /* E */ 691 PCI_SPEED_UNKNOWN /* F */ 692 }; 693 EXPORT_SYMBOL_GPL(pcie_link_speed); 694 695 const char *pci_speed_string(enum pci_bus_speed speed) 696 { 697 /* Indexed by the pci_bus_speed enum */ 698 static const char *speed_strings[] = { 699 "33 MHz PCI", /* 0x00 */ 700 "66 MHz PCI", /* 0x01 */ 701 "66 MHz PCI-X", /* 0x02 */ 702 "100 MHz PCI-X", /* 0x03 */ 703 "133 MHz PCI-X", /* 0x04 */ 704 NULL, /* 0x05 */ 705 NULL, /* 0x06 */ 706 NULL, /* 0x07 */ 707 NULL, /* 0x08 */ 708 "66 MHz PCI-X 266", /* 0x09 */ 709 "100 MHz PCI-X 266", /* 0x0a */ 710 "133 MHz PCI-X 266", /* 0x0b */ 711 "Unknown AGP", /* 0x0c */ 712 "1x AGP", /* 0x0d */ 713 "2x AGP", /* 0x0e */ 714 "4x AGP", /* 0x0f */ 715 "8x AGP", /* 0x10 */ 716 "66 MHz PCI-X 533", /* 0x11 */ 717 "100 MHz PCI-X 533", /* 0x12 */ 718 "133 MHz PCI-X 533", /* 0x13 */ 719 "2.5 GT/s PCIe", /* 0x14 */ 720 "5.0 GT/s PCIe", /* 0x15 */ 721 "8.0 GT/s PCIe", /* 0x16 */ 722 "16.0 GT/s PCIe", /* 0x17 */ 723 "32.0 GT/s PCIe", /* 0x18 */ 724 "64.0 GT/s PCIe", /* 0x19 */ 725 }; 726 727 if (speed < ARRAY_SIZE(speed_strings)) 728 return speed_strings[speed]; 729 return "Unknown"; 730 } 731 EXPORT_SYMBOL_GPL(pci_speed_string); 732 733 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 734 { 735 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 736 } 737 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 738 739 static unsigned char agp_speeds[] = { 740 AGP_UNKNOWN, 741 AGP_1X, 742 AGP_2X, 743 AGP_4X, 744 AGP_8X 745 }; 746 747 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 748 { 749 int index = 0; 750 751 if (agpstat & 4) 752 index = 3; 753 else if (agpstat & 2) 754 index = 2; 755 else if (agpstat & 1) 756 index = 1; 757 else 758 goto out; 759 760 if (agp3) { 761 index += 2; 762 if (index == 5) 763 index = 0; 764 } 765 766 out: 767 return agp_speeds[index]; 768 } 769 770 static void pci_set_bus_speed(struct pci_bus *bus) 771 { 772 struct pci_dev *bridge = bus->self; 773 int pos; 774 775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 776 if (!pos) 777 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 778 if (pos) { 779 u32 agpstat, agpcmd; 780 781 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 782 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 783 784 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 785 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 786 } 787 788 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 789 if (pos) { 790 u16 status; 791 enum pci_bus_speed max; 792 793 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 794 &status); 795 796 if (status & PCI_X_SSTATUS_533MHZ) { 797 max = PCI_SPEED_133MHz_PCIX_533; 798 } else if (status & PCI_X_SSTATUS_266MHZ) { 799 max = PCI_SPEED_133MHz_PCIX_266; 800 } else if (status & PCI_X_SSTATUS_133MHZ) { 801 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 802 max = PCI_SPEED_133MHz_PCIX_ECC; 803 else 804 max = PCI_SPEED_133MHz_PCIX; 805 } else { 806 max = PCI_SPEED_66MHz_PCIX; 807 } 808 809 bus->max_bus_speed = max; 810 bus->cur_bus_speed = pcix_bus_speed[ 811 (status & PCI_X_SSTATUS_FREQ) >> 6]; 812 813 return; 814 } 815 816 if (pci_is_pcie(bridge)) { 817 u32 linkcap; 818 u16 linksta; 819 820 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 821 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 822 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); 823 824 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 825 pcie_update_link_speed(bus, linksta); 826 } 827 } 828 829 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 830 { 831 struct irq_domain *d; 832 833 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 834 d = dev_get_msi_domain(bus->bridge); 835 836 /* 837 * Any firmware interface that can resolve the msi_domain 838 * should be called from here. 839 */ 840 if (!d) 841 d = pci_host_bridge_of_msi_domain(bus); 842 if (!d) 843 d = pci_host_bridge_acpi_msi_domain(bus); 844 845 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN 846 /* 847 * If no IRQ domain was found via the OF tree, try looking it up 848 * directly through the fwnode_handle. 849 */ 850 if (!d) { 851 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 852 853 if (fwnode) 854 d = irq_find_matching_fwnode(fwnode, 855 DOMAIN_BUS_PCI_MSI); 856 } 857 #endif 858 859 return d; 860 } 861 862 static void pci_set_bus_msi_domain(struct pci_bus *bus) 863 { 864 struct irq_domain *d; 865 struct pci_bus *b; 866 867 /* 868 * The bus can be a root bus, a subordinate bus, or a virtual bus 869 * created by an SR-IOV device. Walk up to the first bridge device 870 * found or derive the domain from the host bridge. 871 */ 872 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 873 if (b->self) 874 d = dev_get_msi_domain(&b->self->dev); 875 } 876 877 if (!d) 878 d = pci_host_bridge_msi_domain(b); 879 880 dev_set_msi_domain(&bus->dev, d); 881 } 882 883 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 884 { 885 struct device *parent = bridge->dev.parent; 886 struct resource_entry *window, *next, *n; 887 struct pci_bus *bus, *b; 888 resource_size_t offset, next_offset; 889 LIST_HEAD(resources); 890 struct resource *res, *next_res; 891 char addr[64], *fmt; 892 const char *name; 893 int err; 894 895 bus = pci_alloc_bus(NULL); 896 if (!bus) 897 return -ENOMEM; 898 899 bridge->bus = bus; 900 901 bus->sysdata = bridge->sysdata; 902 bus->ops = bridge->ops; 903 bus->number = bus->busn_res.start = bridge->busnr; 904 #ifdef CONFIG_PCI_DOMAINS_GENERIC 905 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 906 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 907 else 908 bus->domain_nr = bridge->domain_nr; 909 #endif 910 911 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 912 if (b) { 913 /* Ignore it if we already got here via a different bridge */ 914 dev_dbg(&b->dev, "bus already known\n"); 915 err = -EEXIST; 916 goto free; 917 } 918 919 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 920 bridge->busnr); 921 922 err = pcibios_root_bridge_prepare(bridge); 923 if (err) 924 goto free; 925 926 /* Temporarily move resources off the list */ 927 list_splice_init(&bridge->windows, &resources); 928 err = device_add(&bridge->dev); 929 if (err) { 930 put_device(&bridge->dev); 931 goto free; 932 } 933 bus->bridge = get_device(&bridge->dev); 934 device_enable_async_suspend(bus->bridge); 935 pci_set_bus_of_node(bus); 936 pci_set_bus_msi_domain(bus); 937 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 938 !pci_host_of_has_msi_map(parent)) 939 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 940 941 if (!parent) 942 set_dev_node(bus->bridge, pcibus_to_node(bus)); 943 944 bus->dev.class = &pcibus_class; 945 bus->dev.parent = bus->bridge; 946 947 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 948 name = dev_name(&bus->dev); 949 950 err = device_register(&bus->dev); 951 if (err) 952 goto unregister; 953 954 pcibios_add_bus(bus); 955 956 if (bus->ops->add_bus) { 957 err = bus->ops->add_bus(bus); 958 if (WARN_ON(err < 0)) 959 dev_err(&bus->dev, "failed to add bus: %d\n", err); 960 } 961 962 /* Create legacy_io and legacy_mem files for this bus */ 963 pci_create_legacy_files(bus); 964 965 if (parent) 966 dev_info(parent, "PCI host bridge to bus %s\n", name); 967 else 968 pr_info("PCI host bridge to bus %s\n", name); 969 970 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 971 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 972 973 /* Coalesce contiguous windows */ 974 resource_list_for_each_entry_safe(window, n, &resources) { 975 if (list_is_last(&window->node, &resources)) 976 break; 977 978 next = list_next_entry(window, node); 979 offset = window->offset; 980 res = window->res; 981 next_offset = next->offset; 982 next_res = next->res; 983 984 if (res->flags != next_res->flags || offset != next_offset) 985 continue; 986 987 if (res->end + 1 == next_res->start) { 988 next_res->start = res->start; 989 res->flags = res->start = res->end = 0; 990 } 991 } 992 993 /* Add initial resources to the bus */ 994 resource_list_for_each_entry_safe(window, n, &resources) { 995 offset = window->offset; 996 res = window->res; 997 if (!res->end) 998 continue; 999 1000 list_move_tail(&window->node, &bridge->windows); 1001 1002 if (res->flags & IORESOURCE_BUS) 1003 pci_bus_insert_busn_res(bus, bus->number, res->end); 1004 else 1005 pci_bus_add_resource(bus, res, 0); 1006 1007 if (offset) { 1008 if (resource_type(res) == IORESOURCE_IO) 1009 fmt = " (bus address [%#06llx-%#06llx])"; 1010 else 1011 fmt = " (bus address [%#010llx-%#010llx])"; 1012 1013 snprintf(addr, sizeof(addr), fmt, 1014 (unsigned long long)(res->start - offset), 1015 (unsigned long long)(res->end - offset)); 1016 } else 1017 addr[0] = '\0'; 1018 1019 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 1020 } 1021 1022 down_write(&pci_bus_sem); 1023 list_add_tail(&bus->node, &pci_root_buses); 1024 up_write(&pci_bus_sem); 1025 1026 return 0; 1027 1028 unregister: 1029 put_device(&bridge->dev); 1030 device_del(&bridge->dev); 1031 1032 free: 1033 kfree(bus); 1034 return err; 1035 } 1036 1037 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1038 { 1039 int pos; 1040 u32 status; 1041 1042 /* 1043 * If extended config space isn't accessible on a bridge's primary 1044 * bus, we certainly can't access it on the secondary bus. 1045 */ 1046 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1047 return false; 1048 1049 /* 1050 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1051 * extended config space is accessible on the primary, it's also 1052 * accessible on the secondary. 1053 */ 1054 if (pci_is_pcie(bridge) && 1055 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1056 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1057 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1058 return true; 1059 1060 /* 1061 * For the other bridge types: 1062 * - PCI-to-PCI bridges 1063 * - PCIe-to-PCI/PCI-X forward bridges 1064 * - PCI/PCI-X-to-PCIe reverse bridges 1065 * extended config space on the secondary side is only accessible 1066 * if the bridge supports PCI-X Mode 2. 1067 */ 1068 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1069 if (!pos) 1070 return false; 1071 1072 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1073 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1074 } 1075 1076 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1077 struct pci_dev *bridge, int busnr) 1078 { 1079 struct pci_bus *child; 1080 struct pci_host_bridge *host; 1081 int i; 1082 int ret; 1083 1084 /* Allocate a new bus and inherit stuff from the parent */ 1085 child = pci_alloc_bus(parent); 1086 if (!child) 1087 return NULL; 1088 1089 child->parent = parent; 1090 child->sysdata = parent->sysdata; 1091 child->bus_flags = parent->bus_flags; 1092 1093 host = pci_find_host_bridge(parent); 1094 if (host->child_ops) 1095 child->ops = host->child_ops; 1096 else 1097 child->ops = parent->ops; 1098 1099 /* 1100 * Initialize some portions of the bus device, but don't register 1101 * it now as the parent is not properly set up yet. 1102 */ 1103 child->dev.class = &pcibus_class; 1104 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1105 1106 /* Set up the primary, secondary and subordinate bus numbers */ 1107 child->number = child->busn_res.start = busnr; 1108 child->primary = parent->busn_res.start; 1109 child->busn_res.end = 0xff; 1110 1111 if (!bridge) { 1112 child->dev.parent = parent->bridge; 1113 goto add_dev; 1114 } 1115 1116 child->self = bridge; 1117 child->bridge = get_device(&bridge->dev); 1118 child->dev.parent = child->bridge; 1119 pci_set_bus_of_node(child); 1120 pci_set_bus_speed(child); 1121 1122 /* 1123 * Check whether extended config space is accessible on the child 1124 * bus. Note that we currently assume it is always accessible on 1125 * the root bus. 1126 */ 1127 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1128 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1129 pci_info(child, "extended config space not accessible\n"); 1130 } 1131 1132 /* Set up default resource pointers and names */ 1133 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1134 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1135 child->resource[i]->name = child->name; 1136 } 1137 bridge->subordinate = child; 1138 1139 add_dev: 1140 pci_set_bus_msi_domain(child); 1141 ret = device_register(&child->dev); 1142 WARN_ON(ret < 0); 1143 1144 pcibios_add_bus(child); 1145 1146 if (child->ops->add_bus) { 1147 ret = child->ops->add_bus(child); 1148 if (WARN_ON(ret < 0)) 1149 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1150 } 1151 1152 /* Create legacy_io and legacy_mem files for this bus */ 1153 pci_create_legacy_files(child); 1154 1155 return child; 1156 } 1157 1158 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1159 int busnr) 1160 { 1161 struct pci_bus *child; 1162 1163 child = pci_alloc_child_bus(parent, dev, busnr); 1164 if (child) { 1165 down_write(&pci_bus_sem); 1166 list_add_tail(&child->node, &parent->children); 1167 up_write(&pci_bus_sem); 1168 } 1169 return child; 1170 } 1171 EXPORT_SYMBOL(pci_add_new_bus); 1172 1173 static void pci_enable_crs(struct pci_dev *pdev) 1174 { 1175 u16 root_cap = 0; 1176 1177 /* Enable CRS Software Visibility if supported */ 1178 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1179 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1180 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1181 PCI_EXP_RTCTL_CRSSVE); 1182 } 1183 1184 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1185 unsigned int available_buses); 1186 /** 1187 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1188 * numbers from EA capability. 1189 * @dev: Bridge 1190 * @sec: updated with secondary bus number from EA 1191 * @sub: updated with subordinate bus number from EA 1192 * 1193 * If @dev is a bridge with EA capability that specifies valid secondary 1194 * and subordinate bus numbers, return true with the bus numbers in @sec 1195 * and @sub. Otherwise return false. 1196 */ 1197 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1198 { 1199 int ea, offset; 1200 u32 dw; 1201 u8 ea_sec, ea_sub; 1202 1203 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1204 return false; 1205 1206 /* find PCI EA capability in list */ 1207 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1208 if (!ea) 1209 return false; 1210 1211 offset = ea + PCI_EA_FIRST_ENT; 1212 pci_read_config_dword(dev, offset, &dw); 1213 ea_sec = dw & PCI_EA_SEC_BUS_MASK; 1214 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; 1215 if (ea_sec == 0 || ea_sub < ea_sec) 1216 return false; 1217 1218 *sec = ea_sec; 1219 *sub = ea_sub; 1220 return true; 1221 } 1222 1223 /* 1224 * pci_scan_bridge_extend() - Scan buses behind a bridge 1225 * @bus: Parent bus the bridge is on 1226 * @dev: Bridge itself 1227 * @max: Starting subordinate number of buses behind this bridge 1228 * @available_buses: Total number of buses available for this bridge and 1229 * the devices below. After the minimal bus space has 1230 * been allocated the remaining buses will be 1231 * distributed equally between hotplug-capable bridges. 1232 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1233 * that need to be reconfigured. 1234 * 1235 * If it's a bridge, configure it and scan the bus behind it. 1236 * For CardBus bridges, we don't scan behind as the devices will 1237 * be handled by the bridge driver itself. 1238 * 1239 * We need to process bridges in two passes -- first we scan those 1240 * already configured by the BIOS and after we are done with all of 1241 * them, we proceed to assigning numbers to the remaining buses in 1242 * order to avoid overlaps between old and new bus numbers. 1243 * 1244 * Return: New subordinate number covering all buses behind this bridge. 1245 */ 1246 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1247 int max, unsigned int available_buses, 1248 int pass) 1249 { 1250 struct pci_bus *child; 1251 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1252 u32 buses, i, j = 0; 1253 u16 bctl; 1254 u8 primary, secondary, subordinate; 1255 int broken = 0; 1256 bool fixed_buses; 1257 u8 fixed_sec, fixed_sub; 1258 int next_busnr; 1259 1260 /* 1261 * Make sure the bridge is powered on to be able to access config 1262 * space of devices below it. 1263 */ 1264 pm_runtime_get_sync(&dev->dev); 1265 1266 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1267 primary = buses & 0xFF; 1268 secondary = (buses >> 8) & 0xFF; 1269 subordinate = (buses >> 16) & 0xFF; 1270 1271 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1272 secondary, subordinate, pass); 1273 1274 if (!primary && (primary != bus->number) && secondary && subordinate) { 1275 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1276 primary = bus->number; 1277 } 1278 1279 /* Check if setup is sensible at all */ 1280 if (!pass && 1281 (primary != bus->number || secondary <= bus->number || 1282 secondary > subordinate)) { 1283 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1284 secondary, subordinate); 1285 broken = 1; 1286 } 1287 1288 /* 1289 * Disable Master-Abort Mode during probing to avoid reporting of 1290 * bus errors in some architectures. 1291 */ 1292 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1293 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1294 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1295 1296 pci_enable_crs(dev); 1297 1298 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1299 !is_cardbus && !broken) { 1300 unsigned int cmax; 1301 1302 /* 1303 * Bus already configured by firmware, process it in the 1304 * first pass and just note the configuration. 1305 */ 1306 if (pass) 1307 goto out; 1308 1309 /* 1310 * The bus might already exist for two reasons: Either we 1311 * are rescanning the bus or the bus is reachable through 1312 * more than one bridge. The second case can happen with 1313 * the i450NX chipset. 1314 */ 1315 child = pci_find_bus(pci_domain_nr(bus), secondary); 1316 if (!child) { 1317 child = pci_add_new_bus(bus, dev, secondary); 1318 if (!child) 1319 goto out; 1320 child->primary = primary; 1321 pci_bus_insert_busn_res(child, secondary, subordinate); 1322 child->bridge_ctl = bctl; 1323 } 1324 1325 cmax = pci_scan_child_bus(child); 1326 if (cmax > subordinate) 1327 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1328 subordinate, cmax); 1329 1330 /* Subordinate should equal child->busn_res.end */ 1331 if (subordinate > max) 1332 max = subordinate; 1333 } else { 1334 1335 /* 1336 * We need to assign a number to this bus which we always 1337 * do in the second pass. 1338 */ 1339 if (!pass) { 1340 if (pcibios_assign_all_busses() || broken || is_cardbus) 1341 1342 /* 1343 * Temporarily disable forwarding of the 1344 * configuration cycles on all bridges in 1345 * this bus segment to avoid possible 1346 * conflicts in the second pass between two 1347 * bridges programmed with overlapping bus 1348 * ranges. 1349 */ 1350 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1351 buses & ~0xffffff); 1352 goto out; 1353 } 1354 1355 /* Clear errors */ 1356 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1357 1358 /* Read bus numbers from EA Capability (if present) */ 1359 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1360 if (fixed_buses) 1361 next_busnr = fixed_sec; 1362 else 1363 next_busnr = max + 1; 1364 1365 /* 1366 * Prevent assigning a bus number that already exists. 1367 * This can happen when a bridge is hot-plugged, so in this 1368 * case we only re-scan this bus. 1369 */ 1370 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1371 if (!child) { 1372 child = pci_add_new_bus(bus, dev, next_busnr); 1373 if (!child) 1374 goto out; 1375 pci_bus_insert_busn_res(child, next_busnr, 1376 bus->busn_res.end); 1377 } 1378 max++; 1379 if (available_buses) 1380 available_buses--; 1381 1382 buses = (buses & 0xff000000) 1383 | ((unsigned int)(child->primary) << 0) 1384 | ((unsigned int)(child->busn_res.start) << 8) 1385 | ((unsigned int)(child->busn_res.end) << 16); 1386 1387 /* 1388 * yenta.c forces a secondary latency timer of 176. 1389 * Copy that behaviour here. 1390 */ 1391 if (is_cardbus) { 1392 buses &= ~0xff000000; 1393 buses |= CARDBUS_LATENCY_TIMER << 24; 1394 } 1395 1396 /* We need to blast all three values with a single write */ 1397 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1398 1399 if (!is_cardbus) { 1400 child->bridge_ctl = bctl; 1401 max = pci_scan_child_bus_extend(child, available_buses); 1402 } else { 1403 1404 /* 1405 * For CardBus bridges, we leave 4 bus numbers as 1406 * cards with a PCI-to-PCI bridge can be inserted 1407 * later. 1408 */ 1409 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1410 struct pci_bus *parent = bus; 1411 if (pci_find_bus(pci_domain_nr(bus), 1412 max+i+1)) 1413 break; 1414 while (parent->parent) { 1415 if ((!pcibios_assign_all_busses()) && 1416 (parent->busn_res.end > max) && 1417 (parent->busn_res.end <= max+i)) { 1418 j = 1; 1419 } 1420 parent = parent->parent; 1421 } 1422 if (j) { 1423 1424 /* 1425 * Often, there are two CardBus 1426 * bridges -- try to leave one 1427 * valid bus number for each one. 1428 */ 1429 i /= 2; 1430 break; 1431 } 1432 } 1433 max += i; 1434 } 1435 1436 /* 1437 * Set subordinate bus number to its real value. 1438 * If fixed subordinate bus number exists from EA 1439 * capability then use it. 1440 */ 1441 if (fixed_buses) 1442 max = fixed_sub; 1443 pci_bus_update_busn_res_end(child, max); 1444 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1445 } 1446 1447 sprintf(child->name, 1448 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1449 pci_domain_nr(bus), child->number); 1450 1451 /* Check that all devices are accessible */ 1452 while (bus->parent) { 1453 if ((child->busn_res.end > bus->busn_res.end) || 1454 (child->number > bus->busn_res.end) || 1455 (child->number < bus->number) || 1456 (child->busn_res.end < bus->number)) { 1457 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1458 &child->busn_res); 1459 break; 1460 } 1461 bus = bus->parent; 1462 } 1463 1464 out: 1465 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1466 1467 pm_runtime_put(&dev->dev); 1468 1469 return max; 1470 } 1471 1472 /* 1473 * pci_scan_bridge() - Scan buses behind a bridge 1474 * @bus: Parent bus the bridge is on 1475 * @dev: Bridge itself 1476 * @max: Starting subordinate number of buses behind this bridge 1477 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1478 * that need to be reconfigured. 1479 * 1480 * If it's a bridge, configure it and scan the bus behind it. 1481 * For CardBus bridges, we don't scan behind as the devices will 1482 * be handled by the bridge driver itself. 1483 * 1484 * We need to process bridges in two passes -- first we scan those 1485 * already configured by the BIOS and after we are done with all of 1486 * them, we proceed to assigning numbers to the remaining buses in 1487 * order to avoid overlaps between old and new bus numbers. 1488 * 1489 * Return: New subordinate number covering all buses behind this bridge. 1490 */ 1491 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1492 { 1493 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1494 } 1495 EXPORT_SYMBOL(pci_scan_bridge); 1496 1497 /* 1498 * Read interrupt line and base address registers. 1499 * The architecture-dependent code can tweak these, of course. 1500 */ 1501 static void pci_read_irq(struct pci_dev *dev) 1502 { 1503 unsigned char irq; 1504 1505 /* VFs are not allowed to use INTx, so skip the config reads */ 1506 if (dev->is_virtfn) { 1507 dev->pin = 0; 1508 dev->irq = 0; 1509 return; 1510 } 1511 1512 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1513 dev->pin = irq; 1514 if (irq) 1515 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1516 dev->irq = irq; 1517 } 1518 1519 void set_pcie_port_type(struct pci_dev *pdev) 1520 { 1521 int pos; 1522 u16 reg16; 1523 int type; 1524 struct pci_dev *parent; 1525 1526 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1527 if (!pos) 1528 return; 1529 1530 pdev->pcie_cap = pos; 1531 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1532 pdev->pcie_flags_reg = reg16; 1533 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1534 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1535 1536 parent = pci_upstream_bridge(pdev); 1537 if (!parent) 1538 return; 1539 1540 /* 1541 * Some systems do not identify their upstream/downstream ports 1542 * correctly so detect impossible configurations here and correct 1543 * the port type accordingly. 1544 */ 1545 type = pci_pcie_type(pdev); 1546 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1547 /* 1548 * If pdev claims to be downstream port but the parent 1549 * device is also downstream port assume pdev is actually 1550 * upstream port. 1551 */ 1552 if (pcie_downstream_port(parent)) { 1553 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1554 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1555 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1556 } 1557 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1558 /* 1559 * If pdev claims to be upstream port but the parent 1560 * device is also upstream port assume pdev is actually 1561 * downstream port. 1562 */ 1563 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1564 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1565 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1566 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1567 } 1568 } 1569 } 1570 1571 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1572 { 1573 u32 reg32; 1574 1575 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1576 if (reg32 & PCI_EXP_SLTCAP_HPC) 1577 pdev->is_hotplug_bridge = 1; 1578 } 1579 1580 static void set_pcie_thunderbolt(struct pci_dev *dev) 1581 { 1582 u16 vsec; 1583 1584 /* Is the device part of a Thunderbolt controller? */ 1585 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); 1586 if (vsec) 1587 dev->is_thunderbolt = 1; 1588 } 1589 1590 static void set_pcie_untrusted(struct pci_dev *dev) 1591 { 1592 struct pci_dev *parent; 1593 1594 /* 1595 * If the upstream bridge is untrusted we treat this device 1596 * untrusted as well. 1597 */ 1598 parent = pci_upstream_bridge(dev); 1599 if (parent && (parent->untrusted || parent->external_facing)) 1600 dev->untrusted = true; 1601 } 1602 1603 static void pci_set_removable(struct pci_dev *dev) 1604 { 1605 struct pci_dev *parent = pci_upstream_bridge(dev); 1606 1607 /* 1608 * We (only) consider everything downstream from an external_facing 1609 * device to be removable by the user. We're mainly concerned with 1610 * consumer platforms with user accessible thunderbolt ports that are 1611 * vulnerable to DMA attacks, and we expect those ports to be marked by 1612 * the firmware as external_facing. Devices in traditional hotplug 1613 * slots can technically be removed, but the expectation is that unless 1614 * the port is marked with external_facing, such devices are less 1615 * accessible to user / may not be removed by end user, and thus not 1616 * exposed as "removable" to userspace. 1617 */ 1618 if (parent && 1619 (parent->external_facing || dev_is_removable(&parent->dev))) 1620 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1621 } 1622 1623 /** 1624 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1625 * @dev: PCI device 1626 * 1627 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1628 * when forwarding a type1 configuration request the bridge must check that 1629 * the extended register address field is zero. The bridge is not permitted 1630 * to forward the transactions and must handle it as an Unsupported Request. 1631 * Some bridges do not follow this rule and simply drop the extended register 1632 * bits, resulting in the standard config space being aliased, every 256 1633 * bytes across the entire configuration space. Test for this condition by 1634 * comparing the first dword of each potential alias to the vendor/device ID. 1635 * Known offenders: 1636 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1637 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1638 */ 1639 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1640 { 1641 #ifdef CONFIG_PCI_QUIRKS 1642 int pos; 1643 u32 header, tmp; 1644 1645 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1646 1647 for (pos = PCI_CFG_SPACE_SIZE; 1648 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1649 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL 1650 || header != tmp) 1651 return false; 1652 } 1653 1654 return true; 1655 #else 1656 return false; 1657 #endif 1658 } 1659 1660 /** 1661 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1662 * @dev: PCI device 1663 * 1664 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1665 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1666 * access it. Maybe we don't have a way to generate extended config space 1667 * accesses, or the device is behind a reverse Express bridge. So we try 1668 * reading the dword at 0x100 which must either be 0 or a valid extended 1669 * capability header. 1670 */ 1671 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1672 { 1673 u32 status; 1674 int pos = PCI_CFG_SPACE_SIZE; 1675 1676 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1677 return PCI_CFG_SPACE_SIZE; 1678 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) 1679 return PCI_CFG_SPACE_SIZE; 1680 1681 return PCI_CFG_SPACE_EXP_SIZE; 1682 } 1683 1684 int pci_cfg_space_size(struct pci_dev *dev) 1685 { 1686 int pos; 1687 u32 status; 1688 u16 class; 1689 1690 #ifdef CONFIG_PCI_IOV 1691 /* 1692 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1693 * implement a PCIe capability and therefore must implement extended 1694 * config space. We can skip the NO_EXTCFG test below and the 1695 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1696 * the fact that the SR-IOV capability on the PF resides in extended 1697 * config space and must be accessible and non-aliased to have enabled 1698 * support for this VF. This is a micro performance optimization for 1699 * systems supporting many VFs. 1700 */ 1701 if (dev->is_virtfn) 1702 return PCI_CFG_SPACE_EXP_SIZE; 1703 #endif 1704 1705 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1706 return PCI_CFG_SPACE_SIZE; 1707 1708 class = dev->class >> 8; 1709 if (class == PCI_CLASS_BRIDGE_HOST) 1710 return pci_cfg_space_size_ext(dev); 1711 1712 if (pci_is_pcie(dev)) 1713 return pci_cfg_space_size_ext(dev); 1714 1715 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1716 if (!pos) 1717 return PCI_CFG_SPACE_SIZE; 1718 1719 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1720 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1721 return pci_cfg_space_size_ext(dev); 1722 1723 return PCI_CFG_SPACE_SIZE; 1724 } 1725 1726 static u32 pci_class(struct pci_dev *dev) 1727 { 1728 u32 class; 1729 1730 #ifdef CONFIG_PCI_IOV 1731 if (dev->is_virtfn) 1732 return dev->physfn->sriov->class; 1733 #endif 1734 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1735 return class; 1736 } 1737 1738 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1739 { 1740 #ifdef CONFIG_PCI_IOV 1741 if (dev->is_virtfn) { 1742 *vendor = dev->physfn->sriov->subsystem_vendor; 1743 *device = dev->physfn->sriov->subsystem_device; 1744 return; 1745 } 1746 #endif 1747 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1748 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1749 } 1750 1751 static u8 pci_hdr_type(struct pci_dev *dev) 1752 { 1753 u8 hdr_type; 1754 1755 #ifdef CONFIG_PCI_IOV 1756 if (dev->is_virtfn) 1757 return dev->physfn->sriov->hdr_type; 1758 #endif 1759 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1760 return hdr_type; 1761 } 1762 1763 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1764 1765 /** 1766 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1767 * @dev: PCI device 1768 * 1769 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1770 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1771 */ 1772 static int pci_intx_mask_broken(struct pci_dev *dev) 1773 { 1774 u16 orig, toggle, new; 1775 1776 pci_read_config_word(dev, PCI_COMMAND, &orig); 1777 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1778 pci_write_config_word(dev, PCI_COMMAND, toggle); 1779 pci_read_config_word(dev, PCI_COMMAND, &new); 1780 1781 pci_write_config_word(dev, PCI_COMMAND, orig); 1782 1783 /* 1784 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1785 * r2.3, so strictly speaking, a device is not *broken* if it's not 1786 * writable. But we'll live with the misnomer for now. 1787 */ 1788 if (new != toggle) 1789 return 1; 1790 return 0; 1791 } 1792 1793 static void early_dump_pci_device(struct pci_dev *pdev) 1794 { 1795 u32 value[256 / 4]; 1796 int i; 1797 1798 pci_info(pdev, "config space:\n"); 1799 1800 for (i = 0; i < 256; i += 4) 1801 pci_read_config_dword(pdev, i, &value[i / 4]); 1802 1803 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1804 value, 256, false); 1805 } 1806 1807 /** 1808 * pci_setup_device - Fill in class and map information of a device 1809 * @dev: the device structure to fill 1810 * 1811 * Initialize the device structure with information about the device's 1812 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1813 * Called at initialisation of the PCI subsystem and by CardBus services. 1814 * Returns 0 on success and negative if unknown type of device (not normal, 1815 * bridge or CardBus). 1816 */ 1817 int pci_setup_device(struct pci_dev *dev) 1818 { 1819 u32 class; 1820 u16 cmd; 1821 u8 hdr_type; 1822 int pos = 0; 1823 struct pci_bus_region region; 1824 struct resource *res; 1825 1826 hdr_type = pci_hdr_type(dev); 1827 1828 dev->sysdata = dev->bus->sysdata; 1829 dev->dev.parent = dev->bus->bridge; 1830 dev->dev.bus = &pci_bus_type; 1831 dev->hdr_type = hdr_type & 0x7f; 1832 dev->multifunction = !!(hdr_type & 0x80); 1833 dev->error_state = pci_channel_io_normal; 1834 set_pcie_port_type(dev); 1835 1836 pci_set_of_node(dev); 1837 pci_set_acpi_fwnode(dev); 1838 1839 pci_dev_assign_slot(dev); 1840 1841 /* 1842 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1843 * set this higher, assuming the system even supports it. 1844 */ 1845 dev->dma_mask = 0xffffffff; 1846 1847 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1848 dev->bus->number, PCI_SLOT(dev->devfn), 1849 PCI_FUNC(dev->devfn)); 1850 1851 class = pci_class(dev); 1852 1853 dev->revision = class & 0xff; 1854 dev->class = class >> 8; /* upper 3 bytes */ 1855 1856 if (pci_early_dump) 1857 early_dump_pci_device(dev); 1858 1859 /* Need to have dev->class ready */ 1860 dev->cfg_size = pci_cfg_space_size(dev); 1861 1862 /* Need to have dev->cfg_size ready */ 1863 set_pcie_thunderbolt(dev); 1864 1865 set_pcie_untrusted(dev); 1866 1867 /* "Unknown power state" */ 1868 dev->current_state = PCI_UNKNOWN; 1869 1870 /* Early fixups, before probing the BARs */ 1871 pci_fixup_device(pci_fixup_early, dev); 1872 1873 pci_set_removable(dev); 1874 1875 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 1876 dev->vendor, dev->device, dev->hdr_type, dev->class); 1877 1878 /* Device class may be changed after fixup */ 1879 class = dev->class >> 8; 1880 1881 if (dev->non_compliant_bars && !dev->mmio_always_on) { 1882 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1883 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1884 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1885 cmd &= ~PCI_COMMAND_IO; 1886 cmd &= ~PCI_COMMAND_MEMORY; 1887 pci_write_config_word(dev, PCI_COMMAND, cmd); 1888 } 1889 } 1890 1891 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1892 1893 /* Clear errors left from system firmware */ 1894 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1895 1896 switch (dev->hdr_type) { /* header type */ 1897 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1898 if (class == PCI_CLASS_BRIDGE_PCI) 1899 goto bad; 1900 pci_read_irq(dev); 1901 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1902 1903 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1904 1905 /* 1906 * Do the ugly legacy mode stuff here rather than broken chip 1907 * quirk code. Legacy mode ATA controllers have fixed 1908 * addresses. These are not always echoed in BAR0-3, and 1909 * BAR0-3 in a few cases contain junk! 1910 */ 1911 if (class == PCI_CLASS_STORAGE_IDE) { 1912 u8 progif; 1913 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1914 if ((progif & 1) == 0) { 1915 region.start = 0x1F0; 1916 region.end = 0x1F7; 1917 res = &dev->resource[0]; 1918 res->flags = LEGACY_IO_RESOURCE; 1919 pcibios_bus_to_resource(dev->bus, res, ®ion); 1920 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1921 res); 1922 region.start = 0x3F6; 1923 region.end = 0x3F6; 1924 res = &dev->resource[1]; 1925 res->flags = LEGACY_IO_RESOURCE; 1926 pcibios_bus_to_resource(dev->bus, res, ®ion); 1927 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1928 res); 1929 } 1930 if ((progif & 4) == 0) { 1931 region.start = 0x170; 1932 region.end = 0x177; 1933 res = &dev->resource[2]; 1934 res->flags = LEGACY_IO_RESOURCE; 1935 pcibios_bus_to_resource(dev->bus, res, ®ion); 1936 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1937 res); 1938 region.start = 0x376; 1939 region.end = 0x376; 1940 res = &dev->resource[3]; 1941 res->flags = LEGACY_IO_RESOURCE; 1942 pcibios_bus_to_resource(dev->bus, res, ®ion); 1943 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1944 res); 1945 } 1946 } 1947 break; 1948 1949 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1950 /* 1951 * The PCI-to-PCI bridge spec requires that subtractive 1952 * decoding (i.e. transparent) bridge must have programming 1953 * interface code of 0x01. 1954 */ 1955 pci_read_irq(dev); 1956 dev->transparent = ((dev->class & 0xff) == 1); 1957 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1958 pci_read_bridge_windows(dev); 1959 set_pcie_hotplug_bridge(dev); 1960 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1961 if (pos) { 1962 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1963 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1964 } 1965 break; 1966 1967 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1968 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1969 goto bad; 1970 pci_read_irq(dev); 1971 pci_read_bases(dev, 1, 0); 1972 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1973 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1974 break; 1975 1976 default: /* unknown header */ 1977 pci_err(dev, "unknown header type %02x, ignoring device\n", 1978 dev->hdr_type); 1979 pci_release_of_node(dev); 1980 return -EIO; 1981 1982 bad: 1983 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1984 dev->class, dev->hdr_type); 1985 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1986 } 1987 1988 /* We found a fine healthy device, go go go... */ 1989 return 0; 1990 } 1991 1992 static void pci_configure_mps(struct pci_dev *dev) 1993 { 1994 struct pci_dev *bridge = pci_upstream_bridge(dev); 1995 int mps, mpss, p_mps, rc; 1996 1997 if (!pci_is_pcie(dev)) 1998 return; 1999 2000 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 2001 if (dev->is_virtfn) 2002 return; 2003 2004 /* 2005 * For Root Complex Integrated Endpoints, program the maximum 2006 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 2007 */ 2008 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 2009 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2010 mps = 128; 2011 else 2012 mps = 128 << dev->pcie_mpss; 2013 rc = pcie_set_mps(dev, mps); 2014 if (rc) { 2015 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2016 mps); 2017 } 2018 return; 2019 } 2020 2021 if (!bridge || !pci_is_pcie(bridge)) 2022 return; 2023 2024 mps = pcie_get_mps(dev); 2025 p_mps = pcie_get_mps(bridge); 2026 2027 if (mps == p_mps) 2028 return; 2029 2030 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2031 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2032 mps, pci_name(bridge), p_mps); 2033 return; 2034 } 2035 2036 /* 2037 * Fancier MPS configuration is done later by 2038 * pcie_bus_configure_settings() 2039 */ 2040 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2041 return; 2042 2043 mpss = 128 << dev->pcie_mpss; 2044 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2045 pcie_set_mps(bridge, mpss); 2046 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2047 mpss, p_mps, 128 << bridge->pcie_mpss); 2048 p_mps = pcie_get_mps(bridge); 2049 } 2050 2051 rc = pcie_set_mps(dev, p_mps); 2052 if (rc) { 2053 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2054 p_mps); 2055 return; 2056 } 2057 2058 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2059 p_mps, mps, mpss); 2060 } 2061 2062 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2063 { 2064 struct pci_host_bridge *host; 2065 u32 cap; 2066 u16 ctl; 2067 int ret; 2068 2069 if (!pci_is_pcie(dev)) 2070 return 0; 2071 2072 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2073 if (ret) 2074 return 0; 2075 2076 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2077 return 0; 2078 2079 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2080 if (ret) 2081 return 0; 2082 2083 host = pci_find_host_bridge(dev->bus); 2084 if (!host) 2085 return 0; 2086 2087 /* 2088 * If some device in the hierarchy doesn't handle Extended Tags 2089 * correctly, make sure they're disabled. 2090 */ 2091 if (host->no_ext_tags) { 2092 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2093 pci_info(dev, "disabling Extended Tags\n"); 2094 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2095 PCI_EXP_DEVCTL_EXT_TAG); 2096 } 2097 return 0; 2098 } 2099 2100 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2101 pci_info(dev, "enabling Extended Tags\n"); 2102 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2103 PCI_EXP_DEVCTL_EXT_TAG); 2104 } 2105 return 0; 2106 } 2107 2108 /** 2109 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2110 * @dev: PCI device to query 2111 * 2112 * Returns true if the device has enabled relaxed ordering attribute. 2113 */ 2114 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2115 { 2116 u16 v; 2117 2118 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2119 2120 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2121 } 2122 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2123 2124 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2125 { 2126 struct pci_dev *root; 2127 2128 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ 2129 if (dev->is_virtfn) 2130 return; 2131 2132 if (!pcie_relaxed_ordering_enabled(dev)) 2133 return; 2134 2135 /* 2136 * For now, we only deal with Relaxed Ordering issues with Root 2137 * Ports. Peer-to-Peer DMA is another can of worms. 2138 */ 2139 root = pcie_find_root_port(dev); 2140 if (!root) 2141 return; 2142 2143 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2144 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2145 PCI_EXP_DEVCTL_RELAX_EN); 2146 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2147 } 2148 } 2149 2150 static void pci_configure_ltr(struct pci_dev *dev) 2151 { 2152 #ifdef CONFIG_PCIEASPM 2153 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 2154 struct pci_dev *bridge; 2155 u32 cap, ctl; 2156 2157 if (!pci_is_pcie(dev)) 2158 return; 2159 2160 /* Read L1 PM substate capabilities */ 2161 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); 2162 2163 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2164 if (!(cap & PCI_EXP_DEVCAP2_LTR)) 2165 return; 2166 2167 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); 2168 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { 2169 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2170 dev->ltr_path = 1; 2171 return; 2172 } 2173 2174 bridge = pci_upstream_bridge(dev); 2175 if (bridge && bridge->ltr_path) 2176 dev->ltr_path = 1; 2177 2178 return; 2179 } 2180 2181 if (!host->native_ltr) 2182 return; 2183 2184 /* 2185 * Software must not enable LTR in an Endpoint unless the Root 2186 * Complex and all intermediate Switches indicate support for LTR. 2187 * PCIe r4.0, sec 6.18. 2188 */ 2189 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2190 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2191 PCI_EXP_DEVCTL2_LTR_EN); 2192 dev->ltr_path = 1; 2193 return; 2194 } 2195 2196 /* 2197 * If we're configuring a hot-added device, LTR was likely 2198 * disabled in the upstream bridge, so re-enable it before enabling 2199 * it in the new device. 2200 */ 2201 bridge = pci_upstream_bridge(dev); 2202 if (bridge && bridge->ltr_path) { 2203 pci_bridge_reconfigure_ltr(dev); 2204 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2205 PCI_EXP_DEVCTL2_LTR_EN); 2206 dev->ltr_path = 1; 2207 } 2208 #endif 2209 } 2210 2211 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2212 { 2213 #ifdef CONFIG_PCI_PASID 2214 struct pci_dev *bridge; 2215 int pcie_type; 2216 u32 cap; 2217 2218 if (!pci_is_pcie(dev)) 2219 return; 2220 2221 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2222 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2223 return; 2224 2225 pcie_type = pci_pcie_type(dev); 2226 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2227 pcie_type == PCI_EXP_TYPE_RC_END) 2228 dev->eetlp_prefix_path = 1; 2229 else { 2230 bridge = pci_upstream_bridge(dev); 2231 if (bridge && bridge->eetlp_prefix_path) 2232 dev->eetlp_prefix_path = 1; 2233 } 2234 #endif 2235 } 2236 2237 static void pci_configure_serr(struct pci_dev *dev) 2238 { 2239 u16 control; 2240 2241 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2242 2243 /* 2244 * A bridge will not forward ERR_ messages coming from an 2245 * endpoint unless SERR# forwarding is enabled. 2246 */ 2247 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2248 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2249 control |= PCI_BRIDGE_CTL_SERR; 2250 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2251 } 2252 } 2253 } 2254 2255 static void pci_configure_device(struct pci_dev *dev) 2256 { 2257 pci_configure_mps(dev); 2258 pci_configure_extended_tags(dev, NULL); 2259 pci_configure_relaxed_ordering(dev); 2260 pci_configure_ltr(dev); 2261 pci_configure_eetlp_prefix(dev); 2262 pci_configure_serr(dev); 2263 2264 pci_acpi_program_hp_params(dev); 2265 } 2266 2267 static void pci_release_capabilities(struct pci_dev *dev) 2268 { 2269 pci_aer_exit(dev); 2270 pci_rcec_exit(dev); 2271 pci_iov_release(dev); 2272 pci_free_cap_save_buffers(dev); 2273 } 2274 2275 /** 2276 * pci_release_dev - Free a PCI device structure when all users of it are 2277 * finished 2278 * @dev: device that's been disconnected 2279 * 2280 * Will be called only by the device core when all users of this PCI device are 2281 * done. 2282 */ 2283 static void pci_release_dev(struct device *dev) 2284 { 2285 struct pci_dev *pci_dev; 2286 2287 pci_dev = to_pci_dev(dev); 2288 pci_release_capabilities(pci_dev); 2289 pci_release_of_node(pci_dev); 2290 pcibios_release_device(pci_dev); 2291 pci_bus_put(pci_dev->bus); 2292 kfree(pci_dev->driver_override); 2293 bitmap_free(pci_dev->dma_alias_mask); 2294 dev_dbg(dev, "device released\n"); 2295 kfree(pci_dev); 2296 } 2297 2298 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2299 { 2300 struct pci_dev *dev; 2301 2302 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2303 if (!dev) 2304 return NULL; 2305 2306 INIT_LIST_HEAD(&dev->bus_list); 2307 dev->dev.type = &pci_dev_type; 2308 dev->bus = pci_bus_get(bus); 2309 #ifdef CONFIG_PCI_MSI 2310 raw_spin_lock_init(&dev->msi_lock); 2311 #endif 2312 return dev; 2313 } 2314 EXPORT_SYMBOL(pci_alloc_dev); 2315 2316 static bool pci_bus_crs_vendor_id(u32 l) 2317 { 2318 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 2319 } 2320 2321 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2322 int timeout) 2323 { 2324 int delay = 1; 2325 2326 if (!pci_bus_crs_vendor_id(*l)) 2327 return true; /* not a CRS completion */ 2328 2329 if (!timeout) 2330 return false; /* CRS, but caller doesn't want to wait */ 2331 2332 /* 2333 * We got the reserved Vendor ID that indicates a completion with 2334 * Configuration Request Retry Status (CRS). Retry until we get a 2335 * valid Vendor ID or we time out. 2336 */ 2337 while (pci_bus_crs_vendor_id(*l)) { 2338 if (delay > timeout) { 2339 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2340 pci_domain_nr(bus), bus->number, 2341 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2342 2343 return false; 2344 } 2345 if (delay >= 1000) 2346 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2347 pci_domain_nr(bus), bus->number, 2348 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2349 2350 msleep(delay); 2351 delay *= 2; 2352 2353 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2354 return false; 2355 } 2356 2357 if (delay >= 1000) 2358 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2359 pci_domain_nr(bus), bus->number, 2360 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2361 2362 return true; 2363 } 2364 2365 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2366 int timeout) 2367 { 2368 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2369 return false; 2370 2371 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ 2372 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || 2373 *l == 0x0000ffff || *l == 0xffff0000) 2374 return false; 2375 2376 if (pci_bus_crs_vendor_id(*l)) 2377 return pci_bus_wait_crs(bus, devfn, l, timeout); 2378 2379 return true; 2380 } 2381 2382 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2383 int timeout) 2384 { 2385 #ifdef CONFIG_PCI_QUIRKS 2386 struct pci_dev *bridge = bus->self; 2387 2388 /* 2389 * Certain IDT switches have an issue where they improperly trigger 2390 * ACS Source Validation errors on completions for config reads. 2391 */ 2392 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2393 bridge->device == 0x80b5) 2394 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2395 #endif 2396 2397 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2398 } 2399 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2400 2401 /* 2402 * Read the config data for a PCI device, sanity-check it, 2403 * and fill in the dev structure. 2404 */ 2405 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2406 { 2407 struct pci_dev *dev; 2408 u32 l; 2409 2410 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2411 return NULL; 2412 2413 dev = pci_alloc_dev(bus); 2414 if (!dev) 2415 return NULL; 2416 2417 dev->devfn = devfn; 2418 dev->vendor = l & 0xffff; 2419 dev->device = (l >> 16) & 0xffff; 2420 2421 if (pci_setup_device(dev)) { 2422 pci_bus_put(dev->bus); 2423 kfree(dev); 2424 return NULL; 2425 } 2426 2427 return dev; 2428 } 2429 2430 void pcie_report_downtraining(struct pci_dev *dev) 2431 { 2432 if (!pci_is_pcie(dev)) 2433 return; 2434 2435 /* Look from the device up to avoid downstream ports with no devices */ 2436 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2437 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2438 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2439 return; 2440 2441 /* Multi-function PCIe devices share the same link/status */ 2442 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2443 return; 2444 2445 /* Print link status only if the device is constrained by the fabric */ 2446 __pcie_print_link_status(dev, false); 2447 } 2448 2449 static void pci_init_capabilities(struct pci_dev *dev) 2450 { 2451 pci_ea_init(dev); /* Enhanced Allocation */ 2452 pci_msi_init(dev); /* Disable MSI */ 2453 pci_msix_init(dev); /* Disable MSI-X */ 2454 2455 /* Buffers for saving PCIe and PCI-X capabilities */ 2456 pci_allocate_cap_save_buffers(dev); 2457 2458 pci_pm_init(dev); /* Power Management */ 2459 pci_vpd_init(dev); /* Vital Product Data */ 2460 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2461 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2462 pci_ats_init(dev); /* Address Translation Services */ 2463 pci_pri_init(dev); /* Page Request Interface */ 2464 pci_pasid_init(dev); /* Process Address Space ID */ 2465 pci_acs_init(dev); /* Access Control Services */ 2466 pci_ptm_init(dev); /* Precision Time Measurement */ 2467 pci_aer_init(dev); /* Advanced Error Reporting */ 2468 pci_dpc_init(dev); /* Downstream Port Containment */ 2469 pci_rcec_init(dev); /* Root Complex Event Collector */ 2470 2471 pcie_report_downtraining(dev); 2472 pci_init_reset_methods(dev); 2473 } 2474 2475 /* 2476 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2477 * devices. Firmware interfaces that can select the MSI domain on a 2478 * per-device basis should be called from here. 2479 */ 2480 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2481 { 2482 struct irq_domain *d; 2483 2484 /* 2485 * If a domain has been set through the pcibios_device_add() 2486 * callback, then this is the one (platform code knows best). 2487 */ 2488 d = dev_get_msi_domain(&dev->dev); 2489 if (d) 2490 return d; 2491 2492 /* 2493 * Let's see if we have a firmware interface able to provide 2494 * the domain. 2495 */ 2496 d = pci_msi_get_device_domain(dev); 2497 if (d) 2498 return d; 2499 2500 return NULL; 2501 } 2502 2503 static void pci_set_msi_domain(struct pci_dev *dev) 2504 { 2505 struct irq_domain *d; 2506 2507 /* 2508 * If the platform or firmware interfaces cannot supply a 2509 * device-specific MSI domain, then inherit the default domain 2510 * from the host bridge itself. 2511 */ 2512 d = pci_dev_msi_domain(dev); 2513 if (!d) 2514 d = dev_get_msi_domain(&dev->bus->dev); 2515 2516 dev_set_msi_domain(&dev->dev, d); 2517 } 2518 2519 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2520 { 2521 int ret; 2522 2523 pci_configure_device(dev); 2524 2525 device_initialize(&dev->dev); 2526 dev->dev.release = pci_release_dev; 2527 2528 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2529 dev->dev.dma_mask = &dev->dma_mask; 2530 dev->dev.dma_parms = &dev->dma_parms; 2531 dev->dev.coherent_dma_mask = 0xffffffffull; 2532 2533 dma_set_max_seg_size(&dev->dev, 65536); 2534 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2535 2536 /* Fix up broken headers */ 2537 pci_fixup_device(pci_fixup_header, dev); 2538 2539 pci_reassigndev_resource_alignment(dev); 2540 2541 dev->state_saved = false; 2542 2543 pci_init_capabilities(dev); 2544 2545 /* 2546 * Add the device to our list of discovered devices 2547 * and the bus list for fixup functions, etc. 2548 */ 2549 down_write(&pci_bus_sem); 2550 list_add_tail(&dev->bus_list, &bus->devices); 2551 up_write(&pci_bus_sem); 2552 2553 ret = pcibios_device_add(dev); 2554 WARN_ON(ret < 0); 2555 2556 /* Set up MSI IRQ domain */ 2557 pci_set_msi_domain(dev); 2558 2559 /* Notifier could use PCI capabilities */ 2560 dev->match_driver = false; 2561 ret = device_add(&dev->dev); 2562 WARN_ON(ret < 0); 2563 } 2564 2565 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2566 { 2567 struct pci_dev *dev; 2568 2569 dev = pci_get_slot(bus, devfn); 2570 if (dev) { 2571 pci_dev_put(dev); 2572 return dev; 2573 } 2574 2575 dev = pci_scan_device(bus, devfn); 2576 if (!dev) 2577 return NULL; 2578 2579 pci_device_add(dev, bus); 2580 2581 return dev; 2582 } 2583 EXPORT_SYMBOL(pci_scan_single_device); 2584 2585 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2586 { 2587 int pos; 2588 u16 cap = 0; 2589 unsigned int next_fn; 2590 2591 if (!dev) 2592 return -ENODEV; 2593 2594 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2595 if (!pos) 2596 return -ENODEV; 2597 2598 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2599 next_fn = PCI_ARI_CAP_NFN(cap); 2600 if (next_fn <= fn) 2601 return -ENODEV; /* protect against malformed list */ 2602 2603 return next_fn; 2604 } 2605 2606 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2607 { 2608 if (pci_ari_enabled(bus)) 2609 return next_ari_fn(bus, dev, fn); 2610 2611 if (fn >= 7) 2612 return -ENODEV; 2613 /* only multifunction devices may have more functions */ 2614 if (dev && !dev->multifunction) 2615 return -ENODEV; 2616 2617 return fn + 1; 2618 } 2619 2620 static int only_one_child(struct pci_bus *bus) 2621 { 2622 struct pci_dev *bridge = bus->self; 2623 2624 /* 2625 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2626 * we scan for all possible devices, not just Device 0. 2627 */ 2628 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2629 return 0; 2630 2631 /* 2632 * A PCIe Downstream Port normally leads to a Link with only Device 2633 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2634 * only for Device 0 in that situation. 2635 */ 2636 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2637 return 1; 2638 2639 return 0; 2640 } 2641 2642 /** 2643 * pci_scan_slot - Scan a PCI slot on a bus for devices 2644 * @bus: PCI bus to scan 2645 * @devfn: slot number to scan (must have zero function) 2646 * 2647 * Scan a PCI slot on the specified PCI bus for devices, adding 2648 * discovered devices to the @bus->devices list. New devices 2649 * will not have is_added set. 2650 * 2651 * Returns the number of new devices found. 2652 */ 2653 int pci_scan_slot(struct pci_bus *bus, int devfn) 2654 { 2655 struct pci_dev *dev; 2656 int fn = 0, nr = 0; 2657 2658 if (only_one_child(bus) && (devfn > 0)) 2659 return 0; /* Already scanned the entire slot */ 2660 2661 do { 2662 dev = pci_scan_single_device(bus, devfn + fn); 2663 if (dev) { 2664 if (!pci_dev_is_added(dev)) 2665 nr++; 2666 if (fn > 0) 2667 dev->multifunction = 1; 2668 } else if (fn == 0) { 2669 /* 2670 * Function 0 is required unless we are running on 2671 * a hypervisor that passes through individual PCI 2672 * functions. 2673 */ 2674 if (!hypervisor_isolated_pci_functions()) 2675 break; 2676 } 2677 fn = next_fn(bus, dev, fn); 2678 } while (fn >= 0); 2679 2680 /* Only one slot has PCIe device */ 2681 if (bus->self && nr) 2682 pcie_aspm_init_link_state(bus->self); 2683 2684 return nr; 2685 } 2686 EXPORT_SYMBOL(pci_scan_slot); 2687 2688 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2689 { 2690 u8 *smpss = data; 2691 2692 if (!pci_is_pcie(dev)) 2693 return 0; 2694 2695 /* 2696 * We don't have a way to change MPS settings on devices that have 2697 * drivers attached. A hot-added device might support only the minimum 2698 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2699 * where devices may be hot-added, we limit the fabric MPS to 128 so 2700 * hot-added devices will work correctly. 2701 * 2702 * However, if we hot-add a device to a slot directly below a Root 2703 * Port, it's impossible for there to be other existing devices below 2704 * the port. We don't limit the MPS in this case because we can 2705 * reconfigure MPS on both the Root Port and the hot-added device, 2706 * and there are no other devices involved. 2707 * 2708 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2709 */ 2710 if (dev->is_hotplug_bridge && 2711 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2712 *smpss = 0; 2713 2714 if (*smpss > dev->pcie_mpss) 2715 *smpss = dev->pcie_mpss; 2716 2717 return 0; 2718 } 2719 2720 static void pcie_write_mps(struct pci_dev *dev, int mps) 2721 { 2722 int rc; 2723 2724 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2725 mps = 128 << dev->pcie_mpss; 2726 2727 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2728 dev->bus->self) 2729 2730 /* 2731 * For "Performance", the assumption is made that 2732 * downstream communication will never be larger than 2733 * the MRRS. So, the MPS only needs to be configured 2734 * for the upstream communication. This being the case, 2735 * walk from the top down and set the MPS of the child 2736 * to that of the parent bus. 2737 * 2738 * Configure the device MPS with the smaller of the 2739 * device MPSS or the bridge MPS (which is assumed to be 2740 * properly configured at this point to the largest 2741 * allowable MPS based on its parent bus). 2742 */ 2743 mps = min(mps, pcie_get_mps(dev->bus->self)); 2744 } 2745 2746 rc = pcie_set_mps(dev, mps); 2747 if (rc) 2748 pci_err(dev, "Failed attempting to set the MPS\n"); 2749 } 2750 2751 static void pcie_write_mrrs(struct pci_dev *dev) 2752 { 2753 int rc, mrrs; 2754 2755 /* 2756 * In the "safe" case, do not configure the MRRS. There appear to be 2757 * issues with setting MRRS to 0 on a number of devices. 2758 */ 2759 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2760 return; 2761 2762 /* 2763 * For max performance, the MRRS must be set to the largest supported 2764 * value. However, it cannot be configured larger than the MPS the 2765 * device or the bus can support. This should already be properly 2766 * configured by a prior call to pcie_write_mps(). 2767 */ 2768 mrrs = pcie_get_mps(dev); 2769 2770 /* 2771 * MRRS is a R/W register. Invalid values can be written, but a 2772 * subsequent read will verify if the value is acceptable or not. 2773 * If the MRRS value provided is not acceptable (e.g., too large), 2774 * shrink the value until it is acceptable to the HW. 2775 */ 2776 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2777 rc = pcie_set_readrq(dev, mrrs); 2778 if (!rc) 2779 break; 2780 2781 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2782 mrrs /= 2; 2783 } 2784 2785 if (mrrs < 128) 2786 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2787 } 2788 2789 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2790 { 2791 int mps, orig_mps; 2792 2793 if (!pci_is_pcie(dev)) 2794 return 0; 2795 2796 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2797 pcie_bus_config == PCIE_BUS_DEFAULT) 2798 return 0; 2799 2800 mps = 128 << *(u8 *)data; 2801 orig_mps = pcie_get_mps(dev); 2802 2803 pcie_write_mps(dev, mps); 2804 pcie_write_mrrs(dev); 2805 2806 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2807 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2808 orig_mps, pcie_get_readrq(dev)); 2809 2810 return 0; 2811 } 2812 2813 /* 2814 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2815 * parents then children fashion. If this changes, then this code will not 2816 * work as designed. 2817 */ 2818 void pcie_bus_configure_settings(struct pci_bus *bus) 2819 { 2820 u8 smpss = 0; 2821 2822 if (!bus->self) 2823 return; 2824 2825 if (!pci_is_pcie(bus->self)) 2826 return; 2827 2828 /* 2829 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2830 * to be aware of the MPS of the destination. To work around this, 2831 * simply force the MPS of the entire system to the smallest possible. 2832 */ 2833 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2834 smpss = 0; 2835 2836 if (pcie_bus_config == PCIE_BUS_SAFE) { 2837 smpss = bus->self->pcie_mpss; 2838 2839 pcie_find_smpss(bus->self, &smpss); 2840 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2841 } 2842 2843 pcie_bus_configure_set(bus->self, &smpss); 2844 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2845 } 2846 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2847 2848 /* 2849 * Called after each bus is probed, but before its children are examined. This 2850 * is marked as __weak because multiple architectures define it. 2851 */ 2852 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2853 { 2854 /* nothing to do, expected to be removed in the future */ 2855 } 2856 2857 /** 2858 * pci_scan_child_bus_extend() - Scan devices below a bus 2859 * @bus: Bus to scan for devices 2860 * @available_buses: Total number of buses available (%0 does not try to 2861 * extend beyond the minimal) 2862 * 2863 * Scans devices below @bus including subordinate buses. Returns new 2864 * subordinate number including all the found devices. Passing 2865 * @available_buses causes the remaining bus space to be distributed 2866 * equally between hotplug-capable bridges to allow future extension of the 2867 * hierarchy. 2868 */ 2869 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2870 unsigned int available_buses) 2871 { 2872 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2873 unsigned int start = bus->busn_res.start; 2874 unsigned int devfn, cmax, max = start; 2875 struct pci_dev *dev; 2876 2877 dev_dbg(&bus->dev, "scanning bus\n"); 2878 2879 /* Go find them, Rover! */ 2880 for (devfn = 0; devfn < 256; devfn += 8) 2881 pci_scan_slot(bus, devfn); 2882 2883 /* Reserve buses for SR-IOV capability */ 2884 used_buses = pci_iov_bus_range(bus); 2885 max += used_buses; 2886 2887 /* 2888 * After performing arch-dependent fixup of the bus, look behind 2889 * all PCI-to-PCI bridges on this bus. 2890 */ 2891 if (!bus->is_added) { 2892 dev_dbg(&bus->dev, "fixups for bus\n"); 2893 pcibios_fixup_bus(bus); 2894 bus->is_added = 1; 2895 } 2896 2897 /* 2898 * Calculate how many hotplug bridges and normal bridges there 2899 * are on this bus. We will distribute the additional available 2900 * buses between hotplug bridges. 2901 */ 2902 for_each_pci_bridge(dev, bus) { 2903 if (dev->is_hotplug_bridge) 2904 hotplug_bridges++; 2905 else 2906 normal_bridges++; 2907 } 2908 2909 /* 2910 * Scan bridges that are already configured. We don't touch them 2911 * unless they are misconfigured (which will be done in the second 2912 * scan below). 2913 */ 2914 for_each_pci_bridge(dev, bus) { 2915 cmax = max; 2916 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2917 2918 /* 2919 * Reserve one bus for each bridge now to avoid extending 2920 * hotplug bridges too much during the second scan below. 2921 */ 2922 used_buses++; 2923 if (cmax - max > 1) 2924 used_buses += cmax - max - 1; 2925 } 2926 2927 /* Scan bridges that need to be reconfigured */ 2928 for_each_pci_bridge(dev, bus) { 2929 unsigned int buses = 0; 2930 2931 if (!hotplug_bridges && normal_bridges == 1) { 2932 2933 /* 2934 * There is only one bridge on the bus (upstream 2935 * port) so it gets all available buses which it 2936 * can then distribute to the possible hotplug 2937 * bridges below. 2938 */ 2939 buses = available_buses; 2940 } else if (dev->is_hotplug_bridge) { 2941 2942 /* 2943 * Distribute the extra buses between hotplug 2944 * bridges if any. 2945 */ 2946 buses = available_buses / hotplug_bridges; 2947 buses = min(buses, available_buses - used_buses + 1); 2948 } 2949 2950 cmax = max; 2951 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2952 /* One bus is already accounted so don't add it again */ 2953 if (max - cmax > 1) 2954 used_buses += max - cmax - 1; 2955 } 2956 2957 /* 2958 * Make sure a hotplug bridge has at least the minimum requested 2959 * number of buses but allow it to grow up to the maximum available 2960 * bus number of there is room. 2961 */ 2962 if (bus->self && bus->self->is_hotplug_bridge) { 2963 used_buses = max_t(unsigned int, available_buses, 2964 pci_hotplug_bus_size - 1); 2965 if (max - start < used_buses) { 2966 max = start + used_buses; 2967 2968 /* Do not allocate more buses than we have room left */ 2969 if (max > bus->busn_res.end) 2970 max = bus->busn_res.end; 2971 2972 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 2973 &bus->busn_res, max - start); 2974 } 2975 } 2976 2977 /* 2978 * We've scanned the bus and so we know all about what's on 2979 * the other side of any bridges that may be on this bus plus 2980 * any devices. 2981 * 2982 * Return how far we've got finding sub-buses. 2983 */ 2984 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 2985 return max; 2986 } 2987 2988 /** 2989 * pci_scan_child_bus() - Scan devices below a bus 2990 * @bus: Bus to scan for devices 2991 * 2992 * Scans devices below @bus including subordinate buses. Returns new 2993 * subordinate number including all the found devices. 2994 */ 2995 unsigned int pci_scan_child_bus(struct pci_bus *bus) 2996 { 2997 return pci_scan_child_bus_extend(bus, 0); 2998 } 2999 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3000 3001 /** 3002 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3003 * @bridge: Host bridge to set up 3004 * 3005 * Default empty implementation. Replace with an architecture-specific setup 3006 * routine, if necessary. 3007 */ 3008 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3009 { 3010 return 0; 3011 } 3012 3013 void __weak pcibios_add_bus(struct pci_bus *bus) 3014 { 3015 } 3016 3017 void __weak pcibios_remove_bus(struct pci_bus *bus) 3018 { 3019 } 3020 3021 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3022 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3023 { 3024 int error; 3025 struct pci_host_bridge *bridge; 3026 3027 bridge = pci_alloc_host_bridge(0); 3028 if (!bridge) 3029 return NULL; 3030 3031 bridge->dev.parent = parent; 3032 3033 list_splice_init(resources, &bridge->windows); 3034 bridge->sysdata = sysdata; 3035 bridge->busnr = bus; 3036 bridge->ops = ops; 3037 3038 error = pci_register_host_bridge(bridge); 3039 if (error < 0) 3040 goto err_out; 3041 3042 return bridge->bus; 3043 3044 err_out: 3045 put_device(&bridge->dev); 3046 return NULL; 3047 } 3048 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3049 3050 int pci_host_probe(struct pci_host_bridge *bridge) 3051 { 3052 struct pci_bus *bus, *child; 3053 int ret; 3054 3055 ret = pci_scan_root_bus_bridge(bridge); 3056 if (ret < 0) { 3057 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3058 return ret; 3059 } 3060 3061 bus = bridge->bus; 3062 3063 /* 3064 * We insert PCI resources into the iomem_resource and 3065 * ioport_resource trees in either pci_bus_claim_resources() 3066 * or pci_bus_assign_resources(). 3067 */ 3068 if (pci_has_flag(PCI_PROBE_ONLY)) { 3069 pci_bus_claim_resources(bus); 3070 } else { 3071 pci_bus_size_bridges(bus); 3072 pci_bus_assign_resources(bus); 3073 3074 list_for_each_entry(child, &bus->children, node) 3075 pcie_bus_configure_settings(child); 3076 } 3077 3078 pci_bus_add_devices(bus); 3079 return 0; 3080 } 3081 EXPORT_SYMBOL_GPL(pci_host_probe); 3082 3083 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3084 { 3085 struct resource *res = &b->busn_res; 3086 struct resource *parent_res, *conflict; 3087 3088 res->start = bus; 3089 res->end = bus_max; 3090 res->flags = IORESOURCE_BUS; 3091 3092 if (!pci_is_root_bus(b)) 3093 parent_res = &b->parent->busn_res; 3094 else { 3095 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3096 res->flags |= IORESOURCE_PCI_FIXED; 3097 } 3098 3099 conflict = request_resource_conflict(parent_res, res); 3100 3101 if (conflict) 3102 dev_info(&b->dev, 3103 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3104 res, pci_is_root_bus(b) ? "domain " : "", 3105 parent_res, conflict->name, conflict); 3106 3107 return conflict == NULL; 3108 } 3109 3110 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3111 { 3112 struct resource *res = &b->busn_res; 3113 struct resource old_res = *res; 3114 resource_size_t size; 3115 int ret; 3116 3117 if (res->start > bus_max) 3118 return -EINVAL; 3119 3120 size = bus_max - res->start + 1; 3121 ret = adjust_resource(res, res->start, size); 3122 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3123 &old_res, ret ? "can not be" : "is", bus_max); 3124 3125 if (!ret && !res->parent) 3126 pci_bus_insert_busn_res(b, res->start, res->end); 3127 3128 return ret; 3129 } 3130 3131 void pci_bus_release_busn_res(struct pci_bus *b) 3132 { 3133 struct resource *res = &b->busn_res; 3134 int ret; 3135 3136 if (!res->flags || !res->parent) 3137 return; 3138 3139 ret = release_resource(res); 3140 dev_info(&b->dev, "busn_res: %pR %s released\n", 3141 res, ret ? "can not be" : "is"); 3142 } 3143 3144 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3145 { 3146 struct resource_entry *window; 3147 bool found = false; 3148 struct pci_bus *b; 3149 int max, bus, ret; 3150 3151 if (!bridge) 3152 return -EINVAL; 3153 3154 resource_list_for_each_entry(window, &bridge->windows) 3155 if (window->res->flags & IORESOURCE_BUS) { 3156 bridge->busnr = window->res->start; 3157 found = true; 3158 break; 3159 } 3160 3161 ret = pci_register_host_bridge(bridge); 3162 if (ret < 0) 3163 return ret; 3164 3165 b = bridge->bus; 3166 bus = bridge->busnr; 3167 3168 if (!found) { 3169 dev_info(&b->dev, 3170 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3171 bus); 3172 pci_bus_insert_busn_res(b, bus, 255); 3173 } 3174 3175 max = pci_scan_child_bus(b); 3176 3177 if (!found) 3178 pci_bus_update_busn_res_end(b, max); 3179 3180 return 0; 3181 } 3182 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3183 3184 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3185 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3186 { 3187 struct resource_entry *window; 3188 bool found = false; 3189 struct pci_bus *b; 3190 int max; 3191 3192 resource_list_for_each_entry(window, resources) 3193 if (window->res->flags & IORESOURCE_BUS) { 3194 found = true; 3195 break; 3196 } 3197 3198 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3199 if (!b) 3200 return NULL; 3201 3202 if (!found) { 3203 dev_info(&b->dev, 3204 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3205 bus); 3206 pci_bus_insert_busn_res(b, bus, 255); 3207 } 3208 3209 max = pci_scan_child_bus(b); 3210 3211 if (!found) 3212 pci_bus_update_busn_res_end(b, max); 3213 3214 return b; 3215 } 3216 EXPORT_SYMBOL(pci_scan_root_bus); 3217 3218 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3219 void *sysdata) 3220 { 3221 LIST_HEAD(resources); 3222 struct pci_bus *b; 3223 3224 pci_add_resource(&resources, &ioport_resource); 3225 pci_add_resource(&resources, &iomem_resource); 3226 pci_add_resource(&resources, &busn_resource); 3227 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3228 if (b) { 3229 pci_scan_child_bus(b); 3230 } else { 3231 pci_free_resource_list(&resources); 3232 } 3233 return b; 3234 } 3235 EXPORT_SYMBOL(pci_scan_bus); 3236 3237 /** 3238 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3239 * @bridge: PCI bridge for the bus to scan 3240 * 3241 * Scan a PCI bus and child buses for new devices, add them, 3242 * and enable them, resizing bridge mmio/io resource if necessary 3243 * and possible. The caller must ensure the child devices are already 3244 * removed for resizing to occur. 3245 * 3246 * Returns the max number of subordinate bus discovered. 3247 */ 3248 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3249 { 3250 unsigned int max; 3251 struct pci_bus *bus = bridge->subordinate; 3252 3253 max = pci_scan_child_bus(bus); 3254 3255 pci_assign_unassigned_bridge_resources(bridge); 3256 3257 pci_bus_add_devices(bus); 3258 3259 return max; 3260 } 3261 3262 /** 3263 * pci_rescan_bus - Scan a PCI bus for devices 3264 * @bus: PCI bus to scan 3265 * 3266 * Scan a PCI bus and child buses for new devices, add them, 3267 * and enable them. 3268 * 3269 * Returns the max number of subordinate bus discovered. 3270 */ 3271 unsigned int pci_rescan_bus(struct pci_bus *bus) 3272 { 3273 unsigned int max; 3274 3275 max = pci_scan_child_bus(bus); 3276 pci_assign_unassigned_bus_resources(bus); 3277 pci_bus_add_devices(bus); 3278 3279 return max; 3280 } 3281 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3282 3283 /* 3284 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3285 * routines should always be executed under this mutex. 3286 */ 3287 static DEFINE_MUTEX(pci_rescan_remove_lock); 3288 3289 void pci_lock_rescan_remove(void) 3290 { 3291 mutex_lock(&pci_rescan_remove_lock); 3292 } 3293 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3294 3295 void pci_unlock_rescan_remove(void) 3296 { 3297 mutex_unlock(&pci_rescan_remove_lock); 3298 } 3299 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3300 3301 static int __init pci_sort_bf_cmp(const struct device *d_a, 3302 const struct device *d_b) 3303 { 3304 const struct pci_dev *a = to_pci_dev(d_a); 3305 const struct pci_dev *b = to_pci_dev(d_b); 3306 3307 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3308 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3309 3310 if (a->bus->number < b->bus->number) return -1; 3311 else if (a->bus->number > b->bus->number) return 1; 3312 3313 if (a->devfn < b->devfn) return -1; 3314 else if (a->devfn > b->devfn) return 1; 3315 3316 return 0; 3317 } 3318 3319 void __init pci_sort_breadthfirst(void) 3320 { 3321 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3322 } 3323 3324 int pci_hp_add_bridge(struct pci_dev *dev) 3325 { 3326 struct pci_bus *parent = dev->bus; 3327 int busnr, start = parent->busn_res.start; 3328 unsigned int available_buses = 0; 3329 int end = parent->busn_res.end; 3330 3331 for (busnr = start; busnr <= end; busnr++) { 3332 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3333 break; 3334 } 3335 if (busnr-- > end) { 3336 pci_err(dev, "No bus number available for hot-added bridge\n"); 3337 return -1; 3338 } 3339 3340 /* Scan bridges that are already configured */ 3341 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3342 3343 /* 3344 * Distribute the available bus numbers between hotplug-capable 3345 * bridges to make extending the chain later possible. 3346 */ 3347 available_buses = end - busnr; 3348 3349 /* Scan bridges that need to be reconfigured */ 3350 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3351 3352 if (!dev->subordinate) 3353 return -1; 3354 3355 return 0; 3356 } 3357 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3358