1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_pci.h> 12 #include <linux/pci_hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/cpumask.h> 16 #include <linux/aer.h> 17 #include <linux/acpi.h> 18 #include <linux/hypervisor.h> 19 #include <linux/irqdomain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/bitfield.h> 22 #include "pci.h" 23 24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 25 #define CARDBUS_RESERVE_BUSNR 3 26 27 static struct resource busn_resource = { 28 .name = "PCI busn", 29 .start = 0, 30 .end = 255, 31 .flags = IORESOURCE_BUS, 32 }; 33 34 /* Ugh. Need to stop exporting this to modules. */ 35 LIST_HEAD(pci_root_buses); 36 EXPORT_SYMBOL(pci_root_buses); 37 38 static LIST_HEAD(pci_domain_busn_res_list); 39 40 struct pci_domain_busn_res { 41 struct list_head list; 42 struct resource res; 43 int domain_nr; 44 }; 45 46 static struct resource *get_pci_domain_busn_res(int domain_nr) 47 { 48 struct pci_domain_busn_res *r; 49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list) 51 if (r->domain_nr == domain_nr) 52 return &r->res; 53 54 r = kzalloc(sizeof(*r), GFP_KERNEL); 55 if (!r) 56 return NULL; 57 58 r->domain_nr = domain_nr; 59 r->res.start = 0; 60 r->res.end = 0xff; 61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 62 63 list_add_tail(&r->list, &pci_domain_busn_res_list); 64 65 return &r->res; 66 } 67 68 /* 69 * Some device drivers need know if PCI is initiated. 70 * Basically, we think PCI is not initiated when there 71 * is no device to be found on the pci_bus_type. 72 */ 73 int no_pci_devices(void) 74 { 75 struct device *dev; 76 int no_devices; 77 78 dev = bus_find_next_device(&pci_bus_type, NULL); 79 no_devices = (dev == NULL); 80 put_device(dev); 81 return no_devices; 82 } 83 EXPORT_SYMBOL(no_pci_devices); 84 85 /* 86 * PCI Bus Class 87 */ 88 static void release_pcibus_dev(struct device *dev) 89 { 90 struct pci_bus *pci_bus = to_pci_bus(dev); 91 92 put_device(pci_bus->bridge); 93 pci_bus_remove_resources(pci_bus); 94 pci_release_bus_of_node(pci_bus); 95 kfree(pci_bus); 96 } 97 98 static const struct class pcibus_class = { 99 .name = "pci_bus", 100 .dev_release = &release_pcibus_dev, 101 .dev_groups = pcibus_groups, 102 }; 103 104 static int __init pcibus_class_init(void) 105 { 106 return class_register(&pcibus_class); 107 } 108 postcore_initcall(pcibus_class_init); 109 110 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 111 { 112 u64 size = mask & maxbase; /* Find the significant bits */ 113 if (!size) 114 return 0; 115 116 /* 117 * Get the lowest of them to find the decode size, and from that 118 * the extent. 119 */ 120 size = size & ~(size-1); 121 122 /* 123 * base == maxbase can be valid only if the BAR has already been 124 * programmed with all 1s. 125 */ 126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 127 return 0; 128 129 return size; 130 } 131 132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 133 { 134 u32 mem_type; 135 unsigned long flags; 136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 139 flags |= IORESOURCE_IO; 140 return flags; 141 } 142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 144 flags |= IORESOURCE_MEM; 145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 146 flags |= IORESOURCE_PREFETCH; 147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 149 switch (mem_type) { 150 case PCI_BASE_ADDRESS_MEM_TYPE_32: 151 break; 152 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 153 /* 1M mem BAR treated as 32-bit BAR */ 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_64: 156 flags |= IORESOURCE_MEM_64; 157 break; 158 default: 159 /* mem unknown type treated as 32-bit BAR */ 160 break; 161 } 162 return flags; 163 } 164 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 167 /** 168 * __pci_read_base - Read a PCI BAR 169 * @dev: the PCI device 170 * @type: type of the BAR 171 * @res: resource buffer to be filled in 172 * @pos: BAR position in the config space 173 * 174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 175 */ 176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 177 struct resource *res, unsigned int pos) 178 { 179 u32 l = 0, sz = 0, mask; 180 u64 l64, sz64, mask64; 181 u16 orig_cmd; 182 struct pci_bus_region region, inverted_region; 183 const char *res_name = pci_resource_name(dev, res - dev->resource); 184 185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 186 187 /* No printks while decoding is disabled! */ 188 if (!dev->mmio_always_on) { 189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 191 pci_write_config_word(dev, PCI_COMMAND, 192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 193 } 194 } 195 196 res->name = pci_name(dev); 197 198 pci_read_config_dword(dev, pos, &l); 199 pci_write_config_dword(dev, pos, l | mask); 200 pci_read_config_dword(dev, pos, &sz); 201 pci_write_config_dword(dev, pos, l); 202 203 /* 204 * All bits set in sz means the device isn't working properly. 205 * If the BAR isn't implemented, all bits must be 0. If it's a 206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 207 * 1 must be clear. 208 */ 209 if (PCI_POSSIBLE_ERROR(sz)) 210 sz = 0; 211 212 /* 213 * I don't know how l can have all bits set. Copied from old code. 214 * Maybe it fixes a bug on some ancient platform. 215 */ 216 if (PCI_POSSIBLE_ERROR(l)) 217 l = 0; 218 219 if (type == pci_bar_unknown) { 220 res->flags = decode_bar(dev, l); 221 res->flags |= IORESOURCE_SIZEALIGN; 222 if (res->flags & IORESOURCE_IO) { 223 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 226 } else { 227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 230 } 231 } else { 232 if (l & PCI_ROM_ADDRESS_ENABLE) 233 res->flags |= IORESOURCE_ROM_ENABLE; 234 l64 = l & PCI_ROM_ADDRESS_MASK; 235 sz64 = sz & PCI_ROM_ADDRESS_MASK; 236 mask64 = PCI_ROM_ADDRESS_MASK; 237 } 238 239 if (res->flags & IORESOURCE_MEM_64) { 240 pci_read_config_dword(dev, pos + 4, &l); 241 pci_write_config_dword(dev, pos + 4, ~0); 242 pci_read_config_dword(dev, pos + 4, &sz); 243 pci_write_config_dword(dev, pos + 4, l); 244 245 l64 |= ((u64)l << 32); 246 sz64 |= ((u64)sz << 32); 247 mask64 |= ((u64)~0 << 32); 248 } 249 250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 252 253 if (!sz64) 254 goto fail; 255 256 sz64 = pci_size(l64, sz64, mask64); 257 if (!sz64) { 258 pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name); 259 goto fail; 260 } 261 262 if (res->flags & IORESOURCE_MEM_64) { 263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 264 && sz64 > 0x100000000ULL) { 265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 266 res->start = 0; 267 res->end = 0; 268 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n", 269 res_name, (unsigned long long)sz64); 270 goto out; 271 } 272 273 if ((sizeof(pci_bus_addr_t) < 8) && l) { 274 /* Above 32-bit boundary; try to reallocate */ 275 res->flags |= IORESOURCE_UNSET; 276 res->start = 0; 277 res->end = sz64 - 1; 278 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n", 279 res_name, (unsigned long long)l64); 280 goto out; 281 } 282 } 283 284 region.start = l64; 285 region.end = l64 + sz64 - 1; 286 287 pcibios_bus_to_resource(dev->bus, res, ®ion); 288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 289 290 /* 291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 292 * the corresponding resource address (the physical address used by 293 * the CPU. Converting that resource address back to a bus address 294 * should yield the original BAR value: 295 * 296 * resource_to_bus(bus_to_resource(A)) == A 297 * 298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 299 * be claimed by the device. 300 */ 301 if (inverted_region.start != region.start) { 302 res->flags |= IORESOURCE_UNSET; 303 res->start = 0; 304 res->end = region.end - region.start; 305 pci_info(dev, "%s: initial BAR value %#010llx invalid\n", 306 res_name, (unsigned long long)region.start); 307 } 308 309 goto out; 310 311 312 fail: 313 res->flags = 0; 314 out: 315 if (res->flags) 316 pci_info(dev, "%s %pR\n", res_name, res); 317 318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 319 } 320 321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 322 { 323 unsigned int pos, reg; 324 325 if (dev->non_compliant_bars) 326 return; 327 328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 329 if (dev->is_virtfn) 330 return; 331 332 for (pos = 0; pos < howmany; pos++) { 333 struct resource *res = &dev->resource[pos]; 334 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 336 } 337 338 if (rom) { 339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 340 dev->rom_base_reg = rom; 341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 343 __pci_read_base(dev, pci_bar_mem32, res, rom); 344 } 345 } 346 347 static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res, 348 bool log) 349 { 350 u8 io_base_lo, io_limit_lo; 351 unsigned long io_mask, io_granularity, base, limit; 352 struct pci_bus_region region; 353 354 io_mask = PCI_IO_RANGE_MASK; 355 io_granularity = 0x1000; 356 if (dev->io_window_1k) { 357 /* Support 1K I/O space granularity */ 358 io_mask = PCI_IO_1K_RANGE_MASK; 359 io_granularity = 0x400; 360 } 361 362 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 363 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 364 base = (io_base_lo & io_mask) << 8; 365 limit = (io_limit_lo & io_mask) << 8; 366 367 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 368 u16 io_base_hi, io_limit_hi; 369 370 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 371 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 372 base |= ((unsigned long) io_base_hi << 16); 373 limit |= ((unsigned long) io_limit_hi << 16); 374 } 375 376 if (base <= limit) { 377 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 378 region.start = base; 379 region.end = limit + io_granularity - 1; 380 pcibios_bus_to_resource(dev->bus, res, ®ion); 381 if (log) 382 pci_info(dev, " bridge window %pR\n", res); 383 } 384 } 385 386 static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res, 387 bool log) 388 { 389 u16 mem_base_lo, mem_limit_lo; 390 unsigned long base, limit; 391 struct pci_bus_region region; 392 393 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 394 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 395 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 396 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 397 if (base <= limit) { 398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 399 region.start = base; 400 region.end = limit + 0xfffff; 401 pcibios_bus_to_resource(dev->bus, res, ®ion); 402 if (log) 403 pci_info(dev, " bridge window %pR\n", res); 404 } 405 } 406 407 static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res, 408 bool log) 409 { 410 u16 mem_base_lo, mem_limit_lo; 411 u64 base64, limit64; 412 pci_bus_addr_t base, limit; 413 struct pci_bus_region region; 414 415 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 416 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 417 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 418 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 419 420 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 421 u32 mem_base_hi, mem_limit_hi; 422 423 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 424 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 425 426 /* 427 * Some bridges set the base > limit by default, and some 428 * (broken) BIOSes do not initialize them. If we find 429 * this, just assume they are not being used. 430 */ 431 if (mem_base_hi <= mem_limit_hi) { 432 base64 |= (u64) mem_base_hi << 32; 433 limit64 |= (u64) mem_limit_hi << 32; 434 } 435 } 436 437 base = (pci_bus_addr_t) base64; 438 limit = (pci_bus_addr_t) limit64; 439 440 if (base != base64) { 441 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 442 (unsigned long long) base64); 443 return; 444 } 445 446 if (base <= limit) { 447 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 448 IORESOURCE_MEM | IORESOURCE_PREFETCH; 449 if (res->flags & PCI_PREF_RANGE_TYPE_64) 450 res->flags |= IORESOURCE_MEM_64; 451 region.start = base; 452 region.end = limit + 0xfffff; 453 pcibios_bus_to_resource(dev->bus, res, ®ion); 454 if (log) 455 pci_info(dev, " bridge window %pR\n", res); 456 } 457 } 458 459 static void pci_read_bridge_windows(struct pci_dev *bridge) 460 { 461 u32 buses; 462 u16 io; 463 u32 pmem, tmp; 464 struct resource res; 465 466 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses); 467 res.flags = IORESOURCE_BUS; 468 res.start = (buses >> 8) & 0xff; 469 res.end = (buses >> 16) & 0xff; 470 pci_info(bridge, "PCI bridge to %pR%s\n", &res, 471 bridge->transparent ? " (subtractive decode)" : ""); 472 473 pci_read_config_word(bridge, PCI_IO_BASE, &io); 474 if (!io) { 475 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 476 pci_read_config_word(bridge, PCI_IO_BASE, &io); 477 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 478 } 479 if (io) { 480 bridge->io_window = 1; 481 pci_read_bridge_io(bridge, &res, true); 482 } 483 484 pci_read_bridge_mmio(bridge, &res, true); 485 486 /* 487 * DECchip 21050 pass 2 errata: the bridge may miss an address 488 * disconnect boundary by one PCI data phase. Workaround: do not 489 * use prefetching on this device. 490 */ 491 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 492 return; 493 494 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 495 if (!pmem) { 496 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 497 0xffe0fff0); 498 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 499 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 500 } 501 if (!pmem) 502 return; 503 504 bridge->pref_window = 1; 505 506 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 507 508 /* 509 * Bridge claims to have a 64-bit prefetchable memory 510 * window; verify that the upper bits are actually 511 * writable. 512 */ 513 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 514 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 515 0xffffffff); 516 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 517 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 518 if (tmp) 519 bridge->pref_64_window = 1; 520 } 521 522 pci_read_bridge_mmio_pref(bridge, &res, true); 523 } 524 525 void pci_read_bridge_bases(struct pci_bus *child) 526 { 527 struct pci_dev *dev = child->self; 528 struct resource *res; 529 int i; 530 531 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 532 return; 533 534 pci_info(dev, "PCI bridge to %pR%s\n", 535 &child->busn_res, 536 dev->transparent ? " (subtractive decode)" : ""); 537 538 pci_bus_remove_resources(child); 539 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 540 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 541 542 pci_read_bridge_io(child->self, child->resource[0], false); 543 pci_read_bridge_mmio(child->self, child->resource[1], false); 544 pci_read_bridge_mmio_pref(child->self, child->resource[2], false); 545 546 if (dev->transparent) { 547 pci_bus_for_each_resource(child->parent, res) { 548 if (res && res->flags) { 549 pci_bus_add_resource(child, res, 550 PCI_SUBTRACTIVE_DECODE); 551 pci_info(dev, " bridge window %pR (subtractive decode)\n", 552 res); 553 } 554 } 555 } 556 } 557 558 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 559 { 560 struct pci_bus *b; 561 562 b = kzalloc(sizeof(*b), GFP_KERNEL); 563 if (!b) 564 return NULL; 565 566 INIT_LIST_HEAD(&b->node); 567 INIT_LIST_HEAD(&b->children); 568 INIT_LIST_HEAD(&b->devices); 569 INIT_LIST_HEAD(&b->slots); 570 INIT_LIST_HEAD(&b->resources); 571 b->max_bus_speed = PCI_SPEED_UNKNOWN; 572 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 573 #ifdef CONFIG_PCI_DOMAINS_GENERIC 574 if (parent) 575 b->domain_nr = parent->domain_nr; 576 #endif 577 return b; 578 } 579 580 static void pci_release_host_bridge_dev(struct device *dev) 581 { 582 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 583 584 if (bridge->release_fn) 585 bridge->release_fn(bridge); 586 587 pci_free_resource_list(&bridge->windows); 588 pci_free_resource_list(&bridge->dma_ranges); 589 kfree(bridge); 590 } 591 592 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 593 { 594 INIT_LIST_HEAD(&bridge->windows); 595 INIT_LIST_HEAD(&bridge->dma_ranges); 596 597 /* 598 * We assume we can manage these PCIe features. Some systems may 599 * reserve these for use by the platform itself, e.g., an ACPI BIOS 600 * may implement its own AER handling and use _OSC to prevent the 601 * OS from interfering. 602 */ 603 bridge->native_aer = 1; 604 bridge->native_pcie_hotplug = 1; 605 bridge->native_shpc_hotplug = 1; 606 bridge->native_pme = 1; 607 bridge->native_ltr = 1; 608 bridge->native_dpc = 1; 609 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 610 bridge->native_cxl_error = 1; 611 612 device_initialize(&bridge->dev); 613 } 614 615 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 616 { 617 struct pci_host_bridge *bridge; 618 619 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 620 if (!bridge) 621 return NULL; 622 623 pci_init_host_bridge(bridge); 624 bridge->dev.release = pci_release_host_bridge_dev; 625 626 return bridge; 627 } 628 EXPORT_SYMBOL(pci_alloc_host_bridge); 629 630 static void devm_pci_alloc_host_bridge_release(void *data) 631 { 632 pci_free_host_bridge(data); 633 } 634 635 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 636 size_t priv) 637 { 638 int ret; 639 struct pci_host_bridge *bridge; 640 641 bridge = pci_alloc_host_bridge(priv); 642 if (!bridge) 643 return NULL; 644 645 bridge->dev.parent = dev; 646 647 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 648 bridge); 649 if (ret) 650 return NULL; 651 652 ret = devm_of_pci_bridge_init(dev, bridge); 653 if (ret) 654 return NULL; 655 656 return bridge; 657 } 658 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 659 660 void pci_free_host_bridge(struct pci_host_bridge *bridge) 661 { 662 put_device(&bridge->dev); 663 } 664 EXPORT_SYMBOL(pci_free_host_bridge); 665 666 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 667 static const unsigned char pcix_bus_speed[] = { 668 PCI_SPEED_UNKNOWN, /* 0 */ 669 PCI_SPEED_66MHz_PCIX, /* 1 */ 670 PCI_SPEED_100MHz_PCIX, /* 2 */ 671 PCI_SPEED_133MHz_PCIX, /* 3 */ 672 PCI_SPEED_UNKNOWN, /* 4 */ 673 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 674 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 675 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 676 PCI_SPEED_UNKNOWN, /* 8 */ 677 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 678 PCI_SPEED_100MHz_PCIX_266, /* A */ 679 PCI_SPEED_133MHz_PCIX_266, /* B */ 680 PCI_SPEED_UNKNOWN, /* C */ 681 PCI_SPEED_66MHz_PCIX_533, /* D */ 682 PCI_SPEED_100MHz_PCIX_533, /* E */ 683 PCI_SPEED_133MHz_PCIX_533 /* F */ 684 }; 685 686 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 687 const unsigned char pcie_link_speed[] = { 688 PCI_SPEED_UNKNOWN, /* 0 */ 689 PCIE_SPEED_2_5GT, /* 1 */ 690 PCIE_SPEED_5_0GT, /* 2 */ 691 PCIE_SPEED_8_0GT, /* 3 */ 692 PCIE_SPEED_16_0GT, /* 4 */ 693 PCIE_SPEED_32_0GT, /* 5 */ 694 PCIE_SPEED_64_0GT, /* 6 */ 695 PCI_SPEED_UNKNOWN, /* 7 */ 696 PCI_SPEED_UNKNOWN, /* 8 */ 697 PCI_SPEED_UNKNOWN, /* 9 */ 698 PCI_SPEED_UNKNOWN, /* A */ 699 PCI_SPEED_UNKNOWN, /* B */ 700 PCI_SPEED_UNKNOWN, /* C */ 701 PCI_SPEED_UNKNOWN, /* D */ 702 PCI_SPEED_UNKNOWN, /* E */ 703 PCI_SPEED_UNKNOWN /* F */ 704 }; 705 EXPORT_SYMBOL_GPL(pcie_link_speed); 706 707 const char *pci_speed_string(enum pci_bus_speed speed) 708 { 709 /* Indexed by the pci_bus_speed enum */ 710 static const char *speed_strings[] = { 711 "33 MHz PCI", /* 0x00 */ 712 "66 MHz PCI", /* 0x01 */ 713 "66 MHz PCI-X", /* 0x02 */ 714 "100 MHz PCI-X", /* 0x03 */ 715 "133 MHz PCI-X", /* 0x04 */ 716 NULL, /* 0x05 */ 717 NULL, /* 0x06 */ 718 NULL, /* 0x07 */ 719 NULL, /* 0x08 */ 720 "66 MHz PCI-X 266", /* 0x09 */ 721 "100 MHz PCI-X 266", /* 0x0a */ 722 "133 MHz PCI-X 266", /* 0x0b */ 723 "Unknown AGP", /* 0x0c */ 724 "1x AGP", /* 0x0d */ 725 "2x AGP", /* 0x0e */ 726 "4x AGP", /* 0x0f */ 727 "8x AGP", /* 0x10 */ 728 "66 MHz PCI-X 533", /* 0x11 */ 729 "100 MHz PCI-X 533", /* 0x12 */ 730 "133 MHz PCI-X 533", /* 0x13 */ 731 "2.5 GT/s PCIe", /* 0x14 */ 732 "5.0 GT/s PCIe", /* 0x15 */ 733 "8.0 GT/s PCIe", /* 0x16 */ 734 "16.0 GT/s PCIe", /* 0x17 */ 735 "32.0 GT/s PCIe", /* 0x18 */ 736 "64.0 GT/s PCIe", /* 0x19 */ 737 }; 738 739 if (speed < ARRAY_SIZE(speed_strings)) 740 return speed_strings[speed]; 741 return "Unknown"; 742 } 743 EXPORT_SYMBOL_GPL(pci_speed_string); 744 745 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 746 { 747 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 748 } 749 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 750 751 static unsigned char agp_speeds[] = { 752 AGP_UNKNOWN, 753 AGP_1X, 754 AGP_2X, 755 AGP_4X, 756 AGP_8X 757 }; 758 759 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 760 { 761 int index = 0; 762 763 if (agpstat & 4) 764 index = 3; 765 else if (agpstat & 2) 766 index = 2; 767 else if (agpstat & 1) 768 index = 1; 769 else 770 goto out; 771 772 if (agp3) { 773 index += 2; 774 if (index == 5) 775 index = 0; 776 } 777 778 out: 779 return agp_speeds[index]; 780 } 781 782 static void pci_set_bus_speed(struct pci_bus *bus) 783 { 784 struct pci_dev *bridge = bus->self; 785 int pos; 786 787 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 788 if (!pos) 789 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 790 if (pos) { 791 u32 agpstat, agpcmd; 792 793 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 794 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 795 796 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 797 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 798 } 799 800 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 801 if (pos) { 802 u16 status; 803 enum pci_bus_speed max; 804 805 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 806 &status); 807 808 if (status & PCI_X_SSTATUS_533MHZ) { 809 max = PCI_SPEED_133MHz_PCIX_533; 810 } else if (status & PCI_X_SSTATUS_266MHZ) { 811 max = PCI_SPEED_133MHz_PCIX_266; 812 } else if (status & PCI_X_SSTATUS_133MHZ) { 813 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 814 max = PCI_SPEED_133MHz_PCIX_ECC; 815 else 816 max = PCI_SPEED_133MHz_PCIX; 817 } else { 818 max = PCI_SPEED_66MHz_PCIX; 819 } 820 821 bus->max_bus_speed = max; 822 bus->cur_bus_speed = 823 pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)]; 824 825 return; 826 } 827 828 if (pci_is_pcie(bridge)) { 829 u32 linkcap; 830 u16 linksta; 831 832 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 833 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 834 835 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 836 pcie_update_link_speed(bus, linksta); 837 } 838 } 839 840 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 841 { 842 struct irq_domain *d; 843 844 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 845 d = dev_get_msi_domain(bus->bridge); 846 847 /* 848 * Any firmware interface that can resolve the msi_domain 849 * should be called from here. 850 */ 851 if (!d) 852 d = pci_host_bridge_of_msi_domain(bus); 853 if (!d) 854 d = pci_host_bridge_acpi_msi_domain(bus); 855 856 /* 857 * If no IRQ domain was found via the OF tree, try looking it up 858 * directly through the fwnode_handle. 859 */ 860 if (!d) { 861 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 862 863 if (fwnode) 864 d = irq_find_matching_fwnode(fwnode, 865 DOMAIN_BUS_PCI_MSI); 866 } 867 868 return d; 869 } 870 871 static void pci_set_bus_msi_domain(struct pci_bus *bus) 872 { 873 struct irq_domain *d; 874 struct pci_bus *b; 875 876 /* 877 * The bus can be a root bus, a subordinate bus, or a virtual bus 878 * created by an SR-IOV device. Walk up to the first bridge device 879 * found or derive the domain from the host bridge. 880 */ 881 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 882 if (b->self) 883 d = dev_get_msi_domain(&b->self->dev); 884 } 885 886 if (!d) 887 d = pci_host_bridge_msi_domain(b); 888 889 dev_set_msi_domain(&bus->dev, d); 890 } 891 892 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 893 { 894 struct device *parent = bridge->dev.parent; 895 struct resource_entry *window, *next, *n; 896 struct pci_bus *bus, *b; 897 resource_size_t offset, next_offset; 898 LIST_HEAD(resources); 899 struct resource *res, *next_res; 900 char addr[64], *fmt; 901 const char *name; 902 int err; 903 904 bus = pci_alloc_bus(NULL); 905 if (!bus) 906 return -ENOMEM; 907 908 bridge->bus = bus; 909 910 bus->sysdata = bridge->sysdata; 911 bus->ops = bridge->ops; 912 bus->number = bus->busn_res.start = bridge->busnr; 913 #ifdef CONFIG_PCI_DOMAINS_GENERIC 914 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 915 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 916 else 917 bus->domain_nr = bridge->domain_nr; 918 if (bus->domain_nr < 0) { 919 err = bus->domain_nr; 920 goto free; 921 } 922 #endif 923 924 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 925 if (b) { 926 /* Ignore it if we already got here via a different bridge */ 927 dev_dbg(&b->dev, "bus already known\n"); 928 err = -EEXIST; 929 goto free; 930 } 931 932 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 933 bridge->busnr); 934 935 err = pcibios_root_bridge_prepare(bridge); 936 if (err) 937 goto free; 938 939 /* Temporarily move resources off the list */ 940 list_splice_init(&bridge->windows, &resources); 941 err = device_add(&bridge->dev); 942 if (err) { 943 put_device(&bridge->dev); 944 goto free; 945 } 946 bus->bridge = get_device(&bridge->dev); 947 device_enable_async_suspend(bus->bridge); 948 pci_set_bus_of_node(bus); 949 pci_set_bus_msi_domain(bus); 950 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 951 !pci_host_of_has_msi_map(parent)) 952 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 953 954 if (!parent) 955 set_dev_node(bus->bridge, pcibus_to_node(bus)); 956 957 bus->dev.class = &pcibus_class; 958 bus->dev.parent = bus->bridge; 959 960 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 961 name = dev_name(&bus->dev); 962 963 err = device_register(&bus->dev); 964 if (err) 965 goto unregister; 966 967 pcibios_add_bus(bus); 968 969 if (bus->ops->add_bus) { 970 err = bus->ops->add_bus(bus); 971 if (WARN_ON(err < 0)) 972 dev_err(&bus->dev, "failed to add bus: %d\n", err); 973 } 974 975 /* Create legacy_io and legacy_mem files for this bus */ 976 pci_create_legacy_files(bus); 977 978 if (parent) 979 dev_info(parent, "PCI host bridge to bus %s\n", name); 980 else 981 pr_info("PCI host bridge to bus %s\n", name); 982 983 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 984 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 985 986 /* Coalesce contiguous windows */ 987 resource_list_for_each_entry_safe(window, n, &resources) { 988 if (list_is_last(&window->node, &resources)) 989 break; 990 991 next = list_next_entry(window, node); 992 offset = window->offset; 993 res = window->res; 994 next_offset = next->offset; 995 next_res = next->res; 996 997 if (res->flags != next_res->flags || offset != next_offset) 998 continue; 999 1000 if (res->end + 1 == next_res->start) { 1001 next_res->start = res->start; 1002 res->flags = res->start = res->end = 0; 1003 } 1004 } 1005 1006 /* Add initial resources to the bus */ 1007 resource_list_for_each_entry_safe(window, n, &resources) { 1008 offset = window->offset; 1009 res = window->res; 1010 if (!res->flags && !res->start && !res->end) { 1011 release_resource(res); 1012 resource_list_destroy_entry(window); 1013 continue; 1014 } 1015 1016 list_move_tail(&window->node, &bridge->windows); 1017 1018 if (res->flags & IORESOURCE_BUS) 1019 pci_bus_insert_busn_res(bus, bus->number, res->end); 1020 else 1021 pci_bus_add_resource(bus, res, 0); 1022 1023 if (offset) { 1024 if (resource_type(res) == IORESOURCE_IO) 1025 fmt = " (bus address [%#06llx-%#06llx])"; 1026 else 1027 fmt = " (bus address [%#010llx-%#010llx])"; 1028 1029 snprintf(addr, sizeof(addr), fmt, 1030 (unsigned long long)(res->start - offset), 1031 (unsigned long long)(res->end - offset)); 1032 } else 1033 addr[0] = '\0'; 1034 1035 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 1036 } 1037 1038 down_write(&pci_bus_sem); 1039 list_add_tail(&bus->node, &pci_root_buses); 1040 up_write(&pci_bus_sem); 1041 1042 return 0; 1043 1044 unregister: 1045 put_device(&bridge->dev); 1046 device_del(&bridge->dev); 1047 1048 free: 1049 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1050 pci_bus_release_domain_nr(bus, parent); 1051 #endif 1052 kfree(bus); 1053 return err; 1054 } 1055 1056 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1057 { 1058 int pos; 1059 u32 status; 1060 1061 /* 1062 * If extended config space isn't accessible on a bridge's primary 1063 * bus, we certainly can't access it on the secondary bus. 1064 */ 1065 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1066 return false; 1067 1068 /* 1069 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1070 * extended config space is accessible on the primary, it's also 1071 * accessible on the secondary. 1072 */ 1073 if (pci_is_pcie(bridge) && 1074 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1075 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1076 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1077 return true; 1078 1079 /* 1080 * For the other bridge types: 1081 * - PCI-to-PCI bridges 1082 * - PCIe-to-PCI/PCI-X forward bridges 1083 * - PCI/PCI-X-to-PCIe reverse bridges 1084 * extended config space on the secondary side is only accessible 1085 * if the bridge supports PCI-X Mode 2. 1086 */ 1087 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1088 if (!pos) 1089 return false; 1090 1091 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1092 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1093 } 1094 1095 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1096 struct pci_dev *bridge, int busnr) 1097 { 1098 struct pci_bus *child; 1099 struct pci_host_bridge *host; 1100 int i; 1101 int ret; 1102 1103 /* Allocate a new bus and inherit stuff from the parent */ 1104 child = pci_alloc_bus(parent); 1105 if (!child) 1106 return NULL; 1107 1108 child->parent = parent; 1109 child->sysdata = parent->sysdata; 1110 child->bus_flags = parent->bus_flags; 1111 1112 host = pci_find_host_bridge(parent); 1113 if (host->child_ops) 1114 child->ops = host->child_ops; 1115 else 1116 child->ops = parent->ops; 1117 1118 /* 1119 * Initialize some portions of the bus device, but don't register 1120 * it now as the parent is not properly set up yet. 1121 */ 1122 child->dev.class = &pcibus_class; 1123 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1124 1125 /* Set up the primary, secondary and subordinate bus numbers */ 1126 child->number = child->busn_res.start = busnr; 1127 child->primary = parent->busn_res.start; 1128 child->busn_res.end = 0xff; 1129 1130 if (!bridge) { 1131 child->dev.parent = parent->bridge; 1132 goto add_dev; 1133 } 1134 1135 child->self = bridge; 1136 child->bridge = get_device(&bridge->dev); 1137 child->dev.parent = child->bridge; 1138 pci_set_bus_of_node(child); 1139 pci_set_bus_speed(child); 1140 1141 /* 1142 * Check whether extended config space is accessible on the child 1143 * bus. Note that we currently assume it is always accessible on 1144 * the root bus. 1145 */ 1146 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1147 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1148 pci_info(child, "extended config space not accessible\n"); 1149 } 1150 1151 /* Set up default resource pointers and names */ 1152 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1153 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1154 child->resource[i]->name = child->name; 1155 } 1156 bridge->subordinate = child; 1157 1158 add_dev: 1159 pci_set_bus_msi_domain(child); 1160 ret = device_register(&child->dev); 1161 WARN_ON(ret < 0); 1162 1163 pcibios_add_bus(child); 1164 1165 if (child->ops->add_bus) { 1166 ret = child->ops->add_bus(child); 1167 if (WARN_ON(ret < 0)) 1168 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1169 } 1170 1171 /* Create legacy_io and legacy_mem files for this bus */ 1172 pci_create_legacy_files(child); 1173 1174 return child; 1175 } 1176 1177 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1178 int busnr) 1179 { 1180 struct pci_bus *child; 1181 1182 child = pci_alloc_child_bus(parent, dev, busnr); 1183 if (child) { 1184 down_write(&pci_bus_sem); 1185 list_add_tail(&child->node, &parent->children); 1186 up_write(&pci_bus_sem); 1187 } 1188 return child; 1189 } 1190 EXPORT_SYMBOL(pci_add_new_bus); 1191 1192 static void pci_enable_crs(struct pci_dev *pdev) 1193 { 1194 u16 root_cap = 0; 1195 1196 /* Enable CRS Software Visibility if supported */ 1197 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1198 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1199 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1200 PCI_EXP_RTCTL_CRSSVE); 1201 } 1202 1203 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1204 unsigned int available_buses); 1205 /** 1206 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1207 * numbers from EA capability. 1208 * @dev: Bridge 1209 * @sec: updated with secondary bus number from EA 1210 * @sub: updated with subordinate bus number from EA 1211 * 1212 * If @dev is a bridge with EA capability that specifies valid secondary 1213 * and subordinate bus numbers, return true with the bus numbers in @sec 1214 * and @sub. Otherwise return false. 1215 */ 1216 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1217 { 1218 int ea, offset; 1219 u32 dw; 1220 u8 ea_sec, ea_sub; 1221 1222 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1223 return false; 1224 1225 /* find PCI EA capability in list */ 1226 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1227 if (!ea) 1228 return false; 1229 1230 offset = ea + PCI_EA_FIRST_ENT; 1231 pci_read_config_dword(dev, offset, &dw); 1232 ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw); 1233 ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw); 1234 if (ea_sec == 0 || ea_sub < ea_sec) 1235 return false; 1236 1237 *sec = ea_sec; 1238 *sub = ea_sub; 1239 return true; 1240 } 1241 1242 /* 1243 * pci_scan_bridge_extend() - Scan buses behind a bridge 1244 * @bus: Parent bus the bridge is on 1245 * @dev: Bridge itself 1246 * @max: Starting subordinate number of buses behind this bridge 1247 * @available_buses: Total number of buses available for this bridge and 1248 * the devices below. After the minimal bus space has 1249 * been allocated the remaining buses will be 1250 * distributed equally between hotplug-capable bridges. 1251 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1252 * that need to be reconfigured. 1253 * 1254 * If it's a bridge, configure it and scan the bus behind it. 1255 * For CardBus bridges, we don't scan behind as the devices will 1256 * be handled by the bridge driver itself. 1257 * 1258 * We need to process bridges in two passes -- first we scan those 1259 * already configured by the BIOS and after we are done with all of 1260 * them, we proceed to assigning numbers to the remaining buses in 1261 * order to avoid overlaps between old and new bus numbers. 1262 * 1263 * Return: New subordinate number covering all buses behind this bridge. 1264 */ 1265 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1266 int max, unsigned int available_buses, 1267 int pass) 1268 { 1269 struct pci_bus *child; 1270 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1271 u32 buses, i, j = 0; 1272 u16 bctl; 1273 u8 primary, secondary, subordinate; 1274 int broken = 0; 1275 bool fixed_buses; 1276 u8 fixed_sec, fixed_sub; 1277 int next_busnr; 1278 1279 /* 1280 * Make sure the bridge is powered on to be able to access config 1281 * space of devices below it. 1282 */ 1283 pm_runtime_get_sync(&dev->dev); 1284 1285 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1286 primary = buses & 0xFF; 1287 secondary = (buses >> 8) & 0xFF; 1288 subordinate = (buses >> 16) & 0xFF; 1289 1290 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1291 secondary, subordinate, pass); 1292 1293 if (!primary && (primary != bus->number) && secondary && subordinate) { 1294 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1295 primary = bus->number; 1296 } 1297 1298 /* Check if setup is sensible at all */ 1299 if (!pass && 1300 (primary != bus->number || secondary <= bus->number || 1301 secondary > subordinate)) { 1302 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1303 secondary, subordinate); 1304 broken = 1; 1305 } 1306 1307 /* 1308 * Disable Master-Abort Mode during probing to avoid reporting of 1309 * bus errors in some architectures. 1310 */ 1311 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1312 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1313 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1314 1315 pci_enable_crs(dev); 1316 1317 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1318 !is_cardbus && !broken) { 1319 unsigned int cmax, buses; 1320 1321 /* 1322 * Bus already configured by firmware, process it in the 1323 * first pass and just note the configuration. 1324 */ 1325 if (pass) 1326 goto out; 1327 1328 /* 1329 * The bus might already exist for two reasons: Either we 1330 * are rescanning the bus or the bus is reachable through 1331 * more than one bridge. The second case can happen with 1332 * the i450NX chipset. 1333 */ 1334 child = pci_find_bus(pci_domain_nr(bus), secondary); 1335 if (!child) { 1336 child = pci_add_new_bus(bus, dev, secondary); 1337 if (!child) 1338 goto out; 1339 child->primary = primary; 1340 pci_bus_insert_busn_res(child, secondary, subordinate); 1341 child->bridge_ctl = bctl; 1342 } 1343 1344 buses = subordinate - secondary; 1345 cmax = pci_scan_child_bus_extend(child, buses); 1346 if (cmax > subordinate) 1347 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1348 subordinate, cmax); 1349 1350 /* Subordinate should equal child->busn_res.end */ 1351 if (subordinate > max) 1352 max = subordinate; 1353 } else { 1354 1355 /* 1356 * We need to assign a number to this bus which we always 1357 * do in the second pass. 1358 */ 1359 if (!pass) { 1360 if (pcibios_assign_all_busses() || broken || is_cardbus) 1361 1362 /* 1363 * Temporarily disable forwarding of the 1364 * configuration cycles on all bridges in 1365 * this bus segment to avoid possible 1366 * conflicts in the second pass between two 1367 * bridges programmed with overlapping bus 1368 * ranges. 1369 */ 1370 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1371 buses & ~0xffffff); 1372 goto out; 1373 } 1374 1375 /* Clear errors */ 1376 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1377 1378 /* Read bus numbers from EA Capability (if present) */ 1379 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1380 if (fixed_buses) 1381 next_busnr = fixed_sec; 1382 else 1383 next_busnr = max + 1; 1384 1385 /* 1386 * Prevent assigning a bus number that already exists. 1387 * This can happen when a bridge is hot-plugged, so in this 1388 * case we only re-scan this bus. 1389 */ 1390 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1391 if (!child) { 1392 child = pci_add_new_bus(bus, dev, next_busnr); 1393 if (!child) 1394 goto out; 1395 pci_bus_insert_busn_res(child, next_busnr, 1396 bus->busn_res.end); 1397 } 1398 max++; 1399 if (available_buses) 1400 available_buses--; 1401 1402 buses = (buses & 0xff000000) 1403 | ((unsigned int)(child->primary) << 0) 1404 | ((unsigned int)(child->busn_res.start) << 8) 1405 | ((unsigned int)(child->busn_res.end) << 16); 1406 1407 /* 1408 * yenta.c forces a secondary latency timer of 176. 1409 * Copy that behaviour here. 1410 */ 1411 if (is_cardbus) { 1412 buses &= ~0xff000000; 1413 buses |= CARDBUS_LATENCY_TIMER << 24; 1414 } 1415 1416 /* We need to blast all three values with a single write */ 1417 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1418 1419 if (!is_cardbus) { 1420 child->bridge_ctl = bctl; 1421 max = pci_scan_child_bus_extend(child, available_buses); 1422 } else { 1423 1424 /* 1425 * For CardBus bridges, we leave 4 bus numbers as 1426 * cards with a PCI-to-PCI bridge can be inserted 1427 * later. 1428 */ 1429 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1430 struct pci_bus *parent = bus; 1431 if (pci_find_bus(pci_domain_nr(bus), 1432 max+i+1)) 1433 break; 1434 while (parent->parent) { 1435 if ((!pcibios_assign_all_busses()) && 1436 (parent->busn_res.end > max) && 1437 (parent->busn_res.end <= max+i)) { 1438 j = 1; 1439 } 1440 parent = parent->parent; 1441 } 1442 if (j) { 1443 1444 /* 1445 * Often, there are two CardBus 1446 * bridges -- try to leave one 1447 * valid bus number for each one. 1448 */ 1449 i /= 2; 1450 break; 1451 } 1452 } 1453 max += i; 1454 } 1455 1456 /* 1457 * Set subordinate bus number to its real value. 1458 * If fixed subordinate bus number exists from EA 1459 * capability then use it. 1460 */ 1461 if (fixed_buses) 1462 max = fixed_sub; 1463 pci_bus_update_busn_res_end(child, max); 1464 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1465 } 1466 1467 sprintf(child->name, 1468 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1469 pci_domain_nr(bus), child->number); 1470 1471 /* Check that all devices are accessible */ 1472 while (bus->parent) { 1473 if ((child->busn_res.end > bus->busn_res.end) || 1474 (child->number > bus->busn_res.end) || 1475 (child->number < bus->number) || 1476 (child->busn_res.end < bus->number)) { 1477 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1478 &child->busn_res); 1479 break; 1480 } 1481 bus = bus->parent; 1482 } 1483 1484 out: 1485 /* Clear errors in the Secondary Status Register */ 1486 pci_write_config_word(dev, PCI_SEC_STATUS, 0xffff); 1487 1488 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1489 1490 pm_runtime_put(&dev->dev); 1491 1492 return max; 1493 } 1494 1495 /* 1496 * pci_scan_bridge() - Scan buses behind a bridge 1497 * @bus: Parent bus the bridge is on 1498 * @dev: Bridge itself 1499 * @max: Starting subordinate number of buses behind this bridge 1500 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1501 * that need to be reconfigured. 1502 * 1503 * If it's a bridge, configure it and scan the bus behind it. 1504 * For CardBus bridges, we don't scan behind as the devices will 1505 * be handled by the bridge driver itself. 1506 * 1507 * We need to process bridges in two passes -- first we scan those 1508 * already configured by the BIOS and after we are done with all of 1509 * them, we proceed to assigning numbers to the remaining buses in 1510 * order to avoid overlaps between old and new bus numbers. 1511 * 1512 * Return: New subordinate number covering all buses behind this bridge. 1513 */ 1514 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1515 { 1516 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1517 } 1518 EXPORT_SYMBOL(pci_scan_bridge); 1519 1520 /* 1521 * Read interrupt line and base address registers. 1522 * The architecture-dependent code can tweak these, of course. 1523 */ 1524 static void pci_read_irq(struct pci_dev *dev) 1525 { 1526 unsigned char irq; 1527 1528 /* VFs are not allowed to use INTx, so skip the config reads */ 1529 if (dev->is_virtfn) { 1530 dev->pin = 0; 1531 dev->irq = 0; 1532 return; 1533 } 1534 1535 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1536 dev->pin = irq; 1537 if (irq) 1538 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1539 dev->irq = irq; 1540 } 1541 1542 void set_pcie_port_type(struct pci_dev *pdev) 1543 { 1544 int pos; 1545 u16 reg16; 1546 u32 reg32; 1547 int type; 1548 struct pci_dev *parent; 1549 1550 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1551 if (!pos) 1552 return; 1553 1554 pdev->pcie_cap = pos; 1555 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1556 pdev->pcie_flags_reg = reg16; 1557 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1558 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1559 1560 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); 1561 if (reg32 & PCI_EXP_LNKCAP_DLLLARC) 1562 pdev->link_active_reporting = 1; 1563 1564 parent = pci_upstream_bridge(pdev); 1565 if (!parent) 1566 return; 1567 1568 /* 1569 * Some systems do not identify their upstream/downstream ports 1570 * correctly so detect impossible configurations here and correct 1571 * the port type accordingly. 1572 */ 1573 type = pci_pcie_type(pdev); 1574 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1575 /* 1576 * If pdev claims to be downstream port but the parent 1577 * device is also downstream port assume pdev is actually 1578 * upstream port. 1579 */ 1580 if (pcie_downstream_port(parent)) { 1581 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1582 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1583 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1584 } 1585 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1586 /* 1587 * If pdev claims to be upstream port but the parent 1588 * device is also upstream port assume pdev is actually 1589 * downstream port. 1590 */ 1591 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1592 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1593 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1594 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1595 } 1596 } 1597 } 1598 1599 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1600 { 1601 u32 reg32; 1602 1603 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1604 if (reg32 & PCI_EXP_SLTCAP_HPC) 1605 pdev->is_hotplug_bridge = 1; 1606 } 1607 1608 static void set_pcie_thunderbolt(struct pci_dev *dev) 1609 { 1610 u16 vsec; 1611 1612 /* Is the device part of a Thunderbolt controller? */ 1613 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); 1614 if (vsec) 1615 dev->is_thunderbolt = 1; 1616 } 1617 1618 static void set_pcie_untrusted(struct pci_dev *dev) 1619 { 1620 struct pci_dev *parent; 1621 1622 /* 1623 * If the upstream bridge is untrusted we treat this device 1624 * untrusted as well. 1625 */ 1626 parent = pci_upstream_bridge(dev); 1627 if (parent && (parent->untrusted || parent->external_facing)) 1628 dev->untrusted = true; 1629 } 1630 1631 static void pci_set_removable(struct pci_dev *dev) 1632 { 1633 struct pci_dev *parent = pci_upstream_bridge(dev); 1634 1635 /* 1636 * We (only) consider everything downstream from an external_facing 1637 * device to be removable by the user. We're mainly concerned with 1638 * consumer platforms with user accessible thunderbolt ports that are 1639 * vulnerable to DMA attacks, and we expect those ports to be marked by 1640 * the firmware as external_facing. Devices in traditional hotplug 1641 * slots can technically be removed, but the expectation is that unless 1642 * the port is marked with external_facing, such devices are less 1643 * accessible to user / may not be removed by end user, and thus not 1644 * exposed as "removable" to userspace. 1645 */ 1646 if (parent && 1647 (parent->external_facing || dev_is_removable(&parent->dev))) 1648 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1649 } 1650 1651 /** 1652 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1653 * @dev: PCI device 1654 * 1655 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1656 * when forwarding a type1 configuration request the bridge must check that 1657 * the extended register address field is zero. The bridge is not permitted 1658 * to forward the transactions and must handle it as an Unsupported Request. 1659 * Some bridges do not follow this rule and simply drop the extended register 1660 * bits, resulting in the standard config space being aliased, every 256 1661 * bytes across the entire configuration space. Test for this condition by 1662 * comparing the first dword of each potential alias to the vendor/device ID. 1663 * Known offenders: 1664 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1665 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1666 */ 1667 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1668 { 1669 #ifdef CONFIG_PCI_QUIRKS 1670 int pos, ret; 1671 u32 header, tmp; 1672 1673 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1674 1675 for (pos = PCI_CFG_SPACE_SIZE; 1676 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1677 ret = pci_read_config_dword(dev, pos, &tmp); 1678 if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp)) 1679 return false; 1680 } 1681 1682 return true; 1683 #else 1684 return false; 1685 #endif 1686 } 1687 1688 /** 1689 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1690 * @dev: PCI device 1691 * 1692 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1693 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1694 * access it. Maybe we don't have a way to generate extended config space 1695 * accesses, or the device is behind a reverse Express bridge. So we try 1696 * reading the dword at 0x100 which must either be 0 or a valid extended 1697 * capability header. 1698 */ 1699 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1700 { 1701 u32 status; 1702 int pos = PCI_CFG_SPACE_SIZE; 1703 1704 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1705 return PCI_CFG_SPACE_SIZE; 1706 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) 1707 return PCI_CFG_SPACE_SIZE; 1708 1709 return PCI_CFG_SPACE_EXP_SIZE; 1710 } 1711 1712 int pci_cfg_space_size(struct pci_dev *dev) 1713 { 1714 int pos; 1715 u32 status; 1716 u16 class; 1717 1718 #ifdef CONFIG_PCI_IOV 1719 /* 1720 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1721 * implement a PCIe capability and therefore must implement extended 1722 * config space. We can skip the NO_EXTCFG test below and the 1723 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1724 * the fact that the SR-IOV capability on the PF resides in extended 1725 * config space and must be accessible and non-aliased to have enabled 1726 * support for this VF. This is a micro performance optimization for 1727 * systems supporting many VFs. 1728 */ 1729 if (dev->is_virtfn) 1730 return PCI_CFG_SPACE_EXP_SIZE; 1731 #endif 1732 1733 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1734 return PCI_CFG_SPACE_SIZE; 1735 1736 class = dev->class >> 8; 1737 if (class == PCI_CLASS_BRIDGE_HOST) 1738 return pci_cfg_space_size_ext(dev); 1739 1740 if (pci_is_pcie(dev)) 1741 return pci_cfg_space_size_ext(dev); 1742 1743 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1744 if (!pos) 1745 return PCI_CFG_SPACE_SIZE; 1746 1747 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1748 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1749 return pci_cfg_space_size_ext(dev); 1750 1751 return PCI_CFG_SPACE_SIZE; 1752 } 1753 1754 static u32 pci_class(struct pci_dev *dev) 1755 { 1756 u32 class; 1757 1758 #ifdef CONFIG_PCI_IOV 1759 if (dev->is_virtfn) 1760 return dev->physfn->sriov->class; 1761 #endif 1762 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1763 return class; 1764 } 1765 1766 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1767 { 1768 #ifdef CONFIG_PCI_IOV 1769 if (dev->is_virtfn) { 1770 *vendor = dev->physfn->sriov->subsystem_vendor; 1771 *device = dev->physfn->sriov->subsystem_device; 1772 return; 1773 } 1774 #endif 1775 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1776 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1777 } 1778 1779 static u8 pci_hdr_type(struct pci_dev *dev) 1780 { 1781 u8 hdr_type; 1782 1783 #ifdef CONFIG_PCI_IOV 1784 if (dev->is_virtfn) 1785 return dev->physfn->sriov->hdr_type; 1786 #endif 1787 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1788 return hdr_type; 1789 } 1790 1791 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1792 1793 /** 1794 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1795 * @dev: PCI device 1796 * 1797 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1798 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1799 */ 1800 static int pci_intx_mask_broken(struct pci_dev *dev) 1801 { 1802 u16 orig, toggle, new; 1803 1804 pci_read_config_word(dev, PCI_COMMAND, &orig); 1805 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1806 pci_write_config_word(dev, PCI_COMMAND, toggle); 1807 pci_read_config_word(dev, PCI_COMMAND, &new); 1808 1809 pci_write_config_word(dev, PCI_COMMAND, orig); 1810 1811 /* 1812 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1813 * r2.3, so strictly speaking, a device is not *broken* if it's not 1814 * writable. But we'll live with the misnomer for now. 1815 */ 1816 if (new != toggle) 1817 return 1; 1818 return 0; 1819 } 1820 1821 static void early_dump_pci_device(struct pci_dev *pdev) 1822 { 1823 u32 value[256 / 4]; 1824 int i; 1825 1826 pci_info(pdev, "config space:\n"); 1827 1828 for (i = 0; i < 256; i += 4) 1829 pci_read_config_dword(pdev, i, &value[i / 4]); 1830 1831 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1832 value, 256, false); 1833 } 1834 1835 static const char *pci_type_str(struct pci_dev *dev) 1836 { 1837 static const char * const str[] = { 1838 "PCIe Endpoint", 1839 "PCIe Legacy Endpoint", 1840 "PCIe unknown", 1841 "PCIe unknown", 1842 "PCIe Root Port", 1843 "PCIe Switch Upstream Port", 1844 "PCIe Switch Downstream Port", 1845 "PCIe to PCI/PCI-X bridge", 1846 "PCI/PCI-X to PCIe bridge", 1847 "PCIe Root Complex Integrated Endpoint", 1848 "PCIe Root Complex Event Collector", 1849 }; 1850 int type; 1851 1852 if (pci_is_pcie(dev)) { 1853 type = pci_pcie_type(dev); 1854 if (type < ARRAY_SIZE(str)) 1855 return str[type]; 1856 1857 return "PCIe unknown"; 1858 } 1859 1860 switch (dev->hdr_type) { 1861 case PCI_HEADER_TYPE_NORMAL: 1862 return "conventional PCI endpoint"; 1863 case PCI_HEADER_TYPE_BRIDGE: 1864 return "conventional PCI bridge"; 1865 case PCI_HEADER_TYPE_CARDBUS: 1866 return "CardBus bridge"; 1867 default: 1868 return "conventional PCI"; 1869 } 1870 } 1871 1872 /** 1873 * pci_setup_device - Fill in class and map information of a device 1874 * @dev: the device structure to fill 1875 * 1876 * Initialize the device structure with information about the device's 1877 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1878 * Called at initialisation of the PCI subsystem and by CardBus services. 1879 * Returns 0 on success and negative if unknown type of device (not normal, 1880 * bridge or CardBus). 1881 */ 1882 int pci_setup_device(struct pci_dev *dev) 1883 { 1884 u32 class; 1885 u16 cmd; 1886 u8 hdr_type; 1887 int err, pos = 0; 1888 struct pci_bus_region region; 1889 struct resource *res; 1890 1891 hdr_type = pci_hdr_type(dev); 1892 1893 dev->sysdata = dev->bus->sysdata; 1894 dev->dev.parent = dev->bus->bridge; 1895 dev->dev.bus = &pci_bus_type; 1896 dev->hdr_type = hdr_type & 0x7f; 1897 dev->multifunction = !!(hdr_type & 0x80); 1898 dev->error_state = pci_channel_io_normal; 1899 set_pcie_port_type(dev); 1900 1901 err = pci_set_of_node(dev); 1902 if (err) 1903 return err; 1904 pci_set_acpi_fwnode(dev); 1905 1906 pci_dev_assign_slot(dev); 1907 1908 /* 1909 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1910 * set this higher, assuming the system even supports it. 1911 */ 1912 dev->dma_mask = 0xffffffff; 1913 1914 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1915 dev->bus->number, PCI_SLOT(dev->devfn), 1916 PCI_FUNC(dev->devfn)); 1917 1918 class = pci_class(dev); 1919 1920 dev->revision = class & 0xff; 1921 dev->class = class >> 8; /* upper 3 bytes */ 1922 1923 if (pci_early_dump) 1924 early_dump_pci_device(dev); 1925 1926 /* Need to have dev->class ready */ 1927 dev->cfg_size = pci_cfg_space_size(dev); 1928 1929 /* Need to have dev->cfg_size ready */ 1930 set_pcie_thunderbolt(dev); 1931 1932 set_pcie_untrusted(dev); 1933 1934 /* "Unknown power state" */ 1935 dev->current_state = PCI_UNKNOWN; 1936 1937 /* Early fixups, before probing the BARs */ 1938 pci_fixup_device(pci_fixup_early, dev); 1939 1940 pci_set_removable(dev); 1941 1942 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n", 1943 dev->vendor, dev->device, dev->hdr_type, dev->class, 1944 pci_type_str(dev)); 1945 1946 /* Device class may be changed after fixup */ 1947 class = dev->class >> 8; 1948 1949 if (dev->non_compliant_bars && !dev->mmio_always_on) { 1950 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1951 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1952 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1953 cmd &= ~PCI_COMMAND_IO; 1954 cmd &= ~PCI_COMMAND_MEMORY; 1955 pci_write_config_word(dev, PCI_COMMAND, cmd); 1956 } 1957 } 1958 1959 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1960 1961 switch (dev->hdr_type) { /* header type */ 1962 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1963 if (class == PCI_CLASS_BRIDGE_PCI) 1964 goto bad; 1965 pci_read_irq(dev); 1966 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1967 1968 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1969 1970 /* 1971 * Do the ugly legacy mode stuff here rather than broken chip 1972 * quirk code. Legacy mode ATA controllers have fixed 1973 * addresses. These are not always echoed in BAR0-3, and 1974 * BAR0-3 in a few cases contain junk! 1975 */ 1976 if (class == PCI_CLASS_STORAGE_IDE) { 1977 u8 progif; 1978 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1979 if ((progif & 1) == 0) { 1980 region.start = 0x1F0; 1981 region.end = 0x1F7; 1982 res = &dev->resource[0]; 1983 res->flags = LEGACY_IO_RESOURCE; 1984 pcibios_bus_to_resource(dev->bus, res, ®ion); 1985 pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n", 1986 res); 1987 region.start = 0x3F6; 1988 region.end = 0x3F6; 1989 res = &dev->resource[1]; 1990 res->flags = LEGACY_IO_RESOURCE; 1991 pcibios_bus_to_resource(dev->bus, res, ®ion); 1992 pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n", 1993 res); 1994 } 1995 if ((progif & 4) == 0) { 1996 region.start = 0x170; 1997 region.end = 0x177; 1998 res = &dev->resource[2]; 1999 res->flags = LEGACY_IO_RESOURCE; 2000 pcibios_bus_to_resource(dev->bus, res, ®ion); 2001 pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n", 2002 res); 2003 region.start = 0x376; 2004 region.end = 0x376; 2005 res = &dev->resource[3]; 2006 res->flags = LEGACY_IO_RESOURCE; 2007 pcibios_bus_to_resource(dev->bus, res, ®ion); 2008 pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n", 2009 res); 2010 } 2011 } 2012 break; 2013 2014 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 2015 /* 2016 * The PCI-to-PCI bridge spec requires that subtractive 2017 * decoding (i.e. transparent) bridge must have programming 2018 * interface code of 0x01. 2019 */ 2020 pci_read_irq(dev); 2021 dev->transparent = ((dev->class & 0xff) == 1); 2022 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 2023 pci_read_bridge_windows(dev); 2024 set_pcie_hotplug_bridge(dev); 2025 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 2026 if (pos) { 2027 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 2028 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 2029 } 2030 break; 2031 2032 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 2033 if (class != PCI_CLASS_BRIDGE_CARDBUS) 2034 goto bad; 2035 pci_read_irq(dev); 2036 pci_read_bases(dev, 1, 0); 2037 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 2038 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 2039 break; 2040 2041 default: /* unknown header */ 2042 pci_err(dev, "unknown header type %02x, ignoring device\n", 2043 dev->hdr_type); 2044 pci_release_of_node(dev); 2045 return -EIO; 2046 2047 bad: 2048 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 2049 dev->class, dev->hdr_type); 2050 dev->class = PCI_CLASS_NOT_DEFINED << 8; 2051 } 2052 2053 /* We found a fine healthy device, go go go... */ 2054 return 0; 2055 } 2056 2057 static void pci_configure_mps(struct pci_dev *dev) 2058 { 2059 struct pci_dev *bridge = pci_upstream_bridge(dev); 2060 int mps, mpss, p_mps, rc; 2061 2062 if (!pci_is_pcie(dev)) 2063 return; 2064 2065 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 2066 if (dev->is_virtfn) 2067 return; 2068 2069 /* 2070 * For Root Complex Integrated Endpoints, program the maximum 2071 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 2072 */ 2073 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 2074 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2075 mps = 128; 2076 else 2077 mps = 128 << dev->pcie_mpss; 2078 rc = pcie_set_mps(dev, mps); 2079 if (rc) { 2080 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2081 mps); 2082 } 2083 return; 2084 } 2085 2086 if (!bridge || !pci_is_pcie(bridge)) 2087 return; 2088 2089 mps = pcie_get_mps(dev); 2090 p_mps = pcie_get_mps(bridge); 2091 2092 if (mps == p_mps) 2093 return; 2094 2095 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2096 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2097 mps, pci_name(bridge), p_mps); 2098 return; 2099 } 2100 2101 /* 2102 * Fancier MPS configuration is done later by 2103 * pcie_bus_configure_settings() 2104 */ 2105 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2106 return; 2107 2108 mpss = 128 << dev->pcie_mpss; 2109 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2110 pcie_set_mps(bridge, mpss); 2111 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2112 mpss, p_mps, 128 << bridge->pcie_mpss); 2113 p_mps = pcie_get_mps(bridge); 2114 } 2115 2116 rc = pcie_set_mps(dev, p_mps); 2117 if (rc) { 2118 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2119 p_mps); 2120 return; 2121 } 2122 2123 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2124 p_mps, mps, mpss); 2125 } 2126 2127 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2128 { 2129 struct pci_host_bridge *host; 2130 u32 cap; 2131 u16 ctl; 2132 int ret; 2133 2134 if (!pci_is_pcie(dev)) 2135 return 0; 2136 2137 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2138 if (ret) 2139 return 0; 2140 2141 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2142 return 0; 2143 2144 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2145 if (ret) 2146 return 0; 2147 2148 host = pci_find_host_bridge(dev->bus); 2149 if (!host) 2150 return 0; 2151 2152 /* 2153 * If some device in the hierarchy doesn't handle Extended Tags 2154 * correctly, make sure they're disabled. 2155 */ 2156 if (host->no_ext_tags) { 2157 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2158 pci_info(dev, "disabling Extended Tags\n"); 2159 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2160 PCI_EXP_DEVCTL_EXT_TAG); 2161 } 2162 return 0; 2163 } 2164 2165 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2166 pci_info(dev, "enabling Extended Tags\n"); 2167 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2168 PCI_EXP_DEVCTL_EXT_TAG); 2169 } 2170 return 0; 2171 } 2172 2173 /** 2174 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2175 * @dev: PCI device to query 2176 * 2177 * Returns true if the device has enabled relaxed ordering attribute. 2178 */ 2179 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2180 { 2181 u16 v; 2182 2183 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2184 2185 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2186 } 2187 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2188 2189 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2190 { 2191 struct pci_dev *root; 2192 2193 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */ 2194 if (dev->is_virtfn) 2195 return; 2196 2197 if (!pcie_relaxed_ordering_enabled(dev)) 2198 return; 2199 2200 /* 2201 * For now, we only deal with Relaxed Ordering issues with Root 2202 * Ports. Peer-to-Peer DMA is another can of worms. 2203 */ 2204 root = pcie_find_root_port(dev); 2205 if (!root) 2206 return; 2207 2208 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2209 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2210 PCI_EXP_DEVCTL_RELAX_EN); 2211 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2212 } 2213 } 2214 2215 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2216 { 2217 #ifdef CONFIG_PCI_PASID 2218 struct pci_dev *bridge; 2219 int pcie_type; 2220 u32 cap; 2221 2222 if (!pci_is_pcie(dev)) 2223 return; 2224 2225 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2226 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2227 return; 2228 2229 pcie_type = pci_pcie_type(dev); 2230 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2231 pcie_type == PCI_EXP_TYPE_RC_END) 2232 dev->eetlp_prefix_path = 1; 2233 else { 2234 bridge = pci_upstream_bridge(dev); 2235 if (bridge && bridge->eetlp_prefix_path) 2236 dev->eetlp_prefix_path = 1; 2237 } 2238 #endif 2239 } 2240 2241 static void pci_configure_serr(struct pci_dev *dev) 2242 { 2243 u16 control; 2244 2245 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2246 2247 /* 2248 * A bridge will not forward ERR_ messages coming from an 2249 * endpoint unless SERR# forwarding is enabled. 2250 */ 2251 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2252 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2253 control |= PCI_BRIDGE_CTL_SERR; 2254 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2255 } 2256 } 2257 } 2258 2259 static void pci_configure_device(struct pci_dev *dev) 2260 { 2261 pci_configure_mps(dev); 2262 pci_configure_extended_tags(dev, NULL); 2263 pci_configure_relaxed_ordering(dev); 2264 pci_configure_ltr(dev); 2265 pci_configure_aspm_l1ss(dev); 2266 pci_configure_eetlp_prefix(dev); 2267 pci_configure_serr(dev); 2268 2269 pci_acpi_program_hp_params(dev); 2270 } 2271 2272 static void pci_release_capabilities(struct pci_dev *dev) 2273 { 2274 pci_aer_exit(dev); 2275 pci_rcec_exit(dev); 2276 pci_iov_release(dev); 2277 pci_free_cap_save_buffers(dev); 2278 } 2279 2280 /** 2281 * pci_release_dev - Free a PCI device structure when all users of it are 2282 * finished 2283 * @dev: device that's been disconnected 2284 * 2285 * Will be called only by the device core when all users of this PCI device are 2286 * done. 2287 */ 2288 static void pci_release_dev(struct device *dev) 2289 { 2290 struct pci_dev *pci_dev; 2291 2292 pci_dev = to_pci_dev(dev); 2293 pci_release_capabilities(pci_dev); 2294 pci_release_of_node(pci_dev); 2295 pcibios_release_device(pci_dev); 2296 pci_bus_put(pci_dev->bus); 2297 kfree(pci_dev->driver_override); 2298 bitmap_free(pci_dev->dma_alias_mask); 2299 dev_dbg(dev, "device released\n"); 2300 kfree(pci_dev); 2301 } 2302 2303 static const struct device_type pci_dev_type = { 2304 .groups = pci_dev_attr_groups, 2305 }; 2306 2307 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2308 { 2309 struct pci_dev *dev; 2310 2311 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2312 if (!dev) 2313 return NULL; 2314 2315 INIT_LIST_HEAD(&dev->bus_list); 2316 dev->dev.type = &pci_dev_type; 2317 dev->bus = pci_bus_get(bus); 2318 dev->driver_exclusive_resource = (struct resource) { 2319 .name = "PCI Exclusive", 2320 .start = 0, 2321 .end = -1, 2322 }; 2323 2324 spin_lock_init(&dev->pcie_cap_lock); 2325 #ifdef CONFIG_PCI_MSI 2326 raw_spin_lock_init(&dev->msi_lock); 2327 #endif 2328 return dev; 2329 } 2330 EXPORT_SYMBOL(pci_alloc_dev); 2331 2332 static bool pci_bus_crs_vendor_id(u32 l) 2333 { 2334 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 2335 } 2336 2337 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2338 int timeout) 2339 { 2340 int delay = 1; 2341 2342 if (!pci_bus_crs_vendor_id(*l)) 2343 return true; /* not a CRS completion */ 2344 2345 if (!timeout) 2346 return false; /* CRS, but caller doesn't want to wait */ 2347 2348 /* 2349 * We got the reserved Vendor ID that indicates a completion with 2350 * Configuration Request Retry Status (CRS). Retry until we get a 2351 * valid Vendor ID or we time out. 2352 */ 2353 while (pci_bus_crs_vendor_id(*l)) { 2354 if (delay > timeout) { 2355 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2356 pci_domain_nr(bus), bus->number, 2357 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2358 2359 return false; 2360 } 2361 if (delay >= 1000) 2362 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2363 pci_domain_nr(bus), bus->number, 2364 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2365 2366 msleep(delay); 2367 delay *= 2; 2368 2369 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2370 return false; 2371 } 2372 2373 if (delay >= 1000) 2374 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2375 pci_domain_nr(bus), bus->number, 2376 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2377 2378 return true; 2379 } 2380 2381 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2382 int timeout) 2383 { 2384 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2385 return false; 2386 2387 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ 2388 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || 2389 *l == 0x0000ffff || *l == 0xffff0000) 2390 return false; 2391 2392 if (pci_bus_crs_vendor_id(*l)) 2393 return pci_bus_wait_crs(bus, devfn, l, timeout); 2394 2395 return true; 2396 } 2397 2398 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2399 int timeout) 2400 { 2401 #ifdef CONFIG_PCI_QUIRKS 2402 struct pci_dev *bridge = bus->self; 2403 2404 /* 2405 * Certain IDT switches have an issue where they improperly trigger 2406 * ACS Source Validation errors on completions for config reads. 2407 */ 2408 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2409 bridge->device == 0x80b5) 2410 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2411 #endif 2412 2413 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2414 } 2415 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2416 2417 /* 2418 * Read the config data for a PCI device, sanity-check it, 2419 * and fill in the dev structure. 2420 */ 2421 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2422 { 2423 struct pci_dev *dev; 2424 u32 l; 2425 2426 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2427 return NULL; 2428 2429 dev = pci_alloc_dev(bus); 2430 if (!dev) 2431 return NULL; 2432 2433 dev->devfn = devfn; 2434 dev->vendor = l & 0xffff; 2435 dev->device = (l >> 16) & 0xffff; 2436 2437 if (pci_setup_device(dev)) { 2438 pci_bus_put(dev->bus); 2439 kfree(dev); 2440 return NULL; 2441 } 2442 2443 return dev; 2444 } 2445 2446 void pcie_report_downtraining(struct pci_dev *dev) 2447 { 2448 if (!pci_is_pcie(dev)) 2449 return; 2450 2451 /* Look from the device up to avoid downstream ports with no devices */ 2452 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2453 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2454 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2455 return; 2456 2457 /* Multi-function PCIe devices share the same link/status */ 2458 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2459 return; 2460 2461 /* Print link status only if the device is constrained by the fabric */ 2462 __pcie_print_link_status(dev, false); 2463 } 2464 2465 static void pci_init_capabilities(struct pci_dev *dev) 2466 { 2467 pci_ea_init(dev); /* Enhanced Allocation */ 2468 pci_msi_init(dev); /* Disable MSI */ 2469 pci_msix_init(dev); /* Disable MSI-X */ 2470 2471 /* Buffers for saving PCIe and PCI-X capabilities */ 2472 pci_allocate_cap_save_buffers(dev); 2473 2474 pci_pm_init(dev); /* Power Management */ 2475 pci_vpd_init(dev); /* Vital Product Data */ 2476 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2477 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2478 pci_ats_init(dev); /* Address Translation Services */ 2479 pci_pri_init(dev); /* Page Request Interface */ 2480 pci_pasid_init(dev); /* Process Address Space ID */ 2481 pci_acs_init(dev); /* Access Control Services */ 2482 pci_ptm_init(dev); /* Precision Time Measurement */ 2483 pci_aer_init(dev); /* Advanced Error Reporting */ 2484 pci_dpc_init(dev); /* Downstream Port Containment */ 2485 pci_rcec_init(dev); /* Root Complex Event Collector */ 2486 pci_doe_init(dev); /* Data Object Exchange */ 2487 2488 pcie_report_downtraining(dev); 2489 pci_init_reset_methods(dev); 2490 } 2491 2492 /* 2493 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2494 * devices. Firmware interfaces that can select the MSI domain on a 2495 * per-device basis should be called from here. 2496 */ 2497 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2498 { 2499 struct irq_domain *d; 2500 2501 /* 2502 * If a domain has been set through the pcibios_device_add() 2503 * callback, then this is the one (platform code knows best). 2504 */ 2505 d = dev_get_msi_domain(&dev->dev); 2506 if (d) 2507 return d; 2508 2509 /* 2510 * Let's see if we have a firmware interface able to provide 2511 * the domain. 2512 */ 2513 d = pci_msi_get_device_domain(dev); 2514 if (d) 2515 return d; 2516 2517 return NULL; 2518 } 2519 2520 static void pci_set_msi_domain(struct pci_dev *dev) 2521 { 2522 struct irq_domain *d; 2523 2524 /* 2525 * If the platform or firmware interfaces cannot supply a 2526 * device-specific MSI domain, then inherit the default domain 2527 * from the host bridge itself. 2528 */ 2529 d = pci_dev_msi_domain(dev); 2530 if (!d) 2531 d = dev_get_msi_domain(&dev->bus->dev); 2532 2533 dev_set_msi_domain(&dev->dev, d); 2534 } 2535 2536 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2537 { 2538 int ret; 2539 2540 pci_configure_device(dev); 2541 2542 device_initialize(&dev->dev); 2543 dev->dev.release = pci_release_dev; 2544 2545 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2546 dev->dev.dma_mask = &dev->dma_mask; 2547 dev->dev.dma_parms = &dev->dma_parms; 2548 dev->dev.coherent_dma_mask = 0xffffffffull; 2549 lockdep_register_key(&dev->cfg_access_key); 2550 lockdep_init_map(&dev->cfg_access_lock, dev_name(&dev->dev), 2551 &dev->cfg_access_key, 0); 2552 2553 dma_set_max_seg_size(&dev->dev, 65536); 2554 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2555 2556 pcie_failed_link_retrain(dev); 2557 2558 /* Fix up broken headers */ 2559 pci_fixup_device(pci_fixup_header, dev); 2560 2561 pci_reassigndev_resource_alignment(dev); 2562 2563 dev->state_saved = false; 2564 2565 pci_init_capabilities(dev); 2566 2567 /* 2568 * Add the device to our list of discovered devices 2569 * and the bus list for fixup functions, etc. 2570 */ 2571 down_write(&pci_bus_sem); 2572 list_add_tail(&dev->bus_list, &bus->devices); 2573 up_write(&pci_bus_sem); 2574 2575 ret = pcibios_device_add(dev); 2576 WARN_ON(ret < 0); 2577 2578 /* Set up MSI IRQ domain */ 2579 pci_set_msi_domain(dev); 2580 2581 /* Notifier could use PCI capabilities */ 2582 dev->match_driver = false; 2583 ret = device_add(&dev->dev); 2584 WARN_ON(ret < 0); 2585 } 2586 2587 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2588 { 2589 struct pci_dev *dev; 2590 2591 dev = pci_get_slot(bus, devfn); 2592 if (dev) { 2593 pci_dev_put(dev); 2594 return dev; 2595 } 2596 2597 dev = pci_scan_device(bus, devfn); 2598 if (!dev) 2599 return NULL; 2600 2601 pci_device_add(dev, bus); 2602 2603 return dev; 2604 } 2605 EXPORT_SYMBOL(pci_scan_single_device); 2606 2607 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2608 { 2609 int pos; 2610 u16 cap = 0; 2611 unsigned int next_fn; 2612 2613 if (!dev) 2614 return -ENODEV; 2615 2616 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2617 if (!pos) 2618 return -ENODEV; 2619 2620 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2621 next_fn = PCI_ARI_CAP_NFN(cap); 2622 if (next_fn <= fn) 2623 return -ENODEV; /* protect against malformed list */ 2624 2625 return next_fn; 2626 } 2627 2628 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2629 { 2630 if (pci_ari_enabled(bus)) 2631 return next_ari_fn(bus, dev, fn); 2632 2633 if (fn >= 7) 2634 return -ENODEV; 2635 /* only multifunction devices may have more functions */ 2636 if (dev && !dev->multifunction) 2637 return -ENODEV; 2638 2639 return fn + 1; 2640 } 2641 2642 static int only_one_child(struct pci_bus *bus) 2643 { 2644 struct pci_dev *bridge = bus->self; 2645 2646 /* 2647 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2648 * we scan for all possible devices, not just Device 0. 2649 */ 2650 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2651 return 0; 2652 2653 /* 2654 * A PCIe Downstream Port normally leads to a Link with only Device 2655 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2656 * only for Device 0 in that situation. 2657 */ 2658 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2659 return 1; 2660 2661 return 0; 2662 } 2663 2664 /** 2665 * pci_scan_slot - Scan a PCI slot on a bus for devices 2666 * @bus: PCI bus to scan 2667 * @devfn: slot number to scan (must have zero function) 2668 * 2669 * Scan a PCI slot on the specified PCI bus for devices, adding 2670 * discovered devices to the @bus->devices list. New devices 2671 * will not have is_added set. 2672 * 2673 * Returns the number of new devices found. 2674 */ 2675 int pci_scan_slot(struct pci_bus *bus, int devfn) 2676 { 2677 struct pci_dev *dev; 2678 int fn = 0, nr = 0; 2679 2680 if (only_one_child(bus) && (devfn > 0)) 2681 return 0; /* Already scanned the entire slot */ 2682 2683 do { 2684 dev = pci_scan_single_device(bus, devfn + fn); 2685 if (dev) { 2686 if (!pci_dev_is_added(dev)) 2687 nr++; 2688 if (fn > 0) 2689 dev->multifunction = 1; 2690 } else if (fn == 0) { 2691 /* 2692 * Function 0 is required unless we are running on 2693 * a hypervisor that passes through individual PCI 2694 * functions. 2695 */ 2696 if (!hypervisor_isolated_pci_functions()) 2697 break; 2698 } 2699 fn = next_fn(bus, dev, fn); 2700 } while (fn >= 0); 2701 2702 /* Only one slot has PCIe device */ 2703 if (bus->self && nr) 2704 pcie_aspm_init_link_state(bus->self); 2705 2706 return nr; 2707 } 2708 EXPORT_SYMBOL(pci_scan_slot); 2709 2710 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2711 { 2712 u8 *smpss = data; 2713 2714 if (!pci_is_pcie(dev)) 2715 return 0; 2716 2717 /* 2718 * We don't have a way to change MPS settings on devices that have 2719 * drivers attached. A hot-added device might support only the minimum 2720 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2721 * where devices may be hot-added, we limit the fabric MPS to 128 so 2722 * hot-added devices will work correctly. 2723 * 2724 * However, if we hot-add a device to a slot directly below a Root 2725 * Port, it's impossible for there to be other existing devices below 2726 * the port. We don't limit the MPS in this case because we can 2727 * reconfigure MPS on both the Root Port and the hot-added device, 2728 * and there are no other devices involved. 2729 * 2730 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2731 */ 2732 if (dev->is_hotplug_bridge && 2733 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2734 *smpss = 0; 2735 2736 if (*smpss > dev->pcie_mpss) 2737 *smpss = dev->pcie_mpss; 2738 2739 return 0; 2740 } 2741 2742 static void pcie_write_mps(struct pci_dev *dev, int mps) 2743 { 2744 int rc; 2745 2746 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2747 mps = 128 << dev->pcie_mpss; 2748 2749 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2750 dev->bus->self) 2751 2752 /* 2753 * For "Performance", the assumption is made that 2754 * downstream communication will never be larger than 2755 * the MRRS. So, the MPS only needs to be configured 2756 * for the upstream communication. This being the case, 2757 * walk from the top down and set the MPS of the child 2758 * to that of the parent bus. 2759 * 2760 * Configure the device MPS with the smaller of the 2761 * device MPSS or the bridge MPS (which is assumed to be 2762 * properly configured at this point to the largest 2763 * allowable MPS based on its parent bus). 2764 */ 2765 mps = min(mps, pcie_get_mps(dev->bus->self)); 2766 } 2767 2768 rc = pcie_set_mps(dev, mps); 2769 if (rc) 2770 pci_err(dev, "Failed attempting to set the MPS\n"); 2771 } 2772 2773 static void pcie_write_mrrs(struct pci_dev *dev) 2774 { 2775 int rc, mrrs; 2776 2777 /* 2778 * In the "safe" case, do not configure the MRRS. There appear to be 2779 * issues with setting MRRS to 0 on a number of devices. 2780 */ 2781 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2782 return; 2783 2784 /* 2785 * For max performance, the MRRS must be set to the largest supported 2786 * value. However, it cannot be configured larger than the MPS the 2787 * device or the bus can support. This should already be properly 2788 * configured by a prior call to pcie_write_mps(). 2789 */ 2790 mrrs = pcie_get_mps(dev); 2791 2792 /* 2793 * MRRS is a R/W register. Invalid values can be written, but a 2794 * subsequent read will verify if the value is acceptable or not. 2795 * If the MRRS value provided is not acceptable (e.g., too large), 2796 * shrink the value until it is acceptable to the HW. 2797 */ 2798 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2799 rc = pcie_set_readrq(dev, mrrs); 2800 if (!rc) 2801 break; 2802 2803 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2804 mrrs /= 2; 2805 } 2806 2807 if (mrrs < 128) 2808 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2809 } 2810 2811 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2812 { 2813 int mps, orig_mps; 2814 2815 if (!pci_is_pcie(dev)) 2816 return 0; 2817 2818 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2819 pcie_bus_config == PCIE_BUS_DEFAULT) 2820 return 0; 2821 2822 mps = 128 << *(u8 *)data; 2823 orig_mps = pcie_get_mps(dev); 2824 2825 pcie_write_mps(dev, mps); 2826 pcie_write_mrrs(dev); 2827 2828 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2829 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2830 orig_mps, pcie_get_readrq(dev)); 2831 2832 return 0; 2833 } 2834 2835 /* 2836 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2837 * parents then children fashion. If this changes, then this code will not 2838 * work as designed. 2839 */ 2840 void pcie_bus_configure_settings(struct pci_bus *bus) 2841 { 2842 u8 smpss = 0; 2843 2844 if (!bus->self) 2845 return; 2846 2847 if (!pci_is_pcie(bus->self)) 2848 return; 2849 2850 /* 2851 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2852 * to be aware of the MPS of the destination. To work around this, 2853 * simply force the MPS of the entire system to the smallest possible. 2854 */ 2855 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2856 smpss = 0; 2857 2858 if (pcie_bus_config == PCIE_BUS_SAFE) { 2859 smpss = bus->self->pcie_mpss; 2860 2861 pcie_find_smpss(bus->self, &smpss); 2862 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2863 } 2864 2865 pcie_bus_configure_set(bus->self, &smpss); 2866 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2867 } 2868 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2869 2870 /* 2871 * Called after each bus is probed, but before its children are examined. This 2872 * is marked as __weak because multiple architectures define it. 2873 */ 2874 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2875 { 2876 /* nothing to do, expected to be removed in the future */ 2877 } 2878 2879 /** 2880 * pci_scan_child_bus_extend() - Scan devices below a bus 2881 * @bus: Bus to scan for devices 2882 * @available_buses: Total number of buses available (%0 does not try to 2883 * extend beyond the minimal) 2884 * 2885 * Scans devices below @bus including subordinate buses. Returns new 2886 * subordinate number including all the found devices. Passing 2887 * @available_buses causes the remaining bus space to be distributed 2888 * equally between hotplug-capable bridges to allow future extension of the 2889 * hierarchy. 2890 */ 2891 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2892 unsigned int available_buses) 2893 { 2894 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2895 unsigned int start = bus->busn_res.start; 2896 unsigned int devfn, cmax, max = start; 2897 struct pci_dev *dev; 2898 2899 dev_dbg(&bus->dev, "scanning bus\n"); 2900 2901 /* Go find them, Rover! */ 2902 for (devfn = 0; devfn < 256; devfn += 8) 2903 pci_scan_slot(bus, devfn); 2904 2905 /* Reserve buses for SR-IOV capability */ 2906 used_buses = pci_iov_bus_range(bus); 2907 max += used_buses; 2908 2909 /* 2910 * After performing arch-dependent fixup of the bus, look behind 2911 * all PCI-to-PCI bridges on this bus. 2912 */ 2913 if (!bus->is_added) { 2914 dev_dbg(&bus->dev, "fixups for bus\n"); 2915 pcibios_fixup_bus(bus); 2916 bus->is_added = 1; 2917 } 2918 2919 /* 2920 * Calculate how many hotplug bridges and normal bridges there 2921 * are on this bus. We will distribute the additional available 2922 * buses between hotplug bridges. 2923 */ 2924 for_each_pci_bridge(dev, bus) { 2925 if (dev->is_hotplug_bridge) 2926 hotplug_bridges++; 2927 else 2928 normal_bridges++; 2929 } 2930 2931 /* 2932 * Scan bridges that are already configured. We don't touch them 2933 * unless they are misconfigured (which will be done in the second 2934 * scan below). 2935 */ 2936 for_each_pci_bridge(dev, bus) { 2937 cmax = max; 2938 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2939 2940 /* 2941 * Reserve one bus for each bridge now to avoid extending 2942 * hotplug bridges too much during the second scan below. 2943 */ 2944 used_buses++; 2945 if (max - cmax > 1) 2946 used_buses += max - cmax - 1; 2947 } 2948 2949 /* Scan bridges that need to be reconfigured */ 2950 for_each_pci_bridge(dev, bus) { 2951 unsigned int buses = 0; 2952 2953 if (!hotplug_bridges && normal_bridges == 1) { 2954 /* 2955 * There is only one bridge on the bus (upstream 2956 * port) so it gets all available buses which it 2957 * can then distribute to the possible hotplug 2958 * bridges below. 2959 */ 2960 buses = available_buses; 2961 } else if (dev->is_hotplug_bridge) { 2962 /* 2963 * Distribute the extra buses between hotplug 2964 * bridges if any. 2965 */ 2966 buses = available_buses / hotplug_bridges; 2967 buses = min(buses, available_buses - used_buses + 1); 2968 } 2969 2970 cmax = max; 2971 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2972 /* One bus is already accounted so don't add it again */ 2973 if (max - cmax > 1) 2974 used_buses += max - cmax - 1; 2975 } 2976 2977 /* 2978 * Make sure a hotplug bridge has at least the minimum requested 2979 * number of buses but allow it to grow up to the maximum available 2980 * bus number if there is room. 2981 */ 2982 if (bus->self && bus->self->is_hotplug_bridge) { 2983 used_buses = max_t(unsigned int, available_buses, 2984 pci_hotplug_bus_size - 1); 2985 if (max - start < used_buses) { 2986 max = start + used_buses; 2987 2988 /* Do not allocate more buses than we have room left */ 2989 if (max > bus->busn_res.end) 2990 max = bus->busn_res.end; 2991 2992 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 2993 &bus->busn_res, max - start); 2994 } 2995 } 2996 2997 /* 2998 * We've scanned the bus and so we know all about what's on 2999 * the other side of any bridges that may be on this bus plus 3000 * any devices. 3001 * 3002 * Return how far we've got finding sub-buses. 3003 */ 3004 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 3005 return max; 3006 } 3007 3008 /** 3009 * pci_scan_child_bus() - Scan devices below a bus 3010 * @bus: Bus to scan for devices 3011 * 3012 * Scans devices below @bus including subordinate buses. Returns new 3013 * subordinate number including all the found devices. 3014 */ 3015 unsigned int pci_scan_child_bus(struct pci_bus *bus) 3016 { 3017 return pci_scan_child_bus_extend(bus, 0); 3018 } 3019 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3020 3021 /** 3022 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3023 * @bridge: Host bridge to set up 3024 * 3025 * Default empty implementation. Replace with an architecture-specific setup 3026 * routine, if necessary. 3027 */ 3028 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3029 { 3030 return 0; 3031 } 3032 3033 void __weak pcibios_add_bus(struct pci_bus *bus) 3034 { 3035 } 3036 3037 void __weak pcibios_remove_bus(struct pci_bus *bus) 3038 { 3039 } 3040 3041 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3042 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3043 { 3044 int error; 3045 struct pci_host_bridge *bridge; 3046 3047 bridge = pci_alloc_host_bridge(0); 3048 if (!bridge) 3049 return NULL; 3050 3051 bridge->dev.parent = parent; 3052 3053 list_splice_init(resources, &bridge->windows); 3054 bridge->sysdata = sysdata; 3055 bridge->busnr = bus; 3056 bridge->ops = ops; 3057 3058 error = pci_register_host_bridge(bridge); 3059 if (error < 0) 3060 goto err_out; 3061 3062 return bridge->bus; 3063 3064 err_out: 3065 put_device(&bridge->dev); 3066 return NULL; 3067 } 3068 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3069 3070 int pci_host_probe(struct pci_host_bridge *bridge) 3071 { 3072 struct pci_bus *bus, *child; 3073 int ret; 3074 3075 ret = pci_scan_root_bus_bridge(bridge); 3076 if (ret < 0) { 3077 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3078 return ret; 3079 } 3080 3081 bus = bridge->bus; 3082 3083 /* 3084 * We insert PCI resources into the iomem_resource and 3085 * ioport_resource trees in either pci_bus_claim_resources() 3086 * or pci_bus_assign_resources(). 3087 */ 3088 if (pci_has_flag(PCI_PROBE_ONLY)) { 3089 pci_bus_claim_resources(bus); 3090 } else { 3091 pci_bus_size_bridges(bus); 3092 pci_bus_assign_resources(bus); 3093 3094 list_for_each_entry(child, &bus->children, node) 3095 pcie_bus_configure_settings(child); 3096 } 3097 3098 pci_bus_add_devices(bus); 3099 return 0; 3100 } 3101 EXPORT_SYMBOL_GPL(pci_host_probe); 3102 3103 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3104 { 3105 struct resource *res = &b->busn_res; 3106 struct resource *parent_res, *conflict; 3107 3108 res->start = bus; 3109 res->end = bus_max; 3110 res->flags = IORESOURCE_BUS; 3111 3112 if (!pci_is_root_bus(b)) 3113 parent_res = &b->parent->busn_res; 3114 else { 3115 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3116 res->flags |= IORESOURCE_PCI_FIXED; 3117 } 3118 3119 conflict = request_resource_conflict(parent_res, res); 3120 3121 if (conflict) 3122 dev_info(&b->dev, 3123 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3124 res, pci_is_root_bus(b) ? "domain " : "", 3125 parent_res, conflict->name, conflict); 3126 3127 return conflict == NULL; 3128 } 3129 3130 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3131 { 3132 struct resource *res = &b->busn_res; 3133 struct resource old_res = *res; 3134 resource_size_t size; 3135 int ret; 3136 3137 if (res->start > bus_max) 3138 return -EINVAL; 3139 3140 size = bus_max - res->start + 1; 3141 ret = adjust_resource(res, res->start, size); 3142 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3143 &old_res, ret ? "can not be" : "is", bus_max); 3144 3145 if (!ret && !res->parent) 3146 pci_bus_insert_busn_res(b, res->start, res->end); 3147 3148 return ret; 3149 } 3150 3151 void pci_bus_release_busn_res(struct pci_bus *b) 3152 { 3153 struct resource *res = &b->busn_res; 3154 int ret; 3155 3156 if (!res->flags || !res->parent) 3157 return; 3158 3159 ret = release_resource(res); 3160 dev_info(&b->dev, "busn_res: %pR %s released\n", 3161 res, ret ? "can not be" : "is"); 3162 } 3163 3164 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3165 { 3166 struct resource_entry *window; 3167 bool found = false; 3168 struct pci_bus *b; 3169 int max, bus, ret; 3170 3171 if (!bridge) 3172 return -EINVAL; 3173 3174 resource_list_for_each_entry(window, &bridge->windows) 3175 if (window->res->flags & IORESOURCE_BUS) { 3176 bridge->busnr = window->res->start; 3177 found = true; 3178 break; 3179 } 3180 3181 ret = pci_register_host_bridge(bridge); 3182 if (ret < 0) 3183 return ret; 3184 3185 b = bridge->bus; 3186 bus = bridge->busnr; 3187 3188 if (!found) { 3189 dev_info(&b->dev, 3190 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3191 bus); 3192 pci_bus_insert_busn_res(b, bus, 255); 3193 } 3194 3195 max = pci_scan_child_bus(b); 3196 3197 if (!found) 3198 pci_bus_update_busn_res_end(b, max); 3199 3200 return 0; 3201 } 3202 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3203 3204 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3205 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3206 { 3207 struct resource_entry *window; 3208 bool found = false; 3209 struct pci_bus *b; 3210 int max; 3211 3212 resource_list_for_each_entry(window, resources) 3213 if (window->res->flags & IORESOURCE_BUS) { 3214 found = true; 3215 break; 3216 } 3217 3218 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3219 if (!b) 3220 return NULL; 3221 3222 if (!found) { 3223 dev_info(&b->dev, 3224 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3225 bus); 3226 pci_bus_insert_busn_res(b, bus, 255); 3227 } 3228 3229 max = pci_scan_child_bus(b); 3230 3231 if (!found) 3232 pci_bus_update_busn_res_end(b, max); 3233 3234 return b; 3235 } 3236 EXPORT_SYMBOL(pci_scan_root_bus); 3237 3238 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3239 void *sysdata) 3240 { 3241 LIST_HEAD(resources); 3242 struct pci_bus *b; 3243 3244 pci_add_resource(&resources, &ioport_resource); 3245 pci_add_resource(&resources, &iomem_resource); 3246 pci_add_resource(&resources, &busn_resource); 3247 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3248 if (b) { 3249 pci_scan_child_bus(b); 3250 } else { 3251 pci_free_resource_list(&resources); 3252 } 3253 return b; 3254 } 3255 EXPORT_SYMBOL(pci_scan_bus); 3256 3257 /** 3258 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3259 * @bridge: PCI bridge for the bus to scan 3260 * 3261 * Scan a PCI bus and child buses for new devices, add them, 3262 * and enable them, resizing bridge mmio/io resource if necessary 3263 * and possible. The caller must ensure the child devices are already 3264 * removed for resizing to occur. 3265 * 3266 * Returns the max number of subordinate bus discovered. 3267 */ 3268 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3269 { 3270 unsigned int max; 3271 struct pci_bus *bus = bridge->subordinate; 3272 3273 max = pci_scan_child_bus(bus); 3274 3275 pci_assign_unassigned_bridge_resources(bridge); 3276 3277 pci_bus_add_devices(bus); 3278 3279 return max; 3280 } 3281 3282 /** 3283 * pci_rescan_bus - Scan a PCI bus for devices 3284 * @bus: PCI bus to scan 3285 * 3286 * Scan a PCI bus and child buses for new devices, add them, 3287 * and enable them. 3288 * 3289 * Returns the max number of subordinate bus discovered. 3290 */ 3291 unsigned int pci_rescan_bus(struct pci_bus *bus) 3292 { 3293 unsigned int max; 3294 3295 max = pci_scan_child_bus(bus); 3296 pci_assign_unassigned_bus_resources(bus); 3297 pci_bus_add_devices(bus); 3298 3299 return max; 3300 } 3301 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3302 3303 /* 3304 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3305 * routines should always be executed under this mutex. 3306 */ 3307 static DEFINE_MUTEX(pci_rescan_remove_lock); 3308 3309 void pci_lock_rescan_remove(void) 3310 { 3311 mutex_lock(&pci_rescan_remove_lock); 3312 } 3313 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3314 3315 void pci_unlock_rescan_remove(void) 3316 { 3317 mutex_unlock(&pci_rescan_remove_lock); 3318 } 3319 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3320 3321 static int __init pci_sort_bf_cmp(const struct device *d_a, 3322 const struct device *d_b) 3323 { 3324 const struct pci_dev *a = to_pci_dev(d_a); 3325 const struct pci_dev *b = to_pci_dev(d_b); 3326 3327 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3328 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3329 3330 if (a->bus->number < b->bus->number) return -1; 3331 else if (a->bus->number > b->bus->number) return 1; 3332 3333 if (a->devfn < b->devfn) return -1; 3334 else if (a->devfn > b->devfn) return 1; 3335 3336 return 0; 3337 } 3338 3339 void __init pci_sort_breadthfirst(void) 3340 { 3341 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3342 } 3343 3344 int pci_hp_add_bridge(struct pci_dev *dev) 3345 { 3346 struct pci_bus *parent = dev->bus; 3347 int busnr, start = parent->busn_res.start; 3348 unsigned int available_buses = 0; 3349 int end = parent->busn_res.end; 3350 3351 for (busnr = start; busnr <= end; busnr++) { 3352 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3353 break; 3354 } 3355 if (busnr-- > end) { 3356 pci_err(dev, "No bus number available for hot-added bridge\n"); 3357 return -1; 3358 } 3359 3360 /* Scan bridges that are already configured */ 3361 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3362 3363 /* 3364 * Distribute the available bus numbers between hotplug-capable 3365 * bridges to make extending the chain later possible. 3366 */ 3367 available_buses = end - busnr; 3368 3369 /* Scan bridges that need to be reconfigured */ 3370 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3371 3372 if (!dev->subordinate) 3373 return -1; 3374 3375 return 0; 3376 } 3377 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3378