1 /* 2 * probe.c - PCI detection and setup code 3 */ 4 5 #include <linux/kernel.h> 6 #include <linux/delay.h> 7 #include <linux/init.h> 8 #include <linux/pci.h> 9 #include <linux/slab.h> 10 #include <linux/module.h> 11 #include <linux/cpumask.h> 12 #include <linux/pci-aspm.h> 13 #include "pci.h" 14 15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 16 #define CARDBUS_RESERVE_BUSNR 3 17 18 /* Ugh. Need to stop exporting this to modules. */ 19 LIST_HEAD(pci_root_buses); 20 EXPORT_SYMBOL(pci_root_buses); 21 22 23 static int find_anything(struct device *dev, void *data) 24 { 25 return 1; 26 } 27 28 /* 29 * Some device drivers need know if pci is initiated. 30 * Basically, we think pci is not initiated when there 31 * is no device to be found on the pci_bus_type. 32 */ 33 int no_pci_devices(void) 34 { 35 struct device *dev; 36 int no_devices; 37 38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); 39 no_devices = (dev == NULL); 40 put_device(dev); 41 return no_devices; 42 } 43 EXPORT_SYMBOL(no_pci_devices); 44 45 /* 46 * PCI Bus Class Devices 47 */ 48 static ssize_t pci_bus_show_cpuaffinity(struct device *dev, 49 int type, 50 struct device_attribute *attr, 51 char *buf) 52 { 53 int ret; 54 const struct cpumask *cpumask; 55 56 cpumask = cpumask_of_pcibus(to_pci_bus(dev)); 57 ret = type? 58 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) : 59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); 60 buf[ret++] = '\n'; 61 buf[ret] = '\0'; 62 return ret; 63 } 64 65 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, 66 struct device_attribute *attr, 67 char *buf) 68 { 69 return pci_bus_show_cpuaffinity(dev, 0, attr, buf); 70 } 71 72 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, 73 struct device_attribute *attr, 74 char *buf) 75 { 76 return pci_bus_show_cpuaffinity(dev, 1, attr, buf); 77 } 78 79 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); 80 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); 81 82 /* 83 * PCI Bus Class 84 */ 85 static void release_pcibus_dev(struct device *dev) 86 { 87 struct pci_bus *pci_bus = to_pci_bus(dev); 88 89 if (pci_bus->bridge) 90 put_device(pci_bus->bridge); 91 kfree(pci_bus); 92 } 93 94 static struct class pcibus_class = { 95 .name = "pci_bus", 96 .dev_release = &release_pcibus_dev, 97 }; 98 99 static int __init pcibus_class_init(void) 100 { 101 return class_register(&pcibus_class); 102 } 103 postcore_initcall(pcibus_class_init); 104 105 /* 106 * Translate the low bits of the PCI base 107 * to the resource type 108 */ 109 static inline unsigned int pci_calc_resource_flags(unsigned int flags) 110 { 111 if (flags & PCI_BASE_ADDRESS_SPACE_IO) 112 return IORESOURCE_IO; 113 114 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 115 return IORESOURCE_MEM | IORESOURCE_PREFETCH; 116 117 return IORESOURCE_MEM; 118 } 119 120 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 121 { 122 u64 size = mask & maxbase; /* Find the significant bits */ 123 if (!size) 124 return 0; 125 126 /* Get the lowest of them to find the decode size, and 127 from that the extent. */ 128 size = (size & ~(size-1)) - 1; 129 130 /* base == maxbase can be valid only if the BAR has 131 already been programmed with all 1s. */ 132 if (base == maxbase && ((base | size) & mask) != mask) 133 return 0; 134 135 return size; 136 } 137 138 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) 139 { 140 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 141 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 142 return pci_bar_io; 143 } 144 145 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 146 147 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 148 return pci_bar_mem64; 149 return pci_bar_mem32; 150 } 151 152 /** 153 * pci_read_base - read a PCI BAR 154 * @dev: the PCI device 155 * @type: type of the BAR 156 * @res: resource buffer to be filled in 157 * @pos: BAR position in the config space 158 * 159 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 160 */ 161 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 162 struct resource *res, unsigned int pos) 163 { 164 u32 l, sz, mask; 165 166 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0; 167 168 res->name = pci_name(dev); 169 170 pci_read_config_dword(dev, pos, &l); 171 pci_write_config_dword(dev, pos, mask); 172 pci_read_config_dword(dev, pos, &sz); 173 pci_write_config_dword(dev, pos, l); 174 175 /* 176 * All bits set in sz means the device isn't working properly. 177 * If the BAR isn't implemented, all bits must be 0. If it's a 178 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 179 * 1 must be clear. 180 */ 181 if (!sz || sz == 0xffffffff) 182 goto fail; 183 184 /* 185 * I don't know how l can have all bits set. Copied from old code. 186 * Maybe it fixes a bug on some ancient platform. 187 */ 188 if (l == 0xffffffff) 189 l = 0; 190 191 if (type == pci_bar_unknown) { 192 type = decode_bar(res, l); 193 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; 194 if (type == pci_bar_io) { 195 l &= PCI_BASE_ADDRESS_IO_MASK; 196 mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff; 197 } else { 198 l &= PCI_BASE_ADDRESS_MEM_MASK; 199 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 200 } 201 } else { 202 res->flags |= (l & IORESOURCE_ROM_ENABLE); 203 l &= PCI_ROM_ADDRESS_MASK; 204 mask = (u32)PCI_ROM_ADDRESS_MASK; 205 } 206 207 if (type == pci_bar_mem64) { 208 u64 l64 = l; 209 u64 sz64 = sz; 210 u64 mask64 = mask | (u64)~0 << 32; 211 212 pci_read_config_dword(dev, pos + 4, &l); 213 pci_write_config_dword(dev, pos + 4, ~0); 214 pci_read_config_dword(dev, pos + 4, &sz); 215 pci_write_config_dword(dev, pos + 4, l); 216 217 l64 |= ((u64)l << 32); 218 sz64 |= ((u64)sz << 32); 219 220 sz64 = pci_size(l64, sz64, mask64); 221 222 if (!sz64) 223 goto fail; 224 225 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 226 dev_err(&dev->dev, "can't handle 64-bit BAR\n"); 227 goto fail; 228 } else if ((sizeof(resource_size_t) < 8) && l) { 229 /* Address above 32-bit boundary; disable the BAR */ 230 pci_write_config_dword(dev, pos, 0); 231 pci_write_config_dword(dev, pos + 4, 0); 232 res->start = 0; 233 res->end = sz64; 234 } else { 235 res->start = l64; 236 res->end = l64 + sz64; 237 dev_printk(KERN_DEBUG, &dev->dev, 238 "reg %x 64bit mmio: %pR\n", pos, res); 239 } 240 } else { 241 sz = pci_size(l, sz, mask); 242 243 if (!sz) 244 goto fail; 245 246 res->start = l; 247 res->end = l + sz; 248 249 dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos, 250 (res->flags & IORESOURCE_IO) ? "io port" : "32bit mmio", 251 res); 252 } 253 254 out: 255 return (type == pci_bar_mem64) ? 1 : 0; 256 fail: 257 res->flags = 0; 258 goto out; 259 } 260 261 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 262 { 263 unsigned int pos, reg; 264 265 for (pos = 0; pos < howmany; pos++) { 266 struct resource *res = &dev->resource[pos]; 267 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 268 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 269 } 270 271 if (rom) { 272 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 273 dev->rom_base_reg = rom; 274 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 275 IORESOURCE_READONLY | IORESOURCE_CACHEABLE | 276 IORESOURCE_SIZEALIGN; 277 __pci_read_base(dev, pci_bar_mem32, res, rom); 278 } 279 } 280 281 void __devinit pci_read_bridge_bases(struct pci_bus *child) 282 { 283 struct pci_dev *dev = child->self; 284 u8 io_base_lo, io_limit_lo; 285 u16 mem_base_lo, mem_limit_lo; 286 unsigned long base, limit; 287 struct resource *res; 288 int i; 289 290 if (!dev) /* It's a host bus, nothing to read */ 291 return; 292 293 if (dev->transparent) { 294 dev_info(&dev->dev, "transparent bridge\n"); 295 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) 296 child->resource[i] = child->parent->resource[i - 3]; 297 } 298 299 res = child->resource[0]; 300 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 301 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 302 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 303 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 304 305 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 306 u16 io_base_hi, io_limit_hi; 307 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 308 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 309 base |= (io_base_hi << 16); 310 limit |= (io_limit_hi << 16); 311 } 312 313 if (base <= limit) { 314 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 315 if (!res->start) 316 res->start = base; 317 if (!res->end) 318 res->end = limit + 0xfff; 319 dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res); 320 } 321 322 res = child->resource[1]; 323 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 324 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 325 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 326 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 327 if (base <= limit) { 328 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 329 res->start = base; 330 res->end = limit + 0xfffff; 331 dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n", 332 res); 333 } 334 335 res = child->resource[2]; 336 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 337 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 338 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 339 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 340 341 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 342 u32 mem_base_hi, mem_limit_hi; 343 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 344 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 345 346 /* 347 * Some bridges set the base > limit by default, and some 348 * (broken) BIOSes do not initialize them. If we find 349 * this, just assume they are not being used. 350 */ 351 if (mem_base_hi <= mem_limit_hi) { 352 #if BITS_PER_LONG == 64 353 base |= ((long) mem_base_hi) << 32; 354 limit |= ((long) mem_limit_hi) << 32; 355 #else 356 if (mem_base_hi || mem_limit_hi) { 357 dev_err(&dev->dev, "can't handle 64-bit " 358 "address space for bridge\n"); 359 return; 360 } 361 #endif 362 } 363 } 364 if (base <= limit) { 365 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; 366 res->start = base; 367 res->end = limit + 0xfffff; 368 dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n", 369 (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32", 370 res); 371 } 372 } 373 374 static struct pci_bus * pci_alloc_bus(void) 375 { 376 struct pci_bus *b; 377 378 b = kzalloc(sizeof(*b), GFP_KERNEL); 379 if (b) { 380 INIT_LIST_HEAD(&b->node); 381 INIT_LIST_HEAD(&b->children); 382 INIT_LIST_HEAD(&b->devices); 383 INIT_LIST_HEAD(&b->slots); 384 } 385 return b; 386 } 387 388 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 389 struct pci_dev *bridge, int busnr) 390 { 391 struct pci_bus *child; 392 int i; 393 394 /* 395 * Allocate a new bus, and inherit stuff from the parent.. 396 */ 397 child = pci_alloc_bus(); 398 if (!child) 399 return NULL; 400 401 child->parent = parent; 402 child->ops = parent->ops; 403 child->sysdata = parent->sysdata; 404 child->bus_flags = parent->bus_flags; 405 406 /* initialize some portions of the bus device, but don't register it 407 * now as the parent is not properly set up yet. This device will get 408 * registered later in pci_bus_add_devices() 409 */ 410 child->dev.class = &pcibus_class; 411 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 412 413 /* 414 * Set up the primary, secondary and subordinate 415 * bus numbers. 416 */ 417 child->number = child->secondary = busnr; 418 child->primary = parent->secondary; 419 child->subordinate = 0xff; 420 421 if (!bridge) 422 return child; 423 424 child->self = bridge; 425 child->bridge = get_device(&bridge->dev); 426 427 /* Set up default resource pointers and names.. */ 428 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 429 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 430 child->resource[i]->name = child->name; 431 } 432 bridge->subordinate = child; 433 434 return child; 435 } 436 437 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) 438 { 439 struct pci_bus *child; 440 441 child = pci_alloc_child_bus(parent, dev, busnr); 442 if (child) { 443 down_write(&pci_bus_sem); 444 list_add_tail(&child->node, &parent->children); 445 up_write(&pci_bus_sem); 446 } 447 return child; 448 } 449 450 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) 451 { 452 struct pci_bus *parent = child->parent; 453 454 /* Attempts to fix that up are really dangerous unless 455 we're going to re-assign all bus numbers. */ 456 if (!pcibios_assign_all_busses()) 457 return; 458 459 while (parent->parent && parent->subordinate < max) { 460 parent->subordinate = max; 461 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); 462 parent = parent->parent; 463 } 464 } 465 466 /* 467 * If it's a bridge, configure it and scan the bus behind it. 468 * For CardBus bridges, we don't scan behind as the devices will 469 * be handled by the bridge driver itself. 470 * 471 * We need to process bridges in two passes -- first we scan those 472 * already configured by the BIOS and after we are done with all of 473 * them, we proceed to assigning numbers to the remaining buses in 474 * order to avoid overlaps between old and new bus numbers. 475 */ 476 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 477 { 478 struct pci_bus *child; 479 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 480 u32 buses, i, j = 0; 481 u16 bctl; 482 int broken = 0; 483 484 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 485 486 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", 487 buses & 0xffffff, pass); 488 489 /* Check if setup is sensible at all */ 490 if (!pass && 491 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) { 492 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); 493 broken = 1; 494 } 495 496 /* Disable MasterAbortMode during probing to avoid reporting 497 of bus errors (in some architectures) */ 498 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 499 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 500 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 501 502 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) { 503 unsigned int cmax, busnr; 504 /* 505 * Bus already configured by firmware, process it in the first 506 * pass and just note the configuration. 507 */ 508 if (pass) 509 goto out; 510 busnr = (buses >> 8) & 0xFF; 511 512 /* 513 * If we already got to this bus through a different bridge, 514 * ignore it. This can happen with the i450NX chipset. 515 */ 516 if (pci_find_bus(pci_domain_nr(bus), busnr)) { 517 dev_info(&dev->dev, "bus %04x:%02x already known\n", 518 pci_domain_nr(bus), busnr); 519 goto out; 520 } 521 522 child = pci_add_new_bus(bus, dev, busnr); 523 if (!child) 524 goto out; 525 child->primary = buses & 0xFF; 526 child->subordinate = (buses >> 16) & 0xFF; 527 child->bridge_ctl = bctl; 528 529 cmax = pci_scan_child_bus(child); 530 if (cmax > max) 531 max = cmax; 532 if (child->subordinate > max) 533 max = child->subordinate; 534 } else { 535 /* 536 * We need to assign a number to this bus which we always 537 * do in the second pass. 538 */ 539 if (!pass) { 540 if (pcibios_assign_all_busses() || broken) 541 /* Temporarily disable forwarding of the 542 configuration cycles on all bridges in 543 this bus segment to avoid possible 544 conflicts in the second pass between two 545 bridges programmed with overlapping 546 bus ranges. */ 547 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 548 buses & ~0xffffff); 549 goto out; 550 } 551 552 /* Clear errors */ 553 pci_write_config_word(dev, PCI_STATUS, 0xffff); 554 555 /* Prevent assigning a bus number that already exists. 556 * This can happen when a bridge is hot-plugged */ 557 if (pci_find_bus(pci_domain_nr(bus), max+1)) 558 goto out; 559 child = pci_add_new_bus(bus, dev, ++max); 560 buses = (buses & 0xff000000) 561 | ((unsigned int)(child->primary) << 0) 562 | ((unsigned int)(child->secondary) << 8) 563 | ((unsigned int)(child->subordinate) << 16); 564 565 /* 566 * yenta.c forces a secondary latency timer of 176. 567 * Copy that behaviour here. 568 */ 569 if (is_cardbus) { 570 buses &= ~0xff000000; 571 buses |= CARDBUS_LATENCY_TIMER << 24; 572 } 573 574 /* 575 * We need to blast all three values with a single write. 576 */ 577 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 578 579 if (!is_cardbus) { 580 child->bridge_ctl = bctl; 581 /* 582 * Adjust subordinate busnr in parent buses. 583 * We do this before scanning for children because 584 * some devices may not be detected if the bios 585 * was lazy. 586 */ 587 pci_fixup_parent_subordinate_busnr(child, max); 588 /* Now we can scan all subordinate buses... */ 589 max = pci_scan_child_bus(child); 590 /* 591 * now fix it up again since we have found 592 * the real value of max. 593 */ 594 pci_fixup_parent_subordinate_busnr(child, max); 595 } else { 596 /* 597 * For CardBus bridges, we leave 4 bus numbers 598 * as cards with a PCI-to-PCI bridge can be 599 * inserted later. 600 */ 601 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { 602 struct pci_bus *parent = bus; 603 if (pci_find_bus(pci_domain_nr(bus), 604 max+i+1)) 605 break; 606 while (parent->parent) { 607 if ((!pcibios_assign_all_busses()) && 608 (parent->subordinate > max) && 609 (parent->subordinate <= max+i)) { 610 j = 1; 611 } 612 parent = parent->parent; 613 } 614 if (j) { 615 /* 616 * Often, there are two cardbus bridges 617 * -- try to leave one valid bus number 618 * for each one. 619 */ 620 i /= 2; 621 break; 622 } 623 } 624 max += i; 625 pci_fixup_parent_subordinate_busnr(child, max); 626 } 627 /* 628 * Set the subordinate bus number to its real value. 629 */ 630 child->subordinate = max; 631 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 632 } 633 634 sprintf(child->name, 635 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 636 pci_domain_nr(bus), child->number); 637 638 /* Has only triggered on CardBus, fixup is in yenta_socket */ 639 while (bus->parent) { 640 if ((child->subordinate > bus->subordinate) || 641 (child->number > bus->subordinate) || 642 (child->number < bus->number) || 643 (child->subordinate < bus->number)) { 644 pr_debug("PCI: Bus #%02x (-#%02x) is %s " 645 "hidden behind%s bridge #%02x (-#%02x)\n", 646 child->number, child->subordinate, 647 (bus->number > child->subordinate && 648 bus->subordinate < child->number) ? 649 "wholly" : "partially", 650 bus->self->transparent ? " transparent" : "", 651 bus->number, bus->subordinate); 652 } 653 bus = bus->parent; 654 } 655 656 out: 657 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 658 659 return max; 660 } 661 662 /* 663 * Read interrupt line and base address registers. 664 * The architecture-dependent code can tweak these, of course. 665 */ 666 static void pci_read_irq(struct pci_dev *dev) 667 { 668 unsigned char irq; 669 670 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 671 dev->pin = irq; 672 if (irq) 673 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 674 dev->irq = irq; 675 } 676 677 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 678 679 /** 680 * pci_setup_device - fill in class and map information of a device 681 * @dev: the device structure to fill 682 * 683 * Initialize the device structure with information about the device's 684 * vendor,class,memory and IO-space addresses,IRQ lines etc. 685 * Called at initialisation of the PCI subsystem and by CardBus services. 686 * Returns 0 on success and -1 if unknown type of device (not normal, bridge 687 * or CardBus). 688 */ 689 static int pci_setup_device(struct pci_dev * dev) 690 { 691 u32 class; 692 693 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 694 dev->bus->number, PCI_SLOT(dev->devfn), 695 PCI_FUNC(dev->devfn)); 696 697 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 698 dev->revision = class & 0xff; 699 class >>= 8; /* upper 3 bytes */ 700 dev->class = class; 701 class >>= 8; 702 703 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n", 704 dev->vendor, dev->device, class, dev->hdr_type); 705 706 /* "Unknown power state" */ 707 dev->current_state = PCI_UNKNOWN; 708 709 /* Early fixups, before probing the BARs */ 710 pci_fixup_device(pci_fixup_early, dev); 711 class = dev->class >> 8; 712 713 switch (dev->hdr_type) { /* header type */ 714 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 715 if (class == PCI_CLASS_BRIDGE_PCI) 716 goto bad; 717 pci_read_irq(dev); 718 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 719 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 720 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); 721 722 /* 723 * Do the ugly legacy mode stuff here rather than broken chip 724 * quirk code. Legacy mode ATA controllers have fixed 725 * addresses. These are not always echoed in BAR0-3, and 726 * BAR0-3 in a few cases contain junk! 727 */ 728 if (class == PCI_CLASS_STORAGE_IDE) { 729 u8 progif; 730 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 731 if ((progif & 1) == 0) { 732 dev->resource[0].start = 0x1F0; 733 dev->resource[0].end = 0x1F7; 734 dev->resource[0].flags = LEGACY_IO_RESOURCE; 735 dev->resource[1].start = 0x3F6; 736 dev->resource[1].end = 0x3F6; 737 dev->resource[1].flags = LEGACY_IO_RESOURCE; 738 } 739 if ((progif & 4) == 0) { 740 dev->resource[2].start = 0x170; 741 dev->resource[2].end = 0x177; 742 dev->resource[2].flags = LEGACY_IO_RESOURCE; 743 dev->resource[3].start = 0x376; 744 dev->resource[3].end = 0x376; 745 dev->resource[3].flags = LEGACY_IO_RESOURCE; 746 } 747 } 748 break; 749 750 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 751 if (class != PCI_CLASS_BRIDGE_PCI) 752 goto bad; 753 /* The PCI-to-PCI bridge spec requires that subtractive 754 decoding (i.e. transparent) bridge must have programming 755 interface code of 0x01. */ 756 pci_read_irq(dev); 757 dev->transparent = ((dev->class & 0xff) == 1); 758 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 759 break; 760 761 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 762 if (class != PCI_CLASS_BRIDGE_CARDBUS) 763 goto bad; 764 pci_read_irq(dev); 765 pci_read_bases(dev, 1, 0); 766 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 767 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 768 break; 769 770 default: /* unknown header */ 771 dev_err(&dev->dev, "unknown header type %02x, " 772 "ignoring device\n", dev->hdr_type); 773 return -1; 774 775 bad: 776 dev_err(&dev->dev, "ignoring class %02x (doesn't match header " 777 "type %02x)\n", class, dev->hdr_type); 778 dev->class = PCI_CLASS_NOT_DEFINED; 779 } 780 781 /* We found a fine healthy device, go go go... */ 782 return 0; 783 } 784 785 static void pci_release_capabilities(struct pci_dev *dev) 786 { 787 pci_vpd_release(dev); 788 } 789 790 /** 791 * pci_release_dev - free a pci device structure when all users of it are finished. 792 * @dev: device that's been disconnected 793 * 794 * Will be called only by the device core when all users of this pci device are 795 * done. 796 */ 797 static void pci_release_dev(struct device *dev) 798 { 799 struct pci_dev *pci_dev; 800 801 pci_dev = to_pci_dev(dev); 802 pci_release_capabilities(pci_dev); 803 kfree(pci_dev); 804 } 805 806 static void set_pcie_port_type(struct pci_dev *pdev) 807 { 808 int pos; 809 u16 reg16; 810 811 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 812 if (!pos) 813 return; 814 pdev->is_pcie = 1; 815 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 816 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; 817 } 818 819 /** 820 * pci_cfg_space_size - get the configuration space size of the PCI device. 821 * @dev: PCI device 822 * 823 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 824 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 825 * access it. Maybe we don't have a way to generate extended config space 826 * accesses, or the device is behind a reverse Express bridge. So we try 827 * reading the dword at 0x100 which must either be 0 or a valid extended 828 * capability header. 829 */ 830 int pci_cfg_space_size_ext(struct pci_dev *dev) 831 { 832 u32 status; 833 int pos = PCI_CFG_SPACE_SIZE; 834 835 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 836 goto fail; 837 if (status == 0xffffffff) 838 goto fail; 839 840 return PCI_CFG_SPACE_EXP_SIZE; 841 842 fail: 843 return PCI_CFG_SPACE_SIZE; 844 } 845 846 int pci_cfg_space_size(struct pci_dev *dev) 847 { 848 int pos; 849 u32 status; 850 851 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 852 if (!pos) { 853 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 854 if (!pos) 855 goto fail; 856 857 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 858 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) 859 goto fail; 860 } 861 862 return pci_cfg_space_size_ext(dev); 863 864 fail: 865 return PCI_CFG_SPACE_SIZE; 866 } 867 868 static void pci_release_bus_bridge_dev(struct device *dev) 869 { 870 kfree(dev); 871 } 872 873 struct pci_dev *alloc_pci_dev(void) 874 { 875 struct pci_dev *dev; 876 877 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 878 if (!dev) 879 return NULL; 880 881 INIT_LIST_HEAD(&dev->bus_list); 882 883 return dev; 884 } 885 EXPORT_SYMBOL(alloc_pci_dev); 886 887 /* 888 * Read the config data for a PCI device, sanity-check it 889 * and fill in the dev structure... 890 */ 891 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 892 { 893 struct pci_dev *dev; 894 struct pci_slot *slot; 895 u32 l; 896 u8 hdr_type; 897 int delay = 1; 898 899 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 900 return NULL; 901 902 /* some broken boards return 0 or ~0 if a slot is empty: */ 903 if (l == 0xffffffff || l == 0x00000000 || 904 l == 0x0000ffff || l == 0xffff0000) 905 return NULL; 906 907 /* Configuration request Retry Status */ 908 while (l == 0xffff0001) { 909 msleep(delay); 910 delay *= 2; 911 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 912 return NULL; 913 /* Card hasn't responded in 60 seconds? Must be stuck. */ 914 if (delay > 60 * 1000) { 915 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " 916 "responding\n", pci_domain_nr(bus), 917 bus->number, PCI_SLOT(devfn), 918 PCI_FUNC(devfn)); 919 return NULL; 920 } 921 } 922 923 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type)) 924 return NULL; 925 926 dev = alloc_pci_dev(); 927 if (!dev) 928 return NULL; 929 930 dev->bus = bus; 931 dev->sysdata = bus->sysdata; 932 dev->dev.parent = bus->bridge; 933 dev->dev.bus = &pci_bus_type; 934 dev->devfn = devfn; 935 dev->hdr_type = hdr_type & 0x7f; 936 dev->multifunction = !!(hdr_type & 0x80); 937 dev->vendor = l & 0xffff; 938 dev->device = (l >> 16) & 0xffff; 939 dev->cfg_size = pci_cfg_space_size(dev); 940 dev->error_state = pci_channel_io_normal; 941 set_pcie_port_type(dev); 942 943 list_for_each_entry(slot, &bus->slots, list) 944 if (PCI_SLOT(devfn) == slot->number) 945 dev->slot = slot; 946 947 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 948 set this higher, assuming the system even supports it. */ 949 dev->dma_mask = 0xffffffff; 950 if (pci_setup_device(dev) < 0) { 951 kfree(dev); 952 return NULL; 953 } 954 955 return dev; 956 } 957 958 static void pci_init_capabilities(struct pci_dev *dev) 959 { 960 /* MSI/MSI-X list */ 961 pci_msi_init_pci_dev(dev); 962 963 /* Buffers for saving PCIe and PCI-X capabilities */ 964 pci_allocate_cap_save_buffers(dev); 965 966 /* Power Management */ 967 pci_pm_init(dev); 968 platform_pci_wakeup_init(dev); 969 970 /* Vital Product Data */ 971 pci_vpd_pci22_init(dev); 972 973 /* Alternative Routing-ID Forwarding */ 974 pci_enable_ari(dev); 975 } 976 977 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 978 { 979 device_initialize(&dev->dev); 980 dev->dev.release = pci_release_dev; 981 pci_dev_get(dev); 982 983 dev->dev.dma_mask = &dev->dma_mask; 984 dev->dev.dma_parms = &dev->dma_parms; 985 dev->dev.coherent_dma_mask = 0xffffffffull; 986 987 pci_set_dma_max_seg_size(dev, 65536); 988 pci_set_dma_seg_boundary(dev, 0xffffffff); 989 990 /* Fix up broken headers */ 991 pci_fixup_device(pci_fixup_header, dev); 992 993 /* Initialize various capabilities */ 994 pci_init_capabilities(dev); 995 996 /* 997 * Add the device to our list of discovered devices 998 * and the bus list for fixup functions, etc. 999 */ 1000 down_write(&pci_bus_sem); 1001 list_add_tail(&dev->bus_list, &bus->devices); 1002 up_write(&pci_bus_sem); 1003 } 1004 1005 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) 1006 { 1007 struct pci_dev *dev; 1008 1009 dev = pci_scan_device(bus, devfn); 1010 if (!dev) 1011 return NULL; 1012 1013 pci_device_add(dev, bus); 1014 1015 return dev; 1016 } 1017 EXPORT_SYMBOL(pci_scan_single_device); 1018 1019 /** 1020 * pci_scan_slot - scan a PCI slot on a bus for devices. 1021 * @bus: PCI bus to scan 1022 * @devfn: slot number to scan (must have zero function.) 1023 * 1024 * Scan a PCI slot on the specified PCI bus for devices, adding 1025 * discovered devices to the @bus->devices list. New devices 1026 * will not have is_added set. 1027 */ 1028 int pci_scan_slot(struct pci_bus *bus, int devfn) 1029 { 1030 int func, nr = 0; 1031 int scan_all_fns; 1032 1033 scan_all_fns = pcibios_scan_all_fns(bus, devfn); 1034 1035 for (func = 0; func < 8; func++, devfn++) { 1036 struct pci_dev *dev; 1037 1038 dev = pci_scan_single_device(bus, devfn); 1039 if (dev) { 1040 nr++; 1041 1042 /* 1043 * If this is a single function device, 1044 * don't scan past the first function. 1045 */ 1046 if (!dev->multifunction) { 1047 if (func > 0) { 1048 dev->multifunction = 1; 1049 } else { 1050 break; 1051 } 1052 } 1053 } else { 1054 if (func == 0 && !scan_all_fns) 1055 break; 1056 } 1057 } 1058 1059 /* only one slot has pcie device */ 1060 if (bus->self && nr) 1061 pcie_aspm_init_link_state(bus->self); 1062 1063 return nr; 1064 } 1065 1066 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) 1067 { 1068 unsigned int devfn, pass, max = bus->secondary; 1069 struct pci_dev *dev; 1070 1071 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); 1072 1073 /* Go find them, Rover! */ 1074 for (devfn = 0; devfn < 0x100; devfn += 8) 1075 pci_scan_slot(bus, devfn); 1076 1077 /* 1078 * After performing arch-dependent fixup of the bus, look behind 1079 * all PCI-to-PCI bridges on this bus. 1080 */ 1081 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number); 1082 pcibios_fixup_bus(bus); 1083 for (pass=0; pass < 2; pass++) 1084 list_for_each_entry(dev, &bus->devices, bus_list) { 1085 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1086 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1087 max = pci_scan_bridge(bus, dev, max, pass); 1088 } 1089 1090 /* 1091 * We've scanned the bus and so we know all about what's on 1092 * the other side of any bridges that may be on this bus plus 1093 * any devices. 1094 * 1095 * Return how far we've got finding sub-buses. 1096 */ 1097 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", 1098 pci_domain_nr(bus), bus->number, max); 1099 return max; 1100 } 1101 1102 void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b) 1103 { 1104 } 1105 1106 struct pci_bus * pci_create_bus(struct device *parent, 1107 int bus, struct pci_ops *ops, void *sysdata) 1108 { 1109 int error; 1110 struct pci_bus *b; 1111 struct device *dev; 1112 1113 b = pci_alloc_bus(); 1114 if (!b) 1115 return NULL; 1116 1117 dev = kmalloc(sizeof(*dev), GFP_KERNEL); 1118 if (!dev){ 1119 kfree(b); 1120 return NULL; 1121 } 1122 1123 b->sysdata = sysdata; 1124 b->ops = ops; 1125 1126 if (pci_find_bus(pci_domain_nr(b), bus)) { 1127 /* If we already got to this bus through a different bridge, ignore it */ 1128 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); 1129 goto err_out; 1130 } 1131 1132 down_write(&pci_bus_sem); 1133 list_add_tail(&b->node, &pci_root_buses); 1134 up_write(&pci_bus_sem); 1135 1136 memset(dev, 0, sizeof(*dev)); 1137 dev->parent = parent; 1138 dev->release = pci_release_bus_bridge_dev; 1139 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); 1140 error = device_register(dev); 1141 if (error) 1142 goto dev_reg_err; 1143 b->bridge = get_device(dev); 1144 1145 if (!parent) 1146 set_dev_node(b->bridge, pcibus_to_node(b)); 1147 1148 b->dev.class = &pcibus_class; 1149 b->dev.parent = b->bridge; 1150 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); 1151 error = device_register(&b->dev); 1152 if (error) 1153 goto class_dev_reg_err; 1154 error = device_create_file(&b->dev, &dev_attr_cpuaffinity); 1155 if (error) 1156 goto dev_create_file_err; 1157 1158 /* Create legacy_io and legacy_mem files for this bus */ 1159 pci_create_legacy_files(b); 1160 1161 b->number = b->secondary = bus; 1162 b->resource[0] = &ioport_resource; 1163 b->resource[1] = &iomem_resource; 1164 1165 set_pci_bus_resources_arch_default(b); 1166 1167 return b; 1168 1169 dev_create_file_err: 1170 device_unregister(&b->dev); 1171 class_dev_reg_err: 1172 device_unregister(dev); 1173 dev_reg_err: 1174 down_write(&pci_bus_sem); 1175 list_del(&b->node); 1176 up_write(&pci_bus_sem); 1177 err_out: 1178 kfree(dev); 1179 kfree(b); 1180 return NULL; 1181 } 1182 1183 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, 1184 int bus, struct pci_ops *ops, void *sysdata) 1185 { 1186 struct pci_bus *b; 1187 1188 b = pci_create_bus(parent, bus, ops, sysdata); 1189 if (b) 1190 b->subordinate = pci_scan_child_bus(b); 1191 return b; 1192 } 1193 EXPORT_SYMBOL(pci_scan_bus_parented); 1194 1195 #ifdef CONFIG_HOTPLUG 1196 EXPORT_SYMBOL(pci_add_new_bus); 1197 EXPORT_SYMBOL(pci_scan_slot); 1198 EXPORT_SYMBOL(pci_scan_bridge); 1199 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 1200 #endif 1201 1202 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) 1203 { 1204 const struct pci_dev *a = to_pci_dev(d_a); 1205 const struct pci_dev *b = to_pci_dev(d_b); 1206 1207 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 1208 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 1209 1210 if (a->bus->number < b->bus->number) return -1; 1211 else if (a->bus->number > b->bus->number) return 1; 1212 1213 if (a->devfn < b->devfn) return -1; 1214 else if (a->devfn > b->devfn) return 1; 1215 1216 return 0; 1217 } 1218 1219 void __init pci_sort_breadthfirst(void) 1220 { 1221 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 1222 } 1223