1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_pci.h> 12 #include <linux/pci_hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/cpumask.h> 16 #include <linux/aer.h> 17 #include <linux/acpi.h> 18 #include <linux/hypervisor.h> 19 #include <linux/irqdomain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/bitfield.h> 22 #include "pci.h" 23 24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 25 #define CARDBUS_RESERVE_BUSNR 3 26 27 static struct resource busn_resource = { 28 .name = "PCI busn", 29 .start = 0, 30 .end = 255, 31 .flags = IORESOURCE_BUS, 32 }; 33 34 /* Ugh. Need to stop exporting this to modules. */ 35 LIST_HEAD(pci_root_buses); 36 EXPORT_SYMBOL(pci_root_buses); 37 38 static LIST_HEAD(pci_domain_busn_res_list); 39 40 struct pci_domain_busn_res { 41 struct list_head list; 42 struct resource res; 43 int domain_nr; 44 }; 45 46 static struct resource *get_pci_domain_busn_res(int domain_nr) 47 { 48 struct pci_domain_busn_res *r; 49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list) 51 if (r->domain_nr == domain_nr) 52 return &r->res; 53 54 r = kzalloc(sizeof(*r), GFP_KERNEL); 55 if (!r) 56 return NULL; 57 58 r->domain_nr = domain_nr; 59 r->res.start = 0; 60 r->res.end = 0xff; 61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 62 63 list_add_tail(&r->list, &pci_domain_busn_res_list); 64 65 return &r->res; 66 } 67 68 /* 69 * Some device drivers need know if PCI is initiated. 70 * Basically, we think PCI is not initiated when there 71 * is no device to be found on the pci_bus_type. 72 */ 73 int no_pci_devices(void) 74 { 75 struct device *dev; 76 int no_devices; 77 78 dev = bus_find_next_device(&pci_bus_type, NULL); 79 no_devices = (dev == NULL); 80 put_device(dev); 81 return no_devices; 82 } 83 EXPORT_SYMBOL(no_pci_devices); 84 85 /* 86 * PCI Bus Class 87 */ 88 static void release_pcibus_dev(struct device *dev) 89 { 90 struct pci_bus *pci_bus = to_pci_bus(dev); 91 92 put_device(pci_bus->bridge); 93 pci_bus_remove_resources(pci_bus); 94 pci_release_bus_of_node(pci_bus); 95 kfree(pci_bus); 96 } 97 98 static const struct class pcibus_class = { 99 .name = "pci_bus", 100 .dev_release = &release_pcibus_dev, 101 .dev_groups = pcibus_groups, 102 }; 103 104 static int __init pcibus_class_init(void) 105 { 106 return class_register(&pcibus_class); 107 } 108 postcore_initcall(pcibus_class_init); 109 110 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 111 { 112 u64 size = mask & maxbase; /* Find the significant bits */ 113 if (!size) 114 return 0; 115 116 /* 117 * Get the lowest of them to find the decode size, and from that 118 * the extent. 119 */ 120 size = size & ~(size-1); 121 122 /* 123 * base == maxbase can be valid only if the BAR has already been 124 * programmed with all 1s. 125 */ 126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 127 return 0; 128 129 return size; 130 } 131 132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 133 { 134 u32 mem_type; 135 unsigned long flags; 136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 139 flags |= IORESOURCE_IO; 140 return flags; 141 } 142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 144 flags |= IORESOURCE_MEM; 145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 146 flags |= IORESOURCE_PREFETCH; 147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 149 switch (mem_type) { 150 case PCI_BASE_ADDRESS_MEM_TYPE_32: 151 break; 152 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 153 /* 1M mem BAR treated as 32-bit BAR */ 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_64: 156 flags |= IORESOURCE_MEM_64; 157 break; 158 default: 159 /* mem unknown type treated as 32-bit BAR */ 160 break; 161 } 162 return flags; 163 } 164 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 167 /** 168 * __pci_read_base - Read a PCI BAR 169 * @dev: the PCI device 170 * @type: type of the BAR 171 * @res: resource buffer to be filled in 172 * @pos: BAR position in the config space 173 * 174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 175 */ 176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 177 struct resource *res, unsigned int pos) 178 { 179 u32 l = 0, sz = 0, mask; 180 u64 l64, sz64, mask64; 181 u16 orig_cmd; 182 struct pci_bus_region region, inverted_region; 183 const char *res_name = pci_resource_name(dev, res - dev->resource); 184 185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 186 187 /* No printks while decoding is disabled! */ 188 if (!dev->mmio_always_on) { 189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 191 pci_write_config_word(dev, PCI_COMMAND, 192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 193 } 194 } 195 196 res->name = pci_name(dev); 197 198 pci_read_config_dword(dev, pos, &l); 199 pci_write_config_dword(dev, pos, l | mask); 200 pci_read_config_dword(dev, pos, &sz); 201 pci_write_config_dword(dev, pos, l); 202 203 /* 204 * All bits set in sz means the device isn't working properly. 205 * If the BAR isn't implemented, all bits must be 0. If it's a 206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 207 * 1 must be clear. 208 */ 209 if (PCI_POSSIBLE_ERROR(sz)) 210 sz = 0; 211 212 /* 213 * I don't know how l can have all bits set. Copied from old code. 214 * Maybe it fixes a bug on some ancient platform. 215 */ 216 if (PCI_POSSIBLE_ERROR(l)) 217 l = 0; 218 219 if (type == pci_bar_unknown) { 220 res->flags = decode_bar(dev, l); 221 res->flags |= IORESOURCE_SIZEALIGN; 222 if (res->flags & IORESOURCE_IO) { 223 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 226 } else { 227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 230 } 231 } else { 232 if (l & PCI_ROM_ADDRESS_ENABLE) 233 res->flags |= IORESOURCE_ROM_ENABLE; 234 l64 = l & PCI_ROM_ADDRESS_MASK; 235 sz64 = sz & PCI_ROM_ADDRESS_MASK; 236 mask64 = PCI_ROM_ADDRESS_MASK; 237 } 238 239 if (res->flags & IORESOURCE_MEM_64) { 240 pci_read_config_dword(dev, pos + 4, &l); 241 pci_write_config_dword(dev, pos + 4, ~0); 242 pci_read_config_dword(dev, pos + 4, &sz); 243 pci_write_config_dword(dev, pos + 4, l); 244 245 l64 |= ((u64)l << 32); 246 sz64 |= ((u64)sz << 32); 247 mask64 |= ((u64)~0 << 32); 248 } 249 250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 252 253 if (!sz64) 254 goto fail; 255 256 sz64 = pci_size(l64, sz64, mask64); 257 if (!sz64) { 258 pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name); 259 goto fail; 260 } 261 262 if (res->flags & IORESOURCE_MEM_64) { 263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 264 && sz64 > 0x100000000ULL) { 265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 266 res->start = 0; 267 res->end = 0; 268 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n", 269 res_name, (unsigned long long)sz64); 270 goto out; 271 } 272 273 if ((sizeof(pci_bus_addr_t) < 8) && l) { 274 /* Above 32-bit boundary; try to reallocate */ 275 res->flags |= IORESOURCE_UNSET; 276 res->start = 0; 277 res->end = sz64 - 1; 278 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n", 279 res_name, (unsigned long long)l64); 280 goto out; 281 } 282 } 283 284 region.start = l64; 285 region.end = l64 + sz64 - 1; 286 287 pcibios_bus_to_resource(dev->bus, res, ®ion); 288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 289 290 /* 291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 292 * the corresponding resource address (the physical address used by 293 * the CPU. Converting that resource address back to a bus address 294 * should yield the original BAR value: 295 * 296 * resource_to_bus(bus_to_resource(A)) == A 297 * 298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 299 * be claimed by the device. 300 */ 301 if (inverted_region.start != region.start) { 302 res->flags |= IORESOURCE_UNSET; 303 res->start = 0; 304 res->end = region.end - region.start; 305 pci_info(dev, "%s: initial BAR value %#010llx invalid\n", 306 res_name, (unsigned long long)region.start); 307 } 308 309 goto out; 310 311 312 fail: 313 res->flags = 0; 314 out: 315 if (res->flags) 316 pci_info(dev, "%s %pR\n", res_name, res); 317 318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 319 } 320 321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 322 { 323 unsigned int pos, reg; 324 325 if (dev->non_compliant_bars) 326 return; 327 328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 329 if (dev->is_virtfn) 330 return; 331 332 for (pos = 0; pos < howmany; pos++) { 333 struct resource *res = &dev->resource[pos]; 334 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 336 } 337 338 if (rom) { 339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 340 dev->rom_base_reg = rom; 341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 343 __pci_read_base(dev, pci_bar_mem32, res, rom); 344 } 345 } 346 347 static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res, 348 bool log) 349 { 350 u8 io_base_lo, io_limit_lo; 351 unsigned long io_mask, io_granularity, base, limit; 352 struct pci_bus_region region; 353 354 io_mask = PCI_IO_RANGE_MASK; 355 io_granularity = 0x1000; 356 if (dev->io_window_1k) { 357 /* Support 1K I/O space granularity */ 358 io_mask = PCI_IO_1K_RANGE_MASK; 359 io_granularity = 0x400; 360 } 361 362 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 363 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 364 base = (io_base_lo & io_mask) << 8; 365 limit = (io_limit_lo & io_mask) << 8; 366 367 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 368 u16 io_base_hi, io_limit_hi; 369 370 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 371 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 372 base |= ((unsigned long) io_base_hi << 16); 373 limit |= ((unsigned long) io_limit_hi << 16); 374 } 375 376 if (base <= limit) { 377 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 378 region.start = base; 379 region.end = limit + io_granularity - 1; 380 pcibios_bus_to_resource(dev->bus, res, ®ion); 381 if (log) 382 pci_info(dev, " bridge window %pR\n", res); 383 } 384 } 385 386 static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res, 387 bool log) 388 { 389 u16 mem_base_lo, mem_limit_lo; 390 unsigned long base, limit; 391 struct pci_bus_region region; 392 393 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 394 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 395 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 396 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 397 if (base <= limit) { 398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 399 region.start = base; 400 region.end = limit + 0xfffff; 401 pcibios_bus_to_resource(dev->bus, res, ®ion); 402 if (log) 403 pci_info(dev, " bridge window %pR\n", res); 404 } 405 } 406 407 static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res, 408 bool log) 409 { 410 u16 mem_base_lo, mem_limit_lo; 411 u64 base64, limit64; 412 pci_bus_addr_t base, limit; 413 struct pci_bus_region region; 414 415 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 416 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 417 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 418 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 419 420 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 421 u32 mem_base_hi, mem_limit_hi; 422 423 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 424 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 425 426 /* 427 * Some bridges set the base > limit by default, and some 428 * (broken) BIOSes do not initialize them. If we find 429 * this, just assume they are not being used. 430 */ 431 if (mem_base_hi <= mem_limit_hi) { 432 base64 |= (u64) mem_base_hi << 32; 433 limit64 |= (u64) mem_limit_hi << 32; 434 } 435 } 436 437 base = (pci_bus_addr_t) base64; 438 limit = (pci_bus_addr_t) limit64; 439 440 if (base != base64) { 441 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 442 (unsigned long long) base64); 443 return; 444 } 445 446 if (base <= limit) { 447 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 448 IORESOURCE_MEM | IORESOURCE_PREFETCH; 449 if (res->flags & PCI_PREF_RANGE_TYPE_64) 450 res->flags |= IORESOURCE_MEM_64; 451 region.start = base; 452 region.end = limit + 0xfffff; 453 pcibios_bus_to_resource(dev->bus, res, ®ion); 454 if (log) 455 pci_info(dev, " bridge window %pR\n", res); 456 } 457 } 458 459 static void pci_read_bridge_windows(struct pci_dev *bridge) 460 { 461 u32 buses; 462 u16 io; 463 u32 pmem, tmp; 464 struct resource res; 465 466 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses); 467 res.flags = IORESOURCE_BUS; 468 res.start = (buses >> 8) & 0xff; 469 res.end = (buses >> 16) & 0xff; 470 pci_info(bridge, "PCI bridge to %pR%s\n", &res, 471 bridge->transparent ? " (subtractive decode)" : ""); 472 473 pci_read_config_word(bridge, PCI_IO_BASE, &io); 474 if (!io) { 475 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 476 pci_read_config_word(bridge, PCI_IO_BASE, &io); 477 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 478 } 479 if (io) { 480 bridge->io_window = 1; 481 pci_read_bridge_io(bridge, &res, true); 482 } 483 484 pci_read_bridge_mmio(bridge, &res, true); 485 486 /* 487 * DECchip 21050 pass 2 errata: the bridge may miss an address 488 * disconnect boundary by one PCI data phase. Workaround: do not 489 * use prefetching on this device. 490 */ 491 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 492 return; 493 494 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 495 if (!pmem) { 496 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 497 0xffe0fff0); 498 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 499 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 500 } 501 if (!pmem) 502 return; 503 504 bridge->pref_window = 1; 505 506 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 507 508 /* 509 * Bridge claims to have a 64-bit prefetchable memory 510 * window; verify that the upper bits are actually 511 * writable. 512 */ 513 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 514 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 515 0xffffffff); 516 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 517 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 518 if (tmp) 519 bridge->pref_64_window = 1; 520 } 521 522 pci_read_bridge_mmio_pref(bridge, &res, true); 523 } 524 525 void pci_read_bridge_bases(struct pci_bus *child) 526 { 527 struct pci_dev *dev = child->self; 528 struct resource *res; 529 int i; 530 531 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 532 return; 533 534 pci_info(dev, "PCI bridge to %pR%s\n", 535 &child->busn_res, 536 dev->transparent ? " (subtractive decode)" : ""); 537 538 pci_bus_remove_resources(child); 539 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 540 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 541 542 pci_read_bridge_io(child->self, child->resource[0], false); 543 pci_read_bridge_mmio(child->self, child->resource[1], false); 544 pci_read_bridge_mmio_pref(child->self, child->resource[2], false); 545 546 if (dev->transparent) { 547 pci_bus_for_each_resource(child->parent, res) { 548 if (res && res->flags) { 549 pci_bus_add_resource(child, res, 550 PCI_SUBTRACTIVE_DECODE); 551 pci_info(dev, " bridge window %pR (subtractive decode)\n", 552 res); 553 } 554 } 555 } 556 } 557 558 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 559 { 560 struct pci_bus *b; 561 562 b = kzalloc(sizeof(*b), GFP_KERNEL); 563 if (!b) 564 return NULL; 565 566 INIT_LIST_HEAD(&b->node); 567 INIT_LIST_HEAD(&b->children); 568 INIT_LIST_HEAD(&b->devices); 569 INIT_LIST_HEAD(&b->slots); 570 INIT_LIST_HEAD(&b->resources); 571 b->max_bus_speed = PCI_SPEED_UNKNOWN; 572 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 573 #ifdef CONFIG_PCI_DOMAINS_GENERIC 574 if (parent) 575 b->domain_nr = parent->domain_nr; 576 #endif 577 return b; 578 } 579 580 static void pci_release_host_bridge_dev(struct device *dev) 581 { 582 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 583 584 if (bridge->release_fn) 585 bridge->release_fn(bridge); 586 587 pci_free_resource_list(&bridge->windows); 588 pci_free_resource_list(&bridge->dma_ranges); 589 kfree(bridge); 590 } 591 592 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 593 { 594 INIT_LIST_HEAD(&bridge->windows); 595 INIT_LIST_HEAD(&bridge->dma_ranges); 596 597 /* 598 * We assume we can manage these PCIe features. Some systems may 599 * reserve these for use by the platform itself, e.g., an ACPI BIOS 600 * may implement its own AER handling and use _OSC to prevent the 601 * OS from interfering. 602 */ 603 bridge->native_aer = 1; 604 bridge->native_pcie_hotplug = 1; 605 bridge->native_shpc_hotplug = 1; 606 bridge->native_pme = 1; 607 bridge->native_ltr = 1; 608 bridge->native_dpc = 1; 609 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 610 bridge->native_cxl_error = 1; 611 612 device_initialize(&bridge->dev); 613 } 614 615 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 616 { 617 struct pci_host_bridge *bridge; 618 619 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 620 if (!bridge) 621 return NULL; 622 623 pci_init_host_bridge(bridge); 624 bridge->dev.release = pci_release_host_bridge_dev; 625 626 return bridge; 627 } 628 EXPORT_SYMBOL(pci_alloc_host_bridge); 629 630 static void devm_pci_alloc_host_bridge_release(void *data) 631 { 632 pci_free_host_bridge(data); 633 } 634 635 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 636 size_t priv) 637 { 638 int ret; 639 struct pci_host_bridge *bridge; 640 641 bridge = pci_alloc_host_bridge(priv); 642 if (!bridge) 643 return NULL; 644 645 bridge->dev.parent = dev; 646 647 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 648 bridge); 649 if (ret) 650 return NULL; 651 652 ret = devm_of_pci_bridge_init(dev, bridge); 653 if (ret) 654 return NULL; 655 656 return bridge; 657 } 658 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 659 660 void pci_free_host_bridge(struct pci_host_bridge *bridge) 661 { 662 put_device(&bridge->dev); 663 } 664 EXPORT_SYMBOL(pci_free_host_bridge); 665 666 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 667 static const unsigned char pcix_bus_speed[] = { 668 PCI_SPEED_UNKNOWN, /* 0 */ 669 PCI_SPEED_66MHz_PCIX, /* 1 */ 670 PCI_SPEED_100MHz_PCIX, /* 2 */ 671 PCI_SPEED_133MHz_PCIX, /* 3 */ 672 PCI_SPEED_UNKNOWN, /* 4 */ 673 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 674 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 675 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 676 PCI_SPEED_UNKNOWN, /* 8 */ 677 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 678 PCI_SPEED_100MHz_PCIX_266, /* A */ 679 PCI_SPEED_133MHz_PCIX_266, /* B */ 680 PCI_SPEED_UNKNOWN, /* C */ 681 PCI_SPEED_66MHz_PCIX_533, /* D */ 682 PCI_SPEED_100MHz_PCIX_533, /* E */ 683 PCI_SPEED_133MHz_PCIX_533 /* F */ 684 }; 685 686 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 687 const unsigned char pcie_link_speed[] = { 688 PCI_SPEED_UNKNOWN, /* 0 */ 689 PCIE_SPEED_2_5GT, /* 1 */ 690 PCIE_SPEED_5_0GT, /* 2 */ 691 PCIE_SPEED_8_0GT, /* 3 */ 692 PCIE_SPEED_16_0GT, /* 4 */ 693 PCIE_SPEED_32_0GT, /* 5 */ 694 PCIE_SPEED_64_0GT, /* 6 */ 695 PCI_SPEED_UNKNOWN, /* 7 */ 696 PCI_SPEED_UNKNOWN, /* 8 */ 697 PCI_SPEED_UNKNOWN, /* 9 */ 698 PCI_SPEED_UNKNOWN, /* A */ 699 PCI_SPEED_UNKNOWN, /* B */ 700 PCI_SPEED_UNKNOWN, /* C */ 701 PCI_SPEED_UNKNOWN, /* D */ 702 PCI_SPEED_UNKNOWN, /* E */ 703 PCI_SPEED_UNKNOWN /* F */ 704 }; 705 EXPORT_SYMBOL_GPL(pcie_link_speed); 706 707 const char *pci_speed_string(enum pci_bus_speed speed) 708 { 709 /* Indexed by the pci_bus_speed enum */ 710 static const char *speed_strings[] = { 711 "33 MHz PCI", /* 0x00 */ 712 "66 MHz PCI", /* 0x01 */ 713 "66 MHz PCI-X", /* 0x02 */ 714 "100 MHz PCI-X", /* 0x03 */ 715 "133 MHz PCI-X", /* 0x04 */ 716 NULL, /* 0x05 */ 717 NULL, /* 0x06 */ 718 NULL, /* 0x07 */ 719 NULL, /* 0x08 */ 720 "66 MHz PCI-X 266", /* 0x09 */ 721 "100 MHz PCI-X 266", /* 0x0a */ 722 "133 MHz PCI-X 266", /* 0x0b */ 723 "Unknown AGP", /* 0x0c */ 724 "1x AGP", /* 0x0d */ 725 "2x AGP", /* 0x0e */ 726 "4x AGP", /* 0x0f */ 727 "8x AGP", /* 0x10 */ 728 "66 MHz PCI-X 533", /* 0x11 */ 729 "100 MHz PCI-X 533", /* 0x12 */ 730 "133 MHz PCI-X 533", /* 0x13 */ 731 "2.5 GT/s PCIe", /* 0x14 */ 732 "5.0 GT/s PCIe", /* 0x15 */ 733 "8.0 GT/s PCIe", /* 0x16 */ 734 "16.0 GT/s PCIe", /* 0x17 */ 735 "32.0 GT/s PCIe", /* 0x18 */ 736 "64.0 GT/s PCIe", /* 0x19 */ 737 }; 738 739 if (speed < ARRAY_SIZE(speed_strings)) 740 return speed_strings[speed]; 741 return "Unknown"; 742 } 743 EXPORT_SYMBOL_GPL(pci_speed_string); 744 745 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 746 { 747 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 748 } 749 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 750 751 static unsigned char agp_speeds[] = { 752 AGP_UNKNOWN, 753 AGP_1X, 754 AGP_2X, 755 AGP_4X, 756 AGP_8X 757 }; 758 759 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 760 { 761 int index = 0; 762 763 if (agpstat & 4) 764 index = 3; 765 else if (agpstat & 2) 766 index = 2; 767 else if (agpstat & 1) 768 index = 1; 769 else 770 goto out; 771 772 if (agp3) { 773 index += 2; 774 if (index == 5) 775 index = 0; 776 } 777 778 out: 779 return agp_speeds[index]; 780 } 781 782 static void pci_set_bus_speed(struct pci_bus *bus) 783 { 784 struct pci_dev *bridge = bus->self; 785 int pos; 786 787 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 788 if (!pos) 789 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 790 if (pos) { 791 u32 agpstat, agpcmd; 792 793 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 794 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 795 796 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 797 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 798 } 799 800 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 801 if (pos) { 802 u16 status; 803 enum pci_bus_speed max; 804 805 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 806 &status); 807 808 if (status & PCI_X_SSTATUS_533MHZ) { 809 max = PCI_SPEED_133MHz_PCIX_533; 810 } else if (status & PCI_X_SSTATUS_266MHZ) { 811 max = PCI_SPEED_133MHz_PCIX_266; 812 } else if (status & PCI_X_SSTATUS_133MHZ) { 813 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 814 max = PCI_SPEED_133MHz_PCIX_ECC; 815 else 816 max = PCI_SPEED_133MHz_PCIX; 817 } else { 818 max = PCI_SPEED_66MHz_PCIX; 819 } 820 821 bus->max_bus_speed = max; 822 bus->cur_bus_speed = 823 pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)]; 824 825 return; 826 } 827 828 if (pci_is_pcie(bridge)) { 829 u32 linkcap; 830 u16 linksta; 831 832 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 833 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 834 835 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 836 pcie_update_link_speed(bus, linksta); 837 } 838 } 839 840 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 841 { 842 struct irq_domain *d; 843 844 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 845 d = dev_get_msi_domain(bus->bridge); 846 847 /* 848 * Any firmware interface that can resolve the msi_domain 849 * should be called from here. 850 */ 851 if (!d) 852 d = pci_host_bridge_of_msi_domain(bus); 853 if (!d) 854 d = pci_host_bridge_acpi_msi_domain(bus); 855 856 /* 857 * If no IRQ domain was found via the OF tree, try looking it up 858 * directly through the fwnode_handle. 859 */ 860 if (!d) { 861 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 862 863 if (fwnode) 864 d = irq_find_matching_fwnode(fwnode, 865 DOMAIN_BUS_PCI_MSI); 866 } 867 868 return d; 869 } 870 871 static void pci_set_bus_msi_domain(struct pci_bus *bus) 872 { 873 struct irq_domain *d; 874 struct pci_bus *b; 875 876 /* 877 * The bus can be a root bus, a subordinate bus, or a virtual bus 878 * created by an SR-IOV device. Walk up to the first bridge device 879 * found or derive the domain from the host bridge. 880 */ 881 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 882 if (b->self) 883 d = dev_get_msi_domain(&b->self->dev); 884 } 885 886 if (!d) 887 d = pci_host_bridge_msi_domain(b); 888 889 dev_set_msi_domain(&bus->dev, d); 890 } 891 892 static bool pci_preserve_config(struct pci_host_bridge *host_bridge) 893 { 894 if (pci_acpi_preserve_config(host_bridge)) 895 return true; 896 897 if (host_bridge->dev.parent && host_bridge->dev.parent->of_node) 898 return of_pci_preserve_config(host_bridge->dev.parent->of_node); 899 900 return false; 901 } 902 903 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 904 { 905 struct device *parent = bridge->dev.parent; 906 struct resource_entry *window, *next, *n; 907 struct pci_bus *bus, *b; 908 resource_size_t offset, next_offset; 909 LIST_HEAD(resources); 910 struct resource *res, *next_res; 911 char addr[64], *fmt; 912 const char *name; 913 int err; 914 915 bus = pci_alloc_bus(NULL); 916 if (!bus) 917 return -ENOMEM; 918 919 bridge->bus = bus; 920 921 bus->sysdata = bridge->sysdata; 922 bus->ops = bridge->ops; 923 bus->number = bus->busn_res.start = bridge->busnr; 924 #ifdef CONFIG_PCI_DOMAINS_GENERIC 925 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 926 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 927 else 928 bus->domain_nr = bridge->domain_nr; 929 if (bus->domain_nr < 0) { 930 err = bus->domain_nr; 931 goto free; 932 } 933 #endif 934 935 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 936 if (b) { 937 /* Ignore it if we already got here via a different bridge */ 938 dev_dbg(&b->dev, "bus already known\n"); 939 err = -EEXIST; 940 goto free; 941 } 942 943 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 944 bridge->busnr); 945 946 err = pcibios_root_bridge_prepare(bridge); 947 if (err) 948 goto free; 949 950 /* Temporarily move resources off the list */ 951 list_splice_init(&bridge->windows, &resources); 952 err = device_add(&bridge->dev); 953 if (err) { 954 put_device(&bridge->dev); 955 goto free; 956 } 957 bus->bridge = get_device(&bridge->dev); 958 device_enable_async_suspend(bus->bridge); 959 pci_set_bus_of_node(bus); 960 pci_set_bus_msi_domain(bus); 961 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 962 !pci_host_of_has_msi_map(parent)) 963 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 964 965 if (!parent) 966 set_dev_node(bus->bridge, pcibus_to_node(bus)); 967 968 bus->dev.class = &pcibus_class; 969 bus->dev.parent = bus->bridge; 970 971 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 972 name = dev_name(&bus->dev); 973 974 err = device_register(&bus->dev); 975 if (err) 976 goto unregister; 977 978 pcibios_add_bus(bus); 979 980 if (bus->ops->add_bus) { 981 err = bus->ops->add_bus(bus); 982 if (WARN_ON(err < 0)) 983 dev_err(&bus->dev, "failed to add bus: %d\n", err); 984 } 985 986 /* Create legacy_io and legacy_mem files for this bus */ 987 pci_create_legacy_files(bus); 988 989 if (parent) 990 dev_info(parent, "PCI host bridge to bus %s\n", name); 991 else 992 pr_info("PCI host bridge to bus %s\n", name); 993 994 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 995 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 996 997 /* Check if the boot configuration by FW needs to be preserved */ 998 bridge->preserve_config = pci_preserve_config(bridge); 999 1000 /* Coalesce contiguous windows */ 1001 resource_list_for_each_entry_safe(window, n, &resources) { 1002 if (list_is_last(&window->node, &resources)) 1003 break; 1004 1005 next = list_next_entry(window, node); 1006 offset = window->offset; 1007 res = window->res; 1008 next_offset = next->offset; 1009 next_res = next->res; 1010 1011 if (res->flags != next_res->flags || offset != next_offset) 1012 continue; 1013 1014 if (res->end + 1 == next_res->start) { 1015 next_res->start = res->start; 1016 res->flags = res->start = res->end = 0; 1017 } 1018 } 1019 1020 /* Add initial resources to the bus */ 1021 resource_list_for_each_entry_safe(window, n, &resources) { 1022 offset = window->offset; 1023 res = window->res; 1024 if (!res->flags && !res->start && !res->end) { 1025 release_resource(res); 1026 resource_list_destroy_entry(window); 1027 continue; 1028 } 1029 1030 list_move_tail(&window->node, &bridge->windows); 1031 1032 if (res->flags & IORESOURCE_BUS) 1033 pci_bus_insert_busn_res(bus, bus->number, res->end); 1034 else 1035 pci_bus_add_resource(bus, res, 0); 1036 1037 if (offset) { 1038 if (resource_type(res) == IORESOURCE_IO) 1039 fmt = " (bus address [%#06llx-%#06llx])"; 1040 else 1041 fmt = " (bus address [%#010llx-%#010llx])"; 1042 1043 snprintf(addr, sizeof(addr), fmt, 1044 (unsigned long long)(res->start - offset), 1045 (unsigned long long)(res->end - offset)); 1046 } else 1047 addr[0] = '\0'; 1048 1049 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 1050 } 1051 1052 down_write(&pci_bus_sem); 1053 list_add_tail(&bus->node, &pci_root_buses); 1054 up_write(&pci_bus_sem); 1055 1056 return 0; 1057 1058 unregister: 1059 put_device(&bridge->dev); 1060 device_del(&bridge->dev); 1061 1062 free: 1063 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1064 pci_bus_release_domain_nr(bus, parent); 1065 #endif 1066 kfree(bus); 1067 return err; 1068 } 1069 1070 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1071 { 1072 int pos; 1073 u32 status; 1074 1075 /* 1076 * If extended config space isn't accessible on a bridge's primary 1077 * bus, we certainly can't access it on the secondary bus. 1078 */ 1079 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1080 return false; 1081 1082 /* 1083 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1084 * extended config space is accessible on the primary, it's also 1085 * accessible on the secondary. 1086 */ 1087 if (pci_is_pcie(bridge) && 1088 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1089 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1090 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1091 return true; 1092 1093 /* 1094 * For the other bridge types: 1095 * - PCI-to-PCI bridges 1096 * - PCIe-to-PCI/PCI-X forward bridges 1097 * - PCI/PCI-X-to-PCIe reverse bridges 1098 * extended config space on the secondary side is only accessible 1099 * if the bridge supports PCI-X Mode 2. 1100 */ 1101 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1102 if (!pos) 1103 return false; 1104 1105 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1106 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1107 } 1108 1109 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1110 struct pci_dev *bridge, int busnr) 1111 { 1112 struct pci_bus *child; 1113 struct pci_host_bridge *host; 1114 int i; 1115 int ret; 1116 1117 /* Allocate a new bus and inherit stuff from the parent */ 1118 child = pci_alloc_bus(parent); 1119 if (!child) 1120 return NULL; 1121 1122 child->parent = parent; 1123 child->sysdata = parent->sysdata; 1124 child->bus_flags = parent->bus_flags; 1125 1126 host = pci_find_host_bridge(parent); 1127 if (host->child_ops) 1128 child->ops = host->child_ops; 1129 else 1130 child->ops = parent->ops; 1131 1132 /* 1133 * Initialize some portions of the bus device, but don't register 1134 * it now as the parent is not properly set up yet. 1135 */ 1136 child->dev.class = &pcibus_class; 1137 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1138 1139 /* Set up the primary, secondary and subordinate bus numbers */ 1140 child->number = child->busn_res.start = busnr; 1141 child->primary = parent->busn_res.start; 1142 child->busn_res.end = 0xff; 1143 1144 if (!bridge) { 1145 child->dev.parent = parent->bridge; 1146 goto add_dev; 1147 } 1148 1149 child->self = bridge; 1150 child->bridge = get_device(&bridge->dev); 1151 child->dev.parent = child->bridge; 1152 pci_set_bus_of_node(child); 1153 pci_set_bus_speed(child); 1154 1155 /* 1156 * Check whether extended config space is accessible on the child 1157 * bus. Note that we currently assume it is always accessible on 1158 * the root bus. 1159 */ 1160 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1161 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1162 pci_info(child, "extended config space not accessible\n"); 1163 } 1164 1165 /* Set up default resource pointers and names */ 1166 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1167 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1168 child->resource[i]->name = child->name; 1169 } 1170 bridge->subordinate = child; 1171 1172 add_dev: 1173 pci_set_bus_msi_domain(child); 1174 ret = device_register(&child->dev); 1175 WARN_ON(ret < 0); 1176 1177 pcibios_add_bus(child); 1178 1179 if (child->ops->add_bus) { 1180 ret = child->ops->add_bus(child); 1181 if (WARN_ON(ret < 0)) 1182 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1183 } 1184 1185 /* Create legacy_io and legacy_mem files for this bus */ 1186 pci_create_legacy_files(child); 1187 1188 return child; 1189 } 1190 1191 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1192 int busnr) 1193 { 1194 struct pci_bus *child; 1195 1196 child = pci_alloc_child_bus(parent, dev, busnr); 1197 if (child) { 1198 down_write(&pci_bus_sem); 1199 list_add_tail(&child->node, &parent->children); 1200 up_write(&pci_bus_sem); 1201 } 1202 return child; 1203 } 1204 EXPORT_SYMBOL(pci_add_new_bus); 1205 1206 static void pci_enable_crs(struct pci_dev *pdev) 1207 { 1208 u16 root_cap = 0; 1209 1210 /* Enable CRS Software Visibility if supported */ 1211 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1212 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1213 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1214 PCI_EXP_RTCTL_CRSSVE); 1215 } 1216 1217 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1218 unsigned int available_buses); 1219 /** 1220 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1221 * numbers from EA capability. 1222 * @dev: Bridge 1223 * @sec: updated with secondary bus number from EA 1224 * @sub: updated with subordinate bus number from EA 1225 * 1226 * If @dev is a bridge with EA capability that specifies valid secondary 1227 * and subordinate bus numbers, return true with the bus numbers in @sec 1228 * and @sub. Otherwise return false. 1229 */ 1230 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1231 { 1232 int ea, offset; 1233 u32 dw; 1234 u8 ea_sec, ea_sub; 1235 1236 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1237 return false; 1238 1239 /* find PCI EA capability in list */ 1240 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1241 if (!ea) 1242 return false; 1243 1244 offset = ea + PCI_EA_FIRST_ENT; 1245 pci_read_config_dword(dev, offset, &dw); 1246 ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw); 1247 ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw); 1248 if (ea_sec == 0 || ea_sub < ea_sec) 1249 return false; 1250 1251 *sec = ea_sec; 1252 *sub = ea_sub; 1253 return true; 1254 } 1255 1256 /* 1257 * pci_scan_bridge_extend() - Scan buses behind a bridge 1258 * @bus: Parent bus the bridge is on 1259 * @dev: Bridge itself 1260 * @max: Starting subordinate number of buses behind this bridge 1261 * @available_buses: Total number of buses available for this bridge and 1262 * the devices below. After the minimal bus space has 1263 * been allocated the remaining buses will be 1264 * distributed equally between hotplug-capable bridges. 1265 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1266 * that need to be reconfigured. 1267 * 1268 * If it's a bridge, configure it and scan the bus behind it. 1269 * For CardBus bridges, we don't scan behind as the devices will 1270 * be handled by the bridge driver itself. 1271 * 1272 * We need to process bridges in two passes -- first we scan those 1273 * already configured by the BIOS and after we are done with all of 1274 * them, we proceed to assigning numbers to the remaining buses in 1275 * order to avoid overlaps between old and new bus numbers. 1276 * 1277 * Return: New subordinate number covering all buses behind this bridge. 1278 */ 1279 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1280 int max, unsigned int available_buses, 1281 int pass) 1282 { 1283 struct pci_bus *child; 1284 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1285 u32 buses, i, j = 0; 1286 u16 bctl; 1287 u8 primary, secondary, subordinate; 1288 int broken = 0; 1289 bool fixed_buses; 1290 u8 fixed_sec, fixed_sub; 1291 int next_busnr; 1292 1293 /* 1294 * Make sure the bridge is powered on to be able to access config 1295 * space of devices below it. 1296 */ 1297 pm_runtime_get_sync(&dev->dev); 1298 1299 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1300 primary = buses & 0xFF; 1301 secondary = (buses >> 8) & 0xFF; 1302 subordinate = (buses >> 16) & 0xFF; 1303 1304 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1305 secondary, subordinate, pass); 1306 1307 if (!primary && (primary != bus->number) && secondary && subordinate) { 1308 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1309 primary = bus->number; 1310 } 1311 1312 /* Check if setup is sensible at all */ 1313 if (!pass && 1314 (primary != bus->number || secondary <= bus->number || 1315 secondary > subordinate)) { 1316 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1317 secondary, subordinate); 1318 broken = 1; 1319 } 1320 1321 /* 1322 * Disable Master-Abort Mode during probing to avoid reporting of 1323 * bus errors in some architectures. 1324 */ 1325 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1326 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1327 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1328 1329 pci_enable_crs(dev); 1330 1331 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1332 !is_cardbus && !broken) { 1333 unsigned int cmax, buses; 1334 1335 /* 1336 * Bus already configured by firmware, process it in the 1337 * first pass and just note the configuration. 1338 */ 1339 if (pass) 1340 goto out; 1341 1342 /* 1343 * The bus might already exist for two reasons: Either we 1344 * are rescanning the bus or the bus is reachable through 1345 * more than one bridge. The second case can happen with 1346 * the i450NX chipset. 1347 */ 1348 child = pci_find_bus(pci_domain_nr(bus), secondary); 1349 if (!child) { 1350 child = pci_add_new_bus(bus, dev, secondary); 1351 if (!child) 1352 goto out; 1353 child->primary = primary; 1354 pci_bus_insert_busn_res(child, secondary, subordinate); 1355 child->bridge_ctl = bctl; 1356 } 1357 1358 buses = subordinate - secondary; 1359 cmax = pci_scan_child_bus_extend(child, buses); 1360 if (cmax > subordinate) 1361 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1362 subordinate, cmax); 1363 1364 /* Subordinate should equal child->busn_res.end */ 1365 if (subordinate > max) 1366 max = subordinate; 1367 } else { 1368 1369 /* 1370 * We need to assign a number to this bus which we always 1371 * do in the second pass. 1372 */ 1373 if (!pass) { 1374 if (pcibios_assign_all_busses() || broken || is_cardbus) 1375 1376 /* 1377 * Temporarily disable forwarding of the 1378 * configuration cycles on all bridges in 1379 * this bus segment to avoid possible 1380 * conflicts in the second pass between two 1381 * bridges programmed with overlapping bus 1382 * ranges. 1383 */ 1384 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1385 buses & ~0xffffff); 1386 goto out; 1387 } 1388 1389 /* Clear errors */ 1390 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1391 1392 /* Read bus numbers from EA Capability (if present) */ 1393 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1394 if (fixed_buses) 1395 next_busnr = fixed_sec; 1396 else 1397 next_busnr = max + 1; 1398 1399 /* 1400 * Prevent assigning a bus number that already exists. 1401 * This can happen when a bridge is hot-plugged, so in this 1402 * case we only re-scan this bus. 1403 */ 1404 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1405 if (!child) { 1406 child = pci_add_new_bus(bus, dev, next_busnr); 1407 if (!child) 1408 goto out; 1409 pci_bus_insert_busn_res(child, next_busnr, 1410 bus->busn_res.end); 1411 } 1412 max++; 1413 if (available_buses) 1414 available_buses--; 1415 1416 buses = (buses & 0xff000000) 1417 | ((unsigned int)(child->primary) << 0) 1418 | ((unsigned int)(child->busn_res.start) << 8) 1419 | ((unsigned int)(child->busn_res.end) << 16); 1420 1421 /* 1422 * yenta.c forces a secondary latency timer of 176. 1423 * Copy that behaviour here. 1424 */ 1425 if (is_cardbus) { 1426 buses &= ~0xff000000; 1427 buses |= CARDBUS_LATENCY_TIMER << 24; 1428 } 1429 1430 /* We need to blast all three values with a single write */ 1431 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1432 1433 if (!is_cardbus) { 1434 child->bridge_ctl = bctl; 1435 max = pci_scan_child_bus_extend(child, available_buses); 1436 } else { 1437 1438 /* 1439 * For CardBus bridges, we leave 4 bus numbers as 1440 * cards with a PCI-to-PCI bridge can be inserted 1441 * later. 1442 */ 1443 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1444 struct pci_bus *parent = bus; 1445 if (pci_find_bus(pci_domain_nr(bus), 1446 max+i+1)) 1447 break; 1448 while (parent->parent) { 1449 if ((!pcibios_assign_all_busses()) && 1450 (parent->busn_res.end > max) && 1451 (parent->busn_res.end <= max+i)) { 1452 j = 1; 1453 } 1454 parent = parent->parent; 1455 } 1456 if (j) { 1457 1458 /* 1459 * Often, there are two CardBus 1460 * bridges -- try to leave one 1461 * valid bus number for each one. 1462 */ 1463 i /= 2; 1464 break; 1465 } 1466 } 1467 max += i; 1468 } 1469 1470 /* 1471 * Set subordinate bus number to its real value. 1472 * If fixed subordinate bus number exists from EA 1473 * capability then use it. 1474 */ 1475 if (fixed_buses) 1476 max = fixed_sub; 1477 pci_bus_update_busn_res_end(child, max); 1478 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1479 } 1480 1481 sprintf(child->name, 1482 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1483 pci_domain_nr(bus), child->number); 1484 1485 /* Check that all devices are accessible */ 1486 while (bus->parent) { 1487 if ((child->busn_res.end > bus->busn_res.end) || 1488 (child->number > bus->busn_res.end) || 1489 (child->number < bus->number) || 1490 (child->busn_res.end < bus->number)) { 1491 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1492 &child->busn_res); 1493 break; 1494 } 1495 bus = bus->parent; 1496 } 1497 1498 out: 1499 /* Clear errors in the Secondary Status Register */ 1500 pci_write_config_word(dev, PCI_SEC_STATUS, 0xffff); 1501 1502 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1503 1504 pm_runtime_put(&dev->dev); 1505 1506 return max; 1507 } 1508 1509 /* 1510 * pci_scan_bridge() - Scan buses behind a bridge 1511 * @bus: Parent bus the bridge is on 1512 * @dev: Bridge itself 1513 * @max: Starting subordinate number of buses behind this bridge 1514 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1515 * that need to be reconfigured. 1516 * 1517 * If it's a bridge, configure it and scan the bus behind it. 1518 * For CardBus bridges, we don't scan behind as the devices will 1519 * be handled by the bridge driver itself. 1520 * 1521 * We need to process bridges in two passes -- first we scan those 1522 * already configured by the BIOS and after we are done with all of 1523 * them, we proceed to assigning numbers to the remaining buses in 1524 * order to avoid overlaps between old and new bus numbers. 1525 * 1526 * Return: New subordinate number covering all buses behind this bridge. 1527 */ 1528 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1529 { 1530 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1531 } 1532 EXPORT_SYMBOL(pci_scan_bridge); 1533 1534 /* 1535 * Read interrupt line and base address registers. 1536 * The architecture-dependent code can tweak these, of course. 1537 */ 1538 static void pci_read_irq(struct pci_dev *dev) 1539 { 1540 unsigned char irq; 1541 1542 /* VFs are not allowed to use INTx, so skip the config reads */ 1543 if (dev->is_virtfn) { 1544 dev->pin = 0; 1545 dev->irq = 0; 1546 return; 1547 } 1548 1549 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1550 dev->pin = irq; 1551 if (irq) 1552 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1553 dev->irq = irq; 1554 } 1555 1556 void set_pcie_port_type(struct pci_dev *pdev) 1557 { 1558 int pos; 1559 u16 reg16; 1560 u32 reg32; 1561 int type; 1562 struct pci_dev *parent; 1563 1564 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1565 if (!pos) 1566 return; 1567 1568 pdev->pcie_cap = pos; 1569 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1570 pdev->pcie_flags_reg = reg16; 1571 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1572 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1573 1574 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); 1575 if (reg32 & PCI_EXP_LNKCAP_DLLLARC) 1576 pdev->link_active_reporting = 1; 1577 1578 parent = pci_upstream_bridge(pdev); 1579 if (!parent) 1580 return; 1581 1582 /* 1583 * Some systems do not identify their upstream/downstream ports 1584 * correctly so detect impossible configurations here and correct 1585 * the port type accordingly. 1586 */ 1587 type = pci_pcie_type(pdev); 1588 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1589 /* 1590 * If pdev claims to be downstream port but the parent 1591 * device is also downstream port assume pdev is actually 1592 * upstream port. 1593 */ 1594 if (pcie_downstream_port(parent)) { 1595 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1596 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1597 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1598 } 1599 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1600 /* 1601 * If pdev claims to be upstream port but the parent 1602 * device is also upstream port assume pdev is actually 1603 * downstream port. 1604 */ 1605 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1606 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1607 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1608 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1609 } 1610 } 1611 } 1612 1613 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1614 { 1615 u32 reg32; 1616 1617 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1618 if (reg32 & PCI_EXP_SLTCAP_HPC) 1619 pdev->is_hotplug_bridge = 1; 1620 } 1621 1622 static void set_pcie_thunderbolt(struct pci_dev *dev) 1623 { 1624 u16 vsec; 1625 1626 /* Is the device part of a Thunderbolt controller? */ 1627 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); 1628 if (vsec) 1629 dev->is_thunderbolt = 1; 1630 } 1631 1632 static void set_pcie_untrusted(struct pci_dev *dev) 1633 { 1634 struct pci_dev *parent; 1635 1636 /* 1637 * If the upstream bridge is untrusted we treat this device 1638 * untrusted as well. 1639 */ 1640 parent = pci_upstream_bridge(dev); 1641 if (parent && (parent->untrusted || parent->external_facing)) 1642 dev->untrusted = true; 1643 } 1644 1645 static void pci_set_removable(struct pci_dev *dev) 1646 { 1647 struct pci_dev *parent = pci_upstream_bridge(dev); 1648 1649 /* 1650 * We (only) consider everything downstream from an external_facing 1651 * device to be removable by the user. We're mainly concerned with 1652 * consumer platforms with user accessible thunderbolt ports that are 1653 * vulnerable to DMA attacks, and we expect those ports to be marked by 1654 * the firmware as external_facing. Devices in traditional hotplug 1655 * slots can technically be removed, but the expectation is that unless 1656 * the port is marked with external_facing, such devices are less 1657 * accessible to user / may not be removed by end user, and thus not 1658 * exposed as "removable" to userspace. 1659 */ 1660 if (parent && 1661 (parent->external_facing || dev_is_removable(&parent->dev))) 1662 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1663 } 1664 1665 /** 1666 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1667 * @dev: PCI device 1668 * 1669 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1670 * when forwarding a type1 configuration request the bridge must check that 1671 * the extended register address field is zero. The bridge is not permitted 1672 * to forward the transactions and must handle it as an Unsupported Request. 1673 * Some bridges do not follow this rule and simply drop the extended register 1674 * bits, resulting in the standard config space being aliased, every 256 1675 * bytes across the entire configuration space. Test for this condition by 1676 * comparing the first dword of each potential alias to the vendor/device ID. 1677 * Known offenders: 1678 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1679 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1680 */ 1681 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1682 { 1683 #ifdef CONFIG_PCI_QUIRKS 1684 int pos, ret; 1685 u32 header, tmp; 1686 1687 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1688 1689 for (pos = PCI_CFG_SPACE_SIZE; 1690 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1691 ret = pci_read_config_dword(dev, pos, &tmp); 1692 if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp)) 1693 return false; 1694 } 1695 1696 return true; 1697 #else 1698 return false; 1699 #endif 1700 } 1701 1702 /** 1703 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1704 * @dev: PCI device 1705 * 1706 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1707 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1708 * access it. Maybe we don't have a way to generate extended config space 1709 * accesses, or the device is behind a reverse Express bridge. So we try 1710 * reading the dword at 0x100 which must either be 0 or a valid extended 1711 * capability header. 1712 */ 1713 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1714 { 1715 u32 status; 1716 int pos = PCI_CFG_SPACE_SIZE; 1717 1718 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1719 return PCI_CFG_SPACE_SIZE; 1720 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) 1721 return PCI_CFG_SPACE_SIZE; 1722 1723 return PCI_CFG_SPACE_EXP_SIZE; 1724 } 1725 1726 int pci_cfg_space_size(struct pci_dev *dev) 1727 { 1728 int pos; 1729 u32 status; 1730 u16 class; 1731 1732 #ifdef CONFIG_PCI_IOV 1733 /* 1734 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1735 * implement a PCIe capability and therefore must implement extended 1736 * config space. We can skip the NO_EXTCFG test below and the 1737 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1738 * the fact that the SR-IOV capability on the PF resides in extended 1739 * config space and must be accessible and non-aliased to have enabled 1740 * support for this VF. This is a micro performance optimization for 1741 * systems supporting many VFs. 1742 */ 1743 if (dev->is_virtfn) 1744 return PCI_CFG_SPACE_EXP_SIZE; 1745 #endif 1746 1747 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1748 return PCI_CFG_SPACE_SIZE; 1749 1750 class = dev->class >> 8; 1751 if (class == PCI_CLASS_BRIDGE_HOST) 1752 return pci_cfg_space_size_ext(dev); 1753 1754 if (pci_is_pcie(dev)) 1755 return pci_cfg_space_size_ext(dev); 1756 1757 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1758 if (!pos) 1759 return PCI_CFG_SPACE_SIZE; 1760 1761 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1762 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1763 return pci_cfg_space_size_ext(dev); 1764 1765 return PCI_CFG_SPACE_SIZE; 1766 } 1767 1768 static u32 pci_class(struct pci_dev *dev) 1769 { 1770 u32 class; 1771 1772 #ifdef CONFIG_PCI_IOV 1773 if (dev->is_virtfn) 1774 return dev->physfn->sriov->class; 1775 #endif 1776 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1777 return class; 1778 } 1779 1780 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1781 { 1782 #ifdef CONFIG_PCI_IOV 1783 if (dev->is_virtfn) { 1784 *vendor = dev->physfn->sriov->subsystem_vendor; 1785 *device = dev->physfn->sriov->subsystem_device; 1786 return; 1787 } 1788 #endif 1789 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1790 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1791 } 1792 1793 static u8 pci_hdr_type(struct pci_dev *dev) 1794 { 1795 u8 hdr_type; 1796 1797 #ifdef CONFIG_PCI_IOV 1798 if (dev->is_virtfn) 1799 return dev->physfn->sriov->hdr_type; 1800 #endif 1801 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1802 return hdr_type; 1803 } 1804 1805 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1806 1807 /** 1808 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1809 * @dev: PCI device 1810 * 1811 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1812 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1813 */ 1814 static int pci_intx_mask_broken(struct pci_dev *dev) 1815 { 1816 u16 orig, toggle, new; 1817 1818 pci_read_config_word(dev, PCI_COMMAND, &orig); 1819 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1820 pci_write_config_word(dev, PCI_COMMAND, toggle); 1821 pci_read_config_word(dev, PCI_COMMAND, &new); 1822 1823 pci_write_config_word(dev, PCI_COMMAND, orig); 1824 1825 /* 1826 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1827 * r2.3, so strictly speaking, a device is not *broken* if it's not 1828 * writable. But we'll live with the misnomer for now. 1829 */ 1830 if (new != toggle) 1831 return 1; 1832 return 0; 1833 } 1834 1835 static void early_dump_pci_device(struct pci_dev *pdev) 1836 { 1837 u32 value[256 / 4]; 1838 int i; 1839 1840 pci_info(pdev, "config space:\n"); 1841 1842 for (i = 0; i < 256; i += 4) 1843 pci_read_config_dword(pdev, i, &value[i / 4]); 1844 1845 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1846 value, 256, false); 1847 } 1848 1849 static const char *pci_type_str(struct pci_dev *dev) 1850 { 1851 static const char * const str[] = { 1852 "PCIe Endpoint", 1853 "PCIe Legacy Endpoint", 1854 "PCIe unknown", 1855 "PCIe unknown", 1856 "PCIe Root Port", 1857 "PCIe Switch Upstream Port", 1858 "PCIe Switch Downstream Port", 1859 "PCIe to PCI/PCI-X bridge", 1860 "PCI/PCI-X to PCIe bridge", 1861 "PCIe Root Complex Integrated Endpoint", 1862 "PCIe Root Complex Event Collector", 1863 }; 1864 int type; 1865 1866 if (pci_is_pcie(dev)) { 1867 type = pci_pcie_type(dev); 1868 if (type < ARRAY_SIZE(str)) 1869 return str[type]; 1870 1871 return "PCIe unknown"; 1872 } 1873 1874 switch (dev->hdr_type) { 1875 case PCI_HEADER_TYPE_NORMAL: 1876 return "conventional PCI endpoint"; 1877 case PCI_HEADER_TYPE_BRIDGE: 1878 return "conventional PCI bridge"; 1879 case PCI_HEADER_TYPE_CARDBUS: 1880 return "CardBus bridge"; 1881 default: 1882 return "conventional PCI"; 1883 } 1884 } 1885 1886 /** 1887 * pci_setup_device - Fill in class and map information of a device 1888 * @dev: the device structure to fill 1889 * 1890 * Initialize the device structure with information about the device's 1891 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1892 * Called at initialisation of the PCI subsystem and by CardBus services. 1893 * Returns 0 on success and negative if unknown type of device (not normal, 1894 * bridge or CardBus). 1895 */ 1896 int pci_setup_device(struct pci_dev *dev) 1897 { 1898 u32 class; 1899 u16 cmd; 1900 u8 hdr_type; 1901 int err, pos = 0; 1902 struct pci_bus_region region; 1903 struct resource *res; 1904 1905 hdr_type = pci_hdr_type(dev); 1906 1907 dev->sysdata = dev->bus->sysdata; 1908 dev->dev.parent = dev->bus->bridge; 1909 dev->dev.bus = &pci_bus_type; 1910 dev->hdr_type = hdr_type & 0x7f; 1911 dev->multifunction = !!(hdr_type & 0x80); 1912 dev->error_state = pci_channel_io_normal; 1913 set_pcie_port_type(dev); 1914 1915 err = pci_set_of_node(dev); 1916 if (err) 1917 return err; 1918 pci_set_acpi_fwnode(dev); 1919 1920 pci_dev_assign_slot(dev); 1921 1922 /* 1923 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1924 * set this higher, assuming the system even supports it. 1925 */ 1926 dev->dma_mask = 0xffffffff; 1927 1928 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1929 dev->bus->number, PCI_SLOT(dev->devfn), 1930 PCI_FUNC(dev->devfn)); 1931 1932 class = pci_class(dev); 1933 1934 dev->revision = class & 0xff; 1935 dev->class = class >> 8; /* upper 3 bytes */ 1936 1937 if (pci_early_dump) 1938 early_dump_pci_device(dev); 1939 1940 /* Need to have dev->class ready */ 1941 dev->cfg_size = pci_cfg_space_size(dev); 1942 1943 /* Need to have dev->cfg_size ready */ 1944 set_pcie_thunderbolt(dev); 1945 1946 set_pcie_untrusted(dev); 1947 1948 /* "Unknown power state" */ 1949 dev->current_state = PCI_UNKNOWN; 1950 1951 /* Early fixups, before probing the BARs */ 1952 pci_fixup_device(pci_fixup_early, dev); 1953 1954 pci_set_removable(dev); 1955 1956 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n", 1957 dev->vendor, dev->device, dev->hdr_type, dev->class, 1958 pci_type_str(dev)); 1959 1960 /* Device class may be changed after fixup */ 1961 class = dev->class >> 8; 1962 1963 if (dev->non_compliant_bars && !dev->mmio_always_on) { 1964 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1965 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1966 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1967 cmd &= ~PCI_COMMAND_IO; 1968 cmd &= ~PCI_COMMAND_MEMORY; 1969 pci_write_config_word(dev, PCI_COMMAND, cmd); 1970 } 1971 } 1972 1973 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1974 1975 switch (dev->hdr_type) { /* header type */ 1976 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1977 if (class == PCI_CLASS_BRIDGE_PCI) 1978 goto bad; 1979 pci_read_irq(dev); 1980 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1981 1982 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1983 1984 /* 1985 * Do the ugly legacy mode stuff here rather than broken chip 1986 * quirk code. Legacy mode ATA controllers have fixed 1987 * addresses. These are not always echoed in BAR0-3, and 1988 * BAR0-3 in a few cases contain junk! 1989 */ 1990 if (class == PCI_CLASS_STORAGE_IDE) { 1991 u8 progif; 1992 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1993 if ((progif & 1) == 0) { 1994 region.start = 0x1F0; 1995 region.end = 0x1F7; 1996 res = &dev->resource[0]; 1997 res->flags = LEGACY_IO_RESOURCE; 1998 pcibios_bus_to_resource(dev->bus, res, ®ion); 1999 pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n", 2000 res); 2001 region.start = 0x3F6; 2002 region.end = 0x3F6; 2003 res = &dev->resource[1]; 2004 res->flags = LEGACY_IO_RESOURCE; 2005 pcibios_bus_to_resource(dev->bus, res, ®ion); 2006 pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n", 2007 res); 2008 } 2009 if ((progif & 4) == 0) { 2010 region.start = 0x170; 2011 region.end = 0x177; 2012 res = &dev->resource[2]; 2013 res->flags = LEGACY_IO_RESOURCE; 2014 pcibios_bus_to_resource(dev->bus, res, ®ion); 2015 pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n", 2016 res); 2017 region.start = 0x376; 2018 region.end = 0x376; 2019 res = &dev->resource[3]; 2020 res->flags = LEGACY_IO_RESOURCE; 2021 pcibios_bus_to_resource(dev->bus, res, ®ion); 2022 pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n", 2023 res); 2024 } 2025 } 2026 break; 2027 2028 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 2029 /* 2030 * The PCI-to-PCI bridge spec requires that subtractive 2031 * decoding (i.e. transparent) bridge must have programming 2032 * interface code of 0x01. 2033 */ 2034 pci_read_irq(dev); 2035 dev->transparent = ((dev->class & 0xff) == 1); 2036 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 2037 pci_read_bridge_windows(dev); 2038 set_pcie_hotplug_bridge(dev); 2039 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 2040 if (pos) { 2041 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 2042 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 2043 } 2044 break; 2045 2046 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 2047 if (class != PCI_CLASS_BRIDGE_CARDBUS) 2048 goto bad; 2049 pci_read_irq(dev); 2050 pci_read_bases(dev, 1, 0); 2051 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 2052 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 2053 break; 2054 2055 default: /* unknown header */ 2056 pci_err(dev, "unknown header type %02x, ignoring device\n", 2057 dev->hdr_type); 2058 pci_release_of_node(dev); 2059 return -EIO; 2060 2061 bad: 2062 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 2063 dev->class, dev->hdr_type); 2064 dev->class = PCI_CLASS_NOT_DEFINED << 8; 2065 } 2066 2067 /* We found a fine healthy device, go go go... */ 2068 return 0; 2069 } 2070 2071 static void pci_configure_mps(struct pci_dev *dev) 2072 { 2073 struct pci_dev *bridge = pci_upstream_bridge(dev); 2074 int mps, mpss, p_mps, rc; 2075 2076 if (!pci_is_pcie(dev)) 2077 return; 2078 2079 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 2080 if (dev->is_virtfn) 2081 return; 2082 2083 /* 2084 * For Root Complex Integrated Endpoints, program the maximum 2085 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 2086 */ 2087 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 2088 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2089 mps = 128; 2090 else 2091 mps = 128 << dev->pcie_mpss; 2092 rc = pcie_set_mps(dev, mps); 2093 if (rc) { 2094 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2095 mps); 2096 } 2097 return; 2098 } 2099 2100 if (!bridge || !pci_is_pcie(bridge)) 2101 return; 2102 2103 mps = pcie_get_mps(dev); 2104 p_mps = pcie_get_mps(bridge); 2105 2106 if (mps == p_mps) 2107 return; 2108 2109 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2110 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2111 mps, pci_name(bridge), p_mps); 2112 return; 2113 } 2114 2115 /* 2116 * Fancier MPS configuration is done later by 2117 * pcie_bus_configure_settings() 2118 */ 2119 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2120 return; 2121 2122 mpss = 128 << dev->pcie_mpss; 2123 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2124 pcie_set_mps(bridge, mpss); 2125 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2126 mpss, p_mps, 128 << bridge->pcie_mpss); 2127 p_mps = pcie_get_mps(bridge); 2128 } 2129 2130 rc = pcie_set_mps(dev, p_mps); 2131 if (rc) { 2132 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2133 p_mps); 2134 return; 2135 } 2136 2137 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2138 p_mps, mps, mpss); 2139 } 2140 2141 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2142 { 2143 struct pci_host_bridge *host; 2144 u32 cap; 2145 u16 ctl; 2146 int ret; 2147 2148 if (!pci_is_pcie(dev)) 2149 return 0; 2150 2151 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2152 if (ret) 2153 return 0; 2154 2155 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2156 return 0; 2157 2158 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2159 if (ret) 2160 return 0; 2161 2162 host = pci_find_host_bridge(dev->bus); 2163 if (!host) 2164 return 0; 2165 2166 /* 2167 * If some device in the hierarchy doesn't handle Extended Tags 2168 * correctly, make sure they're disabled. 2169 */ 2170 if (host->no_ext_tags) { 2171 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2172 pci_info(dev, "disabling Extended Tags\n"); 2173 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2174 PCI_EXP_DEVCTL_EXT_TAG); 2175 } 2176 return 0; 2177 } 2178 2179 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2180 pci_info(dev, "enabling Extended Tags\n"); 2181 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2182 PCI_EXP_DEVCTL_EXT_TAG); 2183 } 2184 return 0; 2185 } 2186 2187 /** 2188 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2189 * @dev: PCI device to query 2190 * 2191 * Returns true if the device has enabled relaxed ordering attribute. 2192 */ 2193 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2194 { 2195 u16 v; 2196 2197 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2198 2199 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2200 } 2201 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2202 2203 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2204 { 2205 struct pci_dev *root; 2206 2207 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */ 2208 if (dev->is_virtfn) 2209 return; 2210 2211 if (!pcie_relaxed_ordering_enabled(dev)) 2212 return; 2213 2214 /* 2215 * For now, we only deal with Relaxed Ordering issues with Root 2216 * Ports. Peer-to-Peer DMA is another can of worms. 2217 */ 2218 root = pcie_find_root_port(dev); 2219 if (!root) 2220 return; 2221 2222 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2223 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2224 PCI_EXP_DEVCTL_RELAX_EN); 2225 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2226 } 2227 } 2228 2229 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2230 { 2231 #ifdef CONFIG_PCI_PASID 2232 struct pci_dev *bridge; 2233 int pcie_type; 2234 u32 cap; 2235 2236 if (!pci_is_pcie(dev)) 2237 return; 2238 2239 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2240 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2241 return; 2242 2243 pcie_type = pci_pcie_type(dev); 2244 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2245 pcie_type == PCI_EXP_TYPE_RC_END) 2246 dev->eetlp_prefix_path = 1; 2247 else { 2248 bridge = pci_upstream_bridge(dev); 2249 if (bridge && bridge->eetlp_prefix_path) 2250 dev->eetlp_prefix_path = 1; 2251 } 2252 #endif 2253 } 2254 2255 static void pci_configure_serr(struct pci_dev *dev) 2256 { 2257 u16 control; 2258 2259 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2260 2261 /* 2262 * A bridge will not forward ERR_ messages coming from an 2263 * endpoint unless SERR# forwarding is enabled. 2264 */ 2265 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2266 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2267 control |= PCI_BRIDGE_CTL_SERR; 2268 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2269 } 2270 } 2271 } 2272 2273 static void pci_configure_device(struct pci_dev *dev) 2274 { 2275 pci_configure_mps(dev); 2276 pci_configure_extended_tags(dev, NULL); 2277 pci_configure_relaxed_ordering(dev); 2278 pci_configure_ltr(dev); 2279 pci_configure_aspm_l1ss(dev); 2280 pci_configure_eetlp_prefix(dev); 2281 pci_configure_serr(dev); 2282 2283 pci_acpi_program_hp_params(dev); 2284 } 2285 2286 static void pci_release_capabilities(struct pci_dev *dev) 2287 { 2288 pci_aer_exit(dev); 2289 pci_rcec_exit(dev); 2290 pci_iov_release(dev); 2291 pci_free_cap_save_buffers(dev); 2292 } 2293 2294 /** 2295 * pci_release_dev - Free a PCI device structure when all users of it are 2296 * finished 2297 * @dev: device that's been disconnected 2298 * 2299 * Will be called only by the device core when all users of this PCI device are 2300 * done. 2301 */ 2302 static void pci_release_dev(struct device *dev) 2303 { 2304 struct pci_dev *pci_dev; 2305 2306 pci_dev = to_pci_dev(dev); 2307 pci_release_capabilities(pci_dev); 2308 pci_release_of_node(pci_dev); 2309 pcibios_release_device(pci_dev); 2310 pci_bus_put(pci_dev->bus); 2311 kfree(pci_dev->driver_override); 2312 bitmap_free(pci_dev->dma_alias_mask); 2313 dev_dbg(dev, "device released\n"); 2314 kfree(pci_dev); 2315 } 2316 2317 static const struct device_type pci_dev_type = { 2318 .groups = pci_dev_attr_groups, 2319 }; 2320 2321 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2322 { 2323 struct pci_dev *dev; 2324 2325 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2326 if (!dev) 2327 return NULL; 2328 2329 INIT_LIST_HEAD(&dev->bus_list); 2330 dev->dev.type = &pci_dev_type; 2331 dev->bus = pci_bus_get(bus); 2332 dev->driver_exclusive_resource = (struct resource) { 2333 .name = "PCI Exclusive", 2334 .start = 0, 2335 .end = -1, 2336 }; 2337 2338 spin_lock_init(&dev->pcie_cap_lock); 2339 #ifdef CONFIG_PCI_MSI 2340 raw_spin_lock_init(&dev->msi_lock); 2341 #endif 2342 return dev; 2343 } 2344 EXPORT_SYMBOL(pci_alloc_dev); 2345 2346 static bool pci_bus_crs_vendor_id(u32 l) 2347 { 2348 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 2349 } 2350 2351 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2352 int timeout) 2353 { 2354 int delay = 1; 2355 2356 if (!pci_bus_crs_vendor_id(*l)) 2357 return true; /* not a CRS completion */ 2358 2359 if (!timeout) 2360 return false; /* CRS, but caller doesn't want to wait */ 2361 2362 /* 2363 * We got the reserved Vendor ID that indicates a completion with 2364 * Configuration Request Retry Status (CRS). Retry until we get a 2365 * valid Vendor ID or we time out. 2366 */ 2367 while (pci_bus_crs_vendor_id(*l)) { 2368 if (delay > timeout) { 2369 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2370 pci_domain_nr(bus), bus->number, 2371 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2372 2373 return false; 2374 } 2375 if (delay >= 1000) 2376 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2377 pci_domain_nr(bus), bus->number, 2378 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2379 2380 msleep(delay); 2381 delay *= 2; 2382 2383 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2384 return false; 2385 } 2386 2387 if (delay >= 1000) 2388 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2389 pci_domain_nr(bus), bus->number, 2390 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2391 2392 return true; 2393 } 2394 2395 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2396 int timeout) 2397 { 2398 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2399 return false; 2400 2401 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ 2402 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || 2403 *l == 0x0000ffff || *l == 0xffff0000) 2404 return false; 2405 2406 if (pci_bus_crs_vendor_id(*l)) 2407 return pci_bus_wait_crs(bus, devfn, l, timeout); 2408 2409 return true; 2410 } 2411 2412 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2413 int timeout) 2414 { 2415 #ifdef CONFIG_PCI_QUIRKS 2416 struct pci_dev *bridge = bus->self; 2417 2418 /* 2419 * Certain IDT switches have an issue where they improperly trigger 2420 * ACS Source Validation errors on completions for config reads. 2421 */ 2422 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2423 bridge->device == 0x80b5) 2424 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2425 #endif 2426 2427 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2428 } 2429 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2430 2431 /* 2432 * Read the config data for a PCI device, sanity-check it, 2433 * and fill in the dev structure. 2434 */ 2435 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2436 { 2437 struct pci_dev *dev; 2438 u32 l; 2439 2440 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2441 return NULL; 2442 2443 dev = pci_alloc_dev(bus); 2444 if (!dev) 2445 return NULL; 2446 2447 dev->devfn = devfn; 2448 dev->vendor = l & 0xffff; 2449 dev->device = (l >> 16) & 0xffff; 2450 2451 if (pci_setup_device(dev)) { 2452 pci_bus_put(dev->bus); 2453 kfree(dev); 2454 return NULL; 2455 } 2456 2457 return dev; 2458 } 2459 2460 void pcie_report_downtraining(struct pci_dev *dev) 2461 { 2462 if (!pci_is_pcie(dev)) 2463 return; 2464 2465 /* Look from the device up to avoid downstream ports with no devices */ 2466 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2467 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2468 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2469 return; 2470 2471 /* Multi-function PCIe devices share the same link/status */ 2472 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2473 return; 2474 2475 /* Print link status only if the device is constrained by the fabric */ 2476 __pcie_print_link_status(dev, false); 2477 } 2478 2479 static void pci_init_capabilities(struct pci_dev *dev) 2480 { 2481 pci_ea_init(dev); /* Enhanced Allocation */ 2482 pci_msi_init(dev); /* Disable MSI */ 2483 pci_msix_init(dev); /* Disable MSI-X */ 2484 2485 /* Buffers for saving PCIe and PCI-X capabilities */ 2486 pci_allocate_cap_save_buffers(dev); 2487 2488 pci_pm_init(dev); /* Power Management */ 2489 pci_vpd_init(dev); /* Vital Product Data */ 2490 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2491 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2492 pci_ats_init(dev); /* Address Translation Services */ 2493 pci_pri_init(dev); /* Page Request Interface */ 2494 pci_pasid_init(dev); /* Process Address Space ID */ 2495 pci_acs_init(dev); /* Access Control Services */ 2496 pci_ptm_init(dev); /* Precision Time Measurement */ 2497 pci_aer_init(dev); /* Advanced Error Reporting */ 2498 pci_dpc_init(dev); /* Downstream Port Containment */ 2499 pci_rcec_init(dev); /* Root Complex Event Collector */ 2500 pci_doe_init(dev); /* Data Object Exchange */ 2501 2502 pcie_report_downtraining(dev); 2503 pci_init_reset_methods(dev); 2504 } 2505 2506 /* 2507 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2508 * devices. Firmware interfaces that can select the MSI domain on a 2509 * per-device basis should be called from here. 2510 */ 2511 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2512 { 2513 struct irq_domain *d; 2514 2515 /* 2516 * If a domain has been set through the pcibios_device_add() 2517 * callback, then this is the one (platform code knows best). 2518 */ 2519 d = dev_get_msi_domain(&dev->dev); 2520 if (d) 2521 return d; 2522 2523 /* 2524 * Let's see if we have a firmware interface able to provide 2525 * the domain. 2526 */ 2527 d = pci_msi_get_device_domain(dev); 2528 if (d) 2529 return d; 2530 2531 return NULL; 2532 } 2533 2534 static void pci_set_msi_domain(struct pci_dev *dev) 2535 { 2536 struct irq_domain *d; 2537 2538 /* 2539 * If the platform or firmware interfaces cannot supply a 2540 * device-specific MSI domain, then inherit the default domain 2541 * from the host bridge itself. 2542 */ 2543 d = pci_dev_msi_domain(dev); 2544 if (!d) 2545 d = dev_get_msi_domain(&dev->bus->dev); 2546 2547 dev_set_msi_domain(&dev->dev, d); 2548 } 2549 2550 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2551 { 2552 int ret; 2553 2554 pci_configure_device(dev); 2555 2556 device_initialize(&dev->dev); 2557 dev->dev.release = pci_release_dev; 2558 2559 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2560 dev->dev.dma_mask = &dev->dma_mask; 2561 dev->dev.dma_parms = &dev->dma_parms; 2562 dev->dev.coherent_dma_mask = 0xffffffffull; 2563 2564 dma_set_max_seg_size(&dev->dev, 65536); 2565 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2566 2567 pcie_failed_link_retrain(dev); 2568 2569 /* Fix up broken headers */ 2570 pci_fixup_device(pci_fixup_header, dev); 2571 2572 pci_reassigndev_resource_alignment(dev); 2573 2574 dev->state_saved = false; 2575 2576 pci_init_capabilities(dev); 2577 2578 /* 2579 * Add the device to our list of discovered devices 2580 * and the bus list for fixup functions, etc. 2581 */ 2582 down_write(&pci_bus_sem); 2583 list_add_tail(&dev->bus_list, &bus->devices); 2584 up_write(&pci_bus_sem); 2585 2586 ret = pcibios_device_add(dev); 2587 WARN_ON(ret < 0); 2588 2589 /* Set up MSI IRQ domain */ 2590 pci_set_msi_domain(dev); 2591 2592 /* Notifier could use PCI capabilities */ 2593 dev->match_driver = false; 2594 ret = device_add(&dev->dev); 2595 WARN_ON(ret < 0); 2596 } 2597 2598 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2599 { 2600 struct pci_dev *dev; 2601 2602 dev = pci_get_slot(bus, devfn); 2603 if (dev) { 2604 pci_dev_put(dev); 2605 return dev; 2606 } 2607 2608 dev = pci_scan_device(bus, devfn); 2609 if (!dev) 2610 return NULL; 2611 2612 pci_device_add(dev, bus); 2613 2614 return dev; 2615 } 2616 EXPORT_SYMBOL(pci_scan_single_device); 2617 2618 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2619 { 2620 int pos; 2621 u16 cap = 0; 2622 unsigned int next_fn; 2623 2624 if (!dev) 2625 return -ENODEV; 2626 2627 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2628 if (!pos) 2629 return -ENODEV; 2630 2631 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2632 next_fn = PCI_ARI_CAP_NFN(cap); 2633 if (next_fn <= fn) 2634 return -ENODEV; /* protect against malformed list */ 2635 2636 return next_fn; 2637 } 2638 2639 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2640 { 2641 if (pci_ari_enabled(bus)) 2642 return next_ari_fn(bus, dev, fn); 2643 2644 if (fn >= 7) 2645 return -ENODEV; 2646 /* only multifunction devices may have more functions */ 2647 if (dev && !dev->multifunction) 2648 return -ENODEV; 2649 2650 return fn + 1; 2651 } 2652 2653 static int only_one_child(struct pci_bus *bus) 2654 { 2655 struct pci_dev *bridge = bus->self; 2656 2657 /* 2658 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2659 * we scan for all possible devices, not just Device 0. 2660 */ 2661 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2662 return 0; 2663 2664 /* 2665 * A PCIe Downstream Port normally leads to a Link with only Device 2666 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2667 * only for Device 0 in that situation. 2668 */ 2669 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2670 return 1; 2671 2672 return 0; 2673 } 2674 2675 /** 2676 * pci_scan_slot - Scan a PCI slot on a bus for devices 2677 * @bus: PCI bus to scan 2678 * @devfn: slot number to scan (must have zero function) 2679 * 2680 * Scan a PCI slot on the specified PCI bus for devices, adding 2681 * discovered devices to the @bus->devices list. New devices 2682 * will not have is_added set. 2683 * 2684 * Returns the number of new devices found. 2685 */ 2686 int pci_scan_slot(struct pci_bus *bus, int devfn) 2687 { 2688 struct pci_dev *dev; 2689 int fn = 0, nr = 0; 2690 2691 if (only_one_child(bus) && (devfn > 0)) 2692 return 0; /* Already scanned the entire slot */ 2693 2694 do { 2695 dev = pci_scan_single_device(bus, devfn + fn); 2696 if (dev) { 2697 if (!pci_dev_is_added(dev)) 2698 nr++; 2699 if (fn > 0) 2700 dev->multifunction = 1; 2701 } else if (fn == 0) { 2702 /* 2703 * Function 0 is required unless we are running on 2704 * a hypervisor that passes through individual PCI 2705 * functions. 2706 */ 2707 if (!hypervisor_isolated_pci_functions()) 2708 break; 2709 } 2710 fn = next_fn(bus, dev, fn); 2711 } while (fn >= 0); 2712 2713 /* Only one slot has PCIe device */ 2714 if (bus->self && nr) 2715 pcie_aspm_init_link_state(bus->self); 2716 2717 return nr; 2718 } 2719 EXPORT_SYMBOL(pci_scan_slot); 2720 2721 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2722 { 2723 u8 *smpss = data; 2724 2725 if (!pci_is_pcie(dev)) 2726 return 0; 2727 2728 /* 2729 * We don't have a way to change MPS settings on devices that have 2730 * drivers attached. A hot-added device might support only the minimum 2731 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2732 * where devices may be hot-added, we limit the fabric MPS to 128 so 2733 * hot-added devices will work correctly. 2734 * 2735 * However, if we hot-add a device to a slot directly below a Root 2736 * Port, it's impossible for there to be other existing devices below 2737 * the port. We don't limit the MPS in this case because we can 2738 * reconfigure MPS on both the Root Port and the hot-added device, 2739 * and there are no other devices involved. 2740 * 2741 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2742 */ 2743 if (dev->is_hotplug_bridge && 2744 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2745 *smpss = 0; 2746 2747 if (*smpss > dev->pcie_mpss) 2748 *smpss = dev->pcie_mpss; 2749 2750 return 0; 2751 } 2752 2753 static void pcie_write_mps(struct pci_dev *dev, int mps) 2754 { 2755 int rc; 2756 2757 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2758 mps = 128 << dev->pcie_mpss; 2759 2760 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2761 dev->bus->self) 2762 2763 /* 2764 * For "Performance", the assumption is made that 2765 * downstream communication will never be larger than 2766 * the MRRS. So, the MPS only needs to be configured 2767 * for the upstream communication. This being the case, 2768 * walk from the top down and set the MPS of the child 2769 * to that of the parent bus. 2770 * 2771 * Configure the device MPS with the smaller of the 2772 * device MPSS or the bridge MPS (which is assumed to be 2773 * properly configured at this point to the largest 2774 * allowable MPS based on its parent bus). 2775 */ 2776 mps = min(mps, pcie_get_mps(dev->bus->self)); 2777 } 2778 2779 rc = pcie_set_mps(dev, mps); 2780 if (rc) 2781 pci_err(dev, "Failed attempting to set the MPS\n"); 2782 } 2783 2784 static void pcie_write_mrrs(struct pci_dev *dev) 2785 { 2786 int rc, mrrs; 2787 2788 /* 2789 * In the "safe" case, do not configure the MRRS. There appear to be 2790 * issues with setting MRRS to 0 on a number of devices. 2791 */ 2792 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2793 return; 2794 2795 /* 2796 * For max performance, the MRRS must be set to the largest supported 2797 * value. However, it cannot be configured larger than the MPS the 2798 * device or the bus can support. This should already be properly 2799 * configured by a prior call to pcie_write_mps(). 2800 */ 2801 mrrs = pcie_get_mps(dev); 2802 2803 /* 2804 * MRRS is a R/W register. Invalid values can be written, but a 2805 * subsequent read will verify if the value is acceptable or not. 2806 * If the MRRS value provided is not acceptable (e.g., too large), 2807 * shrink the value until it is acceptable to the HW. 2808 */ 2809 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2810 rc = pcie_set_readrq(dev, mrrs); 2811 if (!rc) 2812 break; 2813 2814 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2815 mrrs /= 2; 2816 } 2817 2818 if (mrrs < 128) 2819 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2820 } 2821 2822 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2823 { 2824 int mps, orig_mps; 2825 2826 if (!pci_is_pcie(dev)) 2827 return 0; 2828 2829 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2830 pcie_bus_config == PCIE_BUS_DEFAULT) 2831 return 0; 2832 2833 mps = 128 << *(u8 *)data; 2834 orig_mps = pcie_get_mps(dev); 2835 2836 pcie_write_mps(dev, mps); 2837 pcie_write_mrrs(dev); 2838 2839 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2840 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2841 orig_mps, pcie_get_readrq(dev)); 2842 2843 return 0; 2844 } 2845 2846 /* 2847 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2848 * parents then children fashion. If this changes, then this code will not 2849 * work as designed. 2850 */ 2851 void pcie_bus_configure_settings(struct pci_bus *bus) 2852 { 2853 u8 smpss = 0; 2854 2855 if (!bus->self) 2856 return; 2857 2858 if (!pci_is_pcie(bus->self)) 2859 return; 2860 2861 /* 2862 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2863 * to be aware of the MPS of the destination. To work around this, 2864 * simply force the MPS of the entire system to the smallest possible. 2865 */ 2866 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2867 smpss = 0; 2868 2869 if (pcie_bus_config == PCIE_BUS_SAFE) { 2870 smpss = bus->self->pcie_mpss; 2871 2872 pcie_find_smpss(bus->self, &smpss); 2873 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2874 } 2875 2876 pcie_bus_configure_set(bus->self, &smpss); 2877 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2878 } 2879 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2880 2881 /* 2882 * Called after each bus is probed, but before its children are examined. This 2883 * is marked as __weak because multiple architectures define it. 2884 */ 2885 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2886 { 2887 /* nothing to do, expected to be removed in the future */ 2888 } 2889 2890 /** 2891 * pci_scan_child_bus_extend() - Scan devices below a bus 2892 * @bus: Bus to scan for devices 2893 * @available_buses: Total number of buses available (%0 does not try to 2894 * extend beyond the minimal) 2895 * 2896 * Scans devices below @bus including subordinate buses. Returns new 2897 * subordinate number including all the found devices. Passing 2898 * @available_buses causes the remaining bus space to be distributed 2899 * equally between hotplug-capable bridges to allow future extension of the 2900 * hierarchy. 2901 */ 2902 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2903 unsigned int available_buses) 2904 { 2905 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2906 unsigned int start = bus->busn_res.start; 2907 unsigned int devfn, cmax, max = start; 2908 struct pci_dev *dev; 2909 2910 dev_dbg(&bus->dev, "scanning bus\n"); 2911 2912 /* Go find them, Rover! */ 2913 for (devfn = 0; devfn < 256; devfn += 8) 2914 pci_scan_slot(bus, devfn); 2915 2916 /* Reserve buses for SR-IOV capability */ 2917 used_buses = pci_iov_bus_range(bus); 2918 max += used_buses; 2919 2920 /* 2921 * After performing arch-dependent fixup of the bus, look behind 2922 * all PCI-to-PCI bridges on this bus. 2923 */ 2924 if (!bus->is_added) { 2925 dev_dbg(&bus->dev, "fixups for bus\n"); 2926 pcibios_fixup_bus(bus); 2927 bus->is_added = 1; 2928 } 2929 2930 /* 2931 * Calculate how many hotplug bridges and normal bridges there 2932 * are on this bus. We will distribute the additional available 2933 * buses between hotplug bridges. 2934 */ 2935 for_each_pci_bridge(dev, bus) { 2936 if (dev->is_hotplug_bridge) 2937 hotplug_bridges++; 2938 else 2939 normal_bridges++; 2940 } 2941 2942 /* 2943 * Scan bridges that are already configured. We don't touch them 2944 * unless they are misconfigured (which will be done in the second 2945 * scan below). 2946 */ 2947 for_each_pci_bridge(dev, bus) { 2948 cmax = max; 2949 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2950 2951 /* 2952 * Reserve one bus for each bridge now to avoid extending 2953 * hotplug bridges too much during the second scan below. 2954 */ 2955 used_buses++; 2956 if (max - cmax > 1) 2957 used_buses += max - cmax - 1; 2958 } 2959 2960 /* Scan bridges that need to be reconfigured */ 2961 for_each_pci_bridge(dev, bus) { 2962 unsigned int buses = 0; 2963 2964 if (!hotplug_bridges && normal_bridges == 1) { 2965 /* 2966 * There is only one bridge on the bus (upstream 2967 * port) so it gets all available buses which it 2968 * can then distribute to the possible hotplug 2969 * bridges below. 2970 */ 2971 buses = available_buses; 2972 } else if (dev->is_hotplug_bridge) { 2973 /* 2974 * Distribute the extra buses between hotplug 2975 * bridges if any. 2976 */ 2977 buses = available_buses / hotplug_bridges; 2978 buses = min(buses, available_buses - used_buses + 1); 2979 } 2980 2981 cmax = max; 2982 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2983 /* One bus is already accounted so don't add it again */ 2984 if (max - cmax > 1) 2985 used_buses += max - cmax - 1; 2986 } 2987 2988 /* 2989 * Make sure a hotplug bridge has at least the minimum requested 2990 * number of buses but allow it to grow up to the maximum available 2991 * bus number if there is room. 2992 */ 2993 if (bus->self && bus->self->is_hotplug_bridge) { 2994 used_buses = max_t(unsigned int, available_buses, 2995 pci_hotplug_bus_size - 1); 2996 if (max - start < used_buses) { 2997 max = start + used_buses; 2998 2999 /* Do not allocate more buses than we have room left */ 3000 if (max > bus->busn_res.end) 3001 max = bus->busn_res.end; 3002 3003 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 3004 &bus->busn_res, max - start); 3005 } 3006 } 3007 3008 /* 3009 * We've scanned the bus and so we know all about what's on 3010 * the other side of any bridges that may be on this bus plus 3011 * any devices. 3012 * 3013 * Return how far we've got finding sub-buses. 3014 */ 3015 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 3016 return max; 3017 } 3018 3019 /** 3020 * pci_scan_child_bus() - Scan devices below a bus 3021 * @bus: Bus to scan for devices 3022 * 3023 * Scans devices below @bus including subordinate buses. Returns new 3024 * subordinate number including all the found devices. 3025 */ 3026 unsigned int pci_scan_child_bus(struct pci_bus *bus) 3027 { 3028 return pci_scan_child_bus_extend(bus, 0); 3029 } 3030 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3031 3032 /** 3033 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3034 * @bridge: Host bridge to set up 3035 * 3036 * Default empty implementation. Replace with an architecture-specific setup 3037 * routine, if necessary. 3038 */ 3039 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3040 { 3041 return 0; 3042 } 3043 3044 void __weak pcibios_add_bus(struct pci_bus *bus) 3045 { 3046 } 3047 3048 void __weak pcibios_remove_bus(struct pci_bus *bus) 3049 { 3050 } 3051 3052 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3053 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3054 { 3055 int error; 3056 struct pci_host_bridge *bridge; 3057 3058 bridge = pci_alloc_host_bridge(0); 3059 if (!bridge) 3060 return NULL; 3061 3062 bridge->dev.parent = parent; 3063 3064 list_splice_init(resources, &bridge->windows); 3065 bridge->sysdata = sysdata; 3066 bridge->busnr = bus; 3067 bridge->ops = ops; 3068 3069 error = pci_register_host_bridge(bridge); 3070 if (error < 0) 3071 goto err_out; 3072 3073 return bridge->bus; 3074 3075 err_out: 3076 put_device(&bridge->dev); 3077 return NULL; 3078 } 3079 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3080 3081 int pci_host_probe(struct pci_host_bridge *bridge) 3082 { 3083 struct pci_bus *bus, *child; 3084 int ret; 3085 3086 pci_lock_rescan_remove(); 3087 ret = pci_scan_root_bus_bridge(bridge); 3088 pci_unlock_rescan_remove(); 3089 if (ret < 0) { 3090 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3091 return ret; 3092 } 3093 3094 bus = bridge->bus; 3095 3096 /* If we must preserve the resource configuration, claim now */ 3097 if (bridge->preserve_config) 3098 pci_bus_claim_resources(bus); 3099 3100 /* 3101 * Assign whatever was left unassigned. If we didn't claim above, 3102 * this will reassign everything. 3103 */ 3104 pci_assign_unassigned_root_bus_resources(bus); 3105 3106 list_for_each_entry(child, &bus->children, node) 3107 pcie_bus_configure_settings(child); 3108 3109 pci_bus_add_devices(bus); 3110 return 0; 3111 } 3112 EXPORT_SYMBOL_GPL(pci_host_probe); 3113 3114 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3115 { 3116 struct resource *res = &b->busn_res; 3117 struct resource *parent_res, *conflict; 3118 3119 res->start = bus; 3120 res->end = bus_max; 3121 res->flags = IORESOURCE_BUS; 3122 3123 if (!pci_is_root_bus(b)) 3124 parent_res = &b->parent->busn_res; 3125 else { 3126 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3127 res->flags |= IORESOURCE_PCI_FIXED; 3128 } 3129 3130 conflict = request_resource_conflict(parent_res, res); 3131 3132 if (conflict) 3133 dev_info(&b->dev, 3134 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3135 res, pci_is_root_bus(b) ? "domain " : "", 3136 parent_res, conflict->name, conflict); 3137 3138 return conflict == NULL; 3139 } 3140 3141 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3142 { 3143 struct resource *res = &b->busn_res; 3144 struct resource old_res = *res; 3145 resource_size_t size; 3146 int ret; 3147 3148 if (res->start > bus_max) 3149 return -EINVAL; 3150 3151 size = bus_max - res->start + 1; 3152 ret = adjust_resource(res, res->start, size); 3153 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3154 &old_res, ret ? "can not be" : "is", bus_max); 3155 3156 if (!ret && !res->parent) 3157 pci_bus_insert_busn_res(b, res->start, res->end); 3158 3159 return ret; 3160 } 3161 3162 void pci_bus_release_busn_res(struct pci_bus *b) 3163 { 3164 struct resource *res = &b->busn_res; 3165 int ret; 3166 3167 if (!res->flags || !res->parent) 3168 return; 3169 3170 ret = release_resource(res); 3171 dev_info(&b->dev, "busn_res: %pR %s released\n", 3172 res, ret ? "can not be" : "is"); 3173 } 3174 3175 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3176 { 3177 struct resource_entry *window; 3178 bool found = false; 3179 struct pci_bus *b; 3180 int max, bus, ret; 3181 3182 if (!bridge) 3183 return -EINVAL; 3184 3185 resource_list_for_each_entry(window, &bridge->windows) 3186 if (window->res->flags & IORESOURCE_BUS) { 3187 bridge->busnr = window->res->start; 3188 found = true; 3189 break; 3190 } 3191 3192 ret = pci_register_host_bridge(bridge); 3193 if (ret < 0) 3194 return ret; 3195 3196 b = bridge->bus; 3197 bus = bridge->busnr; 3198 3199 if (!found) { 3200 dev_info(&b->dev, 3201 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3202 bus); 3203 pci_bus_insert_busn_res(b, bus, 255); 3204 } 3205 3206 max = pci_scan_child_bus(b); 3207 3208 if (!found) 3209 pci_bus_update_busn_res_end(b, max); 3210 3211 return 0; 3212 } 3213 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3214 3215 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3216 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3217 { 3218 struct resource_entry *window; 3219 bool found = false; 3220 struct pci_bus *b; 3221 int max; 3222 3223 resource_list_for_each_entry(window, resources) 3224 if (window->res->flags & IORESOURCE_BUS) { 3225 found = true; 3226 break; 3227 } 3228 3229 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3230 if (!b) 3231 return NULL; 3232 3233 if (!found) { 3234 dev_info(&b->dev, 3235 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3236 bus); 3237 pci_bus_insert_busn_res(b, bus, 255); 3238 } 3239 3240 max = pci_scan_child_bus(b); 3241 3242 if (!found) 3243 pci_bus_update_busn_res_end(b, max); 3244 3245 return b; 3246 } 3247 EXPORT_SYMBOL(pci_scan_root_bus); 3248 3249 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3250 void *sysdata) 3251 { 3252 LIST_HEAD(resources); 3253 struct pci_bus *b; 3254 3255 pci_add_resource(&resources, &ioport_resource); 3256 pci_add_resource(&resources, &iomem_resource); 3257 pci_add_resource(&resources, &busn_resource); 3258 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3259 if (b) { 3260 pci_scan_child_bus(b); 3261 } else { 3262 pci_free_resource_list(&resources); 3263 } 3264 return b; 3265 } 3266 EXPORT_SYMBOL(pci_scan_bus); 3267 3268 /** 3269 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3270 * @bridge: PCI bridge for the bus to scan 3271 * 3272 * Scan a PCI bus and child buses for new devices, add them, 3273 * and enable them, resizing bridge mmio/io resource if necessary 3274 * and possible. The caller must ensure the child devices are already 3275 * removed for resizing to occur. 3276 * 3277 * Returns the max number of subordinate bus discovered. 3278 */ 3279 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3280 { 3281 unsigned int max; 3282 struct pci_bus *bus = bridge->subordinate; 3283 3284 max = pci_scan_child_bus(bus); 3285 3286 pci_assign_unassigned_bridge_resources(bridge); 3287 3288 pci_bus_add_devices(bus); 3289 3290 return max; 3291 } 3292 3293 /** 3294 * pci_rescan_bus - Scan a PCI bus for devices 3295 * @bus: PCI bus to scan 3296 * 3297 * Scan a PCI bus and child buses for new devices, add them, 3298 * and enable them. 3299 * 3300 * Returns the max number of subordinate bus discovered. 3301 */ 3302 unsigned int pci_rescan_bus(struct pci_bus *bus) 3303 { 3304 unsigned int max; 3305 3306 max = pci_scan_child_bus(bus); 3307 pci_assign_unassigned_bus_resources(bus); 3308 pci_bus_add_devices(bus); 3309 3310 return max; 3311 } 3312 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3313 3314 /* 3315 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3316 * routines should always be executed under this mutex. 3317 */ 3318 static DEFINE_MUTEX(pci_rescan_remove_lock); 3319 3320 void pci_lock_rescan_remove(void) 3321 { 3322 mutex_lock(&pci_rescan_remove_lock); 3323 } 3324 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3325 3326 void pci_unlock_rescan_remove(void) 3327 { 3328 mutex_unlock(&pci_rescan_remove_lock); 3329 } 3330 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3331 3332 static int __init pci_sort_bf_cmp(const struct device *d_a, 3333 const struct device *d_b) 3334 { 3335 const struct pci_dev *a = to_pci_dev(d_a); 3336 const struct pci_dev *b = to_pci_dev(d_b); 3337 3338 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3339 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3340 3341 if (a->bus->number < b->bus->number) return -1; 3342 else if (a->bus->number > b->bus->number) return 1; 3343 3344 if (a->devfn < b->devfn) return -1; 3345 else if (a->devfn > b->devfn) return 1; 3346 3347 return 0; 3348 } 3349 3350 void __init pci_sort_breadthfirst(void) 3351 { 3352 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3353 } 3354 3355 int pci_hp_add_bridge(struct pci_dev *dev) 3356 { 3357 struct pci_bus *parent = dev->bus; 3358 int busnr, start = parent->busn_res.start; 3359 unsigned int available_buses = 0; 3360 int end = parent->busn_res.end; 3361 3362 for (busnr = start; busnr <= end; busnr++) { 3363 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3364 break; 3365 } 3366 if (busnr-- > end) { 3367 pci_err(dev, "No bus number available for hot-added bridge\n"); 3368 return -1; 3369 } 3370 3371 /* Scan bridges that are already configured */ 3372 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3373 3374 /* 3375 * Distribute the available bus numbers between hotplug-capable 3376 * bridges to make extending the chain later possible. 3377 */ 3378 available_buses = end - busnr; 3379 3380 /* Scan bridges that need to be reconfigured */ 3381 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3382 3383 if (!dev->subordinate) 3384 return -1; 3385 3386 return 0; 3387 } 3388 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3389