1 /* 2 * probe.c - PCI detection and setup code 3 */ 4 5 #include <linux/kernel.h> 6 #include <linux/delay.h> 7 #include <linux/init.h> 8 #include <linux/pci.h> 9 #include <linux/slab.h> 10 #include <linux/module.h> 11 #include <linux/cpumask.h> 12 #include <linux/pci-aspm.h> 13 #include <acpi/acpi_hest.h> 14 #include "pci.h" 15 16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 17 #define CARDBUS_RESERVE_BUSNR 3 18 19 /* Ugh. Need to stop exporting this to modules. */ 20 LIST_HEAD(pci_root_buses); 21 EXPORT_SYMBOL(pci_root_buses); 22 23 24 static int find_anything(struct device *dev, void *data) 25 { 26 return 1; 27 } 28 29 /* 30 * Some device drivers need know if pci is initiated. 31 * Basically, we think pci is not initiated when there 32 * is no device to be found on the pci_bus_type. 33 */ 34 int no_pci_devices(void) 35 { 36 struct device *dev; 37 int no_devices; 38 39 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); 40 no_devices = (dev == NULL); 41 put_device(dev); 42 return no_devices; 43 } 44 EXPORT_SYMBOL(no_pci_devices); 45 46 /* 47 * PCI Bus Class Devices 48 */ 49 static ssize_t pci_bus_show_cpuaffinity(struct device *dev, 50 int type, 51 struct device_attribute *attr, 52 char *buf) 53 { 54 int ret; 55 const struct cpumask *cpumask; 56 57 cpumask = cpumask_of_pcibus(to_pci_bus(dev)); 58 ret = type? 59 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) : 60 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); 61 buf[ret++] = '\n'; 62 buf[ret] = '\0'; 63 return ret; 64 } 65 66 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, 67 struct device_attribute *attr, 68 char *buf) 69 { 70 return pci_bus_show_cpuaffinity(dev, 0, attr, buf); 71 } 72 73 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, 74 struct device_attribute *attr, 75 char *buf) 76 { 77 return pci_bus_show_cpuaffinity(dev, 1, attr, buf); 78 } 79 80 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); 81 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); 82 83 /* 84 * PCI Bus Class 85 */ 86 static void release_pcibus_dev(struct device *dev) 87 { 88 struct pci_bus *pci_bus = to_pci_bus(dev); 89 90 if (pci_bus->bridge) 91 put_device(pci_bus->bridge); 92 pci_bus_remove_resources(pci_bus); 93 kfree(pci_bus); 94 } 95 96 static struct class pcibus_class = { 97 .name = "pci_bus", 98 .dev_release = &release_pcibus_dev, 99 }; 100 101 static int __init pcibus_class_init(void) 102 { 103 return class_register(&pcibus_class); 104 } 105 postcore_initcall(pcibus_class_init); 106 107 /* 108 * Translate the low bits of the PCI base 109 * to the resource type 110 */ 111 static inline unsigned int pci_calc_resource_flags(unsigned int flags) 112 { 113 if (flags & PCI_BASE_ADDRESS_SPACE_IO) 114 return IORESOURCE_IO; 115 116 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 117 return IORESOURCE_MEM | IORESOURCE_PREFETCH; 118 119 return IORESOURCE_MEM; 120 } 121 122 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 123 { 124 u64 size = mask & maxbase; /* Find the significant bits */ 125 if (!size) 126 return 0; 127 128 /* Get the lowest of them to find the decode size, and 129 from that the extent. */ 130 size = (size & ~(size-1)) - 1; 131 132 /* base == maxbase can be valid only if the BAR has 133 already been programmed with all 1s. */ 134 if (base == maxbase && ((base | size) & mask) != mask) 135 return 0; 136 137 return size; 138 } 139 140 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) 141 { 142 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 143 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 144 return pci_bar_io; 145 } 146 147 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 148 149 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 150 return pci_bar_mem64; 151 return pci_bar_mem32; 152 } 153 154 /** 155 * pci_read_base - read a PCI BAR 156 * @dev: the PCI device 157 * @type: type of the BAR 158 * @res: resource buffer to be filled in 159 * @pos: BAR position in the config space 160 * 161 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 162 */ 163 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 164 struct resource *res, unsigned int pos) 165 { 166 u32 l, sz, mask; 167 168 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 169 170 res->name = pci_name(dev); 171 172 pci_read_config_dword(dev, pos, &l); 173 pci_write_config_dword(dev, pos, l | mask); 174 pci_read_config_dword(dev, pos, &sz); 175 pci_write_config_dword(dev, pos, l); 176 177 if (!sz) 178 goto fail; /* BAR not implemented */ 179 180 /* 181 * All bits set in sz means the device isn't working properly. 182 * If it's a memory BAR or a ROM, bit 0 must be clear; if it's 183 * an io BAR, bit 1 must be clear. 184 */ 185 if (sz == 0xffffffff) { 186 dev_err(&dev->dev, "reg %x: invalid size %#x; broken device?\n", 187 pos, sz); 188 goto fail; 189 } 190 191 /* 192 * I don't know how l can have all bits set. Copied from old code. 193 * Maybe it fixes a bug on some ancient platform. 194 */ 195 if (l == 0xffffffff) 196 l = 0; 197 198 if (type == pci_bar_unknown) { 199 type = decode_bar(res, l); 200 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; 201 if (type == pci_bar_io) { 202 l &= PCI_BASE_ADDRESS_IO_MASK; 203 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; 204 } else { 205 l &= PCI_BASE_ADDRESS_MEM_MASK; 206 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 207 } 208 } else { 209 res->flags |= (l & IORESOURCE_ROM_ENABLE); 210 l &= PCI_ROM_ADDRESS_MASK; 211 mask = (u32)PCI_ROM_ADDRESS_MASK; 212 } 213 214 if (type == pci_bar_mem64) { 215 u64 l64 = l; 216 u64 sz64 = sz; 217 u64 mask64 = mask | (u64)~0 << 32; 218 219 pci_read_config_dword(dev, pos + 4, &l); 220 pci_write_config_dword(dev, pos + 4, ~0); 221 pci_read_config_dword(dev, pos + 4, &sz); 222 pci_write_config_dword(dev, pos + 4, l); 223 224 l64 |= ((u64)l << 32); 225 sz64 |= ((u64)sz << 32); 226 227 sz64 = pci_size(l64, sz64, mask64); 228 229 if (!sz64) 230 goto fail; 231 232 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 233 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", 234 pos); 235 goto fail; 236 } 237 238 res->flags |= IORESOURCE_MEM_64; 239 if ((sizeof(resource_size_t) < 8) && l) { 240 /* Address above 32-bit boundary; disable the BAR */ 241 pci_write_config_dword(dev, pos, 0); 242 pci_write_config_dword(dev, pos + 4, 0); 243 res->start = 0; 244 res->end = sz64; 245 } else { 246 res->start = l64; 247 res->end = l64 + sz64; 248 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", 249 pos, res); 250 } 251 } else { 252 u32 size = pci_size(l, sz, mask); 253 254 if (!size) { 255 dev_err(&dev->dev, "reg %x: invalid size " 256 "(l %#x sz %#x mask %#x); broken device?", 257 pos, l, sz, mask); 258 goto fail; 259 } 260 261 res->start = l; 262 res->end = l + size; 263 264 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); 265 } 266 267 out: 268 return (type == pci_bar_mem64) ? 1 : 0; 269 fail: 270 res->flags = 0; 271 goto out; 272 } 273 274 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 275 { 276 unsigned int pos, reg; 277 278 for (pos = 0; pos < howmany; pos++) { 279 struct resource *res = &dev->resource[pos]; 280 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 281 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 282 } 283 284 if (rom) { 285 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 286 dev->rom_base_reg = rom; 287 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 288 IORESOURCE_READONLY | IORESOURCE_CACHEABLE | 289 IORESOURCE_SIZEALIGN; 290 __pci_read_base(dev, pci_bar_mem32, res, rom); 291 } 292 } 293 294 static void __devinit pci_read_bridge_io(struct pci_bus *child) 295 { 296 struct pci_dev *dev = child->self; 297 u8 io_base_lo, io_limit_lo; 298 unsigned long base, limit; 299 struct resource *res; 300 301 res = child->resource[0]; 302 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 303 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 304 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 305 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 306 307 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 308 u16 io_base_hi, io_limit_hi; 309 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 310 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 311 base |= (io_base_hi << 16); 312 limit |= (io_limit_hi << 16); 313 } 314 315 if (base && base <= limit) { 316 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 317 if (!res->start) 318 res->start = base; 319 if (!res->end) 320 res->end = limit + 0xfff; 321 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 322 } else { 323 dev_printk(KERN_DEBUG, &dev->dev, 324 " bridge window [io %#06lx-%#06lx] (disabled)\n", 325 base, limit); 326 } 327 } 328 329 static void __devinit pci_read_bridge_mmio(struct pci_bus *child) 330 { 331 struct pci_dev *dev = child->self; 332 u16 mem_base_lo, mem_limit_lo; 333 unsigned long base, limit; 334 struct resource *res; 335 336 res = child->resource[1]; 337 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 338 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 339 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 340 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 341 if (base && base <= limit) { 342 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 343 res->start = base; 344 res->end = limit + 0xfffff; 345 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 346 } else { 347 dev_printk(KERN_DEBUG, &dev->dev, 348 " bridge window [mem %#010lx-%#010lx] (disabled)\n", 349 base, limit + 0xfffff); 350 } 351 } 352 353 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) 354 { 355 struct pci_dev *dev = child->self; 356 u16 mem_base_lo, mem_limit_lo; 357 unsigned long base, limit; 358 struct resource *res; 359 360 res = child->resource[2]; 361 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 362 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 363 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 364 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 365 366 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 367 u32 mem_base_hi, mem_limit_hi; 368 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 369 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 370 371 /* 372 * Some bridges set the base > limit by default, and some 373 * (broken) BIOSes do not initialize them. If we find 374 * this, just assume they are not being used. 375 */ 376 if (mem_base_hi <= mem_limit_hi) { 377 #if BITS_PER_LONG == 64 378 base |= ((long) mem_base_hi) << 32; 379 limit |= ((long) mem_limit_hi) << 32; 380 #else 381 if (mem_base_hi || mem_limit_hi) { 382 dev_err(&dev->dev, "can't handle 64-bit " 383 "address space for bridge\n"); 384 return; 385 } 386 #endif 387 } 388 } 389 if (base && base <= limit) { 390 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 391 IORESOURCE_MEM | IORESOURCE_PREFETCH; 392 if (res->flags & PCI_PREF_RANGE_TYPE_64) 393 res->flags |= IORESOURCE_MEM_64; 394 res->start = base; 395 res->end = limit + 0xfffff; 396 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 397 } else { 398 dev_printk(KERN_DEBUG, &dev->dev, 399 " bridge window [mem %#010lx-%#010lx pref] (disabled)\n", 400 base, limit + 0xfffff); 401 } 402 } 403 404 void __devinit pci_read_bridge_bases(struct pci_bus *child) 405 { 406 struct pci_dev *dev = child->self; 407 struct resource *res; 408 int i; 409 410 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 411 return; 412 413 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", 414 child->secondary, child->subordinate, 415 dev->transparent ? " (subtractive decode)" : ""); 416 417 pci_bus_remove_resources(child); 418 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 419 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 420 421 pci_read_bridge_io(child); 422 pci_read_bridge_mmio(child); 423 pci_read_bridge_mmio_pref(child); 424 425 if (dev->transparent) { 426 pci_bus_for_each_resource(child->parent, res, i) { 427 if (res) { 428 pci_bus_add_resource(child, res, 429 PCI_SUBTRACTIVE_DECODE); 430 dev_printk(KERN_DEBUG, &dev->dev, 431 " bridge window %pR (subtractive decode)\n", 432 res); 433 } 434 } 435 } 436 } 437 438 static struct pci_bus * pci_alloc_bus(void) 439 { 440 struct pci_bus *b; 441 442 b = kzalloc(sizeof(*b), GFP_KERNEL); 443 if (b) { 444 INIT_LIST_HEAD(&b->node); 445 INIT_LIST_HEAD(&b->children); 446 INIT_LIST_HEAD(&b->devices); 447 INIT_LIST_HEAD(&b->slots); 448 INIT_LIST_HEAD(&b->resources); 449 b->max_bus_speed = PCI_SPEED_UNKNOWN; 450 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 451 } 452 return b; 453 } 454 455 static unsigned char pcix_bus_speed[] = { 456 PCI_SPEED_UNKNOWN, /* 0 */ 457 PCI_SPEED_66MHz_PCIX, /* 1 */ 458 PCI_SPEED_100MHz_PCIX, /* 2 */ 459 PCI_SPEED_133MHz_PCIX, /* 3 */ 460 PCI_SPEED_UNKNOWN, /* 4 */ 461 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 462 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 463 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 464 PCI_SPEED_UNKNOWN, /* 8 */ 465 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 466 PCI_SPEED_100MHz_PCIX_266, /* A */ 467 PCI_SPEED_133MHz_PCIX_266, /* B */ 468 PCI_SPEED_UNKNOWN, /* C */ 469 PCI_SPEED_66MHz_PCIX_533, /* D */ 470 PCI_SPEED_100MHz_PCIX_533, /* E */ 471 PCI_SPEED_133MHz_PCIX_533 /* F */ 472 }; 473 474 static unsigned char pcie_link_speed[] = { 475 PCI_SPEED_UNKNOWN, /* 0 */ 476 PCIE_SPEED_2_5GT, /* 1 */ 477 PCIE_SPEED_5_0GT, /* 2 */ 478 PCIE_SPEED_8_0GT, /* 3 */ 479 PCI_SPEED_UNKNOWN, /* 4 */ 480 PCI_SPEED_UNKNOWN, /* 5 */ 481 PCI_SPEED_UNKNOWN, /* 6 */ 482 PCI_SPEED_UNKNOWN, /* 7 */ 483 PCI_SPEED_UNKNOWN, /* 8 */ 484 PCI_SPEED_UNKNOWN, /* 9 */ 485 PCI_SPEED_UNKNOWN, /* A */ 486 PCI_SPEED_UNKNOWN, /* B */ 487 PCI_SPEED_UNKNOWN, /* C */ 488 PCI_SPEED_UNKNOWN, /* D */ 489 PCI_SPEED_UNKNOWN, /* E */ 490 PCI_SPEED_UNKNOWN /* F */ 491 }; 492 493 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 494 { 495 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; 496 } 497 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 498 499 static unsigned char agp_speeds[] = { 500 AGP_UNKNOWN, 501 AGP_1X, 502 AGP_2X, 503 AGP_4X, 504 AGP_8X 505 }; 506 507 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 508 { 509 int index = 0; 510 511 if (agpstat & 4) 512 index = 3; 513 else if (agpstat & 2) 514 index = 2; 515 else if (agpstat & 1) 516 index = 1; 517 else 518 goto out; 519 520 if (agp3) { 521 index += 2; 522 if (index == 5) 523 index = 0; 524 } 525 526 out: 527 return agp_speeds[index]; 528 } 529 530 531 static void pci_set_bus_speed(struct pci_bus *bus) 532 { 533 struct pci_dev *bridge = bus->self; 534 int pos; 535 536 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 537 if (!pos) 538 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 539 if (pos) { 540 u32 agpstat, agpcmd; 541 542 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 543 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 544 545 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 546 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 547 } 548 549 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 550 if (pos) { 551 u16 status; 552 enum pci_bus_speed max; 553 pci_read_config_word(bridge, pos + 2, &status); 554 555 if (status & 0x8000) { 556 max = PCI_SPEED_133MHz_PCIX_533; 557 } else if (status & 0x4000) { 558 max = PCI_SPEED_133MHz_PCIX_266; 559 } else if (status & 0x0002) { 560 if (((status >> 12) & 0x3) == 2) { 561 max = PCI_SPEED_133MHz_PCIX_ECC; 562 } else { 563 max = PCI_SPEED_133MHz_PCIX; 564 } 565 } else { 566 max = PCI_SPEED_66MHz_PCIX; 567 } 568 569 bus->max_bus_speed = max; 570 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; 571 572 return; 573 } 574 575 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); 576 if (pos) { 577 u32 linkcap; 578 u16 linksta; 579 580 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); 581 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; 582 583 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); 584 pcie_update_link_speed(bus, linksta); 585 } 586 } 587 588 589 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 590 struct pci_dev *bridge, int busnr) 591 { 592 struct pci_bus *child; 593 int i; 594 595 /* 596 * Allocate a new bus, and inherit stuff from the parent.. 597 */ 598 child = pci_alloc_bus(); 599 if (!child) 600 return NULL; 601 602 child->parent = parent; 603 child->ops = parent->ops; 604 child->sysdata = parent->sysdata; 605 child->bus_flags = parent->bus_flags; 606 607 /* initialize some portions of the bus device, but don't register it 608 * now as the parent is not properly set up yet. This device will get 609 * registered later in pci_bus_add_devices() 610 */ 611 child->dev.class = &pcibus_class; 612 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 613 614 /* 615 * Set up the primary, secondary and subordinate 616 * bus numbers. 617 */ 618 child->number = child->secondary = busnr; 619 child->primary = parent->secondary; 620 child->subordinate = 0xff; 621 622 if (!bridge) 623 return child; 624 625 child->self = bridge; 626 child->bridge = get_device(&bridge->dev); 627 628 pci_set_bus_speed(child); 629 630 /* Set up default resource pointers and names.. */ 631 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 632 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 633 child->resource[i]->name = child->name; 634 } 635 bridge->subordinate = child; 636 637 return child; 638 } 639 640 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) 641 { 642 struct pci_bus *child; 643 644 child = pci_alloc_child_bus(parent, dev, busnr); 645 if (child) { 646 down_write(&pci_bus_sem); 647 list_add_tail(&child->node, &parent->children); 648 up_write(&pci_bus_sem); 649 } 650 return child; 651 } 652 653 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) 654 { 655 struct pci_bus *parent = child->parent; 656 657 /* Attempts to fix that up are really dangerous unless 658 we're going to re-assign all bus numbers. */ 659 if (!pcibios_assign_all_busses()) 660 return; 661 662 while (parent->parent && parent->subordinate < max) { 663 parent->subordinate = max; 664 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); 665 parent = parent->parent; 666 } 667 } 668 669 /* 670 * If it's a bridge, configure it and scan the bus behind it. 671 * For CardBus bridges, we don't scan behind as the devices will 672 * be handled by the bridge driver itself. 673 * 674 * We need to process bridges in two passes -- first we scan those 675 * already configured by the BIOS and after we are done with all of 676 * them, we proceed to assigning numbers to the remaining buses in 677 * order to avoid overlaps between old and new bus numbers. 678 */ 679 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 680 { 681 struct pci_bus *child; 682 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 683 u32 buses, i, j = 0; 684 u16 bctl; 685 u8 primary, secondary, subordinate; 686 int broken = 0; 687 688 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 689 primary = buses & 0xFF; 690 secondary = (buses >> 8) & 0xFF; 691 subordinate = (buses >> 16) & 0xFF; 692 693 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 694 secondary, subordinate, pass); 695 696 /* Check if setup is sensible at all */ 697 if (!pass && 698 (primary != bus->number || secondary <= bus->number)) { 699 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); 700 broken = 1; 701 } 702 703 /* Disable MasterAbortMode during probing to avoid reporting 704 of bus errors (in some architectures) */ 705 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 706 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 707 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 708 709 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 710 !is_cardbus && !broken) { 711 unsigned int cmax; 712 /* 713 * Bus already configured by firmware, process it in the first 714 * pass and just note the configuration. 715 */ 716 if (pass) 717 goto out; 718 719 /* 720 * If we already got to this bus through a different bridge, 721 * don't re-add it. This can happen with the i450NX chipset. 722 * 723 * However, we continue to descend down the hierarchy and 724 * scan remaining child buses. 725 */ 726 child = pci_find_bus(pci_domain_nr(bus), secondary); 727 if (!child) { 728 child = pci_add_new_bus(bus, dev, secondary); 729 if (!child) 730 goto out; 731 child->primary = primary; 732 child->subordinate = subordinate; 733 child->bridge_ctl = bctl; 734 } 735 736 cmax = pci_scan_child_bus(child); 737 if (cmax > max) 738 max = cmax; 739 if (child->subordinate > max) 740 max = child->subordinate; 741 } else { 742 /* 743 * We need to assign a number to this bus which we always 744 * do in the second pass. 745 */ 746 if (!pass) { 747 if (pcibios_assign_all_busses() || broken) 748 /* Temporarily disable forwarding of the 749 configuration cycles on all bridges in 750 this bus segment to avoid possible 751 conflicts in the second pass between two 752 bridges programmed with overlapping 753 bus ranges. */ 754 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 755 buses & ~0xffffff); 756 goto out; 757 } 758 759 /* Clear errors */ 760 pci_write_config_word(dev, PCI_STATUS, 0xffff); 761 762 /* Prevent assigning a bus number that already exists. 763 * This can happen when a bridge is hot-plugged */ 764 if (pci_find_bus(pci_domain_nr(bus), max+1)) 765 goto out; 766 child = pci_add_new_bus(bus, dev, ++max); 767 buses = (buses & 0xff000000) 768 | ((unsigned int)(child->primary) << 0) 769 | ((unsigned int)(child->secondary) << 8) 770 | ((unsigned int)(child->subordinate) << 16); 771 772 /* 773 * yenta.c forces a secondary latency timer of 176. 774 * Copy that behaviour here. 775 */ 776 if (is_cardbus) { 777 buses &= ~0xff000000; 778 buses |= CARDBUS_LATENCY_TIMER << 24; 779 } 780 781 /* 782 * We need to blast all three values with a single write. 783 */ 784 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 785 786 if (!is_cardbus) { 787 child->bridge_ctl = bctl; 788 /* 789 * Adjust subordinate busnr in parent buses. 790 * We do this before scanning for children because 791 * some devices may not be detected if the bios 792 * was lazy. 793 */ 794 pci_fixup_parent_subordinate_busnr(child, max); 795 /* Now we can scan all subordinate buses... */ 796 max = pci_scan_child_bus(child); 797 /* 798 * now fix it up again since we have found 799 * the real value of max. 800 */ 801 pci_fixup_parent_subordinate_busnr(child, max); 802 } else { 803 /* 804 * For CardBus bridges, we leave 4 bus numbers 805 * as cards with a PCI-to-PCI bridge can be 806 * inserted later. 807 */ 808 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { 809 struct pci_bus *parent = bus; 810 if (pci_find_bus(pci_domain_nr(bus), 811 max+i+1)) 812 break; 813 while (parent->parent) { 814 if ((!pcibios_assign_all_busses()) && 815 (parent->subordinate > max) && 816 (parent->subordinate <= max+i)) { 817 j = 1; 818 } 819 parent = parent->parent; 820 } 821 if (j) { 822 /* 823 * Often, there are two cardbus bridges 824 * -- try to leave one valid bus number 825 * for each one. 826 */ 827 i /= 2; 828 break; 829 } 830 } 831 max += i; 832 pci_fixup_parent_subordinate_busnr(child, max); 833 } 834 /* 835 * Set the subordinate bus number to its real value. 836 */ 837 child->subordinate = max; 838 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 839 } 840 841 sprintf(child->name, 842 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 843 pci_domain_nr(bus), child->number); 844 845 /* Has only triggered on CardBus, fixup is in yenta_socket */ 846 while (bus->parent) { 847 if ((child->subordinate > bus->subordinate) || 848 (child->number > bus->subordinate) || 849 (child->number < bus->number) || 850 (child->subordinate < bus->number)) { 851 dev_info(&child->dev, "[bus %02x-%02x] %s " 852 "hidden behind%s bridge %s [bus %02x-%02x]\n", 853 child->number, child->subordinate, 854 (bus->number > child->subordinate && 855 bus->subordinate < child->number) ? 856 "wholly" : "partially", 857 bus->self->transparent ? " transparent" : "", 858 dev_name(&bus->dev), 859 bus->number, bus->subordinate); 860 } 861 bus = bus->parent; 862 } 863 864 out: 865 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 866 867 return max; 868 } 869 870 /* 871 * Read interrupt line and base address registers. 872 * The architecture-dependent code can tweak these, of course. 873 */ 874 static void pci_read_irq(struct pci_dev *dev) 875 { 876 unsigned char irq; 877 878 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 879 dev->pin = irq; 880 if (irq) 881 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 882 dev->irq = irq; 883 } 884 885 void set_pcie_port_type(struct pci_dev *pdev) 886 { 887 int pos; 888 u16 reg16; 889 890 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 891 if (!pos) 892 return; 893 pdev->is_pcie = 1; 894 pdev->pcie_cap = pos; 895 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 896 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; 897 } 898 899 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 900 { 901 int pos; 902 u16 reg16; 903 u32 reg32; 904 905 pos = pci_pcie_cap(pdev); 906 if (!pos) 907 return; 908 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 909 if (!(reg16 & PCI_EXP_FLAGS_SLOT)) 910 return; 911 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); 912 if (reg32 & PCI_EXP_SLTCAP_HPC) 913 pdev->is_hotplug_bridge = 1; 914 } 915 916 static void set_pci_aer_firmware_first(struct pci_dev *pdev) 917 { 918 if (acpi_hest_firmware_first_pci(pdev)) 919 pdev->aer_firmware_first = 1; 920 } 921 922 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 923 924 /** 925 * pci_setup_device - fill in class and map information of a device 926 * @dev: the device structure to fill 927 * 928 * Initialize the device structure with information about the device's 929 * vendor,class,memory and IO-space addresses,IRQ lines etc. 930 * Called at initialisation of the PCI subsystem and by CardBus services. 931 * Returns 0 on success and negative if unknown type of device (not normal, 932 * bridge or CardBus). 933 */ 934 int pci_setup_device(struct pci_dev *dev) 935 { 936 u32 class; 937 u8 hdr_type; 938 struct pci_slot *slot; 939 int pos = 0; 940 941 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) 942 return -EIO; 943 944 dev->sysdata = dev->bus->sysdata; 945 dev->dev.parent = dev->bus->bridge; 946 dev->dev.bus = &pci_bus_type; 947 dev->hdr_type = hdr_type & 0x7f; 948 dev->multifunction = !!(hdr_type & 0x80); 949 dev->error_state = pci_channel_io_normal; 950 set_pcie_port_type(dev); 951 set_pci_aer_firmware_first(dev); 952 953 list_for_each_entry(slot, &dev->bus->slots, list) 954 if (PCI_SLOT(dev->devfn) == slot->number) 955 dev->slot = slot; 956 957 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 958 set this higher, assuming the system even supports it. */ 959 dev->dma_mask = 0xffffffff; 960 961 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 962 dev->bus->number, PCI_SLOT(dev->devfn), 963 PCI_FUNC(dev->devfn)); 964 965 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 966 dev->revision = class & 0xff; 967 class >>= 8; /* upper 3 bytes */ 968 dev->class = class; 969 class >>= 8; 970 971 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n", 972 dev->vendor, dev->device, class, dev->hdr_type); 973 974 /* need to have dev->class ready */ 975 dev->cfg_size = pci_cfg_space_size(dev); 976 977 /* "Unknown power state" */ 978 dev->current_state = PCI_UNKNOWN; 979 980 /* Early fixups, before probing the BARs */ 981 pci_fixup_device(pci_fixup_early, dev); 982 /* device class may be changed after fixup */ 983 class = dev->class >> 8; 984 985 switch (dev->hdr_type) { /* header type */ 986 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 987 if (class == PCI_CLASS_BRIDGE_PCI) 988 goto bad; 989 pci_read_irq(dev); 990 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 991 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 992 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); 993 994 /* 995 * Do the ugly legacy mode stuff here rather than broken chip 996 * quirk code. Legacy mode ATA controllers have fixed 997 * addresses. These are not always echoed in BAR0-3, and 998 * BAR0-3 in a few cases contain junk! 999 */ 1000 if (class == PCI_CLASS_STORAGE_IDE) { 1001 u8 progif; 1002 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1003 if ((progif & 1) == 0) { 1004 dev->resource[0].start = 0x1F0; 1005 dev->resource[0].end = 0x1F7; 1006 dev->resource[0].flags = LEGACY_IO_RESOURCE; 1007 dev->resource[1].start = 0x3F6; 1008 dev->resource[1].end = 0x3F6; 1009 dev->resource[1].flags = LEGACY_IO_RESOURCE; 1010 } 1011 if ((progif & 4) == 0) { 1012 dev->resource[2].start = 0x170; 1013 dev->resource[2].end = 0x177; 1014 dev->resource[2].flags = LEGACY_IO_RESOURCE; 1015 dev->resource[3].start = 0x376; 1016 dev->resource[3].end = 0x376; 1017 dev->resource[3].flags = LEGACY_IO_RESOURCE; 1018 } 1019 } 1020 break; 1021 1022 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1023 if (class != PCI_CLASS_BRIDGE_PCI) 1024 goto bad; 1025 /* The PCI-to-PCI bridge spec requires that subtractive 1026 decoding (i.e. transparent) bridge must have programming 1027 interface code of 0x01. */ 1028 pci_read_irq(dev); 1029 dev->transparent = ((dev->class & 0xff) == 1); 1030 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1031 set_pcie_hotplug_bridge(dev); 1032 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1033 if (pos) { 1034 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1035 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1036 } 1037 break; 1038 1039 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1040 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1041 goto bad; 1042 pci_read_irq(dev); 1043 pci_read_bases(dev, 1, 0); 1044 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1045 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1046 break; 1047 1048 default: /* unknown header */ 1049 dev_err(&dev->dev, "unknown header type %02x, " 1050 "ignoring device\n", dev->hdr_type); 1051 return -EIO; 1052 1053 bad: 1054 dev_err(&dev->dev, "ignoring class %02x (doesn't match header " 1055 "type %02x)\n", class, dev->hdr_type); 1056 dev->class = PCI_CLASS_NOT_DEFINED; 1057 } 1058 1059 /* We found a fine healthy device, go go go... */ 1060 return 0; 1061 } 1062 1063 static void pci_release_capabilities(struct pci_dev *dev) 1064 { 1065 pci_vpd_release(dev); 1066 pci_iov_release(dev); 1067 } 1068 1069 /** 1070 * pci_release_dev - free a pci device structure when all users of it are finished. 1071 * @dev: device that's been disconnected 1072 * 1073 * Will be called only by the device core when all users of this pci device are 1074 * done. 1075 */ 1076 static void pci_release_dev(struct device *dev) 1077 { 1078 struct pci_dev *pci_dev; 1079 1080 pci_dev = to_pci_dev(dev); 1081 pci_release_capabilities(pci_dev); 1082 kfree(pci_dev); 1083 } 1084 1085 /** 1086 * pci_cfg_space_size - get the configuration space size of the PCI device. 1087 * @dev: PCI device 1088 * 1089 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1090 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1091 * access it. Maybe we don't have a way to generate extended config space 1092 * accesses, or the device is behind a reverse Express bridge. So we try 1093 * reading the dword at 0x100 which must either be 0 or a valid extended 1094 * capability header. 1095 */ 1096 int pci_cfg_space_size_ext(struct pci_dev *dev) 1097 { 1098 u32 status; 1099 int pos = PCI_CFG_SPACE_SIZE; 1100 1101 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1102 goto fail; 1103 if (status == 0xffffffff) 1104 goto fail; 1105 1106 return PCI_CFG_SPACE_EXP_SIZE; 1107 1108 fail: 1109 return PCI_CFG_SPACE_SIZE; 1110 } 1111 1112 int pci_cfg_space_size(struct pci_dev *dev) 1113 { 1114 int pos; 1115 u32 status; 1116 u16 class; 1117 1118 class = dev->class >> 8; 1119 if (class == PCI_CLASS_BRIDGE_HOST) 1120 return pci_cfg_space_size_ext(dev); 1121 1122 pos = pci_pcie_cap(dev); 1123 if (!pos) { 1124 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1125 if (!pos) 1126 goto fail; 1127 1128 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1129 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) 1130 goto fail; 1131 } 1132 1133 return pci_cfg_space_size_ext(dev); 1134 1135 fail: 1136 return PCI_CFG_SPACE_SIZE; 1137 } 1138 1139 static void pci_release_bus_bridge_dev(struct device *dev) 1140 { 1141 kfree(dev); 1142 } 1143 1144 struct pci_dev *alloc_pci_dev(void) 1145 { 1146 struct pci_dev *dev; 1147 1148 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 1149 if (!dev) 1150 return NULL; 1151 1152 INIT_LIST_HEAD(&dev->bus_list); 1153 1154 return dev; 1155 } 1156 EXPORT_SYMBOL(alloc_pci_dev); 1157 1158 /* 1159 * Read the config data for a PCI device, sanity-check it 1160 * and fill in the dev structure... 1161 */ 1162 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 1163 { 1164 struct pci_dev *dev; 1165 u32 l; 1166 int delay = 1; 1167 1168 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 1169 return NULL; 1170 1171 /* some broken boards return 0 or ~0 if a slot is empty: */ 1172 if (l == 0xffffffff || l == 0x00000000 || 1173 l == 0x0000ffff || l == 0xffff0000) 1174 return NULL; 1175 1176 /* Configuration request Retry Status */ 1177 while (l == 0xffff0001) { 1178 msleep(delay); 1179 delay *= 2; 1180 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 1181 return NULL; 1182 /* Card hasn't responded in 60 seconds? Must be stuck. */ 1183 if (delay > 60 * 1000) { 1184 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " 1185 "responding\n", pci_domain_nr(bus), 1186 bus->number, PCI_SLOT(devfn), 1187 PCI_FUNC(devfn)); 1188 return NULL; 1189 } 1190 } 1191 1192 dev = alloc_pci_dev(); 1193 if (!dev) 1194 return NULL; 1195 1196 dev->bus = bus; 1197 dev->devfn = devfn; 1198 dev->vendor = l & 0xffff; 1199 dev->device = (l >> 16) & 0xffff; 1200 1201 if (pci_setup_device(dev)) { 1202 kfree(dev); 1203 return NULL; 1204 } 1205 1206 return dev; 1207 } 1208 1209 static void pci_init_capabilities(struct pci_dev *dev) 1210 { 1211 /* MSI/MSI-X list */ 1212 pci_msi_init_pci_dev(dev); 1213 1214 /* Buffers for saving PCIe and PCI-X capabilities */ 1215 pci_allocate_cap_save_buffers(dev); 1216 1217 /* Power Management */ 1218 pci_pm_init(dev); 1219 platform_pci_wakeup_init(dev); 1220 1221 /* Vital Product Data */ 1222 pci_vpd_pci22_init(dev); 1223 1224 /* Alternative Routing-ID Forwarding */ 1225 pci_enable_ari(dev); 1226 1227 /* Single Root I/O Virtualization */ 1228 pci_iov_init(dev); 1229 1230 /* Enable ACS P2P upstream forwarding */ 1231 pci_enable_acs(dev); 1232 } 1233 1234 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 1235 { 1236 device_initialize(&dev->dev); 1237 dev->dev.release = pci_release_dev; 1238 pci_dev_get(dev); 1239 1240 dev->dev.dma_mask = &dev->dma_mask; 1241 dev->dev.dma_parms = &dev->dma_parms; 1242 dev->dev.coherent_dma_mask = 0xffffffffull; 1243 1244 pci_set_dma_max_seg_size(dev, 65536); 1245 pci_set_dma_seg_boundary(dev, 0xffffffff); 1246 1247 /* Fix up broken headers */ 1248 pci_fixup_device(pci_fixup_header, dev); 1249 1250 /* Clear the state_saved flag. */ 1251 dev->state_saved = false; 1252 1253 /* Initialize various capabilities */ 1254 pci_init_capabilities(dev); 1255 1256 /* 1257 * Add the device to our list of discovered devices 1258 * and the bus list for fixup functions, etc. 1259 */ 1260 down_write(&pci_bus_sem); 1261 list_add_tail(&dev->bus_list, &bus->devices); 1262 up_write(&pci_bus_sem); 1263 } 1264 1265 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) 1266 { 1267 struct pci_dev *dev; 1268 1269 dev = pci_get_slot(bus, devfn); 1270 if (dev) { 1271 pci_dev_put(dev); 1272 return dev; 1273 } 1274 1275 dev = pci_scan_device(bus, devfn); 1276 if (!dev) 1277 return NULL; 1278 1279 pci_device_add(dev, bus); 1280 1281 return dev; 1282 } 1283 EXPORT_SYMBOL(pci_scan_single_device); 1284 1285 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn) 1286 { 1287 u16 cap; 1288 unsigned pos, next_fn; 1289 1290 if (!dev) 1291 return 0; 1292 1293 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 1294 if (!pos) 1295 return 0; 1296 pci_read_config_word(dev, pos + 4, &cap); 1297 next_fn = cap >> 8; 1298 if (next_fn <= fn) 1299 return 0; 1300 return next_fn; 1301 } 1302 1303 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn) 1304 { 1305 return (fn + 1) % 8; 1306 } 1307 1308 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn) 1309 { 1310 return 0; 1311 } 1312 1313 static int only_one_child(struct pci_bus *bus) 1314 { 1315 struct pci_dev *parent = bus->self; 1316 if (!parent || !pci_is_pcie(parent)) 1317 return 0; 1318 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT || 1319 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) 1320 return 1; 1321 return 0; 1322 } 1323 1324 /** 1325 * pci_scan_slot - scan a PCI slot on a bus for devices. 1326 * @bus: PCI bus to scan 1327 * @devfn: slot number to scan (must have zero function.) 1328 * 1329 * Scan a PCI slot on the specified PCI bus for devices, adding 1330 * discovered devices to the @bus->devices list. New devices 1331 * will not have is_added set. 1332 * 1333 * Returns the number of new devices found. 1334 */ 1335 int pci_scan_slot(struct pci_bus *bus, int devfn) 1336 { 1337 unsigned fn, nr = 0; 1338 struct pci_dev *dev; 1339 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn; 1340 1341 if (only_one_child(bus) && (devfn > 0)) 1342 return 0; /* Already scanned the entire slot */ 1343 1344 dev = pci_scan_single_device(bus, devfn); 1345 if (!dev) 1346 return 0; 1347 if (!dev->is_added) 1348 nr++; 1349 1350 if (pci_ari_enabled(bus)) 1351 next_fn = next_ari_fn; 1352 else if (dev->multifunction) 1353 next_fn = next_trad_fn; 1354 1355 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) { 1356 dev = pci_scan_single_device(bus, devfn + fn); 1357 if (dev) { 1358 if (!dev->is_added) 1359 nr++; 1360 dev->multifunction = 1; 1361 } 1362 } 1363 1364 /* only one slot has pcie device */ 1365 if (bus->self && nr) 1366 pcie_aspm_init_link_state(bus->self); 1367 1368 return nr; 1369 } 1370 1371 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) 1372 { 1373 unsigned int devfn, pass, max = bus->secondary; 1374 struct pci_dev *dev; 1375 1376 dev_dbg(&bus->dev, "scanning bus\n"); 1377 1378 /* Go find them, Rover! */ 1379 for (devfn = 0; devfn < 0x100; devfn += 8) 1380 pci_scan_slot(bus, devfn); 1381 1382 /* Reserve buses for SR-IOV capability. */ 1383 max += pci_iov_bus_range(bus); 1384 1385 /* 1386 * After performing arch-dependent fixup of the bus, look behind 1387 * all PCI-to-PCI bridges on this bus. 1388 */ 1389 if (!bus->is_added) { 1390 dev_dbg(&bus->dev, "fixups for bus\n"); 1391 pcibios_fixup_bus(bus); 1392 if (pci_is_root_bus(bus)) 1393 bus->is_added = 1; 1394 } 1395 1396 for (pass=0; pass < 2; pass++) 1397 list_for_each_entry(dev, &bus->devices, bus_list) { 1398 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1399 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1400 max = pci_scan_bridge(bus, dev, max, pass); 1401 } 1402 1403 /* 1404 * We've scanned the bus and so we know all about what's on 1405 * the other side of any bridges that may be on this bus plus 1406 * any devices. 1407 * 1408 * Return how far we've got finding sub-buses. 1409 */ 1410 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 1411 return max; 1412 } 1413 1414 struct pci_bus * pci_create_bus(struct device *parent, 1415 int bus, struct pci_ops *ops, void *sysdata) 1416 { 1417 int error; 1418 struct pci_bus *b, *b2; 1419 struct device *dev; 1420 1421 b = pci_alloc_bus(); 1422 if (!b) 1423 return NULL; 1424 1425 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1426 if (!dev){ 1427 kfree(b); 1428 return NULL; 1429 } 1430 1431 b->sysdata = sysdata; 1432 b->ops = ops; 1433 1434 b2 = pci_find_bus(pci_domain_nr(b), bus); 1435 if (b2) { 1436 /* If we already got to this bus through a different bridge, ignore it */ 1437 dev_dbg(&b2->dev, "bus already known\n"); 1438 goto err_out; 1439 } 1440 1441 down_write(&pci_bus_sem); 1442 list_add_tail(&b->node, &pci_root_buses); 1443 up_write(&pci_bus_sem); 1444 1445 dev->parent = parent; 1446 dev->release = pci_release_bus_bridge_dev; 1447 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); 1448 error = device_register(dev); 1449 if (error) 1450 goto dev_reg_err; 1451 b->bridge = get_device(dev); 1452 device_enable_async_suspend(b->bridge); 1453 1454 if (!parent) 1455 set_dev_node(b->bridge, pcibus_to_node(b)); 1456 1457 b->dev.class = &pcibus_class; 1458 b->dev.parent = b->bridge; 1459 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); 1460 error = device_register(&b->dev); 1461 if (error) 1462 goto class_dev_reg_err; 1463 error = device_create_file(&b->dev, &dev_attr_cpuaffinity); 1464 if (error) 1465 goto dev_create_file_err; 1466 1467 /* Create legacy_io and legacy_mem files for this bus */ 1468 pci_create_legacy_files(b); 1469 1470 b->number = b->secondary = bus; 1471 b->resource[0] = &ioport_resource; 1472 b->resource[1] = &iomem_resource; 1473 1474 return b; 1475 1476 dev_create_file_err: 1477 device_unregister(&b->dev); 1478 class_dev_reg_err: 1479 device_unregister(dev); 1480 dev_reg_err: 1481 down_write(&pci_bus_sem); 1482 list_del(&b->node); 1483 up_write(&pci_bus_sem); 1484 err_out: 1485 kfree(dev); 1486 kfree(b); 1487 return NULL; 1488 } 1489 1490 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, 1491 int bus, struct pci_ops *ops, void *sysdata) 1492 { 1493 struct pci_bus *b; 1494 1495 b = pci_create_bus(parent, bus, ops, sysdata); 1496 if (b) 1497 b->subordinate = pci_scan_child_bus(b); 1498 return b; 1499 } 1500 EXPORT_SYMBOL(pci_scan_bus_parented); 1501 1502 #ifdef CONFIG_HOTPLUG 1503 /** 1504 * pci_rescan_bus - scan a PCI bus for devices. 1505 * @bus: PCI bus to scan 1506 * 1507 * Scan a PCI bus and child buses for new devices, adds them, 1508 * and enables them. 1509 * 1510 * Returns the max number of subordinate bus discovered. 1511 */ 1512 unsigned int __ref pci_rescan_bus(struct pci_bus *bus) 1513 { 1514 unsigned int max; 1515 struct pci_dev *dev; 1516 1517 max = pci_scan_child_bus(bus); 1518 1519 down_read(&pci_bus_sem); 1520 list_for_each_entry(dev, &bus->devices, bus_list) 1521 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1522 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1523 if (dev->subordinate) 1524 pci_bus_size_bridges(dev->subordinate); 1525 up_read(&pci_bus_sem); 1526 1527 pci_bus_assign_resources(bus); 1528 pci_enable_bridges(bus); 1529 pci_bus_add_devices(bus); 1530 1531 return max; 1532 } 1533 EXPORT_SYMBOL_GPL(pci_rescan_bus); 1534 1535 EXPORT_SYMBOL(pci_add_new_bus); 1536 EXPORT_SYMBOL(pci_scan_slot); 1537 EXPORT_SYMBOL(pci_scan_bridge); 1538 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 1539 #endif 1540 1541 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) 1542 { 1543 const struct pci_dev *a = to_pci_dev(d_a); 1544 const struct pci_dev *b = to_pci_dev(d_b); 1545 1546 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 1547 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 1548 1549 if (a->bus->number < b->bus->number) return -1; 1550 else if (a->bus->number > b->bus->number) return 1; 1551 1552 if (a->devfn < b->devfn) return -1; 1553 else if (a->devfn > b->devfn) return 1; 1554 1555 return 0; 1556 } 1557 1558 void __init pci_sort_breadthfirst(void) 1559 { 1560 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 1561 } 1562