1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_device.h> 12 #include <linux/of_pci.h> 13 #include <linux/pci_hotplug.h> 14 #include <linux/slab.h> 15 #include <linux/module.h> 16 #include <linux/cpumask.h> 17 #include <linux/aer.h> 18 #include <linux/acpi.h> 19 #include <linux/hypervisor.h> 20 #include <linux/irqdomain.h> 21 #include <linux/pm_runtime.h> 22 #include "pci.h" 23 24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 25 #define CARDBUS_RESERVE_BUSNR 3 26 27 static struct resource busn_resource = { 28 .name = "PCI busn", 29 .start = 0, 30 .end = 255, 31 .flags = IORESOURCE_BUS, 32 }; 33 34 /* Ugh. Need to stop exporting this to modules. */ 35 LIST_HEAD(pci_root_buses); 36 EXPORT_SYMBOL(pci_root_buses); 37 38 static LIST_HEAD(pci_domain_busn_res_list); 39 40 struct pci_domain_busn_res { 41 struct list_head list; 42 struct resource res; 43 int domain_nr; 44 }; 45 46 static struct resource *get_pci_domain_busn_res(int domain_nr) 47 { 48 struct pci_domain_busn_res *r; 49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list) 51 if (r->domain_nr == domain_nr) 52 return &r->res; 53 54 r = kzalloc(sizeof(*r), GFP_KERNEL); 55 if (!r) 56 return NULL; 57 58 r->domain_nr = domain_nr; 59 r->res.start = 0; 60 r->res.end = 0xff; 61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 62 63 list_add_tail(&r->list, &pci_domain_busn_res_list); 64 65 return &r->res; 66 } 67 68 /* 69 * Some device drivers need know if PCI is initiated. 70 * Basically, we think PCI is not initiated when there 71 * is no device to be found on the pci_bus_type. 72 */ 73 int no_pci_devices(void) 74 { 75 struct device *dev; 76 int no_devices; 77 78 dev = bus_find_next_device(&pci_bus_type, NULL); 79 no_devices = (dev == NULL); 80 put_device(dev); 81 return no_devices; 82 } 83 EXPORT_SYMBOL(no_pci_devices); 84 85 /* 86 * PCI Bus Class 87 */ 88 static void release_pcibus_dev(struct device *dev) 89 { 90 struct pci_bus *pci_bus = to_pci_bus(dev); 91 92 put_device(pci_bus->bridge); 93 pci_bus_remove_resources(pci_bus); 94 pci_release_bus_of_node(pci_bus); 95 kfree(pci_bus); 96 } 97 98 static struct class pcibus_class = { 99 .name = "pci_bus", 100 .dev_release = &release_pcibus_dev, 101 .dev_groups = pcibus_groups, 102 }; 103 104 static int __init pcibus_class_init(void) 105 { 106 return class_register(&pcibus_class); 107 } 108 postcore_initcall(pcibus_class_init); 109 110 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 111 { 112 u64 size = mask & maxbase; /* Find the significant bits */ 113 if (!size) 114 return 0; 115 116 /* 117 * Get the lowest of them to find the decode size, and from that 118 * the extent. 119 */ 120 size = size & ~(size-1); 121 122 /* 123 * base == maxbase can be valid only if the BAR has already been 124 * programmed with all 1s. 125 */ 126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 127 return 0; 128 129 return size; 130 } 131 132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 133 { 134 u32 mem_type; 135 unsigned long flags; 136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 139 flags |= IORESOURCE_IO; 140 return flags; 141 } 142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 144 flags |= IORESOURCE_MEM; 145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 146 flags |= IORESOURCE_PREFETCH; 147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 149 switch (mem_type) { 150 case PCI_BASE_ADDRESS_MEM_TYPE_32: 151 break; 152 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 153 /* 1M mem BAR treated as 32-bit BAR */ 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_64: 156 flags |= IORESOURCE_MEM_64; 157 break; 158 default: 159 /* mem unknown type treated as 32-bit BAR */ 160 break; 161 } 162 return flags; 163 } 164 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 167 /** 168 * pci_read_base - Read a PCI BAR 169 * @dev: the PCI device 170 * @type: type of the BAR 171 * @res: resource buffer to be filled in 172 * @pos: BAR position in the config space 173 * 174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 175 */ 176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 177 struct resource *res, unsigned int pos) 178 { 179 u32 l = 0, sz = 0, mask; 180 u64 l64, sz64, mask64; 181 u16 orig_cmd; 182 struct pci_bus_region region, inverted_region; 183 184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 185 186 /* No printks while decoding is disabled! */ 187 if (!dev->mmio_always_on) { 188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 190 pci_write_config_word(dev, PCI_COMMAND, 191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 192 } 193 } 194 195 res->name = pci_name(dev); 196 197 pci_read_config_dword(dev, pos, &l); 198 pci_write_config_dword(dev, pos, l | mask); 199 pci_read_config_dword(dev, pos, &sz); 200 pci_write_config_dword(dev, pos, l); 201 202 /* 203 * All bits set in sz means the device isn't working properly. 204 * If the BAR isn't implemented, all bits must be 0. If it's a 205 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 206 * 1 must be clear. 207 */ 208 if (sz == 0xffffffff) 209 sz = 0; 210 211 /* 212 * I don't know how l can have all bits set. Copied from old code. 213 * Maybe it fixes a bug on some ancient platform. 214 */ 215 if (l == 0xffffffff) 216 l = 0; 217 218 if (type == pci_bar_unknown) { 219 res->flags = decode_bar(dev, l); 220 res->flags |= IORESOURCE_SIZEALIGN; 221 if (res->flags & IORESOURCE_IO) { 222 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 225 } else { 226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 229 } 230 } else { 231 if (l & PCI_ROM_ADDRESS_ENABLE) 232 res->flags |= IORESOURCE_ROM_ENABLE; 233 l64 = l & PCI_ROM_ADDRESS_MASK; 234 sz64 = sz & PCI_ROM_ADDRESS_MASK; 235 mask64 = PCI_ROM_ADDRESS_MASK; 236 } 237 238 if (res->flags & IORESOURCE_MEM_64) { 239 pci_read_config_dword(dev, pos + 4, &l); 240 pci_write_config_dword(dev, pos + 4, ~0); 241 pci_read_config_dword(dev, pos + 4, &sz); 242 pci_write_config_dword(dev, pos + 4, l); 243 244 l64 |= ((u64)l << 32); 245 sz64 |= ((u64)sz << 32); 246 mask64 |= ((u64)~0 << 32); 247 } 248 249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 251 252 if (!sz64) 253 goto fail; 254 255 sz64 = pci_size(l64, sz64, mask64); 256 if (!sz64) { 257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", 258 pos); 259 goto fail; 260 } 261 262 if (res->flags & IORESOURCE_MEM_64) { 263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 264 && sz64 > 0x100000000ULL) { 265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 266 res->start = 0; 267 res->end = 0; 268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", 269 pos, (unsigned long long)sz64); 270 goto out; 271 } 272 273 if ((sizeof(pci_bus_addr_t) < 8) && l) { 274 /* Above 32-bit boundary; try to reallocate */ 275 res->flags |= IORESOURCE_UNSET; 276 res->start = 0; 277 res->end = sz64 - 1; 278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", 279 pos, (unsigned long long)l64); 280 goto out; 281 } 282 } 283 284 region.start = l64; 285 region.end = l64 + sz64 - 1; 286 287 pcibios_bus_to_resource(dev->bus, res, ®ion); 288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 289 290 /* 291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 292 * the corresponding resource address (the physical address used by 293 * the CPU. Converting that resource address back to a bus address 294 * should yield the original BAR value: 295 * 296 * resource_to_bus(bus_to_resource(A)) == A 297 * 298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 299 * be claimed by the device. 300 */ 301 if (inverted_region.start != region.start) { 302 res->flags |= IORESOURCE_UNSET; 303 res->start = 0; 304 res->end = region.end - region.start; 305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", 306 pos, (unsigned long long)region.start); 307 } 308 309 goto out; 310 311 312 fail: 313 res->flags = 0; 314 out: 315 if (res->flags) 316 pci_info(dev, "reg 0x%x: %pR\n", pos, res); 317 318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 319 } 320 321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 322 { 323 unsigned int pos, reg; 324 325 if (dev->non_compliant_bars) 326 return; 327 328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 329 if (dev->is_virtfn) 330 return; 331 332 for (pos = 0; pos < howmany; pos++) { 333 struct resource *res = &dev->resource[pos]; 334 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 336 } 337 338 if (rom) { 339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 340 dev->rom_base_reg = rom; 341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 343 __pci_read_base(dev, pci_bar_mem32, res, rom); 344 } 345 } 346 347 static void pci_read_bridge_windows(struct pci_dev *bridge) 348 { 349 u16 io; 350 u32 pmem, tmp; 351 352 pci_read_config_word(bridge, PCI_IO_BASE, &io); 353 if (!io) { 354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 355 pci_read_config_word(bridge, PCI_IO_BASE, &io); 356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 357 } 358 if (io) 359 bridge->io_window = 1; 360 361 /* 362 * DECchip 21050 pass 2 errata: the bridge may miss an address 363 * disconnect boundary by one PCI data phase. Workaround: do not 364 * use prefetching on this device. 365 */ 366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 367 return; 368 369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 370 if (!pmem) { 371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 372 0xffe0fff0); 373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 375 } 376 if (!pmem) 377 return; 378 379 bridge->pref_window = 1; 380 381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 382 383 /* 384 * Bridge claims to have a 64-bit prefetchable memory 385 * window; verify that the upper bits are actually 386 * writable. 387 */ 388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 390 0xffffffff); 391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 393 if (tmp) 394 bridge->pref_64_window = 1; 395 } 396 } 397 398 static void pci_read_bridge_io(struct pci_bus *child) 399 { 400 struct pci_dev *dev = child->self; 401 u8 io_base_lo, io_limit_lo; 402 unsigned long io_mask, io_granularity, base, limit; 403 struct pci_bus_region region; 404 struct resource *res; 405 406 io_mask = PCI_IO_RANGE_MASK; 407 io_granularity = 0x1000; 408 if (dev->io_window_1k) { 409 /* Support 1K I/O space granularity */ 410 io_mask = PCI_IO_1K_RANGE_MASK; 411 io_granularity = 0x400; 412 } 413 414 res = child->resource[0]; 415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 417 base = (io_base_lo & io_mask) << 8; 418 limit = (io_limit_lo & io_mask) << 8; 419 420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 421 u16 io_base_hi, io_limit_hi; 422 423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 425 base |= ((unsigned long) io_base_hi << 16); 426 limit |= ((unsigned long) io_limit_hi << 16); 427 } 428 429 if (base <= limit) { 430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 431 region.start = base; 432 region.end = limit + io_granularity - 1; 433 pcibios_bus_to_resource(dev->bus, res, ®ion); 434 pci_info(dev, " bridge window %pR\n", res); 435 } 436 } 437 438 static void pci_read_bridge_mmio(struct pci_bus *child) 439 { 440 struct pci_dev *dev = child->self; 441 u16 mem_base_lo, mem_limit_lo; 442 unsigned long base, limit; 443 struct pci_bus_region region; 444 struct resource *res; 445 446 res = child->resource[1]; 447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 451 if (base <= limit) { 452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 453 region.start = base; 454 region.end = limit + 0xfffff; 455 pcibios_bus_to_resource(dev->bus, res, ®ion); 456 pci_info(dev, " bridge window %pR\n", res); 457 } 458 } 459 460 static void pci_read_bridge_mmio_pref(struct pci_bus *child) 461 { 462 struct pci_dev *dev = child->self; 463 u16 mem_base_lo, mem_limit_lo; 464 u64 base64, limit64; 465 pci_bus_addr_t base, limit; 466 struct pci_bus_region region; 467 struct resource *res; 468 469 res = child->resource[2]; 470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 474 475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 476 u32 mem_base_hi, mem_limit_hi; 477 478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 480 481 /* 482 * Some bridges set the base > limit by default, and some 483 * (broken) BIOSes do not initialize them. If we find 484 * this, just assume they are not being used. 485 */ 486 if (mem_base_hi <= mem_limit_hi) { 487 base64 |= (u64) mem_base_hi << 32; 488 limit64 |= (u64) mem_limit_hi << 32; 489 } 490 } 491 492 base = (pci_bus_addr_t) base64; 493 limit = (pci_bus_addr_t) limit64; 494 495 if (base != base64) { 496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 497 (unsigned long long) base64); 498 return; 499 } 500 501 if (base <= limit) { 502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 503 IORESOURCE_MEM | IORESOURCE_PREFETCH; 504 if (res->flags & PCI_PREF_RANGE_TYPE_64) 505 res->flags |= IORESOURCE_MEM_64; 506 region.start = base; 507 region.end = limit + 0xfffff; 508 pcibios_bus_to_resource(dev->bus, res, ®ion); 509 pci_info(dev, " bridge window %pR\n", res); 510 } 511 } 512 513 void pci_read_bridge_bases(struct pci_bus *child) 514 { 515 struct pci_dev *dev = child->self; 516 struct resource *res; 517 int i; 518 519 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 520 return; 521 522 pci_info(dev, "PCI bridge to %pR%s\n", 523 &child->busn_res, 524 dev->transparent ? " (subtractive decode)" : ""); 525 526 pci_bus_remove_resources(child); 527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 529 530 pci_read_bridge_io(child); 531 pci_read_bridge_mmio(child); 532 pci_read_bridge_mmio_pref(child); 533 534 if (dev->transparent) { 535 pci_bus_for_each_resource(child->parent, res, i) { 536 if (res && res->flags) { 537 pci_bus_add_resource(child, res, 538 PCI_SUBTRACTIVE_DECODE); 539 pci_info(dev, " bridge window %pR (subtractive decode)\n", 540 res); 541 } 542 } 543 } 544 } 545 546 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 547 { 548 struct pci_bus *b; 549 550 b = kzalloc(sizeof(*b), GFP_KERNEL); 551 if (!b) 552 return NULL; 553 554 INIT_LIST_HEAD(&b->node); 555 INIT_LIST_HEAD(&b->children); 556 INIT_LIST_HEAD(&b->devices); 557 INIT_LIST_HEAD(&b->slots); 558 INIT_LIST_HEAD(&b->resources); 559 b->max_bus_speed = PCI_SPEED_UNKNOWN; 560 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 561 #ifdef CONFIG_PCI_DOMAINS_GENERIC 562 if (parent) 563 b->domain_nr = parent->domain_nr; 564 #endif 565 return b; 566 } 567 568 static void devm_pci_release_host_bridge_dev(struct device *dev) 569 { 570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 571 572 if (bridge->release_fn) 573 bridge->release_fn(bridge); 574 575 pci_free_resource_list(&bridge->windows); 576 pci_free_resource_list(&bridge->dma_ranges); 577 } 578 579 static void pci_release_host_bridge_dev(struct device *dev) 580 { 581 devm_pci_release_host_bridge_dev(dev); 582 kfree(to_pci_host_bridge(dev)); 583 } 584 585 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 586 { 587 INIT_LIST_HEAD(&bridge->windows); 588 INIT_LIST_HEAD(&bridge->dma_ranges); 589 590 /* 591 * We assume we can manage these PCIe features. Some systems may 592 * reserve these for use by the platform itself, e.g., an ACPI BIOS 593 * may implement its own AER handling and use _OSC to prevent the 594 * OS from interfering. 595 */ 596 bridge->native_aer = 1; 597 bridge->native_pcie_hotplug = 1; 598 bridge->native_shpc_hotplug = 1; 599 bridge->native_pme = 1; 600 bridge->native_ltr = 1; 601 } 602 603 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 604 { 605 struct pci_host_bridge *bridge; 606 607 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 608 if (!bridge) 609 return NULL; 610 611 pci_init_host_bridge(bridge); 612 bridge->dev.release = pci_release_host_bridge_dev; 613 614 return bridge; 615 } 616 EXPORT_SYMBOL(pci_alloc_host_bridge); 617 618 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 619 size_t priv) 620 { 621 struct pci_host_bridge *bridge; 622 623 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL); 624 if (!bridge) 625 return NULL; 626 627 pci_init_host_bridge(bridge); 628 bridge->dev.release = devm_pci_release_host_bridge_dev; 629 630 return bridge; 631 } 632 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 633 634 void pci_free_host_bridge(struct pci_host_bridge *bridge) 635 { 636 pci_free_resource_list(&bridge->windows); 637 pci_free_resource_list(&bridge->dma_ranges); 638 639 kfree(bridge); 640 } 641 EXPORT_SYMBOL(pci_free_host_bridge); 642 643 static const unsigned char pcix_bus_speed[] = { 644 PCI_SPEED_UNKNOWN, /* 0 */ 645 PCI_SPEED_66MHz_PCIX, /* 1 */ 646 PCI_SPEED_100MHz_PCIX, /* 2 */ 647 PCI_SPEED_133MHz_PCIX, /* 3 */ 648 PCI_SPEED_UNKNOWN, /* 4 */ 649 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 650 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 651 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 652 PCI_SPEED_UNKNOWN, /* 8 */ 653 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 654 PCI_SPEED_100MHz_PCIX_266, /* A */ 655 PCI_SPEED_133MHz_PCIX_266, /* B */ 656 PCI_SPEED_UNKNOWN, /* C */ 657 PCI_SPEED_66MHz_PCIX_533, /* D */ 658 PCI_SPEED_100MHz_PCIX_533, /* E */ 659 PCI_SPEED_133MHz_PCIX_533 /* F */ 660 }; 661 662 const unsigned char pcie_link_speed[] = { 663 PCI_SPEED_UNKNOWN, /* 0 */ 664 PCIE_SPEED_2_5GT, /* 1 */ 665 PCIE_SPEED_5_0GT, /* 2 */ 666 PCIE_SPEED_8_0GT, /* 3 */ 667 PCIE_SPEED_16_0GT, /* 4 */ 668 PCIE_SPEED_32_0GT, /* 5 */ 669 PCI_SPEED_UNKNOWN, /* 6 */ 670 PCI_SPEED_UNKNOWN, /* 7 */ 671 PCI_SPEED_UNKNOWN, /* 8 */ 672 PCI_SPEED_UNKNOWN, /* 9 */ 673 PCI_SPEED_UNKNOWN, /* A */ 674 PCI_SPEED_UNKNOWN, /* B */ 675 PCI_SPEED_UNKNOWN, /* C */ 676 PCI_SPEED_UNKNOWN, /* D */ 677 PCI_SPEED_UNKNOWN, /* E */ 678 PCI_SPEED_UNKNOWN /* F */ 679 }; 680 681 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 682 { 683 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 684 } 685 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 686 687 static unsigned char agp_speeds[] = { 688 AGP_UNKNOWN, 689 AGP_1X, 690 AGP_2X, 691 AGP_4X, 692 AGP_8X 693 }; 694 695 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 696 { 697 int index = 0; 698 699 if (agpstat & 4) 700 index = 3; 701 else if (agpstat & 2) 702 index = 2; 703 else if (agpstat & 1) 704 index = 1; 705 else 706 goto out; 707 708 if (agp3) { 709 index += 2; 710 if (index == 5) 711 index = 0; 712 } 713 714 out: 715 return agp_speeds[index]; 716 } 717 718 static void pci_set_bus_speed(struct pci_bus *bus) 719 { 720 struct pci_dev *bridge = bus->self; 721 int pos; 722 723 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 724 if (!pos) 725 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 726 if (pos) { 727 u32 agpstat, agpcmd; 728 729 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 730 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 731 732 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 733 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 734 } 735 736 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 737 if (pos) { 738 u16 status; 739 enum pci_bus_speed max; 740 741 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 742 &status); 743 744 if (status & PCI_X_SSTATUS_533MHZ) { 745 max = PCI_SPEED_133MHz_PCIX_533; 746 } else if (status & PCI_X_SSTATUS_266MHZ) { 747 max = PCI_SPEED_133MHz_PCIX_266; 748 } else if (status & PCI_X_SSTATUS_133MHZ) { 749 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 750 max = PCI_SPEED_133MHz_PCIX_ECC; 751 else 752 max = PCI_SPEED_133MHz_PCIX; 753 } else { 754 max = PCI_SPEED_66MHz_PCIX; 755 } 756 757 bus->max_bus_speed = max; 758 bus->cur_bus_speed = pcix_bus_speed[ 759 (status & PCI_X_SSTATUS_FREQ) >> 6]; 760 761 return; 762 } 763 764 if (pci_is_pcie(bridge)) { 765 u32 linkcap; 766 u16 linksta; 767 768 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 769 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 770 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); 771 772 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 773 pcie_update_link_speed(bus, linksta); 774 } 775 } 776 777 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 778 { 779 struct irq_domain *d; 780 781 /* 782 * Any firmware interface that can resolve the msi_domain 783 * should be called from here. 784 */ 785 d = pci_host_bridge_of_msi_domain(bus); 786 if (!d) 787 d = pci_host_bridge_acpi_msi_domain(bus); 788 789 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN 790 /* 791 * If no IRQ domain was found via the OF tree, try looking it up 792 * directly through the fwnode_handle. 793 */ 794 if (!d) { 795 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 796 797 if (fwnode) 798 d = irq_find_matching_fwnode(fwnode, 799 DOMAIN_BUS_PCI_MSI); 800 } 801 #endif 802 803 return d; 804 } 805 806 static void pci_set_bus_msi_domain(struct pci_bus *bus) 807 { 808 struct irq_domain *d; 809 struct pci_bus *b; 810 811 /* 812 * The bus can be a root bus, a subordinate bus, or a virtual bus 813 * created by an SR-IOV device. Walk up to the first bridge device 814 * found or derive the domain from the host bridge. 815 */ 816 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 817 if (b->self) 818 d = dev_get_msi_domain(&b->self->dev); 819 } 820 821 if (!d) 822 d = pci_host_bridge_msi_domain(b); 823 824 dev_set_msi_domain(&bus->dev, d); 825 } 826 827 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 828 { 829 struct device *parent = bridge->dev.parent; 830 struct resource_entry *window, *n; 831 struct pci_bus *bus, *b; 832 resource_size_t offset; 833 LIST_HEAD(resources); 834 struct resource *res; 835 char addr[64], *fmt; 836 const char *name; 837 int err; 838 839 bus = pci_alloc_bus(NULL); 840 if (!bus) 841 return -ENOMEM; 842 843 bridge->bus = bus; 844 845 /* Temporarily move resources off the list */ 846 list_splice_init(&bridge->windows, &resources); 847 bus->sysdata = bridge->sysdata; 848 bus->msi = bridge->msi; 849 bus->ops = bridge->ops; 850 bus->number = bus->busn_res.start = bridge->busnr; 851 #ifdef CONFIG_PCI_DOMAINS_GENERIC 852 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 853 #endif 854 855 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 856 if (b) { 857 /* Ignore it if we already got here via a different bridge */ 858 dev_dbg(&b->dev, "bus already known\n"); 859 err = -EEXIST; 860 goto free; 861 } 862 863 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 864 bridge->busnr); 865 866 err = pcibios_root_bridge_prepare(bridge); 867 if (err) 868 goto free; 869 870 err = device_register(&bridge->dev); 871 if (err) 872 put_device(&bridge->dev); 873 874 bus->bridge = get_device(&bridge->dev); 875 device_enable_async_suspend(bus->bridge); 876 pci_set_bus_of_node(bus); 877 pci_set_bus_msi_domain(bus); 878 879 if (!parent) 880 set_dev_node(bus->bridge, pcibus_to_node(bus)); 881 882 bus->dev.class = &pcibus_class; 883 bus->dev.parent = bus->bridge; 884 885 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 886 name = dev_name(&bus->dev); 887 888 err = device_register(&bus->dev); 889 if (err) 890 goto unregister; 891 892 pcibios_add_bus(bus); 893 894 /* Create legacy_io and legacy_mem files for this bus */ 895 pci_create_legacy_files(bus); 896 897 if (parent) 898 dev_info(parent, "PCI host bridge to bus %s\n", name); 899 else 900 pr_info("PCI host bridge to bus %s\n", name); 901 902 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 903 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 904 905 /* Add initial resources to the bus */ 906 resource_list_for_each_entry_safe(window, n, &resources) { 907 list_move_tail(&window->node, &bridge->windows); 908 offset = window->offset; 909 res = window->res; 910 911 if (res->flags & IORESOURCE_BUS) 912 pci_bus_insert_busn_res(bus, bus->number, res->end); 913 else 914 pci_bus_add_resource(bus, res, 0); 915 916 if (offset) { 917 if (resource_type(res) == IORESOURCE_IO) 918 fmt = " (bus address [%#06llx-%#06llx])"; 919 else 920 fmt = " (bus address [%#010llx-%#010llx])"; 921 922 snprintf(addr, sizeof(addr), fmt, 923 (unsigned long long)(res->start - offset), 924 (unsigned long long)(res->end - offset)); 925 } else 926 addr[0] = '\0'; 927 928 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 929 } 930 931 down_write(&pci_bus_sem); 932 list_add_tail(&bus->node, &pci_root_buses); 933 up_write(&pci_bus_sem); 934 935 return 0; 936 937 unregister: 938 put_device(&bridge->dev); 939 device_unregister(&bridge->dev); 940 941 free: 942 kfree(bus); 943 return err; 944 } 945 946 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 947 { 948 int pos; 949 u32 status; 950 951 /* 952 * If extended config space isn't accessible on a bridge's primary 953 * bus, we certainly can't access it on the secondary bus. 954 */ 955 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 956 return false; 957 958 /* 959 * PCIe Root Ports and switch ports are PCIe on both sides, so if 960 * extended config space is accessible on the primary, it's also 961 * accessible on the secondary. 962 */ 963 if (pci_is_pcie(bridge) && 964 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 965 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 966 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 967 return true; 968 969 /* 970 * For the other bridge types: 971 * - PCI-to-PCI bridges 972 * - PCIe-to-PCI/PCI-X forward bridges 973 * - PCI/PCI-X-to-PCIe reverse bridges 974 * extended config space on the secondary side is only accessible 975 * if the bridge supports PCI-X Mode 2. 976 */ 977 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 978 if (!pos) 979 return false; 980 981 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 982 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 983 } 984 985 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 986 struct pci_dev *bridge, int busnr) 987 { 988 struct pci_bus *child; 989 int i; 990 int ret; 991 992 /* Allocate a new bus and inherit stuff from the parent */ 993 child = pci_alloc_bus(parent); 994 if (!child) 995 return NULL; 996 997 child->parent = parent; 998 child->ops = parent->ops; 999 child->msi = parent->msi; 1000 child->sysdata = parent->sysdata; 1001 child->bus_flags = parent->bus_flags; 1002 1003 /* 1004 * Initialize some portions of the bus device, but don't register 1005 * it now as the parent is not properly set up yet. 1006 */ 1007 child->dev.class = &pcibus_class; 1008 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1009 1010 /* Set up the primary, secondary and subordinate bus numbers */ 1011 child->number = child->busn_res.start = busnr; 1012 child->primary = parent->busn_res.start; 1013 child->busn_res.end = 0xff; 1014 1015 if (!bridge) { 1016 child->dev.parent = parent->bridge; 1017 goto add_dev; 1018 } 1019 1020 child->self = bridge; 1021 child->bridge = get_device(&bridge->dev); 1022 child->dev.parent = child->bridge; 1023 pci_set_bus_of_node(child); 1024 pci_set_bus_speed(child); 1025 1026 /* 1027 * Check whether extended config space is accessible on the child 1028 * bus. Note that we currently assume it is always accessible on 1029 * the root bus. 1030 */ 1031 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1032 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1033 pci_info(child, "extended config space not accessible\n"); 1034 } 1035 1036 /* Set up default resource pointers and names */ 1037 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1038 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1039 child->resource[i]->name = child->name; 1040 } 1041 bridge->subordinate = child; 1042 1043 add_dev: 1044 pci_set_bus_msi_domain(child); 1045 ret = device_register(&child->dev); 1046 WARN_ON(ret < 0); 1047 1048 pcibios_add_bus(child); 1049 1050 if (child->ops->add_bus) { 1051 ret = child->ops->add_bus(child); 1052 if (WARN_ON(ret < 0)) 1053 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1054 } 1055 1056 /* Create legacy_io and legacy_mem files for this bus */ 1057 pci_create_legacy_files(child); 1058 1059 return child; 1060 } 1061 1062 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1063 int busnr) 1064 { 1065 struct pci_bus *child; 1066 1067 child = pci_alloc_child_bus(parent, dev, busnr); 1068 if (child) { 1069 down_write(&pci_bus_sem); 1070 list_add_tail(&child->node, &parent->children); 1071 up_write(&pci_bus_sem); 1072 } 1073 return child; 1074 } 1075 EXPORT_SYMBOL(pci_add_new_bus); 1076 1077 static void pci_enable_crs(struct pci_dev *pdev) 1078 { 1079 u16 root_cap = 0; 1080 1081 /* Enable CRS Software Visibility if supported */ 1082 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1083 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1084 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1085 PCI_EXP_RTCTL_CRSSVE); 1086 } 1087 1088 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1089 unsigned int available_buses); 1090 /** 1091 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1092 * numbers from EA capability. 1093 * @dev: Bridge 1094 * @sec: updated with secondary bus number from EA 1095 * @sub: updated with subordinate bus number from EA 1096 * 1097 * If @dev is a bridge with EA capability that specifies valid secondary 1098 * and subordinate bus numbers, return true with the bus numbers in @sec 1099 * and @sub. Otherwise return false. 1100 */ 1101 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1102 { 1103 int ea, offset; 1104 u32 dw; 1105 u8 ea_sec, ea_sub; 1106 1107 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1108 return false; 1109 1110 /* find PCI EA capability in list */ 1111 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1112 if (!ea) 1113 return false; 1114 1115 offset = ea + PCI_EA_FIRST_ENT; 1116 pci_read_config_dword(dev, offset, &dw); 1117 ea_sec = dw & PCI_EA_SEC_BUS_MASK; 1118 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; 1119 if (ea_sec == 0 || ea_sub < ea_sec) 1120 return false; 1121 1122 *sec = ea_sec; 1123 *sub = ea_sub; 1124 return true; 1125 } 1126 1127 /* 1128 * pci_scan_bridge_extend() - Scan buses behind a bridge 1129 * @bus: Parent bus the bridge is on 1130 * @dev: Bridge itself 1131 * @max: Starting subordinate number of buses behind this bridge 1132 * @available_buses: Total number of buses available for this bridge and 1133 * the devices below. After the minimal bus space has 1134 * been allocated the remaining buses will be 1135 * distributed equally between hotplug-capable bridges. 1136 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1137 * that need to be reconfigured. 1138 * 1139 * If it's a bridge, configure it and scan the bus behind it. 1140 * For CardBus bridges, we don't scan behind as the devices will 1141 * be handled by the bridge driver itself. 1142 * 1143 * We need to process bridges in two passes -- first we scan those 1144 * already configured by the BIOS and after we are done with all of 1145 * them, we proceed to assigning numbers to the remaining buses in 1146 * order to avoid overlaps between old and new bus numbers. 1147 * 1148 * Return: New subordinate number covering all buses behind this bridge. 1149 */ 1150 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1151 int max, unsigned int available_buses, 1152 int pass) 1153 { 1154 struct pci_bus *child; 1155 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1156 u32 buses, i, j = 0; 1157 u16 bctl; 1158 u8 primary, secondary, subordinate; 1159 int broken = 0; 1160 bool fixed_buses; 1161 u8 fixed_sec, fixed_sub; 1162 int next_busnr; 1163 1164 /* 1165 * Make sure the bridge is powered on to be able to access config 1166 * space of devices below it. 1167 */ 1168 pm_runtime_get_sync(&dev->dev); 1169 1170 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1171 primary = buses & 0xFF; 1172 secondary = (buses >> 8) & 0xFF; 1173 subordinate = (buses >> 16) & 0xFF; 1174 1175 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1176 secondary, subordinate, pass); 1177 1178 if (!primary && (primary != bus->number) && secondary && subordinate) { 1179 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1180 primary = bus->number; 1181 } 1182 1183 /* Check if setup is sensible at all */ 1184 if (!pass && 1185 (primary != bus->number || secondary <= bus->number || 1186 secondary > subordinate)) { 1187 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1188 secondary, subordinate); 1189 broken = 1; 1190 } 1191 1192 /* 1193 * Disable Master-Abort Mode during probing to avoid reporting of 1194 * bus errors in some architectures. 1195 */ 1196 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1197 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1198 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1199 1200 pci_enable_crs(dev); 1201 1202 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1203 !is_cardbus && !broken) { 1204 unsigned int cmax; 1205 1206 /* 1207 * Bus already configured by firmware, process it in the 1208 * first pass and just note the configuration. 1209 */ 1210 if (pass) 1211 goto out; 1212 1213 /* 1214 * The bus might already exist for two reasons: Either we 1215 * are rescanning the bus or the bus is reachable through 1216 * more than one bridge. The second case can happen with 1217 * the i450NX chipset. 1218 */ 1219 child = pci_find_bus(pci_domain_nr(bus), secondary); 1220 if (!child) { 1221 child = pci_add_new_bus(bus, dev, secondary); 1222 if (!child) 1223 goto out; 1224 child->primary = primary; 1225 pci_bus_insert_busn_res(child, secondary, subordinate); 1226 child->bridge_ctl = bctl; 1227 } 1228 1229 cmax = pci_scan_child_bus(child); 1230 if (cmax > subordinate) 1231 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1232 subordinate, cmax); 1233 1234 /* Subordinate should equal child->busn_res.end */ 1235 if (subordinate > max) 1236 max = subordinate; 1237 } else { 1238 1239 /* 1240 * We need to assign a number to this bus which we always 1241 * do in the second pass. 1242 */ 1243 if (!pass) { 1244 if (pcibios_assign_all_busses() || broken || is_cardbus) 1245 1246 /* 1247 * Temporarily disable forwarding of the 1248 * configuration cycles on all bridges in 1249 * this bus segment to avoid possible 1250 * conflicts in the second pass between two 1251 * bridges programmed with overlapping bus 1252 * ranges. 1253 */ 1254 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1255 buses & ~0xffffff); 1256 goto out; 1257 } 1258 1259 /* Clear errors */ 1260 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1261 1262 /* Read bus numbers from EA Capability (if present) */ 1263 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1264 if (fixed_buses) 1265 next_busnr = fixed_sec; 1266 else 1267 next_busnr = max + 1; 1268 1269 /* 1270 * Prevent assigning a bus number that already exists. 1271 * This can happen when a bridge is hot-plugged, so in this 1272 * case we only re-scan this bus. 1273 */ 1274 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1275 if (!child) { 1276 child = pci_add_new_bus(bus, dev, next_busnr); 1277 if (!child) 1278 goto out; 1279 pci_bus_insert_busn_res(child, next_busnr, 1280 bus->busn_res.end); 1281 } 1282 max++; 1283 if (available_buses) 1284 available_buses--; 1285 1286 buses = (buses & 0xff000000) 1287 | ((unsigned int)(child->primary) << 0) 1288 | ((unsigned int)(child->busn_res.start) << 8) 1289 | ((unsigned int)(child->busn_res.end) << 16); 1290 1291 /* 1292 * yenta.c forces a secondary latency timer of 176. 1293 * Copy that behaviour here. 1294 */ 1295 if (is_cardbus) { 1296 buses &= ~0xff000000; 1297 buses |= CARDBUS_LATENCY_TIMER << 24; 1298 } 1299 1300 /* We need to blast all three values with a single write */ 1301 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1302 1303 if (!is_cardbus) { 1304 child->bridge_ctl = bctl; 1305 max = pci_scan_child_bus_extend(child, available_buses); 1306 } else { 1307 1308 /* 1309 * For CardBus bridges, we leave 4 bus numbers as 1310 * cards with a PCI-to-PCI bridge can be inserted 1311 * later. 1312 */ 1313 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1314 struct pci_bus *parent = bus; 1315 if (pci_find_bus(pci_domain_nr(bus), 1316 max+i+1)) 1317 break; 1318 while (parent->parent) { 1319 if ((!pcibios_assign_all_busses()) && 1320 (parent->busn_res.end > max) && 1321 (parent->busn_res.end <= max+i)) { 1322 j = 1; 1323 } 1324 parent = parent->parent; 1325 } 1326 if (j) { 1327 1328 /* 1329 * Often, there are two CardBus 1330 * bridges -- try to leave one 1331 * valid bus number for each one. 1332 */ 1333 i /= 2; 1334 break; 1335 } 1336 } 1337 max += i; 1338 } 1339 1340 /* 1341 * Set subordinate bus number to its real value. 1342 * If fixed subordinate bus number exists from EA 1343 * capability then use it. 1344 */ 1345 if (fixed_buses) 1346 max = fixed_sub; 1347 pci_bus_update_busn_res_end(child, max); 1348 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1349 } 1350 1351 sprintf(child->name, 1352 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1353 pci_domain_nr(bus), child->number); 1354 1355 /* Check that all devices are accessible */ 1356 while (bus->parent) { 1357 if ((child->busn_res.end > bus->busn_res.end) || 1358 (child->number > bus->busn_res.end) || 1359 (child->number < bus->number) || 1360 (child->busn_res.end < bus->number)) { 1361 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1362 &child->busn_res); 1363 break; 1364 } 1365 bus = bus->parent; 1366 } 1367 1368 out: 1369 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1370 1371 pm_runtime_put(&dev->dev); 1372 1373 return max; 1374 } 1375 1376 /* 1377 * pci_scan_bridge() - Scan buses behind a bridge 1378 * @bus: Parent bus the bridge is on 1379 * @dev: Bridge itself 1380 * @max: Starting subordinate number of buses behind this bridge 1381 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1382 * that need to be reconfigured. 1383 * 1384 * If it's a bridge, configure it and scan the bus behind it. 1385 * For CardBus bridges, we don't scan behind as the devices will 1386 * be handled by the bridge driver itself. 1387 * 1388 * We need to process bridges in two passes -- first we scan those 1389 * already configured by the BIOS and after we are done with all of 1390 * them, we proceed to assigning numbers to the remaining buses in 1391 * order to avoid overlaps between old and new bus numbers. 1392 * 1393 * Return: New subordinate number covering all buses behind this bridge. 1394 */ 1395 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1396 { 1397 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1398 } 1399 EXPORT_SYMBOL(pci_scan_bridge); 1400 1401 /* 1402 * Read interrupt line and base address registers. 1403 * The architecture-dependent code can tweak these, of course. 1404 */ 1405 static void pci_read_irq(struct pci_dev *dev) 1406 { 1407 unsigned char irq; 1408 1409 /* VFs are not allowed to use INTx, so skip the config reads */ 1410 if (dev->is_virtfn) { 1411 dev->pin = 0; 1412 dev->irq = 0; 1413 return; 1414 } 1415 1416 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1417 dev->pin = irq; 1418 if (irq) 1419 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1420 dev->irq = irq; 1421 } 1422 1423 void set_pcie_port_type(struct pci_dev *pdev) 1424 { 1425 int pos; 1426 u16 reg16; 1427 int type; 1428 struct pci_dev *parent; 1429 1430 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1431 if (!pos) 1432 return; 1433 1434 pdev->pcie_cap = pos; 1435 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1436 pdev->pcie_flags_reg = reg16; 1437 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 1438 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 1439 1440 parent = pci_upstream_bridge(pdev); 1441 if (!parent) 1442 return; 1443 1444 /* 1445 * Some systems do not identify their upstream/downstream ports 1446 * correctly so detect impossible configurations here and correct 1447 * the port type accordingly. 1448 */ 1449 type = pci_pcie_type(pdev); 1450 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1451 /* 1452 * If pdev claims to be downstream port but the parent 1453 * device is also downstream port assume pdev is actually 1454 * upstream port. 1455 */ 1456 if (pcie_downstream_port(parent)) { 1457 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1458 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1459 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1460 } 1461 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1462 /* 1463 * If pdev claims to be upstream port but the parent 1464 * device is also upstream port assume pdev is actually 1465 * downstream port. 1466 */ 1467 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1468 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1469 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1470 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1471 } 1472 } 1473 } 1474 1475 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1476 { 1477 u32 reg32; 1478 1479 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1480 if (reg32 & PCI_EXP_SLTCAP_HPC) 1481 pdev->is_hotplug_bridge = 1; 1482 } 1483 1484 static void set_pcie_thunderbolt(struct pci_dev *dev) 1485 { 1486 int vsec = 0; 1487 u32 header; 1488 1489 while ((vsec = pci_find_next_ext_capability(dev, vsec, 1490 PCI_EXT_CAP_ID_VNDR))) { 1491 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header); 1492 1493 /* Is the device part of a Thunderbolt controller? */ 1494 if (dev->vendor == PCI_VENDOR_ID_INTEL && 1495 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) { 1496 dev->is_thunderbolt = 1; 1497 return; 1498 } 1499 } 1500 } 1501 1502 static void set_pcie_untrusted(struct pci_dev *dev) 1503 { 1504 struct pci_dev *parent; 1505 1506 /* 1507 * If the upstream bridge is untrusted we treat this device 1508 * untrusted as well. 1509 */ 1510 parent = pci_upstream_bridge(dev); 1511 if (parent && parent->untrusted) 1512 dev->untrusted = true; 1513 } 1514 1515 /** 1516 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1517 * @dev: PCI device 1518 * 1519 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1520 * when forwarding a type1 configuration request the bridge must check that 1521 * the extended register address field is zero. The bridge is not permitted 1522 * to forward the transactions and must handle it as an Unsupported Request. 1523 * Some bridges do not follow this rule and simply drop the extended register 1524 * bits, resulting in the standard config space being aliased, every 256 1525 * bytes across the entire configuration space. Test for this condition by 1526 * comparing the first dword of each potential alias to the vendor/device ID. 1527 * Known offenders: 1528 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1529 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1530 */ 1531 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1532 { 1533 #ifdef CONFIG_PCI_QUIRKS 1534 int pos; 1535 u32 header, tmp; 1536 1537 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1538 1539 for (pos = PCI_CFG_SPACE_SIZE; 1540 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1541 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL 1542 || header != tmp) 1543 return false; 1544 } 1545 1546 return true; 1547 #else 1548 return false; 1549 #endif 1550 } 1551 1552 /** 1553 * pci_cfg_space_size - Get the configuration space size of the PCI device 1554 * @dev: PCI device 1555 * 1556 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1557 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1558 * access it. Maybe we don't have a way to generate extended config space 1559 * accesses, or the device is behind a reverse Express bridge. So we try 1560 * reading the dword at 0x100 which must either be 0 or a valid extended 1561 * capability header. 1562 */ 1563 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1564 { 1565 u32 status; 1566 int pos = PCI_CFG_SPACE_SIZE; 1567 1568 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1569 return PCI_CFG_SPACE_SIZE; 1570 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) 1571 return PCI_CFG_SPACE_SIZE; 1572 1573 return PCI_CFG_SPACE_EXP_SIZE; 1574 } 1575 1576 int pci_cfg_space_size(struct pci_dev *dev) 1577 { 1578 int pos; 1579 u32 status; 1580 u16 class; 1581 1582 #ifdef CONFIG_PCI_IOV 1583 /* 1584 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1585 * implement a PCIe capability and therefore must implement extended 1586 * config space. We can skip the NO_EXTCFG test below and the 1587 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1588 * the fact that the SR-IOV capability on the PF resides in extended 1589 * config space and must be accessible and non-aliased to have enabled 1590 * support for this VF. This is a micro performance optimization for 1591 * systems supporting many VFs. 1592 */ 1593 if (dev->is_virtfn) 1594 return PCI_CFG_SPACE_EXP_SIZE; 1595 #endif 1596 1597 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1598 return PCI_CFG_SPACE_SIZE; 1599 1600 class = dev->class >> 8; 1601 if (class == PCI_CLASS_BRIDGE_HOST) 1602 return pci_cfg_space_size_ext(dev); 1603 1604 if (pci_is_pcie(dev)) 1605 return pci_cfg_space_size_ext(dev); 1606 1607 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1608 if (!pos) 1609 return PCI_CFG_SPACE_SIZE; 1610 1611 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1612 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1613 return pci_cfg_space_size_ext(dev); 1614 1615 return PCI_CFG_SPACE_SIZE; 1616 } 1617 1618 static u32 pci_class(struct pci_dev *dev) 1619 { 1620 u32 class; 1621 1622 #ifdef CONFIG_PCI_IOV 1623 if (dev->is_virtfn) 1624 return dev->physfn->sriov->class; 1625 #endif 1626 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1627 return class; 1628 } 1629 1630 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1631 { 1632 #ifdef CONFIG_PCI_IOV 1633 if (dev->is_virtfn) { 1634 *vendor = dev->physfn->sriov->subsystem_vendor; 1635 *device = dev->physfn->sriov->subsystem_device; 1636 return; 1637 } 1638 #endif 1639 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1640 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1641 } 1642 1643 static u8 pci_hdr_type(struct pci_dev *dev) 1644 { 1645 u8 hdr_type; 1646 1647 #ifdef CONFIG_PCI_IOV 1648 if (dev->is_virtfn) 1649 return dev->physfn->sriov->hdr_type; 1650 #endif 1651 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1652 return hdr_type; 1653 } 1654 1655 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1656 1657 static void pci_msi_setup_pci_dev(struct pci_dev *dev) 1658 { 1659 /* 1660 * Disable the MSI hardware to avoid screaming interrupts 1661 * during boot. This is the power on reset default so 1662 * usually this should be a noop. 1663 */ 1664 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); 1665 if (dev->msi_cap) 1666 pci_msi_set_enable(dev, 0); 1667 1668 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1669 if (dev->msix_cap) 1670 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); 1671 } 1672 1673 /** 1674 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1675 * @dev: PCI device 1676 * 1677 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1678 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1679 */ 1680 static int pci_intx_mask_broken(struct pci_dev *dev) 1681 { 1682 u16 orig, toggle, new; 1683 1684 pci_read_config_word(dev, PCI_COMMAND, &orig); 1685 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1686 pci_write_config_word(dev, PCI_COMMAND, toggle); 1687 pci_read_config_word(dev, PCI_COMMAND, &new); 1688 1689 pci_write_config_word(dev, PCI_COMMAND, orig); 1690 1691 /* 1692 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1693 * r2.3, so strictly speaking, a device is not *broken* if it's not 1694 * writable. But we'll live with the misnomer for now. 1695 */ 1696 if (new != toggle) 1697 return 1; 1698 return 0; 1699 } 1700 1701 static void early_dump_pci_device(struct pci_dev *pdev) 1702 { 1703 u32 value[256 / 4]; 1704 int i; 1705 1706 pci_info(pdev, "config space:\n"); 1707 1708 for (i = 0; i < 256; i += 4) 1709 pci_read_config_dword(pdev, i, &value[i / 4]); 1710 1711 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1712 value, 256, false); 1713 } 1714 1715 /** 1716 * pci_setup_device - Fill in class and map information of a device 1717 * @dev: the device structure to fill 1718 * 1719 * Initialize the device structure with information about the device's 1720 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1721 * Called at initialisation of the PCI subsystem and by CardBus services. 1722 * Returns 0 on success and negative if unknown type of device (not normal, 1723 * bridge or CardBus). 1724 */ 1725 int pci_setup_device(struct pci_dev *dev) 1726 { 1727 u32 class; 1728 u16 cmd; 1729 u8 hdr_type; 1730 int pos = 0; 1731 struct pci_bus_region region; 1732 struct resource *res; 1733 1734 hdr_type = pci_hdr_type(dev); 1735 1736 dev->sysdata = dev->bus->sysdata; 1737 dev->dev.parent = dev->bus->bridge; 1738 dev->dev.bus = &pci_bus_type; 1739 dev->hdr_type = hdr_type & 0x7f; 1740 dev->multifunction = !!(hdr_type & 0x80); 1741 dev->error_state = pci_channel_io_normal; 1742 set_pcie_port_type(dev); 1743 1744 pci_dev_assign_slot(dev); 1745 1746 /* 1747 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1748 * set this higher, assuming the system even supports it. 1749 */ 1750 dev->dma_mask = 0xffffffff; 1751 1752 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1753 dev->bus->number, PCI_SLOT(dev->devfn), 1754 PCI_FUNC(dev->devfn)); 1755 1756 class = pci_class(dev); 1757 1758 dev->revision = class & 0xff; 1759 dev->class = class >> 8; /* upper 3 bytes */ 1760 1761 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 1762 dev->vendor, dev->device, dev->hdr_type, dev->class); 1763 1764 if (pci_early_dump) 1765 early_dump_pci_device(dev); 1766 1767 /* Need to have dev->class ready */ 1768 dev->cfg_size = pci_cfg_space_size(dev); 1769 1770 /* Need to have dev->cfg_size ready */ 1771 set_pcie_thunderbolt(dev); 1772 1773 set_pcie_untrusted(dev); 1774 1775 /* "Unknown power state" */ 1776 dev->current_state = PCI_UNKNOWN; 1777 1778 /* Early fixups, before probing the BARs */ 1779 pci_fixup_device(pci_fixup_early, dev); 1780 1781 /* Device class may be changed after fixup */ 1782 class = dev->class >> 8; 1783 1784 if (dev->non_compliant_bars) { 1785 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1786 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1787 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1788 cmd &= ~PCI_COMMAND_IO; 1789 cmd &= ~PCI_COMMAND_MEMORY; 1790 pci_write_config_word(dev, PCI_COMMAND, cmd); 1791 } 1792 } 1793 1794 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1795 1796 switch (dev->hdr_type) { /* header type */ 1797 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1798 if (class == PCI_CLASS_BRIDGE_PCI) 1799 goto bad; 1800 pci_read_irq(dev); 1801 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1802 1803 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1804 1805 /* 1806 * Do the ugly legacy mode stuff here rather than broken chip 1807 * quirk code. Legacy mode ATA controllers have fixed 1808 * addresses. These are not always echoed in BAR0-3, and 1809 * BAR0-3 in a few cases contain junk! 1810 */ 1811 if (class == PCI_CLASS_STORAGE_IDE) { 1812 u8 progif; 1813 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1814 if ((progif & 1) == 0) { 1815 region.start = 0x1F0; 1816 region.end = 0x1F7; 1817 res = &dev->resource[0]; 1818 res->flags = LEGACY_IO_RESOURCE; 1819 pcibios_bus_to_resource(dev->bus, res, ®ion); 1820 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1821 res); 1822 region.start = 0x3F6; 1823 region.end = 0x3F6; 1824 res = &dev->resource[1]; 1825 res->flags = LEGACY_IO_RESOURCE; 1826 pcibios_bus_to_resource(dev->bus, res, ®ion); 1827 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1828 res); 1829 } 1830 if ((progif & 4) == 0) { 1831 region.start = 0x170; 1832 region.end = 0x177; 1833 res = &dev->resource[2]; 1834 res->flags = LEGACY_IO_RESOURCE; 1835 pcibios_bus_to_resource(dev->bus, res, ®ion); 1836 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1837 res); 1838 region.start = 0x376; 1839 region.end = 0x376; 1840 res = &dev->resource[3]; 1841 res->flags = LEGACY_IO_RESOURCE; 1842 pcibios_bus_to_resource(dev->bus, res, ®ion); 1843 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1844 res); 1845 } 1846 } 1847 break; 1848 1849 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1850 /* 1851 * The PCI-to-PCI bridge spec requires that subtractive 1852 * decoding (i.e. transparent) bridge must have programming 1853 * interface code of 0x01. 1854 */ 1855 pci_read_irq(dev); 1856 dev->transparent = ((dev->class & 0xff) == 1); 1857 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1858 pci_read_bridge_windows(dev); 1859 set_pcie_hotplug_bridge(dev); 1860 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1861 if (pos) { 1862 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1863 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1864 } 1865 break; 1866 1867 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1868 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1869 goto bad; 1870 pci_read_irq(dev); 1871 pci_read_bases(dev, 1, 0); 1872 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1873 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1874 break; 1875 1876 default: /* unknown header */ 1877 pci_err(dev, "unknown header type %02x, ignoring device\n", 1878 dev->hdr_type); 1879 return -EIO; 1880 1881 bad: 1882 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1883 dev->class, dev->hdr_type); 1884 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1885 } 1886 1887 /* We found a fine healthy device, go go go... */ 1888 return 0; 1889 } 1890 1891 static void pci_configure_mps(struct pci_dev *dev) 1892 { 1893 struct pci_dev *bridge = pci_upstream_bridge(dev); 1894 int mps, mpss, p_mps, rc; 1895 1896 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge)) 1897 return; 1898 1899 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 1900 if (dev->is_virtfn) 1901 return; 1902 1903 mps = pcie_get_mps(dev); 1904 p_mps = pcie_get_mps(bridge); 1905 1906 if (mps == p_mps) 1907 return; 1908 1909 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 1910 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1911 mps, pci_name(bridge), p_mps); 1912 return; 1913 } 1914 1915 /* 1916 * Fancier MPS configuration is done later by 1917 * pcie_bus_configure_settings() 1918 */ 1919 if (pcie_bus_config != PCIE_BUS_DEFAULT) 1920 return; 1921 1922 mpss = 128 << dev->pcie_mpss; 1923 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 1924 pcie_set_mps(bridge, mpss); 1925 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 1926 mpss, p_mps, 128 << bridge->pcie_mpss); 1927 p_mps = pcie_get_mps(bridge); 1928 } 1929 1930 rc = pcie_set_mps(dev, p_mps); 1931 if (rc) { 1932 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1933 p_mps); 1934 return; 1935 } 1936 1937 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 1938 p_mps, mps, mpss); 1939 } 1940 1941 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 1942 { 1943 struct pci_host_bridge *host; 1944 u32 cap; 1945 u16 ctl; 1946 int ret; 1947 1948 if (!pci_is_pcie(dev)) 1949 return 0; 1950 1951 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 1952 if (ret) 1953 return 0; 1954 1955 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 1956 return 0; 1957 1958 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 1959 if (ret) 1960 return 0; 1961 1962 host = pci_find_host_bridge(dev->bus); 1963 if (!host) 1964 return 0; 1965 1966 /* 1967 * If some device in the hierarchy doesn't handle Extended Tags 1968 * correctly, make sure they're disabled. 1969 */ 1970 if (host->no_ext_tags) { 1971 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 1972 pci_info(dev, "disabling Extended Tags\n"); 1973 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 1974 PCI_EXP_DEVCTL_EXT_TAG); 1975 } 1976 return 0; 1977 } 1978 1979 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 1980 pci_info(dev, "enabling Extended Tags\n"); 1981 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 1982 PCI_EXP_DEVCTL_EXT_TAG); 1983 } 1984 return 0; 1985 } 1986 1987 /** 1988 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 1989 * @dev: PCI device to query 1990 * 1991 * Returns true if the device has enabled relaxed ordering attribute. 1992 */ 1993 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 1994 { 1995 u16 v; 1996 1997 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 1998 1999 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2000 } 2001 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2002 2003 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2004 { 2005 struct pci_dev *root; 2006 2007 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ 2008 if (dev->is_virtfn) 2009 return; 2010 2011 if (!pcie_relaxed_ordering_enabled(dev)) 2012 return; 2013 2014 /* 2015 * For now, we only deal with Relaxed Ordering issues with Root 2016 * Ports. Peer-to-Peer DMA is another can of worms. 2017 */ 2018 root = pci_find_pcie_root_port(dev); 2019 if (!root) 2020 return; 2021 2022 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2023 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2024 PCI_EXP_DEVCTL_RELAX_EN); 2025 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2026 } 2027 } 2028 2029 static void pci_configure_ltr(struct pci_dev *dev) 2030 { 2031 #ifdef CONFIG_PCIEASPM 2032 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 2033 struct pci_dev *bridge; 2034 u32 cap, ctl; 2035 2036 if (!pci_is_pcie(dev)) 2037 return; 2038 2039 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2040 if (!(cap & PCI_EXP_DEVCAP2_LTR)) 2041 return; 2042 2043 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); 2044 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { 2045 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2046 dev->ltr_path = 1; 2047 return; 2048 } 2049 2050 bridge = pci_upstream_bridge(dev); 2051 if (bridge && bridge->ltr_path) 2052 dev->ltr_path = 1; 2053 2054 return; 2055 } 2056 2057 if (!host->native_ltr) 2058 return; 2059 2060 /* 2061 * Software must not enable LTR in an Endpoint unless the Root 2062 * Complex and all intermediate Switches indicate support for LTR. 2063 * PCIe r4.0, sec 6.18. 2064 */ 2065 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 2066 ((bridge = pci_upstream_bridge(dev)) && 2067 bridge->ltr_path)) { 2068 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2069 PCI_EXP_DEVCTL2_LTR_EN); 2070 dev->ltr_path = 1; 2071 } 2072 #endif 2073 } 2074 2075 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2076 { 2077 #ifdef CONFIG_PCI_PASID 2078 struct pci_dev *bridge; 2079 int pcie_type; 2080 u32 cap; 2081 2082 if (!pci_is_pcie(dev)) 2083 return; 2084 2085 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2086 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2087 return; 2088 2089 pcie_type = pci_pcie_type(dev); 2090 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2091 pcie_type == PCI_EXP_TYPE_RC_END) 2092 dev->eetlp_prefix_path = 1; 2093 else { 2094 bridge = pci_upstream_bridge(dev); 2095 if (bridge && bridge->eetlp_prefix_path) 2096 dev->eetlp_prefix_path = 1; 2097 } 2098 #endif 2099 } 2100 2101 static void pci_configure_serr(struct pci_dev *dev) 2102 { 2103 u16 control; 2104 2105 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2106 2107 /* 2108 * A bridge will not forward ERR_ messages coming from an 2109 * endpoint unless SERR# forwarding is enabled. 2110 */ 2111 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2112 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2113 control |= PCI_BRIDGE_CTL_SERR; 2114 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2115 } 2116 } 2117 } 2118 2119 static void pci_configure_device(struct pci_dev *dev) 2120 { 2121 pci_configure_mps(dev); 2122 pci_configure_extended_tags(dev, NULL); 2123 pci_configure_relaxed_ordering(dev); 2124 pci_configure_ltr(dev); 2125 pci_configure_eetlp_prefix(dev); 2126 pci_configure_serr(dev); 2127 2128 pci_acpi_program_hp_params(dev); 2129 } 2130 2131 static void pci_release_capabilities(struct pci_dev *dev) 2132 { 2133 pci_aer_exit(dev); 2134 pci_vpd_release(dev); 2135 pci_iov_release(dev); 2136 pci_free_cap_save_buffers(dev); 2137 } 2138 2139 /** 2140 * pci_release_dev - Free a PCI device structure when all users of it are 2141 * finished 2142 * @dev: device that's been disconnected 2143 * 2144 * Will be called only by the device core when all users of this PCI device are 2145 * done. 2146 */ 2147 static void pci_release_dev(struct device *dev) 2148 { 2149 struct pci_dev *pci_dev; 2150 2151 pci_dev = to_pci_dev(dev); 2152 pci_release_capabilities(pci_dev); 2153 pci_release_of_node(pci_dev); 2154 pcibios_release_device(pci_dev); 2155 pci_bus_put(pci_dev->bus); 2156 kfree(pci_dev->driver_override); 2157 bitmap_free(pci_dev->dma_alias_mask); 2158 kfree(pci_dev); 2159 } 2160 2161 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2162 { 2163 struct pci_dev *dev; 2164 2165 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2166 if (!dev) 2167 return NULL; 2168 2169 INIT_LIST_HEAD(&dev->bus_list); 2170 dev->dev.type = &pci_dev_type; 2171 dev->bus = pci_bus_get(bus); 2172 2173 return dev; 2174 } 2175 EXPORT_SYMBOL(pci_alloc_dev); 2176 2177 static bool pci_bus_crs_vendor_id(u32 l) 2178 { 2179 return (l & 0xffff) == 0x0001; 2180 } 2181 2182 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2183 int timeout) 2184 { 2185 int delay = 1; 2186 2187 if (!pci_bus_crs_vendor_id(*l)) 2188 return true; /* not a CRS completion */ 2189 2190 if (!timeout) 2191 return false; /* CRS, but caller doesn't want to wait */ 2192 2193 /* 2194 * We got the reserved Vendor ID that indicates a completion with 2195 * Configuration Request Retry Status (CRS). Retry until we get a 2196 * valid Vendor ID or we time out. 2197 */ 2198 while (pci_bus_crs_vendor_id(*l)) { 2199 if (delay > timeout) { 2200 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2201 pci_domain_nr(bus), bus->number, 2202 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2203 2204 return false; 2205 } 2206 if (delay >= 1000) 2207 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2208 pci_domain_nr(bus), bus->number, 2209 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2210 2211 msleep(delay); 2212 delay *= 2; 2213 2214 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2215 return false; 2216 } 2217 2218 if (delay >= 1000) 2219 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2220 pci_domain_nr(bus), bus->number, 2221 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2222 2223 return true; 2224 } 2225 2226 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2227 int timeout) 2228 { 2229 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2230 return false; 2231 2232 /* Some broken boards return 0 or ~0 if a slot is empty: */ 2233 if (*l == 0xffffffff || *l == 0x00000000 || 2234 *l == 0x0000ffff || *l == 0xffff0000) 2235 return false; 2236 2237 if (pci_bus_crs_vendor_id(*l)) 2238 return pci_bus_wait_crs(bus, devfn, l, timeout); 2239 2240 return true; 2241 } 2242 2243 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2244 int timeout) 2245 { 2246 #ifdef CONFIG_PCI_QUIRKS 2247 struct pci_dev *bridge = bus->self; 2248 2249 /* 2250 * Certain IDT switches have an issue where they improperly trigger 2251 * ACS Source Validation errors on completions for config reads. 2252 */ 2253 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2254 bridge->device == 0x80b5) 2255 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2256 #endif 2257 2258 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2259 } 2260 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2261 2262 /* 2263 * Read the config data for a PCI device, sanity-check it, 2264 * and fill in the dev structure. 2265 */ 2266 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2267 { 2268 struct pci_dev *dev; 2269 u32 l; 2270 2271 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2272 return NULL; 2273 2274 dev = pci_alloc_dev(bus); 2275 if (!dev) 2276 return NULL; 2277 2278 dev->devfn = devfn; 2279 dev->vendor = l & 0xffff; 2280 dev->device = (l >> 16) & 0xffff; 2281 2282 pci_set_of_node(dev); 2283 2284 if (pci_setup_device(dev)) { 2285 pci_bus_put(dev->bus); 2286 kfree(dev); 2287 return NULL; 2288 } 2289 2290 return dev; 2291 } 2292 2293 void pcie_report_downtraining(struct pci_dev *dev) 2294 { 2295 if (!pci_is_pcie(dev)) 2296 return; 2297 2298 /* Look from the device up to avoid downstream ports with no devices */ 2299 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2300 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2301 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2302 return; 2303 2304 /* Multi-function PCIe devices share the same link/status */ 2305 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2306 return; 2307 2308 /* Print link status only if the device is constrained by the fabric */ 2309 __pcie_print_link_status(dev, false); 2310 } 2311 2312 static void pci_init_capabilities(struct pci_dev *dev) 2313 { 2314 pci_ea_init(dev); /* Enhanced Allocation */ 2315 2316 /* Setup MSI caps & disable MSI/MSI-X interrupts */ 2317 pci_msi_setup_pci_dev(dev); 2318 2319 /* Buffers for saving PCIe and PCI-X capabilities */ 2320 pci_allocate_cap_save_buffers(dev); 2321 2322 pci_pm_init(dev); /* Power Management */ 2323 pci_vpd_init(dev); /* Vital Product Data */ 2324 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2325 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2326 pci_ats_init(dev); /* Address Translation Services */ 2327 pci_pri_init(dev); /* Page Request Interface */ 2328 pci_pasid_init(dev); /* Process Address Space ID */ 2329 pci_enable_acs(dev); /* Enable ACS P2P upstream forwarding */ 2330 pci_ptm_init(dev); /* Precision Time Measurement */ 2331 pci_aer_init(dev); /* Advanced Error Reporting */ 2332 2333 pcie_report_downtraining(dev); 2334 2335 if (pci_probe_reset_function(dev) == 0) 2336 dev->reset_fn = 1; 2337 } 2338 2339 /* 2340 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2341 * devices. Firmware interfaces that can select the MSI domain on a 2342 * per-device basis should be called from here. 2343 */ 2344 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2345 { 2346 struct irq_domain *d; 2347 2348 /* 2349 * If a domain has been set through the pcibios_add_device() 2350 * callback, then this is the one (platform code knows best). 2351 */ 2352 d = dev_get_msi_domain(&dev->dev); 2353 if (d) 2354 return d; 2355 2356 /* 2357 * Let's see if we have a firmware interface able to provide 2358 * the domain. 2359 */ 2360 d = pci_msi_get_device_domain(dev); 2361 if (d) 2362 return d; 2363 2364 return NULL; 2365 } 2366 2367 static void pci_set_msi_domain(struct pci_dev *dev) 2368 { 2369 struct irq_domain *d; 2370 2371 /* 2372 * If the platform or firmware interfaces cannot supply a 2373 * device-specific MSI domain, then inherit the default domain 2374 * from the host bridge itself. 2375 */ 2376 d = pci_dev_msi_domain(dev); 2377 if (!d) 2378 d = dev_get_msi_domain(&dev->bus->dev); 2379 2380 dev_set_msi_domain(&dev->dev, d); 2381 } 2382 2383 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2384 { 2385 int ret; 2386 2387 pci_configure_device(dev); 2388 2389 device_initialize(&dev->dev); 2390 dev->dev.release = pci_release_dev; 2391 2392 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2393 dev->dev.dma_mask = &dev->dma_mask; 2394 dev->dev.dma_parms = &dev->dma_parms; 2395 dev->dev.coherent_dma_mask = 0xffffffffull; 2396 2397 dma_set_max_seg_size(&dev->dev, 65536); 2398 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2399 2400 /* Fix up broken headers */ 2401 pci_fixup_device(pci_fixup_header, dev); 2402 2403 pci_reassigndev_resource_alignment(dev); 2404 2405 dev->state_saved = false; 2406 2407 pci_init_capabilities(dev); 2408 2409 /* 2410 * Add the device to our list of discovered devices 2411 * and the bus list for fixup functions, etc. 2412 */ 2413 down_write(&pci_bus_sem); 2414 list_add_tail(&dev->bus_list, &bus->devices); 2415 up_write(&pci_bus_sem); 2416 2417 ret = pcibios_add_device(dev); 2418 WARN_ON(ret < 0); 2419 2420 /* Set up MSI IRQ domain */ 2421 pci_set_msi_domain(dev); 2422 2423 /* Notifier could use PCI capabilities */ 2424 dev->match_driver = false; 2425 ret = device_add(&dev->dev); 2426 WARN_ON(ret < 0); 2427 } 2428 2429 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2430 { 2431 struct pci_dev *dev; 2432 2433 dev = pci_get_slot(bus, devfn); 2434 if (dev) { 2435 pci_dev_put(dev); 2436 return dev; 2437 } 2438 2439 dev = pci_scan_device(bus, devfn); 2440 if (!dev) 2441 return NULL; 2442 2443 pci_device_add(dev, bus); 2444 2445 return dev; 2446 } 2447 EXPORT_SYMBOL(pci_scan_single_device); 2448 2449 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) 2450 { 2451 int pos; 2452 u16 cap = 0; 2453 unsigned next_fn; 2454 2455 if (pci_ari_enabled(bus)) { 2456 if (!dev) 2457 return 0; 2458 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2459 if (!pos) 2460 return 0; 2461 2462 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2463 next_fn = PCI_ARI_CAP_NFN(cap); 2464 if (next_fn <= fn) 2465 return 0; /* protect against malformed list */ 2466 2467 return next_fn; 2468 } 2469 2470 /* dev may be NULL for non-contiguous multifunction devices */ 2471 if (!dev || dev->multifunction) 2472 return (fn + 1) % 8; 2473 2474 return 0; 2475 } 2476 2477 static int only_one_child(struct pci_bus *bus) 2478 { 2479 struct pci_dev *bridge = bus->self; 2480 2481 /* 2482 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2483 * we scan for all possible devices, not just Device 0. 2484 */ 2485 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2486 return 0; 2487 2488 /* 2489 * A PCIe Downstream Port normally leads to a Link with only Device 2490 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2491 * only for Device 0 in that situation. 2492 */ 2493 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2494 return 1; 2495 2496 return 0; 2497 } 2498 2499 /** 2500 * pci_scan_slot - Scan a PCI slot on a bus for devices 2501 * @bus: PCI bus to scan 2502 * @devfn: slot number to scan (must have zero function) 2503 * 2504 * Scan a PCI slot on the specified PCI bus for devices, adding 2505 * discovered devices to the @bus->devices list. New devices 2506 * will not have is_added set. 2507 * 2508 * Returns the number of new devices found. 2509 */ 2510 int pci_scan_slot(struct pci_bus *bus, int devfn) 2511 { 2512 unsigned fn, nr = 0; 2513 struct pci_dev *dev; 2514 2515 if (only_one_child(bus) && (devfn > 0)) 2516 return 0; /* Already scanned the entire slot */ 2517 2518 dev = pci_scan_single_device(bus, devfn); 2519 if (!dev) 2520 return 0; 2521 if (!pci_dev_is_added(dev)) 2522 nr++; 2523 2524 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { 2525 dev = pci_scan_single_device(bus, devfn + fn); 2526 if (dev) { 2527 if (!pci_dev_is_added(dev)) 2528 nr++; 2529 dev->multifunction = 1; 2530 } 2531 } 2532 2533 /* Only one slot has PCIe device */ 2534 if (bus->self && nr) 2535 pcie_aspm_init_link_state(bus->self); 2536 2537 return nr; 2538 } 2539 EXPORT_SYMBOL(pci_scan_slot); 2540 2541 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2542 { 2543 u8 *smpss = data; 2544 2545 if (!pci_is_pcie(dev)) 2546 return 0; 2547 2548 /* 2549 * We don't have a way to change MPS settings on devices that have 2550 * drivers attached. A hot-added device might support only the minimum 2551 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2552 * where devices may be hot-added, we limit the fabric MPS to 128 so 2553 * hot-added devices will work correctly. 2554 * 2555 * However, if we hot-add a device to a slot directly below a Root 2556 * Port, it's impossible for there to be other existing devices below 2557 * the port. We don't limit the MPS in this case because we can 2558 * reconfigure MPS on both the Root Port and the hot-added device, 2559 * and there are no other devices involved. 2560 * 2561 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2562 */ 2563 if (dev->is_hotplug_bridge && 2564 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2565 *smpss = 0; 2566 2567 if (*smpss > dev->pcie_mpss) 2568 *smpss = dev->pcie_mpss; 2569 2570 return 0; 2571 } 2572 2573 static void pcie_write_mps(struct pci_dev *dev, int mps) 2574 { 2575 int rc; 2576 2577 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2578 mps = 128 << dev->pcie_mpss; 2579 2580 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2581 dev->bus->self) 2582 2583 /* 2584 * For "Performance", the assumption is made that 2585 * downstream communication will never be larger than 2586 * the MRRS. So, the MPS only needs to be configured 2587 * for the upstream communication. This being the case, 2588 * walk from the top down and set the MPS of the child 2589 * to that of the parent bus. 2590 * 2591 * Configure the device MPS with the smaller of the 2592 * device MPSS or the bridge MPS (which is assumed to be 2593 * properly configured at this point to the largest 2594 * allowable MPS based on its parent bus). 2595 */ 2596 mps = min(mps, pcie_get_mps(dev->bus->self)); 2597 } 2598 2599 rc = pcie_set_mps(dev, mps); 2600 if (rc) 2601 pci_err(dev, "Failed attempting to set the MPS\n"); 2602 } 2603 2604 static void pcie_write_mrrs(struct pci_dev *dev) 2605 { 2606 int rc, mrrs; 2607 2608 /* 2609 * In the "safe" case, do not configure the MRRS. There appear to be 2610 * issues with setting MRRS to 0 on a number of devices. 2611 */ 2612 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2613 return; 2614 2615 /* 2616 * For max performance, the MRRS must be set to the largest supported 2617 * value. However, it cannot be configured larger than the MPS the 2618 * device or the bus can support. This should already be properly 2619 * configured by a prior call to pcie_write_mps(). 2620 */ 2621 mrrs = pcie_get_mps(dev); 2622 2623 /* 2624 * MRRS is a R/W register. Invalid values can be written, but a 2625 * subsequent read will verify if the value is acceptable or not. 2626 * If the MRRS value provided is not acceptable (e.g., too large), 2627 * shrink the value until it is acceptable to the HW. 2628 */ 2629 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2630 rc = pcie_set_readrq(dev, mrrs); 2631 if (!rc) 2632 break; 2633 2634 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2635 mrrs /= 2; 2636 } 2637 2638 if (mrrs < 128) 2639 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2640 } 2641 2642 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2643 { 2644 int mps, orig_mps; 2645 2646 if (!pci_is_pcie(dev)) 2647 return 0; 2648 2649 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2650 pcie_bus_config == PCIE_BUS_DEFAULT) 2651 return 0; 2652 2653 mps = 128 << *(u8 *)data; 2654 orig_mps = pcie_get_mps(dev); 2655 2656 pcie_write_mps(dev, mps); 2657 pcie_write_mrrs(dev); 2658 2659 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2660 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2661 orig_mps, pcie_get_readrq(dev)); 2662 2663 return 0; 2664 } 2665 2666 /* 2667 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2668 * parents then children fashion. If this changes, then this code will not 2669 * work as designed. 2670 */ 2671 void pcie_bus_configure_settings(struct pci_bus *bus) 2672 { 2673 u8 smpss = 0; 2674 2675 if (!bus->self) 2676 return; 2677 2678 if (!pci_is_pcie(bus->self)) 2679 return; 2680 2681 /* 2682 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2683 * to be aware of the MPS of the destination. To work around this, 2684 * simply force the MPS of the entire system to the smallest possible. 2685 */ 2686 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2687 smpss = 0; 2688 2689 if (pcie_bus_config == PCIE_BUS_SAFE) { 2690 smpss = bus->self->pcie_mpss; 2691 2692 pcie_find_smpss(bus->self, &smpss); 2693 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2694 } 2695 2696 pcie_bus_configure_set(bus->self, &smpss); 2697 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2698 } 2699 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2700 2701 /* 2702 * Called after each bus is probed, but before its children are examined. This 2703 * is marked as __weak because multiple architectures define it. 2704 */ 2705 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2706 { 2707 /* nothing to do, expected to be removed in the future */ 2708 } 2709 2710 /** 2711 * pci_scan_child_bus_extend() - Scan devices below a bus 2712 * @bus: Bus to scan for devices 2713 * @available_buses: Total number of buses available (%0 does not try to 2714 * extend beyond the minimal) 2715 * 2716 * Scans devices below @bus including subordinate buses. Returns new 2717 * subordinate number including all the found devices. Passing 2718 * @available_buses causes the remaining bus space to be distributed 2719 * equally between hotplug-capable bridges to allow future extension of the 2720 * hierarchy. 2721 */ 2722 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2723 unsigned int available_buses) 2724 { 2725 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2726 unsigned int start = bus->busn_res.start; 2727 unsigned int devfn, fn, cmax, max = start; 2728 struct pci_dev *dev; 2729 int nr_devs; 2730 2731 dev_dbg(&bus->dev, "scanning bus\n"); 2732 2733 /* Go find them, Rover! */ 2734 for (devfn = 0; devfn < 256; devfn += 8) { 2735 nr_devs = pci_scan_slot(bus, devfn); 2736 2737 /* 2738 * The Jailhouse hypervisor may pass individual functions of a 2739 * multi-function device to a guest without passing function 0. 2740 * Look for them as well. 2741 */ 2742 if (jailhouse_paravirt() && nr_devs == 0) { 2743 for (fn = 1; fn < 8; fn++) { 2744 dev = pci_scan_single_device(bus, devfn + fn); 2745 if (dev) 2746 dev->multifunction = 1; 2747 } 2748 } 2749 } 2750 2751 /* Reserve buses for SR-IOV capability */ 2752 used_buses = pci_iov_bus_range(bus); 2753 max += used_buses; 2754 2755 /* 2756 * After performing arch-dependent fixup of the bus, look behind 2757 * all PCI-to-PCI bridges on this bus. 2758 */ 2759 if (!bus->is_added) { 2760 dev_dbg(&bus->dev, "fixups for bus\n"); 2761 pcibios_fixup_bus(bus); 2762 bus->is_added = 1; 2763 } 2764 2765 /* 2766 * Calculate how many hotplug bridges and normal bridges there 2767 * are on this bus. We will distribute the additional available 2768 * buses between hotplug bridges. 2769 */ 2770 for_each_pci_bridge(dev, bus) { 2771 if (dev->is_hotplug_bridge) 2772 hotplug_bridges++; 2773 else 2774 normal_bridges++; 2775 } 2776 2777 /* 2778 * Scan bridges that are already configured. We don't touch them 2779 * unless they are misconfigured (which will be done in the second 2780 * scan below). 2781 */ 2782 for_each_pci_bridge(dev, bus) { 2783 cmax = max; 2784 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2785 2786 /* 2787 * Reserve one bus for each bridge now to avoid extending 2788 * hotplug bridges too much during the second scan below. 2789 */ 2790 used_buses++; 2791 if (cmax - max > 1) 2792 used_buses += cmax - max - 1; 2793 } 2794 2795 /* Scan bridges that need to be reconfigured */ 2796 for_each_pci_bridge(dev, bus) { 2797 unsigned int buses = 0; 2798 2799 if (!hotplug_bridges && normal_bridges == 1) { 2800 2801 /* 2802 * There is only one bridge on the bus (upstream 2803 * port) so it gets all available buses which it 2804 * can then distribute to the possible hotplug 2805 * bridges below. 2806 */ 2807 buses = available_buses; 2808 } else if (dev->is_hotplug_bridge) { 2809 2810 /* 2811 * Distribute the extra buses between hotplug 2812 * bridges if any. 2813 */ 2814 buses = available_buses / hotplug_bridges; 2815 buses = min(buses, available_buses - used_buses + 1); 2816 } 2817 2818 cmax = max; 2819 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2820 /* One bus is already accounted so don't add it again */ 2821 if (max - cmax > 1) 2822 used_buses += max - cmax - 1; 2823 } 2824 2825 /* 2826 * Make sure a hotplug bridge has at least the minimum requested 2827 * number of buses but allow it to grow up to the maximum available 2828 * bus number of there is room. 2829 */ 2830 if (bus->self && bus->self->is_hotplug_bridge) { 2831 used_buses = max_t(unsigned int, available_buses, 2832 pci_hotplug_bus_size - 1); 2833 if (max - start < used_buses) { 2834 max = start + used_buses; 2835 2836 /* Do not allocate more buses than we have room left */ 2837 if (max > bus->busn_res.end) 2838 max = bus->busn_res.end; 2839 2840 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 2841 &bus->busn_res, max - start); 2842 } 2843 } 2844 2845 /* 2846 * We've scanned the bus and so we know all about what's on 2847 * the other side of any bridges that may be on this bus plus 2848 * any devices. 2849 * 2850 * Return how far we've got finding sub-buses. 2851 */ 2852 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 2853 return max; 2854 } 2855 2856 /** 2857 * pci_scan_child_bus() - Scan devices below a bus 2858 * @bus: Bus to scan for devices 2859 * 2860 * Scans devices below @bus including subordinate buses. Returns new 2861 * subordinate number including all the found devices. 2862 */ 2863 unsigned int pci_scan_child_bus(struct pci_bus *bus) 2864 { 2865 return pci_scan_child_bus_extend(bus, 0); 2866 } 2867 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 2868 2869 /** 2870 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 2871 * @bridge: Host bridge to set up 2872 * 2873 * Default empty implementation. Replace with an architecture-specific setup 2874 * routine, if necessary. 2875 */ 2876 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 2877 { 2878 return 0; 2879 } 2880 2881 void __weak pcibios_add_bus(struct pci_bus *bus) 2882 { 2883 } 2884 2885 void __weak pcibios_remove_bus(struct pci_bus *bus) 2886 { 2887 } 2888 2889 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 2890 struct pci_ops *ops, void *sysdata, struct list_head *resources) 2891 { 2892 int error; 2893 struct pci_host_bridge *bridge; 2894 2895 bridge = pci_alloc_host_bridge(0); 2896 if (!bridge) 2897 return NULL; 2898 2899 bridge->dev.parent = parent; 2900 2901 list_splice_init(resources, &bridge->windows); 2902 bridge->sysdata = sysdata; 2903 bridge->busnr = bus; 2904 bridge->ops = ops; 2905 2906 error = pci_register_host_bridge(bridge); 2907 if (error < 0) 2908 goto err_out; 2909 2910 return bridge->bus; 2911 2912 err_out: 2913 kfree(bridge); 2914 return NULL; 2915 } 2916 EXPORT_SYMBOL_GPL(pci_create_root_bus); 2917 2918 int pci_host_probe(struct pci_host_bridge *bridge) 2919 { 2920 struct pci_bus *bus, *child; 2921 int ret; 2922 2923 ret = pci_scan_root_bus_bridge(bridge); 2924 if (ret < 0) { 2925 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 2926 return ret; 2927 } 2928 2929 bus = bridge->bus; 2930 2931 /* 2932 * We insert PCI resources into the iomem_resource and 2933 * ioport_resource trees in either pci_bus_claim_resources() 2934 * or pci_bus_assign_resources(). 2935 */ 2936 if (pci_has_flag(PCI_PROBE_ONLY)) { 2937 pci_bus_claim_resources(bus); 2938 } else { 2939 pci_bus_size_bridges(bus); 2940 pci_bus_assign_resources(bus); 2941 2942 list_for_each_entry(child, &bus->children, node) 2943 pcie_bus_configure_settings(child); 2944 } 2945 2946 pci_bus_add_devices(bus); 2947 return 0; 2948 } 2949 EXPORT_SYMBOL_GPL(pci_host_probe); 2950 2951 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 2952 { 2953 struct resource *res = &b->busn_res; 2954 struct resource *parent_res, *conflict; 2955 2956 res->start = bus; 2957 res->end = bus_max; 2958 res->flags = IORESOURCE_BUS; 2959 2960 if (!pci_is_root_bus(b)) 2961 parent_res = &b->parent->busn_res; 2962 else { 2963 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 2964 res->flags |= IORESOURCE_PCI_FIXED; 2965 } 2966 2967 conflict = request_resource_conflict(parent_res, res); 2968 2969 if (conflict) 2970 dev_info(&b->dev, 2971 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 2972 res, pci_is_root_bus(b) ? "domain " : "", 2973 parent_res, conflict->name, conflict); 2974 2975 return conflict == NULL; 2976 } 2977 2978 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 2979 { 2980 struct resource *res = &b->busn_res; 2981 struct resource old_res = *res; 2982 resource_size_t size; 2983 int ret; 2984 2985 if (res->start > bus_max) 2986 return -EINVAL; 2987 2988 size = bus_max - res->start + 1; 2989 ret = adjust_resource(res, res->start, size); 2990 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 2991 &old_res, ret ? "can not be" : "is", bus_max); 2992 2993 if (!ret && !res->parent) 2994 pci_bus_insert_busn_res(b, res->start, res->end); 2995 2996 return ret; 2997 } 2998 2999 void pci_bus_release_busn_res(struct pci_bus *b) 3000 { 3001 struct resource *res = &b->busn_res; 3002 int ret; 3003 3004 if (!res->flags || !res->parent) 3005 return; 3006 3007 ret = release_resource(res); 3008 dev_info(&b->dev, "busn_res: %pR %s released\n", 3009 res, ret ? "can not be" : "is"); 3010 } 3011 3012 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3013 { 3014 struct resource_entry *window; 3015 bool found = false; 3016 struct pci_bus *b; 3017 int max, bus, ret; 3018 3019 if (!bridge) 3020 return -EINVAL; 3021 3022 resource_list_for_each_entry(window, &bridge->windows) 3023 if (window->res->flags & IORESOURCE_BUS) { 3024 found = true; 3025 break; 3026 } 3027 3028 ret = pci_register_host_bridge(bridge); 3029 if (ret < 0) 3030 return ret; 3031 3032 b = bridge->bus; 3033 bus = bridge->busnr; 3034 3035 if (!found) { 3036 dev_info(&b->dev, 3037 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3038 bus); 3039 pci_bus_insert_busn_res(b, bus, 255); 3040 } 3041 3042 max = pci_scan_child_bus(b); 3043 3044 if (!found) 3045 pci_bus_update_busn_res_end(b, max); 3046 3047 return 0; 3048 } 3049 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3050 3051 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3052 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3053 { 3054 struct resource_entry *window; 3055 bool found = false; 3056 struct pci_bus *b; 3057 int max; 3058 3059 resource_list_for_each_entry(window, resources) 3060 if (window->res->flags & IORESOURCE_BUS) { 3061 found = true; 3062 break; 3063 } 3064 3065 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3066 if (!b) 3067 return NULL; 3068 3069 if (!found) { 3070 dev_info(&b->dev, 3071 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3072 bus); 3073 pci_bus_insert_busn_res(b, bus, 255); 3074 } 3075 3076 max = pci_scan_child_bus(b); 3077 3078 if (!found) 3079 pci_bus_update_busn_res_end(b, max); 3080 3081 return b; 3082 } 3083 EXPORT_SYMBOL(pci_scan_root_bus); 3084 3085 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3086 void *sysdata) 3087 { 3088 LIST_HEAD(resources); 3089 struct pci_bus *b; 3090 3091 pci_add_resource(&resources, &ioport_resource); 3092 pci_add_resource(&resources, &iomem_resource); 3093 pci_add_resource(&resources, &busn_resource); 3094 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3095 if (b) { 3096 pci_scan_child_bus(b); 3097 } else { 3098 pci_free_resource_list(&resources); 3099 } 3100 return b; 3101 } 3102 EXPORT_SYMBOL(pci_scan_bus); 3103 3104 /** 3105 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3106 * @bridge: PCI bridge for the bus to scan 3107 * 3108 * Scan a PCI bus and child buses for new devices, add them, 3109 * and enable them, resizing bridge mmio/io resource if necessary 3110 * and possible. The caller must ensure the child devices are already 3111 * removed for resizing to occur. 3112 * 3113 * Returns the max number of subordinate bus discovered. 3114 */ 3115 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3116 { 3117 unsigned int max; 3118 struct pci_bus *bus = bridge->subordinate; 3119 3120 max = pci_scan_child_bus(bus); 3121 3122 pci_assign_unassigned_bridge_resources(bridge); 3123 3124 pci_bus_add_devices(bus); 3125 3126 return max; 3127 } 3128 3129 /** 3130 * pci_rescan_bus - Scan a PCI bus for devices 3131 * @bus: PCI bus to scan 3132 * 3133 * Scan a PCI bus and child buses for new devices, add them, 3134 * and enable them. 3135 * 3136 * Returns the max number of subordinate bus discovered. 3137 */ 3138 unsigned int pci_rescan_bus(struct pci_bus *bus) 3139 { 3140 unsigned int max; 3141 3142 max = pci_scan_child_bus(bus); 3143 pci_assign_unassigned_bus_resources(bus); 3144 pci_bus_add_devices(bus); 3145 3146 return max; 3147 } 3148 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3149 3150 /* 3151 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3152 * routines should always be executed under this mutex. 3153 */ 3154 static DEFINE_MUTEX(pci_rescan_remove_lock); 3155 3156 void pci_lock_rescan_remove(void) 3157 { 3158 mutex_lock(&pci_rescan_remove_lock); 3159 } 3160 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3161 3162 void pci_unlock_rescan_remove(void) 3163 { 3164 mutex_unlock(&pci_rescan_remove_lock); 3165 } 3166 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3167 3168 static int __init pci_sort_bf_cmp(const struct device *d_a, 3169 const struct device *d_b) 3170 { 3171 const struct pci_dev *a = to_pci_dev(d_a); 3172 const struct pci_dev *b = to_pci_dev(d_b); 3173 3174 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3175 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3176 3177 if (a->bus->number < b->bus->number) return -1; 3178 else if (a->bus->number > b->bus->number) return 1; 3179 3180 if (a->devfn < b->devfn) return -1; 3181 else if (a->devfn > b->devfn) return 1; 3182 3183 return 0; 3184 } 3185 3186 void __init pci_sort_breadthfirst(void) 3187 { 3188 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3189 } 3190 3191 int pci_hp_add_bridge(struct pci_dev *dev) 3192 { 3193 struct pci_bus *parent = dev->bus; 3194 int busnr, start = parent->busn_res.start; 3195 unsigned int available_buses = 0; 3196 int end = parent->busn_res.end; 3197 3198 for (busnr = start; busnr <= end; busnr++) { 3199 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3200 break; 3201 } 3202 if (busnr-- > end) { 3203 pci_err(dev, "No bus number available for hot-added bridge\n"); 3204 return -1; 3205 } 3206 3207 /* Scan bridges that are already configured */ 3208 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3209 3210 /* 3211 * Distribute the available bus numbers between hotplug-capable 3212 * bridges to make extending the chain later possible. 3213 */ 3214 available_buses = end - busnr; 3215 3216 /* Scan bridges that need to be reconfigured */ 3217 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3218 3219 if (!dev->subordinate) 3220 return -1; 3221 3222 return 0; 3223 } 3224 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3225