1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_pci.h> 12 #include <linux/pci_hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/cpumask.h> 16 #include <linux/aer.h> 17 #include <linux/acpi.h> 18 #include <linux/hypervisor.h> 19 #include <linux/irqdomain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/bitfield.h> 22 #include "pci.h" 23 24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 25 #define CARDBUS_RESERVE_BUSNR 3 26 27 static struct resource busn_resource = { 28 .name = "PCI busn", 29 .start = 0, 30 .end = 255, 31 .flags = IORESOURCE_BUS, 32 }; 33 34 /* Ugh. Need to stop exporting this to modules. */ 35 LIST_HEAD(pci_root_buses); 36 EXPORT_SYMBOL(pci_root_buses); 37 38 static LIST_HEAD(pci_domain_busn_res_list); 39 40 struct pci_domain_busn_res { 41 struct list_head list; 42 struct resource res; 43 int domain_nr; 44 }; 45 46 static struct resource *get_pci_domain_busn_res(int domain_nr) 47 { 48 struct pci_domain_busn_res *r; 49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list) 51 if (r->domain_nr == domain_nr) 52 return &r->res; 53 54 r = kzalloc(sizeof(*r), GFP_KERNEL); 55 if (!r) 56 return NULL; 57 58 r->domain_nr = domain_nr; 59 r->res.start = 0; 60 r->res.end = 0xff; 61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 62 63 list_add_tail(&r->list, &pci_domain_busn_res_list); 64 65 return &r->res; 66 } 67 68 /* 69 * Some device drivers need know if PCI is initiated. 70 * Basically, we think PCI is not initiated when there 71 * is no device to be found on the pci_bus_type. 72 */ 73 int no_pci_devices(void) 74 { 75 struct device *dev; 76 int no_devices; 77 78 dev = bus_find_next_device(&pci_bus_type, NULL); 79 no_devices = (dev == NULL); 80 put_device(dev); 81 return no_devices; 82 } 83 EXPORT_SYMBOL(no_pci_devices); 84 85 /* 86 * PCI Bus Class 87 */ 88 static void release_pcibus_dev(struct device *dev) 89 { 90 struct pci_bus *pci_bus = to_pci_bus(dev); 91 92 put_device(pci_bus->bridge); 93 pci_bus_remove_resources(pci_bus); 94 pci_release_bus_of_node(pci_bus); 95 kfree(pci_bus); 96 } 97 98 static const struct class pcibus_class = { 99 .name = "pci_bus", 100 .dev_release = &release_pcibus_dev, 101 .dev_groups = pcibus_groups, 102 }; 103 104 static int __init pcibus_class_init(void) 105 { 106 return class_register(&pcibus_class); 107 } 108 postcore_initcall(pcibus_class_init); 109 110 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 111 { 112 u64 size = mask & maxbase; /* Find the significant bits */ 113 if (!size) 114 return 0; 115 116 /* 117 * Get the lowest of them to find the decode size, and from that 118 * the extent. 119 */ 120 size = size & ~(size-1); 121 122 /* 123 * base == maxbase can be valid only if the BAR has already been 124 * programmed with all 1s. 125 */ 126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 127 return 0; 128 129 return size; 130 } 131 132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 133 { 134 u32 mem_type; 135 unsigned long flags; 136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 139 flags |= IORESOURCE_IO; 140 return flags; 141 } 142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 144 flags |= IORESOURCE_MEM; 145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 146 flags |= IORESOURCE_PREFETCH; 147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 149 switch (mem_type) { 150 case PCI_BASE_ADDRESS_MEM_TYPE_32: 151 break; 152 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 153 /* 1M mem BAR treated as 32-bit BAR */ 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_64: 156 flags |= IORESOURCE_MEM_64; 157 break; 158 default: 159 /* mem unknown type treated as 32-bit BAR */ 160 break; 161 } 162 return flags; 163 } 164 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 167 /** 168 * __pci_read_base - Read a PCI BAR 169 * @dev: the PCI device 170 * @type: type of the BAR 171 * @res: resource buffer to be filled in 172 * @pos: BAR position in the config space 173 * 174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 175 */ 176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 177 struct resource *res, unsigned int pos) 178 { 179 u32 l = 0, sz = 0, mask; 180 u64 l64, sz64, mask64; 181 u16 orig_cmd; 182 struct pci_bus_region region, inverted_region; 183 const char *res_name = pci_resource_name(dev, res - dev->resource); 184 185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 186 187 /* No printks while decoding is disabled! */ 188 if (!dev->mmio_always_on) { 189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 191 pci_write_config_word(dev, PCI_COMMAND, 192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 193 } 194 } 195 196 res->name = pci_name(dev); 197 198 pci_read_config_dword(dev, pos, &l); 199 pci_write_config_dword(dev, pos, l | mask); 200 pci_read_config_dword(dev, pos, &sz); 201 pci_write_config_dword(dev, pos, l); 202 203 /* 204 * All bits set in sz means the device isn't working properly. 205 * If the BAR isn't implemented, all bits must be 0. If it's a 206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 207 * 1 must be clear. 208 */ 209 if (PCI_POSSIBLE_ERROR(sz)) 210 sz = 0; 211 212 /* 213 * I don't know how l can have all bits set. Copied from old code. 214 * Maybe it fixes a bug on some ancient platform. 215 */ 216 if (PCI_POSSIBLE_ERROR(l)) 217 l = 0; 218 219 if (type == pci_bar_unknown) { 220 res->flags = decode_bar(dev, l); 221 res->flags |= IORESOURCE_SIZEALIGN; 222 if (res->flags & IORESOURCE_IO) { 223 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 226 } else { 227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 230 } 231 } else { 232 if (l & PCI_ROM_ADDRESS_ENABLE) 233 res->flags |= IORESOURCE_ROM_ENABLE; 234 l64 = l & PCI_ROM_ADDRESS_MASK; 235 sz64 = sz & PCI_ROM_ADDRESS_MASK; 236 mask64 = PCI_ROM_ADDRESS_MASK; 237 } 238 239 if (res->flags & IORESOURCE_MEM_64) { 240 pci_read_config_dword(dev, pos + 4, &l); 241 pci_write_config_dword(dev, pos + 4, ~0); 242 pci_read_config_dword(dev, pos + 4, &sz); 243 pci_write_config_dword(dev, pos + 4, l); 244 245 l64 |= ((u64)l << 32); 246 sz64 |= ((u64)sz << 32); 247 mask64 |= ((u64)~0 << 32); 248 } 249 250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 252 253 if (!sz64) 254 goto fail; 255 256 sz64 = pci_size(l64, sz64, mask64); 257 if (!sz64) { 258 pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name); 259 goto fail; 260 } 261 262 if (res->flags & IORESOURCE_MEM_64) { 263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 264 && sz64 > 0x100000000ULL) { 265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 266 res->start = 0; 267 res->end = 0; 268 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n", 269 res_name, (unsigned long long)sz64); 270 goto out; 271 } 272 273 if ((sizeof(pci_bus_addr_t) < 8) && l) { 274 /* Above 32-bit boundary; try to reallocate */ 275 res->flags |= IORESOURCE_UNSET; 276 res->start = 0; 277 res->end = sz64 - 1; 278 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n", 279 res_name, (unsigned long long)l64); 280 goto out; 281 } 282 } 283 284 region.start = l64; 285 region.end = l64 + sz64 - 1; 286 287 pcibios_bus_to_resource(dev->bus, res, ®ion); 288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 289 290 /* 291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 292 * the corresponding resource address (the physical address used by 293 * the CPU. Converting that resource address back to a bus address 294 * should yield the original BAR value: 295 * 296 * resource_to_bus(bus_to_resource(A)) == A 297 * 298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 299 * be claimed by the device. 300 */ 301 if (inverted_region.start != region.start) { 302 res->flags |= IORESOURCE_UNSET; 303 res->start = 0; 304 res->end = region.end - region.start; 305 pci_info(dev, "%s: initial BAR value %#010llx invalid\n", 306 res_name, (unsigned long long)region.start); 307 } 308 309 goto out; 310 311 312 fail: 313 res->flags = 0; 314 out: 315 if (res->flags) 316 pci_info(dev, "%s %pR\n", res_name, res); 317 318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 319 } 320 321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 322 { 323 unsigned int pos, reg; 324 325 if (dev->non_compliant_bars) 326 return; 327 328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 329 if (dev->is_virtfn) 330 return; 331 332 for (pos = 0; pos < howmany; pos++) { 333 struct resource *res = &dev->resource[pos]; 334 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 336 } 337 338 if (rom) { 339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 340 dev->rom_base_reg = rom; 341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 343 __pci_read_base(dev, pci_bar_mem32, res, rom); 344 } 345 } 346 347 static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res, 348 bool log) 349 { 350 u8 io_base_lo, io_limit_lo; 351 unsigned long io_mask, io_granularity, base, limit; 352 struct pci_bus_region region; 353 354 io_mask = PCI_IO_RANGE_MASK; 355 io_granularity = 0x1000; 356 if (dev->io_window_1k) { 357 /* Support 1K I/O space granularity */ 358 io_mask = PCI_IO_1K_RANGE_MASK; 359 io_granularity = 0x400; 360 } 361 362 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 363 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 364 base = (io_base_lo & io_mask) << 8; 365 limit = (io_limit_lo & io_mask) << 8; 366 367 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 368 u16 io_base_hi, io_limit_hi; 369 370 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 371 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 372 base |= ((unsigned long) io_base_hi << 16); 373 limit |= ((unsigned long) io_limit_hi << 16); 374 } 375 376 if (base <= limit) { 377 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 378 region.start = base; 379 region.end = limit + io_granularity - 1; 380 pcibios_bus_to_resource(dev->bus, res, ®ion); 381 if (log) 382 pci_info(dev, " bridge window %pR\n", res); 383 } 384 } 385 386 static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res, 387 bool log) 388 { 389 u16 mem_base_lo, mem_limit_lo; 390 unsigned long base, limit; 391 struct pci_bus_region region; 392 393 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 394 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 395 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 396 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 397 if (base <= limit) { 398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 399 region.start = base; 400 region.end = limit + 0xfffff; 401 pcibios_bus_to_resource(dev->bus, res, ®ion); 402 if (log) 403 pci_info(dev, " bridge window %pR\n", res); 404 } 405 } 406 407 static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res, 408 bool log) 409 { 410 u16 mem_base_lo, mem_limit_lo; 411 u64 base64, limit64; 412 pci_bus_addr_t base, limit; 413 struct pci_bus_region region; 414 415 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 416 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 417 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 418 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 419 420 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 421 u32 mem_base_hi, mem_limit_hi; 422 423 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 424 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 425 426 /* 427 * Some bridges set the base > limit by default, and some 428 * (broken) BIOSes do not initialize them. If we find 429 * this, just assume they are not being used. 430 */ 431 if (mem_base_hi <= mem_limit_hi) { 432 base64 |= (u64) mem_base_hi << 32; 433 limit64 |= (u64) mem_limit_hi << 32; 434 } 435 } 436 437 base = (pci_bus_addr_t) base64; 438 limit = (pci_bus_addr_t) limit64; 439 440 if (base != base64) { 441 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 442 (unsigned long long) base64); 443 return; 444 } 445 446 if (base <= limit) { 447 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 448 IORESOURCE_MEM | IORESOURCE_PREFETCH; 449 if (res->flags & PCI_PREF_RANGE_TYPE_64) 450 res->flags |= IORESOURCE_MEM_64; 451 region.start = base; 452 region.end = limit + 0xfffff; 453 pcibios_bus_to_resource(dev->bus, res, ®ion); 454 if (log) 455 pci_info(dev, " bridge window %pR\n", res); 456 } 457 } 458 459 static void pci_read_bridge_windows(struct pci_dev *bridge) 460 { 461 u32 buses; 462 u16 io; 463 u32 pmem, tmp; 464 struct resource res; 465 466 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses); 467 res.flags = IORESOURCE_BUS; 468 res.start = (buses >> 8) & 0xff; 469 res.end = (buses >> 16) & 0xff; 470 pci_info(bridge, "PCI bridge to %pR%s\n", &res, 471 bridge->transparent ? " (subtractive decode)" : ""); 472 473 pci_read_config_word(bridge, PCI_IO_BASE, &io); 474 if (!io) { 475 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 476 pci_read_config_word(bridge, PCI_IO_BASE, &io); 477 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 478 } 479 if (io) { 480 bridge->io_window = 1; 481 pci_read_bridge_io(bridge, &res, true); 482 } 483 484 pci_read_bridge_mmio(bridge, &res, true); 485 486 /* 487 * DECchip 21050 pass 2 errata: the bridge may miss an address 488 * disconnect boundary by one PCI data phase. Workaround: do not 489 * use prefetching on this device. 490 */ 491 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 492 return; 493 494 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 495 if (!pmem) { 496 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 497 0xffe0fff0); 498 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 499 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 500 } 501 if (!pmem) 502 return; 503 504 bridge->pref_window = 1; 505 506 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 507 508 /* 509 * Bridge claims to have a 64-bit prefetchable memory 510 * window; verify that the upper bits are actually 511 * writable. 512 */ 513 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 514 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 515 0xffffffff); 516 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 517 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 518 if (tmp) 519 bridge->pref_64_window = 1; 520 } 521 522 pci_read_bridge_mmio_pref(bridge, &res, true); 523 } 524 525 void pci_read_bridge_bases(struct pci_bus *child) 526 { 527 struct pci_dev *dev = child->self; 528 struct resource *res; 529 int i; 530 531 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 532 return; 533 534 pci_info(dev, "PCI bridge to %pR%s\n", 535 &child->busn_res, 536 dev->transparent ? " (subtractive decode)" : ""); 537 538 pci_bus_remove_resources(child); 539 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 540 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 541 542 pci_read_bridge_io(child->self, child->resource[0], false); 543 pci_read_bridge_mmio(child->self, child->resource[1], false); 544 pci_read_bridge_mmio_pref(child->self, child->resource[2], false); 545 546 if (!dev->transparent) 547 return; 548 549 pci_bus_for_each_resource(child->parent, res) { 550 if (!res || !res->flags) 551 continue; 552 553 pci_bus_add_resource(child, res); 554 pci_info(dev, " bridge window %pR (subtractive decode)\n", res); 555 } 556 } 557 558 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 559 { 560 struct pci_bus *b; 561 562 b = kzalloc(sizeof(*b), GFP_KERNEL); 563 if (!b) 564 return NULL; 565 566 INIT_LIST_HEAD(&b->node); 567 INIT_LIST_HEAD(&b->children); 568 INIT_LIST_HEAD(&b->devices); 569 INIT_LIST_HEAD(&b->slots); 570 INIT_LIST_HEAD(&b->resources); 571 b->max_bus_speed = PCI_SPEED_UNKNOWN; 572 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 573 #ifdef CONFIG_PCI_DOMAINS_GENERIC 574 if (parent) 575 b->domain_nr = parent->domain_nr; 576 #endif 577 return b; 578 } 579 580 static void pci_release_host_bridge_dev(struct device *dev) 581 { 582 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 583 584 if (bridge->release_fn) 585 bridge->release_fn(bridge); 586 587 pci_free_resource_list(&bridge->windows); 588 pci_free_resource_list(&bridge->dma_ranges); 589 kfree(bridge); 590 } 591 592 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 593 { 594 INIT_LIST_HEAD(&bridge->windows); 595 INIT_LIST_HEAD(&bridge->dma_ranges); 596 597 /* 598 * We assume we can manage these PCIe features. Some systems may 599 * reserve these for use by the platform itself, e.g., an ACPI BIOS 600 * may implement its own AER handling and use _OSC to prevent the 601 * OS from interfering. 602 */ 603 bridge->native_aer = 1; 604 bridge->native_pcie_hotplug = 1; 605 bridge->native_shpc_hotplug = 1; 606 bridge->native_pme = 1; 607 bridge->native_ltr = 1; 608 bridge->native_dpc = 1; 609 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 610 bridge->native_cxl_error = 1; 611 612 device_initialize(&bridge->dev); 613 } 614 615 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 616 { 617 struct pci_host_bridge *bridge; 618 619 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 620 if (!bridge) 621 return NULL; 622 623 pci_init_host_bridge(bridge); 624 bridge->dev.release = pci_release_host_bridge_dev; 625 626 return bridge; 627 } 628 EXPORT_SYMBOL(pci_alloc_host_bridge); 629 630 static void devm_pci_alloc_host_bridge_release(void *data) 631 { 632 pci_free_host_bridge(data); 633 } 634 635 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 636 size_t priv) 637 { 638 int ret; 639 struct pci_host_bridge *bridge; 640 641 bridge = pci_alloc_host_bridge(priv); 642 if (!bridge) 643 return NULL; 644 645 bridge->dev.parent = dev; 646 647 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 648 bridge); 649 if (ret) 650 return NULL; 651 652 ret = devm_of_pci_bridge_init(dev, bridge); 653 if (ret) 654 return NULL; 655 656 return bridge; 657 } 658 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 659 660 void pci_free_host_bridge(struct pci_host_bridge *bridge) 661 { 662 put_device(&bridge->dev); 663 } 664 EXPORT_SYMBOL(pci_free_host_bridge); 665 666 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 667 static const unsigned char pcix_bus_speed[] = { 668 PCI_SPEED_UNKNOWN, /* 0 */ 669 PCI_SPEED_66MHz_PCIX, /* 1 */ 670 PCI_SPEED_100MHz_PCIX, /* 2 */ 671 PCI_SPEED_133MHz_PCIX, /* 3 */ 672 PCI_SPEED_UNKNOWN, /* 4 */ 673 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 674 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 675 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 676 PCI_SPEED_UNKNOWN, /* 8 */ 677 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 678 PCI_SPEED_100MHz_PCIX_266, /* A */ 679 PCI_SPEED_133MHz_PCIX_266, /* B */ 680 PCI_SPEED_UNKNOWN, /* C */ 681 PCI_SPEED_66MHz_PCIX_533, /* D */ 682 PCI_SPEED_100MHz_PCIX_533, /* E */ 683 PCI_SPEED_133MHz_PCIX_533 /* F */ 684 }; 685 686 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 687 const unsigned char pcie_link_speed[] = { 688 PCI_SPEED_UNKNOWN, /* 0 */ 689 PCIE_SPEED_2_5GT, /* 1 */ 690 PCIE_SPEED_5_0GT, /* 2 */ 691 PCIE_SPEED_8_0GT, /* 3 */ 692 PCIE_SPEED_16_0GT, /* 4 */ 693 PCIE_SPEED_32_0GT, /* 5 */ 694 PCIE_SPEED_64_0GT, /* 6 */ 695 PCI_SPEED_UNKNOWN, /* 7 */ 696 PCI_SPEED_UNKNOWN, /* 8 */ 697 PCI_SPEED_UNKNOWN, /* 9 */ 698 PCI_SPEED_UNKNOWN, /* A */ 699 PCI_SPEED_UNKNOWN, /* B */ 700 PCI_SPEED_UNKNOWN, /* C */ 701 PCI_SPEED_UNKNOWN, /* D */ 702 PCI_SPEED_UNKNOWN, /* E */ 703 PCI_SPEED_UNKNOWN /* F */ 704 }; 705 EXPORT_SYMBOL_GPL(pcie_link_speed); 706 707 const char *pci_speed_string(enum pci_bus_speed speed) 708 { 709 /* Indexed by the pci_bus_speed enum */ 710 static const char *speed_strings[] = { 711 "33 MHz PCI", /* 0x00 */ 712 "66 MHz PCI", /* 0x01 */ 713 "66 MHz PCI-X", /* 0x02 */ 714 "100 MHz PCI-X", /* 0x03 */ 715 "133 MHz PCI-X", /* 0x04 */ 716 NULL, /* 0x05 */ 717 NULL, /* 0x06 */ 718 NULL, /* 0x07 */ 719 NULL, /* 0x08 */ 720 "66 MHz PCI-X 266", /* 0x09 */ 721 "100 MHz PCI-X 266", /* 0x0a */ 722 "133 MHz PCI-X 266", /* 0x0b */ 723 "Unknown AGP", /* 0x0c */ 724 "1x AGP", /* 0x0d */ 725 "2x AGP", /* 0x0e */ 726 "4x AGP", /* 0x0f */ 727 "8x AGP", /* 0x10 */ 728 "66 MHz PCI-X 533", /* 0x11 */ 729 "100 MHz PCI-X 533", /* 0x12 */ 730 "133 MHz PCI-X 533", /* 0x13 */ 731 "2.5 GT/s PCIe", /* 0x14 */ 732 "5.0 GT/s PCIe", /* 0x15 */ 733 "8.0 GT/s PCIe", /* 0x16 */ 734 "16.0 GT/s PCIe", /* 0x17 */ 735 "32.0 GT/s PCIe", /* 0x18 */ 736 "64.0 GT/s PCIe", /* 0x19 */ 737 }; 738 739 if (speed < ARRAY_SIZE(speed_strings)) 740 return speed_strings[speed]; 741 return "Unknown"; 742 } 743 EXPORT_SYMBOL_GPL(pci_speed_string); 744 745 void pcie_update_link_speed(struct pci_bus *bus) 746 { 747 struct pci_dev *bridge = bus->self; 748 u16 linksta; 749 750 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 751 __pcie_update_link_speed(bus, linksta); 752 } 753 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 754 755 static unsigned char agp_speeds[] = { 756 AGP_UNKNOWN, 757 AGP_1X, 758 AGP_2X, 759 AGP_4X, 760 AGP_8X 761 }; 762 763 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 764 { 765 int index = 0; 766 767 if (agpstat & 4) 768 index = 3; 769 else if (agpstat & 2) 770 index = 2; 771 else if (agpstat & 1) 772 index = 1; 773 else 774 goto out; 775 776 if (agp3) { 777 index += 2; 778 if (index == 5) 779 index = 0; 780 } 781 782 out: 783 return agp_speeds[index]; 784 } 785 786 static void pci_set_bus_speed(struct pci_bus *bus) 787 { 788 struct pci_dev *bridge = bus->self; 789 int pos; 790 791 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 792 if (!pos) 793 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 794 if (pos) { 795 u32 agpstat, agpcmd; 796 797 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 798 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 799 800 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 801 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 802 } 803 804 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 805 if (pos) { 806 u16 status; 807 enum pci_bus_speed max; 808 809 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 810 &status); 811 812 if (status & PCI_X_SSTATUS_533MHZ) { 813 max = PCI_SPEED_133MHz_PCIX_533; 814 } else if (status & PCI_X_SSTATUS_266MHZ) { 815 max = PCI_SPEED_133MHz_PCIX_266; 816 } else if (status & PCI_X_SSTATUS_133MHZ) { 817 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 818 max = PCI_SPEED_133MHz_PCIX_ECC; 819 else 820 max = PCI_SPEED_133MHz_PCIX; 821 } else { 822 max = PCI_SPEED_66MHz_PCIX; 823 } 824 825 bus->max_bus_speed = max; 826 bus->cur_bus_speed = 827 pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)]; 828 829 return; 830 } 831 832 if (pci_is_pcie(bridge)) { 833 u32 linkcap; 834 835 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 836 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 837 838 pcie_update_link_speed(bus); 839 } 840 } 841 842 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 843 { 844 struct irq_domain *d; 845 846 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 847 d = dev_get_msi_domain(bus->bridge); 848 849 /* 850 * Any firmware interface that can resolve the msi_domain 851 * should be called from here. 852 */ 853 if (!d) 854 d = pci_host_bridge_of_msi_domain(bus); 855 if (!d) 856 d = pci_host_bridge_acpi_msi_domain(bus); 857 858 /* 859 * If no IRQ domain was found via the OF tree, try looking it up 860 * directly through the fwnode_handle. 861 */ 862 if (!d) { 863 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 864 865 if (fwnode) 866 d = irq_find_matching_fwnode(fwnode, 867 DOMAIN_BUS_PCI_MSI); 868 } 869 870 return d; 871 } 872 873 static void pci_set_bus_msi_domain(struct pci_bus *bus) 874 { 875 struct irq_domain *d; 876 struct pci_bus *b; 877 878 /* 879 * The bus can be a root bus, a subordinate bus, or a virtual bus 880 * created by an SR-IOV device. Walk up to the first bridge device 881 * found or derive the domain from the host bridge. 882 */ 883 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 884 if (b->self) 885 d = dev_get_msi_domain(&b->self->dev); 886 } 887 888 if (!d) 889 d = pci_host_bridge_msi_domain(b); 890 891 dev_set_msi_domain(&bus->dev, d); 892 } 893 894 static bool pci_preserve_config(struct pci_host_bridge *host_bridge) 895 { 896 if (pci_acpi_preserve_config(host_bridge)) 897 return true; 898 899 if (host_bridge->dev.parent && host_bridge->dev.parent->of_node) 900 return of_pci_preserve_config(host_bridge->dev.parent->of_node); 901 902 return false; 903 } 904 905 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 906 { 907 struct device *parent = bridge->dev.parent; 908 struct resource_entry *window, *next, *n; 909 struct pci_bus *bus, *b; 910 resource_size_t offset, next_offset; 911 LIST_HEAD(resources); 912 struct resource *res, *next_res; 913 char addr[64], *fmt; 914 const char *name; 915 int err; 916 917 bus = pci_alloc_bus(NULL); 918 if (!bus) 919 return -ENOMEM; 920 921 bridge->bus = bus; 922 923 bus->sysdata = bridge->sysdata; 924 bus->ops = bridge->ops; 925 bus->number = bus->busn_res.start = bridge->busnr; 926 #ifdef CONFIG_PCI_DOMAINS_GENERIC 927 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 928 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 929 else 930 bus->domain_nr = bridge->domain_nr; 931 if (bus->domain_nr < 0) { 932 err = bus->domain_nr; 933 goto free; 934 } 935 #endif 936 937 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 938 if (b) { 939 /* Ignore it if we already got here via a different bridge */ 940 dev_dbg(&b->dev, "bus already known\n"); 941 err = -EEXIST; 942 goto free; 943 } 944 945 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 946 bridge->busnr); 947 948 err = pcibios_root_bridge_prepare(bridge); 949 if (err) 950 goto free; 951 952 /* Temporarily move resources off the list */ 953 list_splice_init(&bridge->windows, &resources); 954 err = device_add(&bridge->dev); 955 if (err) { 956 put_device(&bridge->dev); 957 goto free; 958 } 959 bus->bridge = get_device(&bridge->dev); 960 device_enable_async_suspend(bus->bridge); 961 pci_set_bus_of_node(bus); 962 pci_set_bus_msi_domain(bus); 963 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 964 !pci_host_of_has_msi_map(parent)) 965 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 966 967 if (!parent) 968 set_dev_node(bus->bridge, pcibus_to_node(bus)); 969 970 bus->dev.class = &pcibus_class; 971 bus->dev.parent = bus->bridge; 972 973 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 974 name = dev_name(&bus->dev); 975 976 err = device_register(&bus->dev); 977 if (err) 978 goto unregister; 979 980 pcibios_add_bus(bus); 981 982 if (bus->ops->add_bus) { 983 err = bus->ops->add_bus(bus); 984 if (WARN_ON(err < 0)) 985 dev_err(&bus->dev, "failed to add bus: %d\n", err); 986 } 987 988 /* Create legacy_io and legacy_mem files for this bus */ 989 pci_create_legacy_files(bus); 990 991 if (parent) 992 dev_info(parent, "PCI host bridge to bus %s\n", name); 993 else 994 pr_info("PCI host bridge to bus %s\n", name); 995 996 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 997 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 998 999 /* Check if the boot configuration by FW needs to be preserved */ 1000 bridge->preserve_config = pci_preserve_config(bridge); 1001 1002 /* Coalesce contiguous windows */ 1003 resource_list_for_each_entry_safe(window, n, &resources) { 1004 if (list_is_last(&window->node, &resources)) 1005 break; 1006 1007 next = list_next_entry(window, node); 1008 offset = window->offset; 1009 res = window->res; 1010 next_offset = next->offset; 1011 next_res = next->res; 1012 1013 if (res->flags != next_res->flags || offset != next_offset) 1014 continue; 1015 1016 if (res->end + 1 == next_res->start) { 1017 next_res->start = res->start; 1018 res->flags = res->start = res->end = 0; 1019 } 1020 } 1021 1022 /* Add initial resources to the bus */ 1023 resource_list_for_each_entry_safe(window, n, &resources) { 1024 offset = window->offset; 1025 res = window->res; 1026 if (!res->flags && !res->start && !res->end) { 1027 release_resource(res); 1028 resource_list_destroy_entry(window); 1029 continue; 1030 } 1031 1032 list_move_tail(&window->node, &bridge->windows); 1033 1034 if (res->flags & IORESOURCE_BUS) 1035 pci_bus_insert_busn_res(bus, bus->number, res->end); 1036 else 1037 pci_bus_add_resource(bus, res); 1038 1039 if (offset) { 1040 if (resource_type(res) == IORESOURCE_IO) 1041 fmt = " (bus address [%#06llx-%#06llx])"; 1042 else 1043 fmt = " (bus address [%#010llx-%#010llx])"; 1044 1045 snprintf(addr, sizeof(addr), fmt, 1046 (unsigned long long)(res->start - offset), 1047 (unsigned long long)(res->end - offset)); 1048 } else 1049 addr[0] = '\0'; 1050 1051 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 1052 } 1053 1054 down_write(&pci_bus_sem); 1055 list_add_tail(&bus->node, &pci_root_buses); 1056 up_write(&pci_bus_sem); 1057 1058 return 0; 1059 1060 unregister: 1061 put_device(&bridge->dev); 1062 device_del(&bridge->dev); 1063 1064 free: 1065 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1066 pci_bus_release_domain_nr(parent, bus->domain_nr); 1067 #endif 1068 kfree(bus); 1069 return err; 1070 } 1071 1072 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1073 { 1074 int pos; 1075 u32 status; 1076 1077 /* 1078 * If extended config space isn't accessible on a bridge's primary 1079 * bus, we certainly can't access it on the secondary bus. 1080 */ 1081 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1082 return false; 1083 1084 /* 1085 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1086 * extended config space is accessible on the primary, it's also 1087 * accessible on the secondary. 1088 */ 1089 if (pci_is_pcie(bridge) && 1090 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1091 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1092 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1093 return true; 1094 1095 /* 1096 * For the other bridge types: 1097 * - PCI-to-PCI bridges 1098 * - PCIe-to-PCI/PCI-X forward bridges 1099 * - PCI/PCI-X-to-PCIe reverse bridges 1100 * extended config space on the secondary side is only accessible 1101 * if the bridge supports PCI-X Mode 2. 1102 */ 1103 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1104 if (!pos) 1105 return false; 1106 1107 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1108 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1109 } 1110 1111 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1112 struct pci_dev *bridge, int busnr) 1113 { 1114 struct pci_bus *child; 1115 struct pci_host_bridge *host; 1116 int i; 1117 int ret; 1118 1119 /* Allocate a new bus and inherit stuff from the parent */ 1120 child = pci_alloc_bus(parent); 1121 if (!child) 1122 return NULL; 1123 1124 child->parent = parent; 1125 child->sysdata = parent->sysdata; 1126 child->bus_flags = parent->bus_flags; 1127 1128 host = pci_find_host_bridge(parent); 1129 if (host->child_ops) 1130 child->ops = host->child_ops; 1131 else 1132 child->ops = parent->ops; 1133 1134 /* 1135 * Initialize some portions of the bus device, but don't register 1136 * it now as the parent is not properly set up yet. 1137 */ 1138 child->dev.class = &pcibus_class; 1139 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1140 1141 /* Set up the primary, secondary and subordinate bus numbers */ 1142 child->number = child->busn_res.start = busnr; 1143 child->primary = parent->busn_res.start; 1144 child->busn_res.end = 0xff; 1145 1146 if (!bridge) { 1147 child->dev.parent = parent->bridge; 1148 goto add_dev; 1149 } 1150 1151 child->self = bridge; 1152 child->bridge = get_device(&bridge->dev); 1153 child->dev.parent = child->bridge; 1154 pci_set_bus_of_node(child); 1155 pci_set_bus_speed(child); 1156 1157 /* 1158 * Check whether extended config space is accessible on the child 1159 * bus. Note that we currently assume it is always accessible on 1160 * the root bus. 1161 */ 1162 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1163 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1164 pci_info(child, "extended config space not accessible\n"); 1165 } 1166 1167 /* Set up default resource pointers and names */ 1168 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1169 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1170 child->resource[i]->name = child->name; 1171 } 1172 bridge->subordinate = child; 1173 1174 add_dev: 1175 pci_set_bus_msi_domain(child); 1176 ret = device_register(&child->dev); 1177 WARN_ON(ret < 0); 1178 1179 pcibios_add_bus(child); 1180 1181 if (child->ops->add_bus) { 1182 ret = child->ops->add_bus(child); 1183 if (WARN_ON(ret < 0)) 1184 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1185 } 1186 1187 /* Create legacy_io and legacy_mem files for this bus */ 1188 pci_create_legacy_files(child); 1189 1190 return child; 1191 } 1192 1193 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1194 int busnr) 1195 { 1196 struct pci_bus *child; 1197 1198 child = pci_alloc_child_bus(parent, dev, busnr); 1199 if (child) { 1200 down_write(&pci_bus_sem); 1201 list_add_tail(&child->node, &parent->children); 1202 up_write(&pci_bus_sem); 1203 } 1204 return child; 1205 } 1206 EXPORT_SYMBOL(pci_add_new_bus); 1207 1208 static void pci_enable_rrs_sv(struct pci_dev *pdev) 1209 { 1210 u16 root_cap = 0; 1211 1212 /* Enable Configuration RRS Software Visibility if supported */ 1213 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1214 if (root_cap & PCI_EXP_RTCAP_RRS_SV) { 1215 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1216 PCI_EXP_RTCTL_RRS_SVE); 1217 pdev->config_rrs_sv = 1; 1218 } 1219 } 1220 1221 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1222 unsigned int available_buses); 1223 /** 1224 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1225 * numbers from EA capability. 1226 * @dev: Bridge 1227 * @sec: updated with secondary bus number from EA 1228 * @sub: updated with subordinate bus number from EA 1229 * 1230 * If @dev is a bridge with EA capability that specifies valid secondary 1231 * and subordinate bus numbers, return true with the bus numbers in @sec 1232 * and @sub. Otherwise return false. 1233 */ 1234 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1235 { 1236 int ea, offset; 1237 u32 dw; 1238 u8 ea_sec, ea_sub; 1239 1240 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1241 return false; 1242 1243 /* find PCI EA capability in list */ 1244 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1245 if (!ea) 1246 return false; 1247 1248 offset = ea + PCI_EA_FIRST_ENT; 1249 pci_read_config_dword(dev, offset, &dw); 1250 ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw); 1251 ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw); 1252 if (ea_sec == 0 || ea_sub < ea_sec) 1253 return false; 1254 1255 *sec = ea_sec; 1256 *sub = ea_sub; 1257 return true; 1258 } 1259 1260 /* 1261 * pci_scan_bridge_extend() - Scan buses behind a bridge 1262 * @bus: Parent bus the bridge is on 1263 * @dev: Bridge itself 1264 * @max: Starting subordinate number of buses behind this bridge 1265 * @available_buses: Total number of buses available for this bridge and 1266 * the devices below. After the minimal bus space has 1267 * been allocated the remaining buses will be 1268 * distributed equally between hotplug-capable bridges. 1269 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1270 * that need to be reconfigured. 1271 * 1272 * If it's a bridge, configure it and scan the bus behind it. 1273 * For CardBus bridges, we don't scan behind as the devices will 1274 * be handled by the bridge driver itself. 1275 * 1276 * We need to process bridges in two passes -- first we scan those 1277 * already configured by the BIOS and after we are done with all of 1278 * them, we proceed to assigning numbers to the remaining buses in 1279 * order to avoid overlaps between old and new bus numbers. 1280 * 1281 * Return: New subordinate number covering all buses behind this bridge. 1282 */ 1283 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1284 int max, unsigned int available_buses, 1285 int pass) 1286 { 1287 struct pci_bus *child; 1288 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1289 u32 buses, i, j = 0; 1290 u16 bctl; 1291 u8 primary, secondary, subordinate; 1292 int broken = 0; 1293 bool fixed_buses; 1294 u8 fixed_sec, fixed_sub; 1295 int next_busnr; 1296 1297 /* 1298 * Make sure the bridge is powered on to be able to access config 1299 * space of devices below it. 1300 */ 1301 pm_runtime_get_sync(&dev->dev); 1302 1303 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1304 primary = buses & 0xFF; 1305 secondary = (buses >> 8) & 0xFF; 1306 subordinate = (buses >> 16) & 0xFF; 1307 1308 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1309 secondary, subordinate, pass); 1310 1311 if (!primary && (primary != bus->number) && secondary && subordinate) { 1312 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1313 primary = bus->number; 1314 } 1315 1316 /* Check if setup is sensible at all */ 1317 if (!pass && 1318 (primary != bus->number || secondary <= bus->number || 1319 secondary > subordinate)) { 1320 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1321 secondary, subordinate); 1322 broken = 1; 1323 } 1324 1325 /* 1326 * Disable Master-Abort Mode during probing to avoid reporting of 1327 * bus errors in some architectures. 1328 */ 1329 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1330 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1331 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1332 1333 pci_enable_rrs_sv(dev); 1334 1335 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1336 !is_cardbus && !broken) { 1337 unsigned int cmax, buses; 1338 1339 /* 1340 * Bus already configured by firmware, process it in the 1341 * first pass and just note the configuration. 1342 */ 1343 if (pass) 1344 goto out; 1345 1346 /* 1347 * The bus might already exist for two reasons: Either we 1348 * are rescanning the bus or the bus is reachable through 1349 * more than one bridge. The second case can happen with 1350 * the i450NX chipset. 1351 */ 1352 child = pci_find_bus(pci_domain_nr(bus), secondary); 1353 if (!child) { 1354 child = pci_add_new_bus(bus, dev, secondary); 1355 if (!child) 1356 goto out; 1357 child->primary = primary; 1358 pci_bus_insert_busn_res(child, secondary, subordinate); 1359 child->bridge_ctl = bctl; 1360 } 1361 1362 buses = subordinate - secondary; 1363 cmax = pci_scan_child_bus_extend(child, buses); 1364 if (cmax > subordinate) 1365 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1366 subordinate, cmax); 1367 1368 /* Subordinate should equal child->busn_res.end */ 1369 if (subordinate > max) 1370 max = subordinate; 1371 } else { 1372 1373 /* 1374 * We need to assign a number to this bus which we always 1375 * do in the second pass. 1376 */ 1377 if (!pass) { 1378 if (pcibios_assign_all_busses() || broken || is_cardbus) 1379 1380 /* 1381 * Temporarily disable forwarding of the 1382 * configuration cycles on all bridges in 1383 * this bus segment to avoid possible 1384 * conflicts in the second pass between two 1385 * bridges programmed with overlapping bus 1386 * ranges. 1387 */ 1388 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1389 buses & ~0xffffff); 1390 goto out; 1391 } 1392 1393 /* Clear errors */ 1394 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1395 1396 /* Read bus numbers from EA Capability (if present) */ 1397 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1398 if (fixed_buses) 1399 next_busnr = fixed_sec; 1400 else 1401 next_busnr = max + 1; 1402 1403 /* 1404 * Prevent assigning a bus number that already exists. 1405 * This can happen when a bridge is hot-plugged, so in this 1406 * case we only re-scan this bus. 1407 */ 1408 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1409 if (!child) { 1410 child = pci_add_new_bus(bus, dev, next_busnr); 1411 if (!child) 1412 goto out; 1413 pci_bus_insert_busn_res(child, next_busnr, 1414 bus->busn_res.end); 1415 } 1416 max++; 1417 if (available_buses) 1418 available_buses--; 1419 1420 buses = (buses & 0xff000000) 1421 | ((unsigned int)(child->primary) << 0) 1422 | ((unsigned int)(child->busn_res.start) << 8) 1423 | ((unsigned int)(child->busn_res.end) << 16); 1424 1425 /* 1426 * yenta.c forces a secondary latency timer of 176. 1427 * Copy that behaviour here. 1428 */ 1429 if (is_cardbus) { 1430 buses &= ~0xff000000; 1431 buses |= CARDBUS_LATENCY_TIMER << 24; 1432 } 1433 1434 /* We need to blast all three values with a single write */ 1435 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1436 1437 if (!is_cardbus) { 1438 child->bridge_ctl = bctl; 1439 max = pci_scan_child_bus_extend(child, available_buses); 1440 } else { 1441 1442 /* 1443 * For CardBus bridges, we leave 4 bus numbers as 1444 * cards with a PCI-to-PCI bridge can be inserted 1445 * later. 1446 */ 1447 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1448 struct pci_bus *parent = bus; 1449 if (pci_find_bus(pci_domain_nr(bus), 1450 max+i+1)) 1451 break; 1452 while (parent->parent) { 1453 if ((!pcibios_assign_all_busses()) && 1454 (parent->busn_res.end > max) && 1455 (parent->busn_res.end <= max+i)) { 1456 j = 1; 1457 } 1458 parent = parent->parent; 1459 } 1460 if (j) { 1461 1462 /* 1463 * Often, there are two CardBus 1464 * bridges -- try to leave one 1465 * valid bus number for each one. 1466 */ 1467 i /= 2; 1468 break; 1469 } 1470 } 1471 max += i; 1472 } 1473 1474 /* 1475 * Set subordinate bus number to its real value. 1476 * If fixed subordinate bus number exists from EA 1477 * capability then use it. 1478 */ 1479 if (fixed_buses) 1480 max = fixed_sub; 1481 pci_bus_update_busn_res_end(child, max); 1482 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1483 } 1484 1485 sprintf(child->name, 1486 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1487 pci_domain_nr(bus), child->number); 1488 1489 /* Check that all devices are accessible */ 1490 while (bus->parent) { 1491 if ((child->busn_res.end > bus->busn_res.end) || 1492 (child->number > bus->busn_res.end) || 1493 (child->number < bus->number) || 1494 (child->busn_res.end < bus->number)) { 1495 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1496 &child->busn_res); 1497 break; 1498 } 1499 bus = bus->parent; 1500 } 1501 1502 out: 1503 /* Clear errors in the Secondary Status Register */ 1504 pci_write_config_word(dev, PCI_SEC_STATUS, 0xffff); 1505 1506 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1507 1508 pm_runtime_put(&dev->dev); 1509 1510 return max; 1511 } 1512 1513 /* 1514 * pci_scan_bridge() - Scan buses behind a bridge 1515 * @bus: Parent bus the bridge is on 1516 * @dev: Bridge itself 1517 * @max: Starting subordinate number of buses behind this bridge 1518 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1519 * that need to be reconfigured. 1520 * 1521 * If it's a bridge, configure it and scan the bus behind it. 1522 * For CardBus bridges, we don't scan behind as the devices will 1523 * be handled by the bridge driver itself. 1524 * 1525 * We need to process bridges in two passes -- first we scan those 1526 * already configured by the BIOS and after we are done with all of 1527 * them, we proceed to assigning numbers to the remaining buses in 1528 * order to avoid overlaps between old and new bus numbers. 1529 * 1530 * Return: New subordinate number covering all buses behind this bridge. 1531 */ 1532 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1533 { 1534 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1535 } 1536 EXPORT_SYMBOL(pci_scan_bridge); 1537 1538 /* 1539 * Read interrupt line and base address registers. 1540 * The architecture-dependent code can tweak these, of course. 1541 */ 1542 static void pci_read_irq(struct pci_dev *dev) 1543 { 1544 unsigned char irq; 1545 1546 /* VFs are not allowed to use INTx, so skip the config reads */ 1547 if (dev->is_virtfn) { 1548 dev->pin = 0; 1549 dev->irq = 0; 1550 return; 1551 } 1552 1553 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1554 dev->pin = irq; 1555 if (irq) 1556 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1557 dev->irq = irq; 1558 } 1559 1560 void set_pcie_port_type(struct pci_dev *pdev) 1561 { 1562 int pos; 1563 u16 reg16; 1564 u32 reg32; 1565 int type; 1566 struct pci_dev *parent; 1567 1568 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1569 if (!pos) 1570 return; 1571 1572 pdev->pcie_cap = pos; 1573 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1574 pdev->pcie_flags_reg = reg16; 1575 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1576 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1577 1578 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); 1579 if (reg32 & PCI_EXP_LNKCAP_DLLLARC) 1580 pdev->link_active_reporting = 1; 1581 1582 parent = pci_upstream_bridge(pdev); 1583 if (!parent) 1584 return; 1585 1586 /* 1587 * Some systems do not identify their upstream/downstream ports 1588 * correctly so detect impossible configurations here and correct 1589 * the port type accordingly. 1590 */ 1591 type = pci_pcie_type(pdev); 1592 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1593 /* 1594 * If pdev claims to be downstream port but the parent 1595 * device is also downstream port assume pdev is actually 1596 * upstream port. 1597 */ 1598 if (pcie_downstream_port(parent)) { 1599 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1600 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1601 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1602 } 1603 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1604 /* 1605 * If pdev claims to be upstream port but the parent 1606 * device is also upstream port assume pdev is actually 1607 * downstream port. 1608 */ 1609 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1610 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1611 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1612 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1613 } 1614 } 1615 } 1616 1617 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1618 { 1619 u32 reg32; 1620 1621 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1622 if (reg32 & PCI_EXP_SLTCAP_HPC) 1623 pdev->is_hotplug_bridge = 1; 1624 } 1625 1626 static void set_pcie_thunderbolt(struct pci_dev *dev) 1627 { 1628 u16 vsec; 1629 1630 /* Is the device part of a Thunderbolt controller? */ 1631 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); 1632 if (vsec) 1633 dev->is_thunderbolt = 1; 1634 } 1635 1636 static void set_pcie_untrusted(struct pci_dev *dev) 1637 { 1638 struct pci_dev *parent = pci_upstream_bridge(dev); 1639 1640 if (!parent) 1641 return; 1642 /* 1643 * If the upstream bridge is untrusted we treat this device as 1644 * untrusted as well. 1645 */ 1646 if (parent->untrusted) { 1647 dev->untrusted = true; 1648 return; 1649 } 1650 1651 if (arch_pci_dev_is_removable(dev)) { 1652 pci_dbg(dev, "marking as untrusted\n"); 1653 dev->untrusted = true; 1654 } 1655 } 1656 1657 static void pci_set_removable(struct pci_dev *dev) 1658 { 1659 struct pci_dev *parent = pci_upstream_bridge(dev); 1660 1661 if (!parent) 1662 return; 1663 /* 1664 * We (only) consider everything tunneled below an external_facing 1665 * device to be removable by the user. We're mainly concerned with 1666 * consumer platforms with user accessible thunderbolt ports that are 1667 * vulnerable to DMA attacks, and we expect those ports to be marked by 1668 * the firmware as external_facing. Devices in traditional hotplug 1669 * slots can technically be removed, but the expectation is that unless 1670 * the port is marked with external_facing, such devices are less 1671 * accessible to user / may not be removed by end user, and thus not 1672 * exposed as "removable" to userspace. 1673 */ 1674 if (dev_is_removable(&parent->dev)) { 1675 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1676 return; 1677 } 1678 1679 if (arch_pci_dev_is_removable(dev)) { 1680 pci_dbg(dev, "marking as removable\n"); 1681 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1682 } 1683 } 1684 1685 /** 1686 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1687 * @dev: PCI device 1688 * 1689 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1690 * when forwarding a type1 configuration request the bridge must check that 1691 * the extended register address field is zero. The bridge is not permitted 1692 * to forward the transactions and must handle it as an Unsupported Request. 1693 * Some bridges do not follow this rule and simply drop the extended register 1694 * bits, resulting in the standard config space being aliased, every 256 1695 * bytes across the entire configuration space. Test for this condition by 1696 * comparing the first dword of each potential alias to the vendor/device ID. 1697 * Known offenders: 1698 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1699 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1700 */ 1701 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1702 { 1703 #ifdef CONFIG_PCI_QUIRKS 1704 int pos, ret; 1705 u32 header, tmp; 1706 1707 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1708 1709 for (pos = PCI_CFG_SPACE_SIZE; 1710 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1711 ret = pci_read_config_dword(dev, pos, &tmp); 1712 if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp)) 1713 return false; 1714 } 1715 1716 return true; 1717 #else 1718 return false; 1719 #endif 1720 } 1721 1722 /** 1723 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1724 * @dev: PCI device 1725 * 1726 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1727 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1728 * access it. Maybe we don't have a way to generate extended config space 1729 * accesses, or the device is behind a reverse Express bridge. So we try 1730 * reading the dword at 0x100 which must either be 0 or a valid extended 1731 * capability header. 1732 */ 1733 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1734 { 1735 u32 status; 1736 int pos = PCI_CFG_SPACE_SIZE; 1737 1738 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1739 return PCI_CFG_SPACE_SIZE; 1740 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) 1741 return PCI_CFG_SPACE_SIZE; 1742 1743 return PCI_CFG_SPACE_EXP_SIZE; 1744 } 1745 1746 int pci_cfg_space_size(struct pci_dev *dev) 1747 { 1748 int pos; 1749 u32 status; 1750 u16 class; 1751 1752 #ifdef CONFIG_PCI_IOV 1753 /* 1754 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1755 * implement a PCIe capability and therefore must implement extended 1756 * config space. We can skip the NO_EXTCFG test below and the 1757 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1758 * the fact that the SR-IOV capability on the PF resides in extended 1759 * config space and must be accessible and non-aliased to have enabled 1760 * support for this VF. This is a micro performance optimization for 1761 * systems supporting many VFs. 1762 */ 1763 if (dev->is_virtfn) 1764 return PCI_CFG_SPACE_EXP_SIZE; 1765 #endif 1766 1767 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1768 return PCI_CFG_SPACE_SIZE; 1769 1770 class = dev->class >> 8; 1771 if (class == PCI_CLASS_BRIDGE_HOST) 1772 return pci_cfg_space_size_ext(dev); 1773 1774 if (pci_is_pcie(dev)) 1775 return pci_cfg_space_size_ext(dev); 1776 1777 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1778 if (!pos) 1779 return PCI_CFG_SPACE_SIZE; 1780 1781 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1782 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1783 return pci_cfg_space_size_ext(dev); 1784 1785 return PCI_CFG_SPACE_SIZE; 1786 } 1787 1788 static u32 pci_class(struct pci_dev *dev) 1789 { 1790 u32 class; 1791 1792 #ifdef CONFIG_PCI_IOV 1793 if (dev->is_virtfn) 1794 return dev->physfn->sriov->class; 1795 #endif 1796 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1797 return class; 1798 } 1799 1800 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1801 { 1802 #ifdef CONFIG_PCI_IOV 1803 if (dev->is_virtfn) { 1804 *vendor = dev->physfn->sriov->subsystem_vendor; 1805 *device = dev->physfn->sriov->subsystem_device; 1806 return; 1807 } 1808 #endif 1809 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1810 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1811 } 1812 1813 static u8 pci_hdr_type(struct pci_dev *dev) 1814 { 1815 u8 hdr_type; 1816 1817 #ifdef CONFIG_PCI_IOV 1818 if (dev->is_virtfn) 1819 return dev->physfn->sriov->hdr_type; 1820 #endif 1821 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1822 return hdr_type; 1823 } 1824 1825 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1826 1827 /** 1828 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1829 * @dev: PCI device 1830 * 1831 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1832 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1833 */ 1834 static int pci_intx_mask_broken(struct pci_dev *dev) 1835 { 1836 u16 orig, toggle, new; 1837 1838 pci_read_config_word(dev, PCI_COMMAND, &orig); 1839 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1840 pci_write_config_word(dev, PCI_COMMAND, toggle); 1841 pci_read_config_word(dev, PCI_COMMAND, &new); 1842 1843 pci_write_config_word(dev, PCI_COMMAND, orig); 1844 1845 /* 1846 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1847 * r2.3, so strictly speaking, a device is not *broken* if it's not 1848 * writable. But we'll live with the misnomer for now. 1849 */ 1850 if (new != toggle) 1851 return 1; 1852 return 0; 1853 } 1854 1855 static void early_dump_pci_device(struct pci_dev *pdev) 1856 { 1857 u32 value[256 / 4]; 1858 int i; 1859 1860 pci_info(pdev, "config space:\n"); 1861 1862 for (i = 0; i < 256; i += 4) 1863 pci_read_config_dword(pdev, i, &value[i / 4]); 1864 1865 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1866 value, 256, false); 1867 } 1868 1869 static const char *pci_type_str(struct pci_dev *dev) 1870 { 1871 static const char * const str[] = { 1872 "PCIe Endpoint", 1873 "PCIe Legacy Endpoint", 1874 "PCIe unknown", 1875 "PCIe unknown", 1876 "PCIe Root Port", 1877 "PCIe Switch Upstream Port", 1878 "PCIe Switch Downstream Port", 1879 "PCIe to PCI/PCI-X bridge", 1880 "PCI/PCI-X to PCIe bridge", 1881 "PCIe Root Complex Integrated Endpoint", 1882 "PCIe Root Complex Event Collector", 1883 }; 1884 int type; 1885 1886 if (pci_is_pcie(dev)) { 1887 type = pci_pcie_type(dev); 1888 if (type < ARRAY_SIZE(str)) 1889 return str[type]; 1890 1891 return "PCIe unknown"; 1892 } 1893 1894 switch (dev->hdr_type) { 1895 case PCI_HEADER_TYPE_NORMAL: 1896 return "conventional PCI endpoint"; 1897 case PCI_HEADER_TYPE_BRIDGE: 1898 return "conventional PCI bridge"; 1899 case PCI_HEADER_TYPE_CARDBUS: 1900 return "CardBus bridge"; 1901 default: 1902 return "conventional PCI"; 1903 } 1904 } 1905 1906 /** 1907 * pci_setup_device - Fill in class and map information of a device 1908 * @dev: the device structure to fill 1909 * 1910 * Initialize the device structure with information about the device's 1911 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1912 * Called at initialisation of the PCI subsystem and by CardBus services. 1913 * Returns 0 on success and negative if unknown type of device (not normal, 1914 * bridge or CardBus). 1915 */ 1916 int pci_setup_device(struct pci_dev *dev) 1917 { 1918 u32 class; 1919 u16 cmd; 1920 u8 hdr_type; 1921 int err, pos = 0; 1922 struct pci_bus_region region; 1923 struct resource *res; 1924 1925 hdr_type = pci_hdr_type(dev); 1926 1927 dev->sysdata = dev->bus->sysdata; 1928 dev->dev.parent = dev->bus->bridge; 1929 dev->dev.bus = &pci_bus_type; 1930 dev->hdr_type = hdr_type & 0x7f; 1931 dev->multifunction = !!(hdr_type & 0x80); 1932 dev->error_state = pci_channel_io_normal; 1933 set_pcie_port_type(dev); 1934 1935 err = pci_set_of_node(dev); 1936 if (err) 1937 return err; 1938 pci_set_acpi_fwnode(dev); 1939 1940 pci_dev_assign_slot(dev); 1941 1942 /* 1943 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1944 * set this higher, assuming the system even supports it. 1945 */ 1946 dev->dma_mask = 0xffffffff; 1947 1948 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1949 dev->bus->number, PCI_SLOT(dev->devfn), 1950 PCI_FUNC(dev->devfn)); 1951 1952 class = pci_class(dev); 1953 1954 dev->revision = class & 0xff; 1955 dev->class = class >> 8; /* upper 3 bytes */ 1956 1957 if (pci_early_dump) 1958 early_dump_pci_device(dev); 1959 1960 /* Need to have dev->class ready */ 1961 dev->cfg_size = pci_cfg_space_size(dev); 1962 1963 /* Need to have dev->cfg_size ready */ 1964 set_pcie_thunderbolt(dev); 1965 1966 set_pcie_untrusted(dev); 1967 1968 if (pci_is_pcie(dev)) 1969 dev->supported_speeds = pcie_get_supported_speeds(dev); 1970 1971 /* "Unknown power state" */ 1972 dev->current_state = PCI_UNKNOWN; 1973 1974 /* Early fixups, before probing the BARs */ 1975 pci_fixup_device(pci_fixup_early, dev); 1976 1977 pci_set_removable(dev); 1978 1979 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n", 1980 dev->vendor, dev->device, dev->hdr_type, dev->class, 1981 pci_type_str(dev)); 1982 1983 /* Device class may be changed after fixup */ 1984 class = dev->class >> 8; 1985 1986 if (dev->non_compliant_bars && !dev->mmio_always_on) { 1987 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1988 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1989 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1990 cmd &= ~PCI_COMMAND_IO; 1991 cmd &= ~PCI_COMMAND_MEMORY; 1992 pci_write_config_word(dev, PCI_COMMAND, cmd); 1993 } 1994 } 1995 1996 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1997 1998 switch (dev->hdr_type) { /* header type */ 1999 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 2000 if (class == PCI_CLASS_BRIDGE_PCI) 2001 goto bad; 2002 pci_read_irq(dev); 2003 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 2004 2005 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 2006 2007 /* 2008 * Do the ugly legacy mode stuff here rather than broken chip 2009 * quirk code. Legacy mode ATA controllers have fixed 2010 * addresses. These are not always echoed in BAR0-3, and 2011 * BAR0-3 in a few cases contain junk! 2012 */ 2013 if (class == PCI_CLASS_STORAGE_IDE) { 2014 u8 progif; 2015 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 2016 if ((progif & 1) == 0) { 2017 region.start = 0x1F0; 2018 region.end = 0x1F7; 2019 res = &dev->resource[0]; 2020 res->flags = LEGACY_IO_RESOURCE; 2021 pcibios_bus_to_resource(dev->bus, res, ®ion); 2022 pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n", 2023 res); 2024 region.start = 0x3F6; 2025 region.end = 0x3F6; 2026 res = &dev->resource[1]; 2027 res->flags = LEGACY_IO_RESOURCE; 2028 pcibios_bus_to_resource(dev->bus, res, ®ion); 2029 pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n", 2030 res); 2031 } 2032 if ((progif & 4) == 0) { 2033 region.start = 0x170; 2034 region.end = 0x177; 2035 res = &dev->resource[2]; 2036 res->flags = LEGACY_IO_RESOURCE; 2037 pcibios_bus_to_resource(dev->bus, res, ®ion); 2038 pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n", 2039 res); 2040 region.start = 0x376; 2041 region.end = 0x376; 2042 res = &dev->resource[3]; 2043 res->flags = LEGACY_IO_RESOURCE; 2044 pcibios_bus_to_resource(dev->bus, res, ®ion); 2045 pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n", 2046 res); 2047 } 2048 } 2049 break; 2050 2051 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 2052 /* 2053 * The PCI-to-PCI bridge spec requires that subtractive 2054 * decoding (i.e. transparent) bridge must have programming 2055 * interface code of 0x01. 2056 */ 2057 pci_read_irq(dev); 2058 dev->transparent = ((dev->class & 0xff) == 1); 2059 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 2060 pci_read_bridge_windows(dev); 2061 set_pcie_hotplug_bridge(dev); 2062 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 2063 if (pos) { 2064 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 2065 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 2066 } 2067 break; 2068 2069 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 2070 if (class != PCI_CLASS_BRIDGE_CARDBUS) 2071 goto bad; 2072 pci_read_irq(dev); 2073 pci_read_bases(dev, 1, 0); 2074 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 2075 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 2076 break; 2077 2078 default: /* unknown header */ 2079 pci_err(dev, "unknown header type %02x, ignoring device\n", 2080 dev->hdr_type); 2081 pci_release_of_node(dev); 2082 return -EIO; 2083 2084 bad: 2085 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 2086 dev->class, dev->hdr_type); 2087 dev->class = PCI_CLASS_NOT_DEFINED << 8; 2088 } 2089 2090 /* We found a fine healthy device, go go go... */ 2091 return 0; 2092 } 2093 2094 static void pci_configure_mps(struct pci_dev *dev) 2095 { 2096 struct pci_dev *bridge = pci_upstream_bridge(dev); 2097 int mps, mpss, p_mps, rc; 2098 2099 if (!pci_is_pcie(dev)) 2100 return; 2101 2102 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 2103 if (dev->is_virtfn) 2104 return; 2105 2106 /* 2107 * For Root Complex Integrated Endpoints, program the maximum 2108 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 2109 */ 2110 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 2111 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2112 mps = 128; 2113 else 2114 mps = 128 << dev->pcie_mpss; 2115 rc = pcie_set_mps(dev, mps); 2116 if (rc) { 2117 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2118 mps); 2119 } 2120 return; 2121 } 2122 2123 if (!bridge || !pci_is_pcie(bridge)) 2124 return; 2125 2126 mps = pcie_get_mps(dev); 2127 p_mps = pcie_get_mps(bridge); 2128 2129 if (mps == p_mps) 2130 return; 2131 2132 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2133 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2134 mps, pci_name(bridge), p_mps); 2135 return; 2136 } 2137 2138 /* 2139 * Fancier MPS configuration is done later by 2140 * pcie_bus_configure_settings() 2141 */ 2142 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2143 return; 2144 2145 mpss = 128 << dev->pcie_mpss; 2146 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2147 pcie_set_mps(bridge, mpss); 2148 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2149 mpss, p_mps, 128 << bridge->pcie_mpss); 2150 p_mps = pcie_get_mps(bridge); 2151 } 2152 2153 rc = pcie_set_mps(dev, p_mps); 2154 if (rc) { 2155 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2156 p_mps); 2157 return; 2158 } 2159 2160 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2161 p_mps, mps, mpss); 2162 } 2163 2164 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2165 { 2166 struct pci_host_bridge *host; 2167 u32 cap; 2168 u16 ctl; 2169 int ret; 2170 2171 if (!pci_is_pcie(dev)) 2172 return 0; 2173 2174 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2175 if (ret) 2176 return 0; 2177 2178 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2179 return 0; 2180 2181 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2182 if (ret) 2183 return 0; 2184 2185 host = pci_find_host_bridge(dev->bus); 2186 if (!host) 2187 return 0; 2188 2189 /* 2190 * If some device in the hierarchy doesn't handle Extended Tags 2191 * correctly, make sure they're disabled. 2192 */ 2193 if (host->no_ext_tags) { 2194 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2195 pci_info(dev, "disabling Extended Tags\n"); 2196 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2197 PCI_EXP_DEVCTL_EXT_TAG); 2198 } 2199 return 0; 2200 } 2201 2202 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2203 pci_info(dev, "enabling Extended Tags\n"); 2204 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2205 PCI_EXP_DEVCTL_EXT_TAG); 2206 } 2207 return 0; 2208 } 2209 2210 /** 2211 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2212 * @dev: PCI device to query 2213 * 2214 * Returns true if the device has enabled relaxed ordering attribute. 2215 */ 2216 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2217 { 2218 u16 v; 2219 2220 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2221 2222 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2223 } 2224 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2225 2226 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2227 { 2228 struct pci_dev *root; 2229 2230 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */ 2231 if (dev->is_virtfn) 2232 return; 2233 2234 if (!pcie_relaxed_ordering_enabled(dev)) 2235 return; 2236 2237 /* 2238 * For now, we only deal with Relaxed Ordering issues with Root 2239 * Ports. Peer-to-Peer DMA is another can of worms. 2240 */ 2241 root = pcie_find_root_port(dev); 2242 if (!root) 2243 return; 2244 2245 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2246 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2247 PCI_EXP_DEVCTL_RELAX_EN); 2248 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2249 } 2250 } 2251 2252 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2253 { 2254 #ifdef CONFIG_PCI_PASID 2255 struct pci_dev *bridge; 2256 int pcie_type; 2257 u32 cap; 2258 2259 if (!pci_is_pcie(dev)) 2260 return; 2261 2262 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2263 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2264 return; 2265 2266 pcie_type = pci_pcie_type(dev); 2267 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2268 pcie_type == PCI_EXP_TYPE_RC_END) 2269 dev->eetlp_prefix_path = 1; 2270 else { 2271 bridge = pci_upstream_bridge(dev); 2272 if (bridge && bridge->eetlp_prefix_path) 2273 dev->eetlp_prefix_path = 1; 2274 } 2275 #endif 2276 } 2277 2278 static void pci_configure_serr(struct pci_dev *dev) 2279 { 2280 u16 control; 2281 2282 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2283 2284 /* 2285 * A bridge will not forward ERR_ messages coming from an 2286 * endpoint unless SERR# forwarding is enabled. 2287 */ 2288 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2289 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2290 control |= PCI_BRIDGE_CTL_SERR; 2291 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2292 } 2293 } 2294 } 2295 2296 static void pci_configure_device(struct pci_dev *dev) 2297 { 2298 pci_configure_mps(dev); 2299 pci_configure_extended_tags(dev, NULL); 2300 pci_configure_relaxed_ordering(dev); 2301 pci_configure_ltr(dev); 2302 pci_configure_aspm_l1ss(dev); 2303 pci_configure_eetlp_prefix(dev); 2304 pci_configure_serr(dev); 2305 2306 pci_acpi_program_hp_params(dev); 2307 } 2308 2309 static void pci_release_capabilities(struct pci_dev *dev) 2310 { 2311 pci_aer_exit(dev); 2312 pci_rcec_exit(dev); 2313 pci_iov_release(dev); 2314 pci_free_cap_save_buffers(dev); 2315 } 2316 2317 /** 2318 * pci_release_dev - Free a PCI device structure when all users of it are 2319 * finished 2320 * @dev: device that's been disconnected 2321 * 2322 * Will be called only by the device core when all users of this PCI device are 2323 * done. 2324 */ 2325 static void pci_release_dev(struct device *dev) 2326 { 2327 struct pci_dev *pci_dev; 2328 2329 pci_dev = to_pci_dev(dev); 2330 pci_release_capabilities(pci_dev); 2331 pci_release_of_node(pci_dev); 2332 pcibios_release_device(pci_dev); 2333 pci_bus_put(pci_dev->bus); 2334 kfree(pci_dev->driver_override); 2335 bitmap_free(pci_dev->dma_alias_mask); 2336 dev_dbg(dev, "device released\n"); 2337 kfree(pci_dev); 2338 } 2339 2340 static const struct device_type pci_dev_type = { 2341 .groups = pci_dev_attr_groups, 2342 }; 2343 2344 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2345 { 2346 struct pci_dev *dev; 2347 2348 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2349 if (!dev) 2350 return NULL; 2351 2352 INIT_LIST_HEAD(&dev->bus_list); 2353 dev->dev.type = &pci_dev_type; 2354 dev->bus = pci_bus_get(bus); 2355 dev->driver_exclusive_resource = (struct resource) { 2356 .name = "PCI Exclusive", 2357 .start = 0, 2358 .end = -1, 2359 }; 2360 2361 spin_lock_init(&dev->pcie_cap_lock); 2362 #ifdef CONFIG_PCI_MSI 2363 raw_spin_lock_init(&dev->msi_lock); 2364 #endif 2365 return dev; 2366 } 2367 EXPORT_SYMBOL(pci_alloc_dev); 2368 2369 static bool pci_bus_wait_rrs(struct pci_bus *bus, int devfn, u32 *l, 2370 int timeout) 2371 { 2372 int delay = 1; 2373 2374 if (!pci_bus_rrs_vendor_id(*l)) 2375 return true; /* not a Configuration RRS completion */ 2376 2377 if (!timeout) 2378 return false; /* RRS, but caller doesn't want to wait */ 2379 2380 /* 2381 * We got the reserved Vendor ID that indicates a completion with 2382 * Configuration Request Retry Status (RRS). Retry until we get a 2383 * valid Vendor ID or we time out. 2384 */ 2385 while (pci_bus_rrs_vendor_id(*l)) { 2386 if (delay > timeout) { 2387 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2388 pci_domain_nr(bus), bus->number, 2389 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2390 2391 return false; 2392 } 2393 if (delay >= 1000) 2394 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2395 pci_domain_nr(bus), bus->number, 2396 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2397 2398 msleep(delay); 2399 delay *= 2; 2400 2401 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2402 return false; 2403 } 2404 2405 if (delay >= 1000) 2406 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2407 pci_domain_nr(bus), bus->number, 2408 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2409 2410 return true; 2411 } 2412 2413 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2414 int timeout) 2415 { 2416 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2417 return false; 2418 2419 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ 2420 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || 2421 *l == 0x0000ffff || *l == 0xffff0000) 2422 return false; 2423 2424 if (pci_bus_rrs_vendor_id(*l)) 2425 return pci_bus_wait_rrs(bus, devfn, l, timeout); 2426 2427 return true; 2428 } 2429 2430 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2431 int timeout) 2432 { 2433 #ifdef CONFIG_PCI_QUIRKS 2434 struct pci_dev *bridge = bus->self; 2435 2436 /* 2437 * Certain IDT switches have an issue where they improperly trigger 2438 * ACS Source Validation errors on completions for config reads. 2439 */ 2440 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2441 bridge->device == 0x80b5) 2442 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2443 #endif 2444 2445 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2446 } 2447 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2448 2449 /* 2450 * Read the config data for a PCI device, sanity-check it, 2451 * and fill in the dev structure. 2452 */ 2453 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2454 { 2455 struct pci_dev *dev; 2456 u32 l; 2457 2458 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2459 return NULL; 2460 2461 dev = pci_alloc_dev(bus); 2462 if (!dev) 2463 return NULL; 2464 2465 dev->devfn = devfn; 2466 dev->vendor = l & 0xffff; 2467 dev->device = (l >> 16) & 0xffff; 2468 2469 if (pci_setup_device(dev)) { 2470 pci_bus_put(dev->bus); 2471 kfree(dev); 2472 return NULL; 2473 } 2474 2475 return dev; 2476 } 2477 2478 void pcie_report_downtraining(struct pci_dev *dev) 2479 { 2480 if (!pci_is_pcie(dev)) 2481 return; 2482 2483 /* Look from the device up to avoid downstream ports with no devices */ 2484 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2485 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2486 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2487 return; 2488 2489 /* Multi-function PCIe devices share the same link/status */ 2490 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2491 return; 2492 2493 /* Print link status only if the device is constrained by the fabric */ 2494 __pcie_print_link_status(dev, false); 2495 } 2496 2497 static void pci_init_capabilities(struct pci_dev *dev) 2498 { 2499 pci_ea_init(dev); /* Enhanced Allocation */ 2500 pci_msi_init(dev); /* Disable MSI */ 2501 pci_msix_init(dev); /* Disable MSI-X */ 2502 2503 /* Buffers for saving PCIe and PCI-X capabilities */ 2504 pci_allocate_cap_save_buffers(dev); 2505 2506 pci_pm_init(dev); /* Power Management */ 2507 pci_vpd_init(dev); /* Vital Product Data */ 2508 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2509 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2510 pci_ats_init(dev); /* Address Translation Services */ 2511 pci_pri_init(dev); /* Page Request Interface */ 2512 pci_pasid_init(dev); /* Process Address Space ID */ 2513 pci_acs_init(dev); /* Access Control Services */ 2514 pci_ptm_init(dev); /* Precision Time Measurement */ 2515 pci_aer_init(dev); /* Advanced Error Reporting */ 2516 pci_dpc_init(dev); /* Downstream Port Containment */ 2517 pci_rcec_init(dev); /* Root Complex Event Collector */ 2518 pci_doe_init(dev); /* Data Object Exchange */ 2519 pci_tph_init(dev); /* TLP Processing Hints */ 2520 2521 pcie_report_downtraining(dev); 2522 pci_init_reset_methods(dev); 2523 } 2524 2525 /* 2526 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2527 * devices. Firmware interfaces that can select the MSI domain on a 2528 * per-device basis should be called from here. 2529 */ 2530 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2531 { 2532 struct irq_domain *d; 2533 2534 /* 2535 * If a domain has been set through the pcibios_device_add() 2536 * callback, then this is the one (platform code knows best). 2537 */ 2538 d = dev_get_msi_domain(&dev->dev); 2539 if (d) 2540 return d; 2541 2542 /* 2543 * Let's see if we have a firmware interface able to provide 2544 * the domain. 2545 */ 2546 d = pci_msi_get_device_domain(dev); 2547 if (d) 2548 return d; 2549 2550 return NULL; 2551 } 2552 2553 static void pci_set_msi_domain(struct pci_dev *dev) 2554 { 2555 struct irq_domain *d; 2556 2557 /* 2558 * If the platform or firmware interfaces cannot supply a 2559 * device-specific MSI domain, then inherit the default domain 2560 * from the host bridge itself. 2561 */ 2562 d = pci_dev_msi_domain(dev); 2563 if (!d) 2564 d = dev_get_msi_domain(&dev->bus->dev); 2565 2566 dev_set_msi_domain(&dev->dev, d); 2567 } 2568 2569 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2570 { 2571 int ret; 2572 2573 pci_configure_device(dev); 2574 2575 device_initialize(&dev->dev); 2576 dev->dev.release = pci_release_dev; 2577 2578 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2579 dev->dev.dma_mask = &dev->dma_mask; 2580 dev->dev.dma_parms = &dev->dma_parms; 2581 dev->dev.coherent_dma_mask = 0xffffffffull; 2582 2583 dma_set_max_seg_size(&dev->dev, 65536); 2584 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2585 2586 pcie_failed_link_retrain(dev); 2587 2588 /* Fix up broken headers */ 2589 pci_fixup_device(pci_fixup_header, dev); 2590 2591 pci_reassigndev_resource_alignment(dev); 2592 2593 dev->state_saved = false; 2594 2595 pci_init_capabilities(dev); 2596 2597 /* 2598 * Add the device to our list of discovered devices 2599 * and the bus list for fixup functions, etc. 2600 */ 2601 down_write(&pci_bus_sem); 2602 list_add_tail(&dev->bus_list, &bus->devices); 2603 up_write(&pci_bus_sem); 2604 2605 ret = pcibios_device_add(dev); 2606 WARN_ON(ret < 0); 2607 2608 /* Set up MSI IRQ domain */ 2609 pci_set_msi_domain(dev); 2610 2611 /* Notifier could use PCI capabilities */ 2612 dev->match_driver = false; 2613 ret = device_add(&dev->dev); 2614 WARN_ON(ret < 0); 2615 2616 pci_npem_create(dev); 2617 } 2618 2619 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2620 { 2621 struct pci_dev *dev; 2622 2623 dev = pci_get_slot(bus, devfn); 2624 if (dev) { 2625 pci_dev_put(dev); 2626 return dev; 2627 } 2628 2629 dev = pci_scan_device(bus, devfn); 2630 if (!dev) 2631 return NULL; 2632 2633 pci_device_add(dev, bus); 2634 2635 return dev; 2636 } 2637 EXPORT_SYMBOL(pci_scan_single_device); 2638 2639 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2640 { 2641 int pos; 2642 u16 cap = 0; 2643 unsigned int next_fn; 2644 2645 if (!dev) 2646 return -ENODEV; 2647 2648 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2649 if (!pos) 2650 return -ENODEV; 2651 2652 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2653 next_fn = PCI_ARI_CAP_NFN(cap); 2654 if (next_fn <= fn) 2655 return -ENODEV; /* protect against malformed list */ 2656 2657 return next_fn; 2658 } 2659 2660 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2661 { 2662 if (pci_ari_enabled(bus)) 2663 return next_ari_fn(bus, dev, fn); 2664 2665 if (fn >= 7) 2666 return -ENODEV; 2667 /* only multifunction devices may have more functions */ 2668 if (dev && !dev->multifunction) 2669 return -ENODEV; 2670 2671 return fn + 1; 2672 } 2673 2674 static int only_one_child(struct pci_bus *bus) 2675 { 2676 struct pci_dev *bridge = bus->self; 2677 2678 /* 2679 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2680 * we scan for all possible devices, not just Device 0. 2681 */ 2682 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2683 return 0; 2684 2685 /* 2686 * A PCIe Downstream Port normally leads to a Link with only Device 2687 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2688 * only for Device 0 in that situation. 2689 */ 2690 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2691 return 1; 2692 2693 return 0; 2694 } 2695 2696 /** 2697 * pci_scan_slot - Scan a PCI slot on a bus for devices 2698 * @bus: PCI bus to scan 2699 * @devfn: slot number to scan (must have zero function) 2700 * 2701 * Scan a PCI slot on the specified PCI bus for devices, adding 2702 * discovered devices to the @bus->devices list. New devices 2703 * will not have is_added set. 2704 * 2705 * Returns the number of new devices found. 2706 */ 2707 int pci_scan_slot(struct pci_bus *bus, int devfn) 2708 { 2709 struct pci_dev *dev; 2710 int fn = 0, nr = 0; 2711 2712 if (only_one_child(bus) && (devfn > 0)) 2713 return 0; /* Already scanned the entire slot */ 2714 2715 do { 2716 dev = pci_scan_single_device(bus, devfn + fn); 2717 if (dev) { 2718 if (!pci_dev_is_added(dev)) 2719 nr++; 2720 if (fn > 0) 2721 dev->multifunction = 1; 2722 } else if (fn == 0) { 2723 /* 2724 * Function 0 is required unless we are running on 2725 * a hypervisor that passes through individual PCI 2726 * functions. 2727 */ 2728 if (!hypervisor_isolated_pci_functions()) 2729 break; 2730 } 2731 fn = next_fn(bus, dev, fn); 2732 } while (fn >= 0); 2733 2734 /* Only one slot has PCIe device */ 2735 if (bus->self && nr) 2736 pcie_aspm_init_link_state(bus->self); 2737 2738 return nr; 2739 } 2740 EXPORT_SYMBOL(pci_scan_slot); 2741 2742 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2743 { 2744 u8 *smpss = data; 2745 2746 if (!pci_is_pcie(dev)) 2747 return 0; 2748 2749 /* 2750 * We don't have a way to change MPS settings on devices that have 2751 * drivers attached. A hot-added device might support only the minimum 2752 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2753 * where devices may be hot-added, we limit the fabric MPS to 128 so 2754 * hot-added devices will work correctly. 2755 * 2756 * However, if we hot-add a device to a slot directly below a Root 2757 * Port, it's impossible for there to be other existing devices below 2758 * the port. We don't limit the MPS in this case because we can 2759 * reconfigure MPS on both the Root Port and the hot-added device, 2760 * and there are no other devices involved. 2761 * 2762 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2763 */ 2764 if (dev->is_hotplug_bridge && 2765 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2766 *smpss = 0; 2767 2768 if (*smpss > dev->pcie_mpss) 2769 *smpss = dev->pcie_mpss; 2770 2771 return 0; 2772 } 2773 2774 static void pcie_write_mps(struct pci_dev *dev, int mps) 2775 { 2776 int rc; 2777 2778 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2779 mps = 128 << dev->pcie_mpss; 2780 2781 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2782 dev->bus->self) 2783 2784 /* 2785 * For "Performance", the assumption is made that 2786 * downstream communication will never be larger than 2787 * the MRRS. So, the MPS only needs to be configured 2788 * for the upstream communication. This being the case, 2789 * walk from the top down and set the MPS of the child 2790 * to that of the parent bus. 2791 * 2792 * Configure the device MPS with the smaller of the 2793 * device MPSS or the bridge MPS (which is assumed to be 2794 * properly configured at this point to the largest 2795 * allowable MPS based on its parent bus). 2796 */ 2797 mps = min(mps, pcie_get_mps(dev->bus->self)); 2798 } 2799 2800 rc = pcie_set_mps(dev, mps); 2801 if (rc) 2802 pci_err(dev, "Failed attempting to set the MPS\n"); 2803 } 2804 2805 static void pcie_write_mrrs(struct pci_dev *dev) 2806 { 2807 int rc, mrrs; 2808 2809 /* 2810 * In the "safe" case, do not configure the MRRS. There appear to be 2811 * issues with setting MRRS to 0 on a number of devices. 2812 */ 2813 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2814 return; 2815 2816 /* 2817 * For max performance, the MRRS must be set to the largest supported 2818 * value. However, it cannot be configured larger than the MPS the 2819 * device or the bus can support. This should already be properly 2820 * configured by a prior call to pcie_write_mps(). 2821 */ 2822 mrrs = pcie_get_mps(dev); 2823 2824 /* 2825 * MRRS is a R/W register. Invalid values can be written, but a 2826 * subsequent read will verify if the value is acceptable or not. 2827 * If the MRRS value provided is not acceptable (e.g., too large), 2828 * shrink the value until it is acceptable to the HW. 2829 */ 2830 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2831 rc = pcie_set_readrq(dev, mrrs); 2832 if (!rc) 2833 break; 2834 2835 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2836 mrrs /= 2; 2837 } 2838 2839 if (mrrs < 128) 2840 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2841 } 2842 2843 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2844 { 2845 int mps, orig_mps; 2846 2847 if (!pci_is_pcie(dev)) 2848 return 0; 2849 2850 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2851 pcie_bus_config == PCIE_BUS_DEFAULT) 2852 return 0; 2853 2854 mps = 128 << *(u8 *)data; 2855 orig_mps = pcie_get_mps(dev); 2856 2857 pcie_write_mps(dev, mps); 2858 pcie_write_mrrs(dev); 2859 2860 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2861 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2862 orig_mps, pcie_get_readrq(dev)); 2863 2864 return 0; 2865 } 2866 2867 /* 2868 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2869 * parents then children fashion. If this changes, then this code will not 2870 * work as designed. 2871 */ 2872 void pcie_bus_configure_settings(struct pci_bus *bus) 2873 { 2874 u8 smpss = 0; 2875 2876 if (!bus->self) 2877 return; 2878 2879 if (!pci_is_pcie(bus->self)) 2880 return; 2881 2882 /* 2883 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2884 * to be aware of the MPS of the destination. To work around this, 2885 * simply force the MPS of the entire system to the smallest possible. 2886 */ 2887 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2888 smpss = 0; 2889 2890 if (pcie_bus_config == PCIE_BUS_SAFE) { 2891 smpss = bus->self->pcie_mpss; 2892 2893 pcie_find_smpss(bus->self, &smpss); 2894 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2895 } 2896 2897 pcie_bus_configure_set(bus->self, &smpss); 2898 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2899 } 2900 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2901 2902 /* 2903 * Called after each bus is probed, but before its children are examined. This 2904 * is marked as __weak because multiple architectures define it. 2905 */ 2906 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2907 { 2908 /* nothing to do, expected to be removed in the future */ 2909 } 2910 2911 /** 2912 * pci_scan_child_bus_extend() - Scan devices below a bus 2913 * @bus: Bus to scan for devices 2914 * @available_buses: Total number of buses available (%0 does not try to 2915 * extend beyond the minimal) 2916 * 2917 * Scans devices below @bus including subordinate buses. Returns new 2918 * subordinate number including all the found devices. Passing 2919 * @available_buses causes the remaining bus space to be distributed 2920 * equally between hotplug-capable bridges to allow future extension of the 2921 * hierarchy. 2922 */ 2923 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2924 unsigned int available_buses) 2925 { 2926 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2927 unsigned int start = bus->busn_res.start; 2928 unsigned int devfn, cmax, max = start; 2929 struct pci_dev *dev; 2930 2931 dev_dbg(&bus->dev, "scanning bus\n"); 2932 2933 /* Go find them, Rover! */ 2934 for (devfn = 0; devfn < 256; devfn += 8) 2935 pci_scan_slot(bus, devfn); 2936 2937 /* Reserve buses for SR-IOV capability */ 2938 used_buses = pci_iov_bus_range(bus); 2939 max += used_buses; 2940 2941 /* 2942 * After performing arch-dependent fixup of the bus, look behind 2943 * all PCI-to-PCI bridges on this bus. 2944 */ 2945 if (!bus->is_added) { 2946 dev_dbg(&bus->dev, "fixups for bus\n"); 2947 pcibios_fixup_bus(bus); 2948 bus->is_added = 1; 2949 } 2950 2951 /* 2952 * Calculate how many hotplug bridges and normal bridges there 2953 * are on this bus. We will distribute the additional available 2954 * buses between hotplug bridges. 2955 */ 2956 for_each_pci_bridge(dev, bus) { 2957 if (dev->is_hotplug_bridge) 2958 hotplug_bridges++; 2959 else 2960 normal_bridges++; 2961 } 2962 2963 /* 2964 * Scan bridges that are already configured. We don't touch them 2965 * unless they are misconfigured (which will be done in the second 2966 * scan below). 2967 */ 2968 for_each_pci_bridge(dev, bus) { 2969 cmax = max; 2970 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2971 2972 /* 2973 * Reserve one bus for each bridge now to avoid extending 2974 * hotplug bridges too much during the second scan below. 2975 */ 2976 used_buses++; 2977 if (max - cmax > 1) 2978 used_buses += max - cmax - 1; 2979 } 2980 2981 /* Scan bridges that need to be reconfigured */ 2982 for_each_pci_bridge(dev, bus) { 2983 unsigned int buses = 0; 2984 2985 if (!hotplug_bridges && normal_bridges == 1) { 2986 /* 2987 * There is only one bridge on the bus (upstream 2988 * port) so it gets all available buses which it 2989 * can then distribute to the possible hotplug 2990 * bridges below. 2991 */ 2992 buses = available_buses; 2993 } else if (dev->is_hotplug_bridge) { 2994 /* 2995 * Distribute the extra buses between hotplug 2996 * bridges if any. 2997 */ 2998 buses = available_buses / hotplug_bridges; 2999 buses = min(buses, available_buses - used_buses + 1); 3000 } 3001 3002 cmax = max; 3003 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 3004 /* One bus is already accounted so don't add it again */ 3005 if (max - cmax > 1) 3006 used_buses += max - cmax - 1; 3007 } 3008 3009 /* 3010 * Make sure a hotplug bridge has at least the minimum requested 3011 * number of buses but allow it to grow up to the maximum available 3012 * bus number if there is room. 3013 */ 3014 if (bus->self && bus->self->is_hotplug_bridge) { 3015 used_buses = max_t(unsigned int, available_buses, 3016 pci_hotplug_bus_size - 1); 3017 if (max - start < used_buses) { 3018 max = start + used_buses; 3019 3020 /* Do not allocate more buses than we have room left */ 3021 if (max > bus->busn_res.end) 3022 max = bus->busn_res.end; 3023 3024 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 3025 &bus->busn_res, max - start); 3026 } 3027 } 3028 3029 /* 3030 * We've scanned the bus and so we know all about what's on 3031 * the other side of any bridges that may be on this bus plus 3032 * any devices. 3033 * 3034 * Return how far we've got finding sub-buses. 3035 */ 3036 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 3037 return max; 3038 } 3039 3040 /** 3041 * pci_scan_child_bus() - Scan devices below a bus 3042 * @bus: Bus to scan for devices 3043 * 3044 * Scans devices below @bus including subordinate buses. Returns new 3045 * subordinate number including all the found devices. 3046 */ 3047 unsigned int pci_scan_child_bus(struct pci_bus *bus) 3048 { 3049 return pci_scan_child_bus_extend(bus, 0); 3050 } 3051 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3052 3053 /** 3054 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3055 * @bridge: Host bridge to set up 3056 * 3057 * Default empty implementation. Replace with an architecture-specific setup 3058 * routine, if necessary. 3059 */ 3060 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3061 { 3062 return 0; 3063 } 3064 3065 void __weak pcibios_add_bus(struct pci_bus *bus) 3066 { 3067 } 3068 3069 void __weak pcibios_remove_bus(struct pci_bus *bus) 3070 { 3071 } 3072 3073 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3074 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3075 { 3076 int error; 3077 struct pci_host_bridge *bridge; 3078 3079 bridge = pci_alloc_host_bridge(0); 3080 if (!bridge) 3081 return NULL; 3082 3083 bridge->dev.parent = parent; 3084 3085 list_splice_init(resources, &bridge->windows); 3086 bridge->sysdata = sysdata; 3087 bridge->busnr = bus; 3088 bridge->ops = ops; 3089 3090 error = pci_register_host_bridge(bridge); 3091 if (error < 0) 3092 goto err_out; 3093 3094 return bridge->bus; 3095 3096 err_out: 3097 put_device(&bridge->dev); 3098 return NULL; 3099 } 3100 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3101 3102 int pci_host_probe(struct pci_host_bridge *bridge) 3103 { 3104 struct pci_bus *bus, *child; 3105 int ret; 3106 3107 pci_lock_rescan_remove(); 3108 ret = pci_scan_root_bus_bridge(bridge); 3109 pci_unlock_rescan_remove(); 3110 if (ret < 0) { 3111 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3112 return ret; 3113 } 3114 3115 bus = bridge->bus; 3116 3117 /* If we must preserve the resource configuration, claim now */ 3118 if (bridge->preserve_config) 3119 pci_bus_claim_resources(bus); 3120 3121 /* 3122 * Assign whatever was left unassigned. If we didn't claim above, 3123 * this will reassign everything. 3124 */ 3125 pci_assign_unassigned_root_bus_resources(bus); 3126 3127 list_for_each_entry(child, &bus->children, node) 3128 pcie_bus_configure_settings(child); 3129 3130 pci_lock_rescan_remove(); 3131 pci_bus_add_devices(bus); 3132 pci_unlock_rescan_remove(); 3133 3134 /* 3135 * Ensure pm_runtime_enable() is called for the controller drivers 3136 * before calling pci_host_probe(). The PM framework expects that 3137 * if the parent device supports runtime PM, it will be enabled 3138 * before child runtime PM is enabled. 3139 */ 3140 pm_runtime_set_active(&bridge->dev); 3141 pm_runtime_no_callbacks(&bridge->dev); 3142 devm_pm_runtime_enable(&bridge->dev); 3143 3144 return 0; 3145 } 3146 EXPORT_SYMBOL_GPL(pci_host_probe); 3147 3148 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3149 { 3150 struct resource *res = &b->busn_res; 3151 struct resource *parent_res, *conflict; 3152 3153 res->start = bus; 3154 res->end = bus_max; 3155 res->flags = IORESOURCE_BUS; 3156 3157 if (!pci_is_root_bus(b)) 3158 parent_res = &b->parent->busn_res; 3159 else { 3160 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3161 res->flags |= IORESOURCE_PCI_FIXED; 3162 } 3163 3164 conflict = request_resource_conflict(parent_res, res); 3165 3166 if (conflict) 3167 dev_info(&b->dev, 3168 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3169 res, pci_is_root_bus(b) ? "domain " : "", 3170 parent_res, conflict->name, conflict); 3171 3172 return conflict == NULL; 3173 } 3174 3175 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3176 { 3177 struct resource *res = &b->busn_res; 3178 struct resource old_res = *res; 3179 resource_size_t size; 3180 int ret; 3181 3182 if (res->start > bus_max) 3183 return -EINVAL; 3184 3185 size = bus_max - res->start + 1; 3186 ret = adjust_resource(res, res->start, size); 3187 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3188 &old_res, ret ? "can not be" : "is", bus_max); 3189 3190 if (!ret && !res->parent) 3191 pci_bus_insert_busn_res(b, res->start, res->end); 3192 3193 return ret; 3194 } 3195 3196 void pci_bus_release_busn_res(struct pci_bus *b) 3197 { 3198 struct resource *res = &b->busn_res; 3199 int ret; 3200 3201 if (!res->flags || !res->parent) 3202 return; 3203 3204 ret = release_resource(res); 3205 dev_info(&b->dev, "busn_res: %pR %s released\n", 3206 res, ret ? "can not be" : "is"); 3207 } 3208 3209 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3210 { 3211 struct resource_entry *window; 3212 bool found = false; 3213 struct pci_bus *b; 3214 int max, bus, ret; 3215 3216 if (!bridge) 3217 return -EINVAL; 3218 3219 resource_list_for_each_entry(window, &bridge->windows) 3220 if (window->res->flags & IORESOURCE_BUS) { 3221 bridge->busnr = window->res->start; 3222 found = true; 3223 break; 3224 } 3225 3226 ret = pci_register_host_bridge(bridge); 3227 if (ret < 0) 3228 return ret; 3229 3230 b = bridge->bus; 3231 bus = bridge->busnr; 3232 3233 if (!found) { 3234 dev_info(&b->dev, 3235 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3236 bus); 3237 pci_bus_insert_busn_res(b, bus, 255); 3238 } 3239 3240 max = pci_scan_child_bus(b); 3241 3242 if (!found) 3243 pci_bus_update_busn_res_end(b, max); 3244 3245 return 0; 3246 } 3247 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3248 3249 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3250 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3251 { 3252 struct resource_entry *window; 3253 bool found = false; 3254 struct pci_bus *b; 3255 int max; 3256 3257 resource_list_for_each_entry(window, resources) 3258 if (window->res->flags & IORESOURCE_BUS) { 3259 found = true; 3260 break; 3261 } 3262 3263 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3264 if (!b) 3265 return NULL; 3266 3267 if (!found) { 3268 dev_info(&b->dev, 3269 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3270 bus); 3271 pci_bus_insert_busn_res(b, bus, 255); 3272 } 3273 3274 max = pci_scan_child_bus(b); 3275 3276 if (!found) 3277 pci_bus_update_busn_res_end(b, max); 3278 3279 return b; 3280 } 3281 EXPORT_SYMBOL(pci_scan_root_bus); 3282 3283 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3284 void *sysdata) 3285 { 3286 LIST_HEAD(resources); 3287 struct pci_bus *b; 3288 3289 pci_add_resource(&resources, &ioport_resource); 3290 pci_add_resource(&resources, &iomem_resource); 3291 pci_add_resource(&resources, &busn_resource); 3292 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3293 if (b) { 3294 pci_scan_child_bus(b); 3295 } else { 3296 pci_free_resource_list(&resources); 3297 } 3298 return b; 3299 } 3300 EXPORT_SYMBOL(pci_scan_bus); 3301 3302 /** 3303 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3304 * @bridge: PCI bridge for the bus to scan 3305 * 3306 * Scan a PCI bus and child buses for new devices, add them, 3307 * and enable them, resizing bridge mmio/io resource if necessary 3308 * and possible. The caller must ensure the child devices are already 3309 * removed for resizing to occur. 3310 * 3311 * Returns the max number of subordinate bus discovered. 3312 */ 3313 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3314 { 3315 unsigned int max; 3316 struct pci_bus *bus = bridge->subordinate; 3317 3318 max = pci_scan_child_bus(bus); 3319 3320 pci_assign_unassigned_bridge_resources(bridge); 3321 3322 pci_bus_add_devices(bus); 3323 3324 return max; 3325 } 3326 3327 /** 3328 * pci_rescan_bus - Scan a PCI bus for devices 3329 * @bus: PCI bus to scan 3330 * 3331 * Scan a PCI bus and child buses for new devices, add them, 3332 * and enable them. 3333 * 3334 * Returns the max number of subordinate bus discovered. 3335 */ 3336 unsigned int pci_rescan_bus(struct pci_bus *bus) 3337 { 3338 unsigned int max; 3339 3340 max = pci_scan_child_bus(bus); 3341 pci_assign_unassigned_bus_resources(bus); 3342 pci_bus_add_devices(bus); 3343 3344 return max; 3345 } 3346 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3347 3348 /* 3349 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3350 * routines should always be executed under this mutex. 3351 */ 3352 static DEFINE_MUTEX(pci_rescan_remove_lock); 3353 3354 void pci_lock_rescan_remove(void) 3355 { 3356 mutex_lock(&pci_rescan_remove_lock); 3357 } 3358 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3359 3360 void pci_unlock_rescan_remove(void) 3361 { 3362 mutex_unlock(&pci_rescan_remove_lock); 3363 } 3364 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3365 3366 static int __init pci_sort_bf_cmp(const struct device *d_a, 3367 const struct device *d_b) 3368 { 3369 const struct pci_dev *a = to_pci_dev(d_a); 3370 const struct pci_dev *b = to_pci_dev(d_b); 3371 3372 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3373 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3374 3375 if (a->bus->number < b->bus->number) return -1; 3376 else if (a->bus->number > b->bus->number) return 1; 3377 3378 if (a->devfn < b->devfn) return -1; 3379 else if (a->devfn > b->devfn) return 1; 3380 3381 return 0; 3382 } 3383 3384 void __init pci_sort_breadthfirst(void) 3385 { 3386 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3387 } 3388 3389 int pci_hp_add_bridge(struct pci_dev *dev) 3390 { 3391 struct pci_bus *parent = dev->bus; 3392 int busnr, start = parent->busn_res.start; 3393 unsigned int available_buses = 0; 3394 int end = parent->busn_res.end; 3395 3396 for (busnr = start; busnr <= end; busnr++) { 3397 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3398 break; 3399 } 3400 if (busnr-- > end) { 3401 pci_err(dev, "No bus number available for hot-added bridge\n"); 3402 return -1; 3403 } 3404 3405 /* Scan bridges that are already configured */ 3406 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3407 3408 /* 3409 * Distribute the available bus numbers between hotplug-capable 3410 * bridges to make extending the chain later possible. 3411 */ 3412 available_buses = end - busnr; 3413 3414 /* Scan bridges that need to be reconfigured */ 3415 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3416 3417 if (!dev->subordinate) 3418 return -1; 3419 3420 return 0; 3421 } 3422 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3423