1 /* 2 * probe.c - PCI detection and setup code 3 */ 4 5 #include <linux/kernel.h> 6 #include <linux/delay.h> 7 #include <linux/init.h> 8 #include <linux/pci.h> 9 #include <linux/slab.h> 10 #include <linux/module.h> 11 #include <linux/cpumask.h> 12 #include <linux/pci-aspm.h> 13 #include "pci.h" 14 15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 16 #define CARDBUS_RESERVE_BUSNR 3 17 18 /* Ugh. Need to stop exporting this to modules. */ 19 LIST_HEAD(pci_root_buses); 20 EXPORT_SYMBOL(pci_root_buses); 21 22 23 static int find_anything(struct device *dev, void *data) 24 { 25 return 1; 26 } 27 28 /* 29 * Some device drivers need know if pci is initiated. 30 * Basically, we think pci is not initiated when there 31 * is no device to be found on the pci_bus_type. 32 */ 33 int no_pci_devices(void) 34 { 35 struct device *dev; 36 int no_devices; 37 38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); 39 no_devices = (dev == NULL); 40 put_device(dev); 41 return no_devices; 42 } 43 EXPORT_SYMBOL(no_pci_devices); 44 45 /* 46 * PCI Bus Class 47 */ 48 static void release_pcibus_dev(struct device *dev) 49 { 50 struct pci_bus *pci_bus = to_pci_bus(dev); 51 52 if (pci_bus->bridge) 53 put_device(pci_bus->bridge); 54 pci_bus_remove_resources(pci_bus); 55 pci_release_bus_of_node(pci_bus); 56 kfree(pci_bus); 57 } 58 59 static struct class pcibus_class = { 60 .name = "pci_bus", 61 .dev_release = &release_pcibus_dev, 62 .dev_attrs = pcibus_dev_attrs, 63 }; 64 65 static int __init pcibus_class_init(void) 66 { 67 return class_register(&pcibus_class); 68 } 69 postcore_initcall(pcibus_class_init); 70 71 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 72 { 73 u64 size = mask & maxbase; /* Find the significant bits */ 74 if (!size) 75 return 0; 76 77 /* Get the lowest of them to find the decode size, and 78 from that the extent. */ 79 size = (size & ~(size-1)) - 1; 80 81 /* base == maxbase can be valid only if the BAR has 82 already been programmed with all 1s. */ 83 if (base == maxbase && ((base | size) & mask) != mask) 84 return 0; 85 86 return size; 87 } 88 89 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 90 { 91 u32 mem_type; 92 unsigned long flags; 93 94 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 95 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 96 flags |= IORESOURCE_IO; 97 return flags; 98 } 99 100 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 101 flags |= IORESOURCE_MEM; 102 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 103 flags |= IORESOURCE_PREFETCH; 104 105 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 106 switch (mem_type) { 107 case PCI_BASE_ADDRESS_MEM_TYPE_32: 108 break; 109 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 110 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n"); 111 break; 112 case PCI_BASE_ADDRESS_MEM_TYPE_64: 113 flags |= IORESOURCE_MEM_64; 114 break; 115 default: 116 dev_warn(&dev->dev, 117 "mem unknown type %x treated as 32-bit BAR\n", 118 mem_type); 119 break; 120 } 121 return flags; 122 } 123 124 /** 125 * pci_read_base - read a PCI BAR 126 * @dev: the PCI device 127 * @type: type of the BAR 128 * @res: resource buffer to be filled in 129 * @pos: BAR position in the config space 130 * 131 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 132 */ 133 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 134 struct resource *res, unsigned int pos) 135 { 136 u32 l, sz, mask; 137 u16 orig_cmd; 138 139 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 140 141 if (!dev->mmio_always_on) { 142 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 143 pci_write_config_word(dev, PCI_COMMAND, 144 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); 145 } 146 147 res->name = pci_name(dev); 148 149 pci_read_config_dword(dev, pos, &l); 150 pci_write_config_dword(dev, pos, l | mask); 151 pci_read_config_dword(dev, pos, &sz); 152 pci_write_config_dword(dev, pos, l); 153 154 if (!dev->mmio_always_on) 155 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 156 157 /* 158 * All bits set in sz means the device isn't working properly. 159 * If the BAR isn't implemented, all bits must be 0. If it's a 160 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 161 * 1 must be clear. 162 */ 163 if (!sz || sz == 0xffffffff) 164 goto fail; 165 166 /* 167 * I don't know how l can have all bits set. Copied from old code. 168 * Maybe it fixes a bug on some ancient platform. 169 */ 170 if (l == 0xffffffff) 171 l = 0; 172 173 if (type == pci_bar_unknown) { 174 res->flags = decode_bar(dev, l); 175 res->flags |= IORESOURCE_SIZEALIGN; 176 if (res->flags & IORESOURCE_IO) { 177 l &= PCI_BASE_ADDRESS_IO_MASK; 178 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; 179 } else { 180 l &= PCI_BASE_ADDRESS_MEM_MASK; 181 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 182 } 183 } else { 184 res->flags |= (l & IORESOURCE_ROM_ENABLE); 185 l &= PCI_ROM_ADDRESS_MASK; 186 mask = (u32)PCI_ROM_ADDRESS_MASK; 187 } 188 189 if (res->flags & IORESOURCE_MEM_64) { 190 u64 l64 = l; 191 u64 sz64 = sz; 192 u64 mask64 = mask | (u64)~0 << 32; 193 194 pci_read_config_dword(dev, pos + 4, &l); 195 pci_write_config_dword(dev, pos + 4, ~0); 196 pci_read_config_dword(dev, pos + 4, &sz); 197 pci_write_config_dword(dev, pos + 4, l); 198 199 l64 |= ((u64)l << 32); 200 sz64 |= ((u64)sz << 32); 201 202 sz64 = pci_size(l64, sz64, mask64); 203 204 if (!sz64) 205 goto fail; 206 207 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 208 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", 209 pos); 210 goto fail; 211 } 212 213 if ((sizeof(resource_size_t) < 8) && l) { 214 /* Address above 32-bit boundary; disable the BAR */ 215 pci_write_config_dword(dev, pos, 0); 216 pci_write_config_dword(dev, pos + 4, 0); 217 res->start = 0; 218 res->end = sz64; 219 } else { 220 res->start = l64; 221 res->end = l64 + sz64; 222 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", 223 pos, res); 224 } 225 } else { 226 sz = pci_size(l, sz, mask); 227 228 if (!sz) 229 goto fail; 230 231 res->start = l; 232 res->end = l + sz; 233 234 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); 235 } 236 237 out: 238 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 239 fail: 240 res->flags = 0; 241 goto out; 242 } 243 244 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 245 { 246 unsigned int pos, reg; 247 248 for (pos = 0; pos < howmany; pos++) { 249 struct resource *res = &dev->resource[pos]; 250 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 251 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 252 } 253 254 if (rom) { 255 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 256 dev->rom_base_reg = rom; 257 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 258 IORESOURCE_READONLY | IORESOURCE_CACHEABLE | 259 IORESOURCE_SIZEALIGN; 260 __pci_read_base(dev, pci_bar_mem32, res, rom); 261 } 262 } 263 264 static void __devinit pci_read_bridge_io(struct pci_bus *child) 265 { 266 struct pci_dev *dev = child->self; 267 u8 io_base_lo, io_limit_lo; 268 unsigned long base, limit; 269 struct resource *res; 270 271 res = child->resource[0]; 272 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 273 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 274 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 275 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 276 277 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 278 u16 io_base_hi, io_limit_hi; 279 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 280 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 281 base |= (io_base_hi << 16); 282 limit |= (io_limit_hi << 16); 283 } 284 285 if (base && base <= limit) { 286 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 287 if (!res->start) 288 res->start = base; 289 if (!res->end) 290 res->end = limit + 0xfff; 291 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 292 } 293 } 294 295 static void __devinit pci_read_bridge_mmio(struct pci_bus *child) 296 { 297 struct pci_dev *dev = child->self; 298 u16 mem_base_lo, mem_limit_lo; 299 unsigned long base, limit; 300 struct resource *res; 301 302 res = child->resource[1]; 303 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 304 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 305 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 306 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 307 if (base && base <= limit) { 308 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 309 res->start = base; 310 res->end = limit + 0xfffff; 311 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 312 } 313 } 314 315 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) 316 { 317 struct pci_dev *dev = child->self; 318 u16 mem_base_lo, mem_limit_lo; 319 unsigned long base, limit; 320 struct resource *res; 321 322 res = child->resource[2]; 323 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 324 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 325 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 326 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 327 328 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 329 u32 mem_base_hi, mem_limit_hi; 330 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 331 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 332 333 /* 334 * Some bridges set the base > limit by default, and some 335 * (broken) BIOSes do not initialize them. If we find 336 * this, just assume they are not being used. 337 */ 338 if (mem_base_hi <= mem_limit_hi) { 339 #if BITS_PER_LONG == 64 340 base |= ((long) mem_base_hi) << 32; 341 limit |= ((long) mem_limit_hi) << 32; 342 #else 343 if (mem_base_hi || mem_limit_hi) { 344 dev_err(&dev->dev, "can't handle 64-bit " 345 "address space for bridge\n"); 346 return; 347 } 348 #endif 349 } 350 } 351 if (base && base <= limit) { 352 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 353 IORESOURCE_MEM | IORESOURCE_PREFETCH; 354 if (res->flags & PCI_PREF_RANGE_TYPE_64) 355 res->flags |= IORESOURCE_MEM_64; 356 res->start = base; 357 res->end = limit + 0xfffff; 358 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 359 } 360 } 361 362 void __devinit pci_read_bridge_bases(struct pci_bus *child) 363 { 364 struct pci_dev *dev = child->self; 365 struct resource *res; 366 int i; 367 368 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 369 return; 370 371 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", 372 child->secondary, child->subordinate, 373 dev->transparent ? " (subtractive decode)" : ""); 374 375 pci_bus_remove_resources(child); 376 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 377 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 378 379 pci_read_bridge_io(child); 380 pci_read_bridge_mmio(child); 381 pci_read_bridge_mmio_pref(child); 382 383 if (dev->transparent) { 384 pci_bus_for_each_resource(child->parent, res, i) { 385 if (res) { 386 pci_bus_add_resource(child, res, 387 PCI_SUBTRACTIVE_DECODE); 388 dev_printk(KERN_DEBUG, &dev->dev, 389 " bridge window %pR (subtractive decode)\n", 390 res); 391 } 392 } 393 } 394 } 395 396 static struct pci_bus * pci_alloc_bus(void) 397 { 398 struct pci_bus *b; 399 400 b = kzalloc(sizeof(*b), GFP_KERNEL); 401 if (b) { 402 INIT_LIST_HEAD(&b->node); 403 INIT_LIST_HEAD(&b->children); 404 INIT_LIST_HEAD(&b->devices); 405 INIT_LIST_HEAD(&b->slots); 406 INIT_LIST_HEAD(&b->resources); 407 b->max_bus_speed = PCI_SPEED_UNKNOWN; 408 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 409 } 410 return b; 411 } 412 413 static unsigned char pcix_bus_speed[] = { 414 PCI_SPEED_UNKNOWN, /* 0 */ 415 PCI_SPEED_66MHz_PCIX, /* 1 */ 416 PCI_SPEED_100MHz_PCIX, /* 2 */ 417 PCI_SPEED_133MHz_PCIX, /* 3 */ 418 PCI_SPEED_UNKNOWN, /* 4 */ 419 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 420 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 421 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 422 PCI_SPEED_UNKNOWN, /* 8 */ 423 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 424 PCI_SPEED_100MHz_PCIX_266, /* A */ 425 PCI_SPEED_133MHz_PCIX_266, /* B */ 426 PCI_SPEED_UNKNOWN, /* C */ 427 PCI_SPEED_66MHz_PCIX_533, /* D */ 428 PCI_SPEED_100MHz_PCIX_533, /* E */ 429 PCI_SPEED_133MHz_PCIX_533 /* F */ 430 }; 431 432 static unsigned char pcie_link_speed[] = { 433 PCI_SPEED_UNKNOWN, /* 0 */ 434 PCIE_SPEED_2_5GT, /* 1 */ 435 PCIE_SPEED_5_0GT, /* 2 */ 436 PCIE_SPEED_8_0GT, /* 3 */ 437 PCI_SPEED_UNKNOWN, /* 4 */ 438 PCI_SPEED_UNKNOWN, /* 5 */ 439 PCI_SPEED_UNKNOWN, /* 6 */ 440 PCI_SPEED_UNKNOWN, /* 7 */ 441 PCI_SPEED_UNKNOWN, /* 8 */ 442 PCI_SPEED_UNKNOWN, /* 9 */ 443 PCI_SPEED_UNKNOWN, /* A */ 444 PCI_SPEED_UNKNOWN, /* B */ 445 PCI_SPEED_UNKNOWN, /* C */ 446 PCI_SPEED_UNKNOWN, /* D */ 447 PCI_SPEED_UNKNOWN, /* E */ 448 PCI_SPEED_UNKNOWN /* F */ 449 }; 450 451 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 452 { 453 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; 454 } 455 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 456 457 static unsigned char agp_speeds[] = { 458 AGP_UNKNOWN, 459 AGP_1X, 460 AGP_2X, 461 AGP_4X, 462 AGP_8X 463 }; 464 465 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 466 { 467 int index = 0; 468 469 if (agpstat & 4) 470 index = 3; 471 else if (agpstat & 2) 472 index = 2; 473 else if (agpstat & 1) 474 index = 1; 475 else 476 goto out; 477 478 if (agp3) { 479 index += 2; 480 if (index == 5) 481 index = 0; 482 } 483 484 out: 485 return agp_speeds[index]; 486 } 487 488 489 static void pci_set_bus_speed(struct pci_bus *bus) 490 { 491 struct pci_dev *bridge = bus->self; 492 int pos; 493 494 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 495 if (!pos) 496 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 497 if (pos) { 498 u32 agpstat, agpcmd; 499 500 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 501 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 502 503 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 504 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 505 } 506 507 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 508 if (pos) { 509 u16 status; 510 enum pci_bus_speed max; 511 pci_read_config_word(bridge, pos + 2, &status); 512 513 if (status & 0x8000) { 514 max = PCI_SPEED_133MHz_PCIX_533; 515 } else if (status & 0x4000) { 516 max = PCI_SPEED_133MHz_PCIX_266; 517 } else if (status & 0x0002) { 518 if (((status >> 12) & 0x3) == 2) { 519 max = PCI_SPEED_133MHz_PCIX_ECC; 520 } else { 521 max = PCI_SPEED_133MHz_PCIX; 522 } 523 } else { 524 max = PCI_SPEED_66MHz_PCIX; 525 } 526 527 bus->max_bus_speed = max; 528 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; 529 530 return; 531 } 532 533 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); 534 if (pos) { 535 u32 linkcap; 536 u16 linksta; 537 538 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); 539 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; 540 541 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); 542 pcie_update_link_speed(bus, linksta); 543 } 544 } 545 546 547 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 548 struct pci_dev *bridge, int busnr) 549 { 550 struct pci_bus *child; 551 int i; 552 553 /* 554 * Allocate a new bus, and inherit stuff from the parent.. 555 */ 556 child = pci_alloc_bus(); 557 if (!child) 558 return NULL; 559 560 child->parent = parent; 561 child->ops = parent->ops; 562 child->sysdata = parent->sysdata; 563 child->bus_flags = parent->bus_flags; 564 565 /* initialize some portions of the bus device, but don't register it 566 * now as the parent is not properly set up yet. This device will get 567 * registered later in pci_bus_add_devices() 568 */ 569 child->dev.class = &pcibus_class; 570 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 571 572 /* 573 * Set up the primary, secondary and subordinate 574 * bus numbers. 575 */ 576 child->number = child->secondary = busnr; 577 child->primary = parent->secondary; 578 child->subordinate = 0xff; 579 580 if (!bridge) 581 return child; 582 583 child->self = bridge; 584 child->bridge = get_device(&bridge->dev); 585 pci_set_bus_of_node(child); 586 pci_set_bus_speed(child); 587 588 /* Set up default resource pointers and names.. */ 589 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 590 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 591 child->resource[i]->name = child->name; 592 } 593 bridge->subordinate = child; 594 595 return child; 596 } 597 598 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) 599 { 600 struct pci_bus *child; 601 602 child = pci_alloc_child_bus(parent, dev, busnr); 603 if (child) { 604 down_write(&pci_bus_sem); 605 list_add_tail(&child->node, &parent->children); 606 up_write(&pci_bus_sem); 607 } 608 return child; 609 } 610 611 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) 612 { 613 struct pci_bus *parent = child->parent; 614 615 /* Attempts to fix that up are really dangerous unless 616 we're going to re-assign all bus numbers. */ 617 if (!pcibios_assign_all_busses()) 618 return; 619 620 while (parent->parent && parent->subordinate < max) { 621 parent->subordinate = max; 622 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); 623 parent = parent->parent; 624 } 625 } 626 627 /* 628 * If it's a bridge, configure it and scan the bus behind it. 629 * For CardBus bridges, we don't scan behind as the devices will 630 * be handled by the bridge driver itself. 631 * 632 * We need to process bridges in two passes -- first we scan those 633 * already configured by the BIOS and after we are done with all of 634 * them, we proceed to assigning numbers to the remaining buses in 635 * order to avoid overlaps between old and new bus numbers. 636 */ 637 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 638 { 639 struct pci_bus *child; 640 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 641 u32 buses, i, j = 0; 642 u16 bctl; 643 u8 primary, secondary, subordinate; 644 int broken = 0; 645 646 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 647 primary = buses & 0xFF; 648 secondary = (buses >> 8) & 0xFF; 649 subordinate = (buses >> 16) & 0xFF; 650 651 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 652 secondary, subordinate, pass); 653 654 /* Check if setup is sensible at all */ 655 if (!pass && 656 (primary != bus->number || secondary <= bus->number)) { 657 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); 658 broken = 1; 659 } 660 661 /* Disable MasterAbortMode during probing to avoid reporting 662 of bus errors (in some architectures) */ 663 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 664 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 665 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 666 667 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 668 !is_cardbus && !broken) { 669 unsigned int cmax; 670 /* 671 * Bus already configured by firmware, process it in the first 672 * pass and just note the configuration. 673 */ 674 if (pass) 675 goto out; 676 677 /* 678 * If we already got to this bus through a different bridge, 679 * don't re-add it. This can happen with the i450NX chipset. 680 * 681 * However, we continue to descend down the hierarchy and 682 * scan remaining child buses. 683 */ 684 child = pci_find_bus(pci_domain_nr(bus), secondary); 685 if (!child) { 686 child = pci_add_new_bus(bus, dev, secondary); 687 if (!child) 688 goto out; 689 child->primary = primary; 690 child->subordinate = subordinate; 691 child->bridge_ctl = bctl; 692 } 693 694 cmax = pci_scan_child_bus(child); 695 if (cmax > max) 696 max = cmax; 697 if (child->subordinate > max) 698 max = child->subordinate; 699 } else { 700 /* 701 * We need to assign a number to this bus which we always 702 * do in the second pass. 703 */ 704 if (!pass) { 705 if (pcibios_assign_all_busses() || broken) 706 /* Temporarily disable forwarding of the 707 configuration cycles on all bridges in 708 this bus segment to avoid possible 709 conflicts in the second pass between two 710 bridges programmed with overlapping 711 bus ranges. */ 712 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 713 buses & ~0xffffff); 714 goto out; 715 } 716 717 /* Clear errors */ 718 pci_write_config_word(dev, PCI_STATUS, 0xffff); 719 720 /* Prevent assigning a bus number that already exists. 721 * This can happen when a bridge is hot-plugged, so in 722 * this case we only re-scan this bus. */ 723 child = pci_find_bus(pci_domain_nr(bus), max+1); 724 if (!child) { 725 child = pci_add_new_bus(bus, dev, ++max); 726 if (!child) 727 goto out; 728 } 729 buses = (buses & 0xff000000) 730 | ((unsigned int)(child->primary) << 0) 731 | ((unsigned int)(child->secondary) << 8) 732 | ((unsigned int)(child->subordinate) << 16); 733 734 /* 735 * yenta.c forces a secondary latency timer of 176. 736 * Copy that behaviour here. 737 */ 738 if (is_cardbus) { 739 buses &= ~0xff000000; 740 buses |= CARDBUS_LATENCY_TIMER << 24; 741 } 742 743 /* 744 * We need to blast all three values with a single write. 745 */ 746 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 747 748 if (!is_cardbus) { 749 child->bridge_ctl = bctl; 750 /* 751 * Adjust subordinate busnr in parent buses. 752 * We do this before scanning for children because 753 * some devices may not be detected if the bios 754 * was lazy. 755 */ 756 pci_fixup_parent_subordinate_busnr(child, max); 757 /* Now we can scan all subordinate buses... */ 758 max = pci_scan_child_bus(child); 759 /* 760 * now fix it up again since we have found 761 * the real value of max. 762 */ 763 pci_fixup_parent_subordinate_busnr(child, max); 764 } else { 765 /* 766 * For CardBus bridges, we leave 4 bus numbers 767 * as cards with a PCI-to-PCI bridge can be 768 * inserted later. 769 */ 770 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { 771 struct pci_bus *parent = bus; 772 if (pci_find_bus(pci_domain_nr(bus), 773 max+i+1)) 774 break; 775 while (parent->parent) { 776 if ((!pcibios_assign_all_busses()) && 777 (parent->subordinate > max) && 778 (parent->subordinate <= max+i)) { 779 j = 1; 780 } 781 parent = parent->parent; 782 } 783 if (j) { 784 /* 785 * Often, there are two cardbus bridges 786 * -- try to leave one valid bus number 787 * for each one. 788 */ 789 i /= 2; 790 break; 791 } 792 } 793 max += i; 794 pci_fixup_parent_subordinate_busnr(child, max); 795 } 796 /* 797 * Set the subordinate bus number to its real value. 798 */ 799 child->subordinate = max; 800 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 801 } 802 803 sprintf(child->name, 804 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 805 pci_domain_nr(bus), child->number); 806 807 /* Has only triggered on CardBus, fixup is in yenta_socket */ 808 while (bus->parent) { 809 if ((child->subordinate > bus->subordinate) || 810 (child->number > bus->subordinate) || 811 (child->number < bus->number) || 812 (child->subordinate < bus->number)) { 813 dev_info(&child->dev, "[bus %02x-%02x] %s " 814 "hidden behind%s bridge %s [bus %02x-%02x]\n", 815 child->number, child->subordinate, 816 (bus->number > child->subordinate && 817 bus->subordinate < child->number) ? 818 "wholly" : "partially", 819 bus->self->transparent ? " transparent" : "", 820 dev_name(&bus->dev), 821 bus->number, bus->subordinate); 822 } 823 bus = bus->parent; 824 } 825 826 out: 827 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 828 829 return max; 830 } 831 832 /* 833 * Read interrupt line and base address registers. 834 * The architecture-dependent code can tweak these, of course. 835 */ 836 static void pci_read_irq(struct pci_dev *dev) 837 { 838 unsigned char irq; 839 840 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 841 dev->pin = irq; 842 if (irq) 843 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 844 dev->irq = irq; 845 } 846 847 void set_pcie_port_type(struct pci_dev *pdev) 848 { 849 int pos; 850 u16 reg16; 851 852 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 853 if (!pos) 854 return; 855 pdev->is_pcie = 1; 856 pdev->pcie_cap = pos; 857 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 858 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; 859 } 860 861 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 862 { 863 int pos; 864 u16 reg16; 865 u32 reg32; 866 867 pos = pci_pcie_cap(pdev); 868 if (!pos) 869 return; 870 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 871 if (!(reg16 & PCI_EXP_FLAGS_SLOT)) 872 return; 873 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); 874 if (reg32 & PCI_EXP_SLTCAP_HPC) 875 pdev->is_hotplug_bridge = 1; 876 } 877 878 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 879 880 /** 881 * pci_setup_device - fill in class and map information of a device 882 * @dev: the device structure to fill 883 * 884 * Initialize the device structure with information about the device's 885 * vendor,class,memory and IO-space addresses,IRQ lines etc. 886 * Called at initialisation of the PCI subsystem and by CardBus services. 887 * Returns 0 on success and negative if unknown type of device (not normal, 888 * bridge or CardBus). 889 */ 890 int pci_setup_device(struct pci_dev *dev) 891 { 892 u32 class; 893 u8 hdr_type; 894 struct pci_slot *slot; 895 int pos = 0; 896 897 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) 898 return -EIO; 899 900 dev->sysdata = dev->bus->sysdata; 901 dev->dev.parent = dev->bus->bridge; 902 dev->dev.bus = &pci_bus_type; 903 dev->hdr_type = hdr_type & 0x7f; 904 dev->multifunction = !!(hdr_type & 0x80); 905 dev->error_state = pci_channel_io_normal; 906 set_pcie_port_type(dev); 907 908 list_for_each_entry(slot, &dev->bus->slots, list) 909 if (PCI_SLOT(dev->devfn) == slot->number) 910 dev->slot = slot; 911 912 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 913 set this higher, assuming the system even supports it. */ 914 dev->dma_mask = 0xffffffff; 915 916 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 917 dev->bus->number, PCI_SLOT(dev->devfn), 918 PCI_FUNC(dev->devfn)); 919 920 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 921 dev->revision = class & 0xff; 922 class >>= 8; /* upper 3 bytes */ 923 dev->class = class; 924 class >>= 8; 925 926 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n", 927 dev->vendor, dev->device, dev->hdr_type, class); 928 929 /* need to have dev->class ready */ 930 dev->cfg_size = pci_cfg_space_size(dev); 931 932 /* "Unknown power state" */ 933 dev->current_state = PCI_UNKNOWN; 934 935 /* Early fixups, before probing the BARs */ 936 pci_fixup_device(pci_fixup_early, dev); 937 /* device class may be changed after fixup */ 938 class = dev->class >> 8; 939 940 switch (dev->hdr_type) { /* header type */ 941 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 942 if (class == PCI_CLASS_BRIDGE_PCI) 943 goto bad; 944 pci_read_irq(dev); 945 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 946 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 947 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); 948 949 /* 950 * Do the ugly legacy mode stuff here rather than broken chip 951 * quirk code. Legacy mode ATA controllers have fixed 952 * addresses. These are not always echoed in BAR0-3, and 953 * BAR0-3 in a few cases contain junk! 954 */ 955 if (class == PCI_CLASS_STORAGE_IDE) { 956 u8 progif; 957 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 958 if ((progif & 1) == 0) { 959 dev->resource[0].start = 0x1F0; 960 dev->resource[0].end = 0x1F7; 961 dev->resource[0].flags = LEGACY_IO_RESOURCE; 962 dev->resource[1].start = 0x3F6; 963 dev->resource[1].end = 0x3F6; 964 dev->resource[1].flags = LEGACY_IO_RESOURCE; 965 } 966 if ((progif & 4) == 0) { 967 dev->resource[2].start = 0x170; 968 dev->resource[2].end = 0x177; 969 dev->resource[2].flags = LEGACY_IO_RESOURCE; 970 dev->resource[3].start = 0x376; 971 dev->resource[3].end = 0x376; 972 dev->resource[3].flags = LEGACY_IO_RESOURCE; 973 } 974 } 975 break; 976 977 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 978 if (class != PCI_CLASS_BRIDGE_PCI) 979 goto bad; 980 /* The PCI-to-PCI bridge spec requires that subtractive 981 decoding (i.e. transparent) bridge must have programming 982 interface code of 0x01. */ 983 pci_read_irq(dev); 984 dev->transparent = ((dev->class & 0xff) == 1); 985 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 986 set_pcie_hotplug_bridge(dev); 987 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 988 if (pos) { 989 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 990 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 991 } 992 break; 993 994 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 995 if (class != PCI_CLASS_BRIDGE_CARDBUS) 996 goto bad; 997 pci_read_irq(dev); 998 pci_read_bases(dev, 1, 0); 999 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1000 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1001 break; 1002 1003 default: /* unknown header */ 1004 dev_err(&dev->dev, "unknown header type %02x, " 1005 "ignoring device\n", dev->hdr_type); 1006 return -EIO; 1007 1008 bad: 1009 dev_err(&dev->dev, "ignoring class %02x (doesn't match header " 1010 "type %02x)\n", class, dev->hdr_type); 1011 dev->class = PCI_CLASS_NOT_DEFINED; 1012 } 1013 1014 /* We found a fine healthy device, go go go... */ 1015 return 0; 1016 } 1017 1018 static void pci_release_capabilities(struct pci_dev *dev) 1019 { 1020 pci_vpd_release(dev); 1021 pci_iov_release(dev); 1022 } 1023 1024 /** 1025 * pci_release_dev - free a pci device structure when all users of it are finished. 1026 * @dev: device that's been disconnected 1027 * 1028 * Will be called only by the device core when all users of this pci device are 1029 * done. 1030 */ 1031 static void pci_release_dev(struct device *dev) 1032 { 1033 struct pci_dev *pci_dev; 1034 1035 pci_dev = to_pci_dev(dev); 1036 pci_release_capabilities(pci_dev); 1037 pci_release_of_node(pci_dev); 1038 kfree(pci_dev); 1039 } 1040 1041 /** 1042 * pci_cfg_space_size - get the configuration space size of the PCI device. 1043 * @dev: PCI device 1044 * 1045 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1046 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1047 * access it. Maybe we don't have a way to generate extended config space 1048 * accesses, or the device is behind a reverse Express bridge. So we try 1049 * reading the dword at 0x100 which must either be 0 or a valid extended 1050 * capability header. 1051 */ 1052 int pci_cfg_space_size_ext(struct pci_dev *dev) 1053 { 1054 u32 status; 1055 int pos = PCI_CFG_SPACE_SIZE; 1056 1057 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1058 goto fail; 1059 if (status == 0xffffffff) 1060 goto fail; 1061 1062 return PCI_CFG_SPACE_EXP_SIZE; 1063 1064 fail: 1065 return PCI_CFG_SPACE_SIZE; 1066 } 1067 1068 int pci_cfg_space_size(struct pci_dev *dev) 1069 { 1070 int pos; 1071 u32 status; 1072 u16 class; 1073 1074 class = dev->class >> 8; 1075 if (class == PCI_CLASS_BRIDGE_HOST) 1076 return pci_cfg_space_size_ext(dev); 1077 1078 pos = pci_pcie_cap(dev); 1079 if (!pos) { 1080 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1081 if (!pos) 1082 goto fail; 1083 1084 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1085 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) 1086 goto fail; 1087 } 1088 1089 return pci_cfg_space_size_ext(dev); 1090 1091 fail: 1092 return PCI_CFG_SPACE_SIZE; 1093 } 1094 1095 static void pci_release_bus_bridge_dev(struct device *dev) 1096 { 1097 kfree(dev); 1098 } 1099 1100 struct pci_dev *alloc_pci_dev(void) 1101 { 1102 struct pci_dev *dev; 1103 1104 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 1105 if (!dev) 1106 return NULL; 1107 1108 INIT_LIST_HEAD(&dev->bus_list); 1109 1110 return dev; 1111 } 1112 EXPORT_SYMBOL(alloc_pci_dev); 1113 1114 /* 1115 * Read the config data for a PCI device, sanity-check it 1116 * and fill in the dev structure... 1117 */ 1118 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 1119 { 1120 struct pci_dev *dev; 1121 u32 l; 1122 int delay = 1; 1123 1124 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 1125 return NULL; 1126 1127 /* some broken boards return 0 or ~0 if a slot is empty: */ 1128 if (l == 0xffffffff || l == 0x00000000 || 1129 l == 0x0000ffff || l == 0xffff0000) 1130 return NULL; 1131 1132 /* Configuration request Retry Status */ 1133 while (l == 0xffff0001) { 1134 msleep(delay); 1135 delay *= 2; 1136 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 1137 return NULL; 1138 /* Card hasn't responded in 60 seconds? Must be stuck. */ 1139 if (delay > 60 * 1000) { 1140 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " 1141 "responding\n", pci_domain_nr(bus), 1142 bus->number, PCI_SLOT(devfn), 1143 PCI_FUNC(devfn)); 1144 return NULL; 1145 } 1146 } 1147 1148 dev = alloc_pci_dev(); 1149 if (!dev) 1150 return NULL; 1151 1152 dev->bus = bus; 1153 dev->devfn = devfn; 1154 dev->vendor = l & 0xffff; 1155 dev->device = (l >> 16) & 0xffff; 1156 1157 pci_set_of_node(dev); 1158 1159 if (pci_setup_device(dev)) { 1160 kfree(dev); 1161 return NULL; 1162 } 1163 1164 return dev; 1165 } 1166 1167 static void pci_init_capabilities(struct pci_dev *dev) 1168 { 1169 /* MSI/MSI-X list */ 1170 pci_msi_init_pci_dev(dev); 1171 1172 /* Buffers for saving PCIe and PCI-X capabilities */ 1173 pci_allocate_cap_save_buffers(dev); 1174 1175 /* Power Management */ 1176 pci_pm_init(dev); 1177 platform_pci_wakeup_init(dev); 1178 1179 /* Vital Product Data */ 1180 pci_vpd_pci22_init(dev); 1181 1182 /* Alternative Routing-ID Forwarding */ 1183 pci_enable_ari(dev); 1184 1185 /* Single Root I/O Virtualization */ 1186 pci_iov_init(dev); 1187 1188 /* Enable ACS P2P upstream forwarding */ 1189 pci_enable_acs(dev); 1190 } 1191 1192 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 1193 { 1194 device_initialize(&dev->dev); 1195 dev->dev.release = pci_release_dev; 1196 pci_dev_get(dev); 1197 1198 dev->dev.dma_mask = &dev->dma_mask; 1199 dev->dev.dma_parms = &dev->dma_parms; 1200 dev->dev.coherent_dma_mask = 0xffffffffull; 1201 1202 pci_set_dma_max_seg_size(dev, 65536); 1203 pci_set_dma_seg_boundary(dev, 0xffffffff); 1204 1205 /* Fix up broken headers */ 1206 pci_fixup_device(pci_fixup_header, dev); 1207 1208 /* Clear the state_saved flag. */ 1209 dev->state_saved = false; 1210 1211 /* Initialize various capabilities */ 1212 pci_init_capabilities(dev); 1213 1214 /* 1215 * Add the device to our list of discovered devices 1216 * and the bus list for fixup functions, etc. 1217 */ 1218 down_write(&pci_bus_sem); 1219 list_add_tail(&dev->bus_list, &bus->devices); 1220 up_write(&pci_bus_sem); 1221 } 1222 1223 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) 1224 { 1225 struct pci_dev *dev; 1226 1227 dev = pci_get_slot(bus, devfn); 1228 if (dev) { 1229 pci_dev_put(dev); 1230 return dev; 1231 } 1232 1233 dev = pci_scan_device(bus, devfn); 1234 if (!dev) 1235 return NULL; 1236 1237 pci_device_add(dev, bus); 1238 1239 return dev; 1240 } 1241 EXPORT_SYMBOL(pci_scan_single_device); 1242 1243 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn) 1244 { 1245 u16 cap; 1246 unsigned pos, next_fn; 1247 1248 if (!dev) 1249 return 0; 1250 1251 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 1252 if (!pos) 1253 return 0; 1254 pci_read_config_word(dev, pos + 4, &cap); 1255 next_fn = cap >> 8; 1256 if (next_fn <= fn) 1257 return 0; 1258 return next_fn; 1259 } 1260 1261 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn) 1262 { 1263 return (fn + 1) % 8; 1264 } 1265 1266 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn) 1267 { 1268 return 0; 1269 } 1270 1271 static int only_one_child(struct pci_bus *bus) 1272 { 1273 struct pci_dev *parent = bus->self; 1274 if (!parent || !pci_is_pcie(parent)) 1275 return 0; 1276 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT || 1277 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) 1278 return 1; 1279 return 0; 1280 } 1281 1282 /** 1283 * pci_scan_slot - scan a PCI slot on a bus for devices. 1284 * @bus: PCI bus to scan 1285 * @devfn: slot number to scan (must have zero function.) 1286 * 1287 * Scan a PCI slot on the specified PCI bus for devices, adding 1288 * discovered devices to the @bus->devices list. New devices 1289 * will not have is_added set. 1290 * 1291 * Returns the number of new devices found. 1292 */ 1293 int pci_scan_slot(struct pci_bus *bus, int devfn) 1294 { 1295 unsigned fn, nr = 0; 1296 struct pci_dev *dev; 1297 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn; 1298 1299 if (only_one_child(bus) && (devfn > 0)) 1300 return 0; /* Already scanned the entire slot */ 1301 1302 dev = pci_scan_single_device(bus, devfn); 1303 if (!dev) 1304 return 0; 1305 if (!dev->is_added) 1306 nr++; 1307 1308 if (pci_ari_enabled(bus)) 1309 next_fn = next_ari_fn; 1310 else if (dev->multifunction) 1311 next_fn = next_trad_fn; 1312 1313 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) { 1314 dev = pci_scan_single_device(bus, devfn + fn); 1315 if (dev) { 1316 if (!dev->is_added) 1317 nr++; 1318 dev->multifunction = 1; 1319 } 1320 } 1321 1322 /* only one slot has pcie device */ 1323 if (bus->self && nr) 1324 pcie_aspm_init_link_state(bus->self); 1325 1326 return nr; 1327 } 1328 1329 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) 1330 { 1331 unsigned int devfn, pass, max = bus->secondary; 1332 struct pci_dev *dev; 1333 1334 dev_dbg(&bus->dev, "scanning bus\n"); 1335 1336 /* Go find them, Rover! */ 1337 for (devfn = 0; devfn < 0x100; devfn += 8) 1338 pci_scan_slot(bus, devfn); 1339 1340 /* Reserve buses for SR-IOV capability. */ 1341 max += pci_iov_bus_range(bus); 1342 1343 /* 1344 * After performing arch-dependent fixup of the bus, look behind 1345 * all PCI-to-PCI bridges on this bus. 1346 */ 1347 if (!bus->is_added) { 1348 dev_dbg(&bus->dev, "fixups for bus\n"); 1349 pcibios_fixup_bus(bus); 1350 if (pci_is_root_bus(bus)) 1351 bus->is_added = 1; 1352 } 1353 1354 for (pass=0; pass < 2; pass++) 1355 list_for_each_entry(dev, &bus->devices, bus_list) { 1356 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1357 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1358 max = pci_scan_bridge(bus, dev, max, pass); 1359 } 1360 1361 /* 1362 * We've scanned the bus and so we know all about what's on 1363 * the other side of any bridges that may be on this bus plus 1364 * any devices. 1365 * 1366 * Return how far we've got finding sub-buses. 1367 */ 1368 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 1369 return max; 1370 } 1371 1372 struct pci_bus * pci_create_bus(struct device *parent, 1373 int bus, struct pci_ops *ops, void *sysdata) 1374 { 1375 int error; 1376 struct pci_bus *b, *b2; 1377 struct device *dev; 1378 1379 b = pci_alloc_bus(); 1380 if (!b) 1381 return NULL; 1382 1383 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1384 if (!dev){ 1385 kfree(b); 1386 return NULL; 1387 } 1388 1389 b->sysdata = sysdata; 1390 b->ops = ops; 1391 1392 b2 = pci_find_bus(pci_domain_nr(b), bus); 1393 if (b2) { 1394 /* If we already got to this bus through a different bridge, ignore it */ 1395 dev_dbg(&b2->dev, "bus already known\n"); 1396 goto err_out; 1397 } 1398 1399 down_write(&pci_bus_sem); 1400 list_add_tail(&b->node, &pci_root_buses); 1401 up_write(&pci_bus_sem); 1402 1403 dev->parent = parent; 1404 dev->release = pci_release_bus_bridge_dev; 1405 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); 1406 error = device_register(dev); 1407 if (error) 1408 goto dev_reg_err; 1409 b->bridge = get_device(dev); 1410 device_enable_async_suspend(b->bridge); 1411 pci_set_bus_of_node(b); 1412 1413 if (!parent) 1414 set_dev_node(b->bridge, pcibus_to_node(b)); 1415 1416 b->dev.class = &pcibus_class; 1417 b->dev.parent = b->bridge; 1418 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); 1419 error = device_register(&b->dev); 1420 if (error) 1421 goto class_dev_reg_err; 1422 1423 /* Create legacy_io and legacy_mem files for this bus */ 1424 pci_create_legacy_files(b); 1425 1426 b->number = b->secondary = bus; 1427 b->resource[0] = &ioport_resource; 1428 b->resource[1] = &iomem_resource; 1429 1430 return b; 1431 1432 class_dev_reg_err: 1433 device_unregister(dev); 1434 dev_reg_err: 1435 down_write(&pci_bus_sem); 1436 list_del(&b->node); 1437 up_write(&pci_bus_sem); 1438 err_out: 1439 kfree(dev); 1440 kfree(b); 1441 return NULL; 1442 } 1443 1444 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, 1445 int bus, struct pci_ops *ops, void *sysdata) 1446 { 1447 struct pci_bus *b; 1448 1449 b = pci_create_bus(parent, bus, ops, sysdata); 1450 if (b) 1451 b->subordinate = pci_scan_child_bus(b); 1452 return b; 1453 } 1454 EXPORT_SYMBOL(pci_scan_bus_parented); 1455 1456 #ifdef CONFIG_HOTPLUG 1457 /** 1458 * pci_rescan_bus - scan a PCI bus for devices. 1459 * @bus: PCI bus to scan 1460 * 1461 * Scan a PCI bus and child buses for new devices, adds them, 1462 * and enables them. 1463 * 1464 * Returns the max number of subordinate bus discovered. 1465 */ 1466 unsigned int __ref pci_rescan_bus(struct pci_bus *bus) 1467 { 1468 unsigned int max; 1469 struct pci_dev *dev; 1470 1471 max = pci_scan_child_bus(bus); 1472 1473 down_read(&pci_bus_sem); 1474 list_for_each_entry(dev, &bus->devices, bus_list) 1475 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1476 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1477 if (dev->subordinate) 1478 pci_bus_size_bridges(dev->subordinate); 1479 up_read(&pci_bus_sem); 1480 1481 pci_bus_assign_resources(bus); 1482 pci_enable_bridges(bus); 1483 pci_bus_add_devices(bus); 1484 1485 return max; 1486 } 1487 EXPORT_SYMBOL_GPL(pci_rescan_bus); 1488 1489 EXPORT_SYMBOL(pci_add_new_bus); 1490 EXPORT_SYMBOL(pci_scan_slot); 1491 EXPORT_SYMBOL(pci_scan_bridge); 1492 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 1493 #endif 1494 1495 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) 1496 { 1497 const struct pci_dev *a = to_pci_dev(d_a); 1498 const struct pci_dev *b = to_pci_dev(d_b); 1499 1500 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 1501 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 1502 1503 if (a->bus->number < b->bus->number) return -1; 1504 else if (a->bus->number > b->bus->number) return 1; 1505 1506 if (a->devfn < b->devfn) return -1; 1507 else if (a->devfn > b->devfn) return 1; 1508 1509 return 0; 1510 } 1511 1512 void __init pci_sort_breadthfirst(void) 1513 { 1514 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 1515 } 1516