1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_pci.h> 12 #include <linux/pci_hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/cpumask.h> 16 #include <linux/aer.h> 17 #include <linux/acpi.h> 18 #include <linux/hypervisor.h> 19 #include <linux/irqdomain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/bitfield.h> 22 #include "pci.h" 23 24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 25 #define CARDBUS_RESERVE_BUSNR 3 26 27 static struct resource busn_resource = { 28 .name = "PCI busn", 29 .start = 0, 30 .end = 255, 31 .flags = IORESOURCE_BUS, 32 }; 33 34 /* Ugh. Need to stop exporting this to modules. */ 35 LIST_HEAD(pci_root_buses); 36 EXPORT_SYMBOL(pci_root_buses); 37 38 static LIST_HEAD(pci_domain_busn_res_list); 39 40 struct pci_domain_busn_res { 41 struct list_head list; 42 struct resource res; 43 int domain_nr; 44 }; 45 46 static struct resource *get_pci_domain_busn_res(int domain_nr) 47 { 48 struct pci_domain_busn_res *r; 49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list) 51 if (r->domain_nr == domain_nr) 52 return &r->res; 53 54 r = kzalloc(sizeof(*r), GFP_KERNEL); 55 if (!r) 56 return NULL; 57 58 r->domain_nr = domain_nr; 59 r->res.start = 0; 60 r->res.end = 0xff; 61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 62 63 list_add_tail(&r->list, &pci_domain_busn_res_list); 64 65 return &r->res; 66 } 67 68 /* 69 * Some device drivers need know if PCI is initiated. 70 * Basically, we think PCI is not initiated when there 71 * is no device to be found on the pci_bus_type. 72 */ 73 int no_pci_devices(void) 74 { 75 struct device *dev; 76 int no_devices; 77 78 dev = bus_find_next_device(&pci_bus_type, NULL); 79 no_devices = (dev == NULL); 80 put_device(dev); 81 return no_devices; 82 } 83 EXPORT_SYMBOL(no_pci_devices); 84 85 /* 86 * PCI Bus Class 87 */ 88 static void release_pcibus_dev(struct device *dev) 89 { 90 struct pci_bus *pci_bus = to_pci_bus(dev); 91 92 put_device(pci_bus->bridge); 93 pci_bus_remove_resources(pci_bus); 94 pci_release_bus_of_node(pci_bus); 95 kfree(pci_bus); 96 } 97 98 static const struct class pcibus_class = { 99 .name = "pci_bus", 100 .dev_release = &release_pcibus_dev, 101 .dev_groups = pcibus_groups, 102 }; 103 104 static int __init pcibus_class_init(void) 105 { 106 return class_register(&pcibus_class); 107 } 108 postcore_initcall(pcibus_class_init); 109 110 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 111 { 112 u64 size = mask & maxbase; /* Find the significant bits */ 113 if (!size) 114 return 0; 115 116 /* 117 * Get the lowest of them to find the decode size, and from that 118 * the extent. 119 */ 120 size = size & ~(size-1); 121 122 /* 123 * base == maxbase can be valid only if the BAR has already been 124 * programmed with all 1s. 125 */ 126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 127 return 0; 128 129 return size; 130 } 131 132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 133 { 134 u32 mem_type; 135 unsigned long flags; 136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 139 flags |= IORESOURCE_IO; 140 return flags; 141 } 142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 144 flags |= IORESOURCE_MEM; 145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 146 flags |= IORESOURCE_PREFETCH; 147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 149 switch (mem_type) { 150 case PCI_BASE_ADDRESS_MEM_TYPE_32: 151 break; 152 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 153 /* 1M mem BAR treated as 32-bit BAR */ 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_64: 156 flags |= IORESOURCE_MEM_64; 157 break; 158 default: 159 /* mem unknown type treated as 32-bit BAR */ 160 break; 161 } 162 return flags; 163 } 164 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 167 /** 168 * __pci_size_bars - Read the raw BAR mask for a range of PCI BARs 169 * @dev: the PCI device 170 * @count: number of BARs to size 171 * @pos: starting config space position 172 * @sizes: array to store mask values 173 * @rom: indicate whether to use ROM mask, which avoids enabling ROM BARs 174 * 175 * Provided @sizes array must be sufficiently sized to store results for 176 * @count u32 BARs. Caller is responsible for disabling decode to specified 177 * BAR range around calling this function. This function is intended to avoid 178 * disabling decode around sizing each BAR individually, which can result in 179 * non-trivial overhead in virtualized environments with very large PCI BARs. 180 */ 181 static void __pci_size_bars(struct pci_dev *dev, int count, 182 unsigned int pos, u32 *sizes, bool rom) 183 { 184 u32 orig, mask = rom ? PCI_ROM_ADDRESS_MASK : ~0; 185 int i; 186 187 for (i = 0; i < count; i++, pos += 4, sizes++) { 188 pci_read_config_dword(dev, pos, &orig); 189 pci_write_config_dword(dev, pos, mask); 190 pci_read_config_dword(dev, pos, sizes); 191 pci_write_config_dword(dev, pos, orig); 192 } 193 } 194 195 void __pci_size_stdbars(struct pci_dev *dev, int count, 196 unsigned int pos, u32 *sizes) 197 { 198 __pci_size_bars(dev, count, pos, sizes, false); 199 } 200 201 static void __pci_size_rom(struct pci_dev *dev, unsigned int pos, u32 *sizes) 202 { 203 __pci_size_bars(dev, 1, pos, sizes, true); 204 } 205 206 /** 207 * __pci_read_base - Read a PCI BAR 208 * @dev: the PCI device 209 * @type: type of the BAR 210 * @res: resource buffer to be filled in 211 * @pos: BAR position in the config space 212 * @sizes: array of one or more pre-read BAR masks 213 * 214 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 215 */ 216 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 217 struct resource *res, unsigned int pos, u32 *sizes) 218 { 219 u32 l = 0, sz; 220 u64 l64, sz64, mask64; 221 struct pci_bus_region region, inverted_region; 222 const char *res_name = pci_resource_name(dev, res - dev->resource); 223 224 res->name = pci_name(dev); 225 226 pci_read_config_dword(dev, pos, &l); 227 sz = sizes[0]; 228 229 /* 230 * All bits set in sz means the device isn't working properly. 231 * If the BAR isn't implemented, all bits must be 0. If it's a 232 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 233 * 1 must be clear. 234 */ 235 if (PCI_POSSIBLE_ERROR(sz)) 236 sz = 0; 237 238 /* 239 * I don't know how l can have all bits set. Copied from old code. 240 * Maybe it fixes a bug on some ancient platform. 241 */ 242 if (PCI_POSSIBLE_ERROR(l)) 243 l = 0; 244 245 if (type == pci_bar_unknown) { 246 res->flags = decode_bar(dev, l); 247 res->flags |= IORESOURCE_SIZEALIGN; 248 if (res->flags & IORESOURCE_IO) { 249 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 250 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 251 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 252 } else { 253 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 254 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 255 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 256 } 257 } else { 258 if (l & PCI_ROM_ADDRESS_ENABLE) 259 res->flags |= IORESOURCE_ROM_ENABLE; 260 l64 = l & PCI_ROM_ADDRESS_MASK; 261 sz64 = sz & PCI_ROM_ADDRESS_MASK; 262 mask64 = PCI_ROM_ADDRESS_MASK; 263 } 264 265 if (res->flags & IORESOURCE_MEM_64) { 266 pci_read_config_dword(dev, pos + 4, &l); 267 sz = sizes[1]; 268 269 l64 |= ((u64)l << 32); 270 sz64 |= ((u64)sz << 32); 271 mask64 |= ((u64)~0 << 32); 272 } 273 274 if (!sz64) 275 goto fail; 276 277 sz64 = pci_size(l64, sz64, mask64); 278 if (!sz64) { 279 pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name); 280 goto fail; 281 } 282 283 if (res->flags & IORESOURCE_MEM_64) { 284 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 285 && sz64 > 0x100000000ULL) { 286 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 287 res->start = 0; 288 res->end = 0; 289 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n", 290 res_name, (unsigned long long)sz64); 291 goto out; 292 } 293 294 if ((sizeof(pci_bus_addr_t) < 8) && l) { 295 /* Above 32-bit boundary; try to reallocate */ 296 res->flags |= IORESOURCE_UNSET; 297 res->start = 0; 298 res->end = sz64 - 1; 299 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n", 300 res_name, (unsigned long long)l64); 301 goto out; 302 } 303 } 304 305 region.start = l64; 306 region.end = l64 + sz64 - 1; 307 308 pcibios_bus_to_resource(dev->bus, res, ®ion); 309 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 310 311 /* 312 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 313 * the corresponding resource address (the physical address used by 314 * the CPU. Converting that resource address back to a bus address 315 * should yield the original BAR value: 316 * 317 * resource_to_bus(bus_to_resource(A)) == A 318 * 319 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 320 * be claimed by the device. 321 */ 322 if (inverted_region.start != region.start) { 323 res->flags |= IORESOURCE_UNSET; 324 res->start = 0; 325 res->end = region.end - region.start; 326 pci_info(dev, "%s: initial BAR value %#010llx invalid\n", 327 res_name, (unsigned long long)region.start); 328 } 329 330 goto out; 331 332 333 fail: 334 res->flags = 0; 335 out: 336 if (res->flags) 337 pci_info(dev, "%s %pR\n", res_name, res); 338 339 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 340 } 341 342 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 343 { 344 u32 rombar, stdbars[PCI_STD_NUM_BARS]; 345 unsigned int pos, reg; 346 u16 orig_cmd; 347 348 BUILD_BUG_ON(howmany > PCI_STD_NUM_BARS); 349 350 if (dev->non_compliant_bars) 351 return; 352 353 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 354 if (dev->is_virtfn) 355 return; 356 357 /* No printks while decoding is disabled! */ 358 if (!dev->mmio_always_on) { 359 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 360 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 361 pci_write_config_word(dev, PCI_COMMAND, 362 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 363 } 364 } 365 366 __pci_size_stdbars(dev, howmany, PCI_BASE_ADDRESS_0, stdbars); 367 if (rom) 368 __pci_size_rom(dev, rom, &rombar); 369 370 if (!dev->mmio_always_on && 371 (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 372 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 373 374 for (pos = 0; pos < howmany; pos++) { 375 struct resource *res = &dev->resource[pos]; 376 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 377 pos += __pci_read_base(dev, pci_bar_unknown, 378 res, reg, &stdbars[pos]); 379 } 380 381 if (rom) { 382 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 383 dev->rom_base_reg = rom; 384 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 385 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 386 __pci_read_base(dev, pci_bar_mem32, res, rom, &rombar); 387 } 388 } 389 390 static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res, 391 bool log) 392 { 393 u8 io_base_lo, io_limit_lo; 394 unsigned long io_mask, io_granularity, base, limit; 395 struct pci_bus_region region; 396 397 io_mask = PCI_IO_RANGE_MASK; 398 io_granularity = 0x1000; 399 if (dev->io_window_1k) { 400 /* Support 1K I/O space granularity */ 401 io_mask = PCI_IO_1K_RANGE_MASK; 402 io_granularity = 0x400; 403 } 404 405 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 406 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 407 base = (io_base_lo & io_mask) << 8; 408 limit = (io_limit_lo & io_mask) << 8; 409 410 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 411 u16 io_base_hi, io_limit_hi; 412 413 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 414 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 415 base |= ((unsigned long) io_base_hi << 16); 416 limit |= ((unsigned long) io_limit_hi << 16); 417 } 418 419 if (base <= limit) { 420 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 421 region.start = base; 422 region.end = limit + io_granularity - 1; 423 pcibios_bus_to_resource(dev->bus, res, ®ion); 424 if (log) 425 pci_info(dev, " bridge window %pR\n", res); 426 } 427 } 428 429 static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res, 430 bool log) 431 { 432 u16 mem_base_lo, mem_limit_lo; 433 unsigned long base, limit; 434 struct pci_bus_region region; 435 436 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 437 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 438 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 439 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 440 if (base <= limit) { 441 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 442 region.start = base; 443 region.end = limit + 0xfffff; 444 pcibios_bus_to_resource(dev->bus, res, ®ion); 445 if (log) 446 pci_info(dev, " bridge window %pR\n", res); 447 } 448 } 449 450 static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res, 451 bool log) 452 { 453 u16 mem_base_lo, mem_limit_lo; 454 u64 base64, limit64; 455 pci_bus_addr_t base, limit; 456 struct pci_bus_region region; 457 458 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 459 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 460 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 461 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 462 463 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 464 u32 mem_base_hi, mem_limit_hi; 465 466 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 467 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 468 469 /* 470 * Some bridges set the base > limit by default, and some 471 * (broken) BIOSes do not initialize them. If we find 472 * this, just assume they are not being used. 473 */ 474 if (mem_base_hi <= mem_limit_hi) { 475 base64 |= (u64) mem_base_hi << 32; 476 limit64 |= (u64) mem_limit_hi << 32; 477 } 478 } 479 480 base = (pci_bus_addr_t) base64; 481 limit = (pci_bus_addr_t) limit64; 482 483 if (base != base64) { 484 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 485 (unsigned long long) base64); 486 return; 487 } 488 489 if (base <= limit) { 490 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 491 IORESOURCE_MEM | IORESOURCE_PREFETCH; 492 if (res->flags & PCI_PREF_RANGE_TYPE_64) 493 res->flags |= IORESOURCE_MEM_64; 494 region.start = base; 495 region.end = limit + 0xfffff; 496 pcibios_bus_to_resource(dev->bus, res, ®ion); 497 if (log) 498 pci_info(dev, " bridge window %pR\n", res); 499 } 500 } 501 502 static void pci_read_bridge_windows(struct pci_dev *bridge) 503 { 504 u32 buses; 505 u16 io; 506 u32 pmem, tmp; 507 struct resource res; 508 509 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses); 510 res.flags = IORESOURCE_BUS; 511 res.start = (buses >> 8) & 0xff; 512 res.end = (buses >> 16) & 0xff; 513 pci_info(bridge, "PCI bridge to %pR%s\n", &res, 514 bridge->transparent ? " (subtractive decode)" : ""); 515 516 pci_read_config_word(bridge, PCI_IO_BASE, &io); 517 if (!io) { 518 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 519 pci_read_config_word(bridge, PCI_IO_BASE, &io); 520 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 521 } 522 if (io) { 523 bridge->io_window = 1; 524 pci_read_bridge_io(bridge, &res, true); 525 } 526 527 pci_read_bridge_mmio(bridge, &res, true); 528 529 /* 530 * DECchip 21050 pass 2 errata: the bridge may miss an address 531 * disconnect boundary by one PCI data phase. Workaround: do not 532 * use prefetching on this device. 533 */ 534 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 535 return; 536 537 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 538 if (!pmem) { 539 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 540 0xffe0fff0); 541 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 542 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 543 } 544 if (!pmem) 545 return; 546 547 bridge->pref_window = 1; 548 549 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 550 551 /* 552 * Bridge claims to have a 64-bit prefetchable memory 553 * window; verify that the upper bits are actually 554 * writable. 555 */ 556 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 557 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 558 0xffffffff); 559 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 560 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 561 if (tmp) 562 bridge->pref_64_window = 1; 563 } 564 565 pci_read_bridge_mmio_pref(bridge, &res, true); 566 } 567 568 void pci_read_bridge_bases(struct pci_bus *child) 569 { 570 struct pci_dev *dev = child->self; 571 struct resource *res; 572 int i; 573 574 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 575 return; 576 577 pci_info(dev, "PCI bridge to %pR%s\n", 578 &child->busn_res, 579 dev->transparent ? " (subtractive decode)" : ""); 580 581 pci_bus_remove_resources(child); 582 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 583 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 584 585 pci_read_bridge_io(child->self, child->resource[0], false); 586 pci_read_bridge_mmio(child->self, child->resource[1], false); 587 pci_read_bridge_mmio_pref(child->self, child->resource[2], false); 588 589 if (!dev->transparent) 590 return; 591 592 pci_bus_for_each_resource(child->parent, res) { 593 if (!res || !res->flags) 594 continue; 595 596 pci_bus_add_resource(child, res); 597 pci_info(dev, " bridge window %pR (subtractive decode)\n", res); 598 } 599 } 600 601 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 602 { 603 struct pci_bus *b; 604 605 b = kzalloc(sizeof(*b), GFP_KERNEL); 606 if (!b) 607 return NULL; 608 609 INIT_LIST_HEAD(&b->node); 610 INIT_LIST_HEAD(&b->children); 611 INIT_LIST_HEAD(&b->devices); 612 INIT_LIST_HEAD(&b->slots); 613 INIT_LIST_HEAD(&b->resources); 614 b->max_bus_speed = PCI_SPEED_UNKNOWN; 615 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 616 #ifdef CONFIG_PCI_DOMAINS_GENERIC 617 if (parent) 618 b->domain_nr = parent->domain_nr; 619 #endif 620 return b; 621 } 622 623 static void pci_release_host_bridge_dev(struct device *dev) 624 { 625 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 626 627 if (bridge->release_fn) 628 bridge->release_fn(bridge); 629 630 pci_free_resource_list(&bridge->windows); 631 pci_free_resource_list(&bridge->dma_ranges); 632 kfree(bridge); 633 } 634 635 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 636 { 637 INIT_LIST_HEAD(&bridge->windows); 638 INIT_LIST_HEAD(&bridge->dma_ranges); 639 640 /* 641 * We assume we can manage these PCIe features. Some systems may 642 * reserve these for use by the platform itself, e.g., an ACPI BIOS 643 * may implement its own AER handling and use _OSC to prevent the 644 * OS from interfering. 645 */ 646 bridge->native_aer = 1; 647 bridge->native_pcie_hotplug = 1; 648 bridge->native_shpc_hotplug = 1; 649 bridge->native_pme = 1; 650 bridge->native_ltr = 1; 651 bridge->native_dpc = 1; 652 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 653 bridge->native_cxl_error = 1; 654 655 device_initialize(&bridge->dev); 656 } 657 658 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 659 { 660 struct pci_host_bridge *bridge; 661 662 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 663 if (!bridge) 664 return NULL; 665 666 pci_init_host_bridge(bridge); 667 bridge->dev.release = pci_release_host_bridge_dev; 668 669 return bridge; 670 } 671 EXPORT_SYMBOL(pci_alloc_host_bridge); 672 673 static void devm_pci_alloc_host_bridge_release(void *data) 674 { 675 pci_free_host_bridge(data); 676 } 677 678 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 679 size_t priv) 680 { 681 int ret; 682 struct pci_host_bridge *bridge; 683 684 bridge = pci_alloc_host_bridge(priv); 685 if (!bridge) 686 return NULL; 687 688 bridge->dev.parent = dev; 689 690 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 691 bridge); 692 if (ret) 693 return NULL; 694 695 ret = devm_of_pci_bridge_init(dev, bridge); 696 if (ret) 697 return NULL; 698 699 return bridge; 700 } 701 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 702 703 void pci_free_host_bridge(struct pci_host_bridge *bridge) 704 { 705 put_device(&bridge->dev); 706 } 707 EXPORT_SYMBOL(pci_free_host_bridge); 708 709 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 710 static const unsigned char pcix_bus_speed[] = { 711 PCI_SPEED_UNKNOWN, /* 0 */ 712 PCI_SPEED_66MHz_PCIX, /* 1 */ 713 PCI_SPEED_100MHz_PCIX, /* 2 */ 714 PCI_SPEED_133MHz_PCIX, /* 3 */ 715 PCI_SPEED_UNKNOWN, /* 4 */ 716 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 717 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 718 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 719 PCI_SPEED_UNKNOWN, /* 8 */ 720 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 721 PCI_SPEED_100MHz_PCIX_266, /* A */ 722 PCI_SPEED_133MHz_PCIX_266, /* B */ 723 PCI_SPEED_UNKNOWN, /* C */ 724 PCI_SPEED_66MHz_PCIX_533, /* D */ 725 PCI_SPEED_100MHz_PCIX_533, /* E */ 726 PCI_SPEED_133MHz_PCIX_533 /* F */ 727 }; 728 729 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 730 const unsigned char pcie_link_speed[] = { 731 PCI_SPEED_UNKNOWN, /* 0 */ 732 PCIE_SPEED_2_5GT, /* 1 */ 733 PCIE_SPEED_5_0GT, /* 2 */ 734 PCIE_SPEED_8_0GT, /* 3 */ 735 PCIE_SPEED_16_0GT, /* 4 */ 736 PCIE_SPEED_32_0GT, /* 5 */ 737 PCIE_SPEED_64_0GT, /* 6 */ 738 PCI_SPEED_UNKNOWN, /* 7 */ 739 PCI_SPEED_UNKNOWN, /* 8 */ 740 PCI_SPEED_UNKNOWN, /* 9 */ 741 PCI_SPEED_UNKNOWN, /* A */ 742 PCI_SPEED_UNKNOWN, /* B */ 743 PCI_SPEED_UNKNOWN, /* C */ 744 PCI_SPEED_UNKNOWN, /* D */ 745 PCI_SPEED_UNKNOWN, /* E */ 746 PCI_SPEED_UNKNOWN /* F */ 747 }; 748 EXPORT_SYMBOL_GPL(pcie_link_speed); 749 750 const char *pci_speed_string(enum pci_bus_speed speed) 751 { 752 /* Indexed by the pci_bus_speed enum */ 753 static const char *speed_strings[] = { 754 "33 MHz PCI", /* 0x00 */ 755 "66 MHz PCI", /* 0x01 */ 756 "66 MHz PCI-X", /* 0x02 */ 757 "100 MHz PCI-X", /* 0x03 */ 758 "133 MHz PCI-X", /* 0x04 */ 759 NULL, /* 0x05 */ 760 NULL, /* 0x06 */ 761 NULL, /* 0x07 */ 762 NULL, /* 0x08 */ 763 "66 MHz PCI-X 266", /* 0x09 */ 764 "100 MHz PCI-X 266", /* 0x0a */ 765 "133 MHz PCI-X 266", /* 0x0b */ 766 "Unknown AGP", /* 0x0c */ 767 "1x AGP", /* 0x0d */ 768 "2x AGP", /* 0x0e */ 769 "4x AGP", /* 0x0f */ 770 "8x AGP", /* 0x10 */ 771 "66 MHz PCI-X 533", /* 0x11 */ 772 "100 MHz PCI-X 533", /* 0x12 */ 773 "133 MHz PCI-X 533", /* 0x13 */ 774 "2.5 GT/s PCIe", /* 0x14 */ 775 "5.0 GT/s PCIe", /* 0x15 */ 776 "8.0 GT/s PCIe", /* 0x16 */ 777 "16.0 GT/s PCIe", /* 0x17 */ 778 "32.0 GT/s PCIe", /* 0x18 */ 779 "64.0 GT/s PCIe", /* 0x19 */ 780 }; 781 782 if (speed < ARRAY_SIZE(speed_strings)) 783 return speed_strings[speed]; 784 return "Unknown"; 785 } 786 EXPORT_SYMBOL_GPL(pci_speed_string); 787 788 void pcie_update_link_speed(struct pci_bus *bus) 789 { 790 struct pci_dev *bridge = bus->self; 791 u16 linksta; 792 793 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 794 __pcie_update_link_speed(bus, linksta); 795 } 796 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 797 798 static unsigned char agp_speeds[] = { 799 AGP_UNKNOWN, 800 AGP_1X, 801 AGP_2X, 802 AGP_4X, 803 AGP_8X 804 }; 805 806 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 807 { 808 int index = 0; 809 810 if (agpstat & 4) 811 index = 3; 812 else if (agpstat & 2) 813 index = 2; 814 else if (agpstat & 1) 815 index = 1; 816 else 817 goto out; 818 819 if (agp3) { 820 index += 2; 821 if (index == 5) 822 index = 0; 823 } 824 825 out: 826 return agp_speeds[index]; 827 } 828 829 static void pci_set_bus_speed(struct pci_bus *bus) 830 { 831 struct pci_dev *bridge = bus->self; 832 int pos; 833 834 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 835 if (!pos) 836 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 837 if (pos) { 838 u32 agpstat, agpcmd; 839 840 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 841 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 842 843 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 844 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 845 } 846 847 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 848 if (pos) { 849 u16 status; 850 enum pci_bus_speed max; 851 852 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 853 &status); 854 855 if (status & PCI_X_SSTATUS_533MHZ) { 856 max = PCI_SPEED_133MHz_PCIX_533; 857 } else if (status & PCI_X_SSTATUS_266MHZ) { 858 max = PCI_SPEED_133MHz_PCIX_266; 859 } else if (status & PCI_X_SSTATUS_133MHZ) { 860 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 861 max = PCI_SPEED_133MHz_PCIX_ECC; 862 else 863 max = PCI_SPEED_133MHz_PCIX; 864 } else { 865 max = PCI_SPEED_66MHz_PCIX; 866 } 867 868 bus->max_bus_speed = max; 869 bus->cur_bus_speed = 870 pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)]; 871 872 return; 873 } 874 875 if (pci_is_pcie(bridge)) { 876 u32 linkcap; 877 878 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 879 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 880 881 pcie_update_link_speed(bus); 882 } 883 } 884 885 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 886 { 887 struct irq_domain *d; 888 889 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 890 d = dev_get_msi_domain(bus->bridge); 891 892 /* 893 * Any firmware interface that can resolve the msi_domain 894 * should be called from here. 895 */ 896 if (!d) 897 d = pci_host_bridge_of_msi_domain(bus); 898 if (!d) 899 d = pci_host_bridge_acpi_msi_domain(bus); 900 901 /* 902 * If no IRQ domain was found via the OF tree, try looking it up 903 * directly through the fwnode_handle. 904 */ 905 if (!d) { 906 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 907 908 if (fwnode) 909 d = irq_find_matching_fwnode(fwnode, 910 DOMAIN_BUS_PCI_MSI); 911 } 912 913 return d; 914 } 915 916 static void pci_set_bus_msi_domain(struct pci_bus *bus) 917 { 918 struct irq_domain *d; 919 struct pci_bus *b; 920 921 /* 922 * The bus can be a root bus, a subordinate bus, or a virtual bus 923 * created by an SR-IOV device. Walk up to the first bridge device 924 * found or derive the domain from the host bridge. 925 */ 926 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 927 if (b->self) 928 d = dev_get_msi_domain(&b->self->dev); 929 } 930 931 if (!d) 932 d = pci_host_bridge_msi_domain(b); 933 934 dev_set_msi_domain(&bus->dev, d); 935 } 936 937 static bool pci_preserve_config(struct pci_host_bridge *host_bridge) 938 { 939 if (pci_acpi_preserve_config(host_bridge)) 940 return true; 941 942 if (host_bridge->dev.parent && host_bridge->dev.parent->of_node) 943 return of_pci_preserve_config(host_bridge->dev.parent->of_node); 944 945 return false; 946 } 947 948 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 949 { 950 struct device *parent = bridge->dev.parent; 951 struct resource_entry *window, *next, *n; 952 struct pci_bus *bus, *b; 953 resource_size_t offset, next_offset; 954 LIST_HEAD(resources); 955 struct resource *res, *next_res; 956 char addr[64], *fmt; 957 const char *name; 958 int err; 959 960 bus = pci_alloc_bus(NULL); 961 if (!bus) 962 return -ENOMEM; 963 964 bridge->bus = bus; 965 966 bus->sysdata = bridge->sysdata; 967 bus->ops = bridge->ops; 968 bus->number = bus->busn_res.start = bridge->busnr; 969 #ifdef CONFIG_PCI_DOMAINS_GENERIC 970 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 971 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 972 else 973 bus->domain_nr = bridge->domain_nr; 974 if (bus->domain_nr < 0) { 975 err = bus->domain_nr; 976 goto free; 977 } 978 #endif 979 980 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 981 if (b) { 982 /* Ignore it if we already got here via a different bridge */ 983 dev_dbg(&b->dev, "bus already known\n"); 984 err = -EEXIST; 985 goto free; 986 } 987 988 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 989 bridge->busnr); 990 991 err = pcibios_root_bridge_prepare(bridge); 992 if (err) 993 goto free; 994 995 /* Temporarily move resources off the list */ 996 list_splice_init(&bridge->windows, &resources); 997 err = device_add(&bridge->dev); 998 if (err) { 999 put_device(&bridge->dev); 1000 goto free; 1001 } 1002 bus->bridge = get_device(&bridge->dev); 1003 device_enable_async_suspend(bus->bridge); 1004 pci_set_bus_of_node(bus); 1005 pci_set_bus_msi_domain(bus); 1006 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 1007 !pci_host_of_has_msi_map(parent)) 1008 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1009 1010 if (!parent) 1011 set_dev_node(bus->bridge, pcibus_to_node(bus)); 1012 1013 bus->dev.class = &pcibus_class; 1014 bus->dev.parent = bus->bridge; 1015 1016 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 1017 name = dev_name(&bus->dev); 1018 1019 err = device_register(&bus->dev); 1020 if (err) 1021 goto unregister; 1022 1023 pcibios_add_bus(bus); 1024 1025 if (bus->ops->add_bus) { 1026 err = bus->ops->add_bus(bus); 1027 if (WARN_ON(err < 0)) 1028 dev_err(&bus->dev, "failed to add bus: %d\n", err); 1029 } 1030 1031 /* Create legacy_io and legacy_mem files for this bus */ 1032 pci_create_legacy_files(bus); 1033 1034 if (parent) 1035 dev_info(parent, "PCI host bridge to bus %s\n", name); 1036 else 1037 pr_info("PCI host bridge to bus %s\n", name); 1038 1039 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 1040 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 1041 1042 /* Check if the boot configuration by FW needs to be preserved */ 1043 bridge->preserve_config = pci_preserve_config(bridge); 1044 1045 /* Coalesce contiguous windows */ 1046 resource_list_for_each_entry_safe(window, n, &resources) { 1047 if (list_is_last(&window->node, &resources)) 1048 break; 1049 1050 next = list_next_entry(window, node); 1051 offset = window->offset; 1052 res = window->res; 1053 next_offset = next->offset; 1054 next_res = next->res; 1055 1056 if (res->flags != next_res->flags || offset != next_offset) 1057 continue; 1058 1059 if (res->end + 1 == next_res->start) { 1060 next_res->start = res->start; 1061 res->flags = res->start = res->end = 0; 1062 } 1063 } 1064 1065 /* Add initial resources to the bus */ 1066 resource_list_for_each_entry_safe(window, n, &resources) { 1067 offset = window->offset; 1068 res = window->res; 1069 if (!res->flags && !res->start && !res->end) { 1070 release_resource(res); 1071 resource_list_destroy_entry(window); 1072 continue; 1073 } 1074 1075 list_move_tail(&window->node, &bridge->windows); 1076 1077 if (res->flags & IORESOURCE_BUS) 1078 pci_bus_insert_busn_res(bus, bus->number, res->end); 1079 else 1080 pci_bus_add_resource(bus, res); 1081 1082 if (offset) { 1083 if (resource_type(res) == IORESOURCE_IO) 1084 fmt = " (bus address [%#06llx-%#06llx])"; 1085 else 1086 fmt = " (bus address [%#010llx-%#010llx])"; 1087 1088 snprintf(addr, sizeof(addr), fmt, 1089 (unsigned long long)(res->start - offset), 1090 (unsigned long long)(res->end - offset)); 1091 } else 1092 addr[0] = '\0'; 1093 1094 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 1095 } 1096 1097 down_write(&pci_bus_sem); 1098 list_add_tail(&bus->node, &pci_root_buses); 1099 up_write(&pci_bus_sem); 1100 1101 return 0; 1102 1103 unregister: 1104 put_device(&bridge->dev); 1105 device_del(&bridge->dev); 1106 1107 free: 1108 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1109 pci_bus_release_domain_nr(parent, bus->domain_nr); 1110 #endif 1111 kfree(bus); 1112 return err; 1113 } 1114 1115 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1116 { 1117 int pos; 1118 u32 status; 1119 1120 /* 1121 * If extended config space isn't accessible on a bridge's primary 1122 * bus, we certainly can't access it on the secondary bus. 1123 */ 1124 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1125 return false; 1126 1127 /* 1128 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1129 * extended config space is accessible on the primary, it's also 1130 * accessible on the secondary. 1131 */ 1132 if (pci_is_pcie(bridge) && 1133 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1134 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1135 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1136 return true; 1137 1138 /* 1139 * For the other bridge types: 1140 * - PCI-to-PCI bridges 1141 * - PCIe-to-PCI/PCI-X forward bridges 1142 * - PCI/PCI-X-to-PCIe reverse bridges 1143 * extended config space on the secondary side is only accessible 1144 * if the bridge supports PCI-X Mode 2. 1145 */ 1146 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1147 if (!pos) 1148 return false; 1149 1150 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1151 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1152 } 1153 1154 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1155 struct pci_dev *bridge, int busnr) 1156 { 1157 struct pci_bus *child; 1158 struct pci_host_bridge *host; 1159 int i; 1160 int ret; 1161 1162 /* Allocate a new bus and inherit stuff from the parent */ 1163 child = pci_alloc_bus(parent); 1164 if (!child) 1165 return NULL; 1166 1167 child->parent = parent; 1168 child->sysdata = parent->sysdata; 1169 child->bus_flags = parent->bus_flags; 1170 1171 host = pci_find_host_bridge(parent); 1172 if (host->child_ops) 1173 child->ops = host->child_ops; 1174 else 1175 child->ops = parent->ops; 1176 1177 /* 1178 * Initialize some portions of the bus device, but don't register 1179 * it now as the parent is not properly set up yet. 1180 */ 1181 child->dev.class = &pcibus_class; 1182 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1183 1184 /* Set up the primary, secondary and subordinate bus numbers */ 1185 child->number = child->busn_res.start = busnr; 1186 child->primary = parent->busn_res.start; 1187 child->busn_res.end = 0xff; 1188 1189 if (!bridge) { 1190 child->dev.parent = parent->bridge; 1191 goto add_dev; 1192 } 1193 1194 child->self = bridge; 1195 child->bridge = get_device(&bridge->dev); 1196 child->dev.parent = child->bridge; 1197 pci_set_bus_of_node(child); 1198 pci_set_bus_speed(child); 1199 1200 /* 1201 * Check whether extended config space is accessible on the child 1202 * bus. Note that we currently assume it is always accessible on 1203 * the root bus. 1204 */ 1205 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1206 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1207 pci_info(child, "extended config space not accessible\n"); 1208 } 1209 1210 /* Set up default resource pointers and names */ 1211 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1212 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1213 child->resource[i]->name = child->name; 1214 } 1215 bridge->subordinate = child; 1216 1217 add_dev: 1218 pci_set_bus_msi_domain(child); 1219 ret = device_register(&child->dev); 1220 WARN_ON(ret < 0); 1221 1222 pcibios_add_bus(child); 1223 1224 if (child->ops->add_bus) { 1225 ret = child->ops->add_bus(child); 1226 if (WARN_ON(ret < 0)) 1227 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1228 } 1229 1230 /* Create legacy_io and legacy_mem files for this bus */ 1231 pci_create_legacy_files(child); 1232 1233 return child; 1234 } 1235 1236 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1237 int busnr) 1238 { 1239 struct pci_bus *child; 1240 1241 child = pci_alloc_child_bus(parent, dev, busnr); 1242 if (child) { 1243 down_write(&pci_bus_sem); 1244 list_add_tail(&child->node, &parent->children); 1245 up_write(&pci_bus_sem); 1246 } 1247 return child; 1248 } 1249 EXPORT_SYMBOL(pci_add_new_bus); 1250 1251 static void pci_enable_rrs_sv(struct pci_dev *pdev) 1252 { 1253 u16 root_cap = 0; 1254 1255 /* Enable Configuration RRS Software Visibility if supported */ 1256 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1257 if (root_cap & PCI_EXP_RTCAP_RRS_SV) { 1258 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1259 PCI_EXP_RTCTL_RRS_SVE); 1260 pdev->config_rrs_sv = 1; 1261 } 1262 } 1263 1264 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1265 unsigned int available_buses); 1266 /** 1267 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1268 * numbers from EA capability. 1269 * @dev: Bridge 1270 * @sec: updated with secondary bus number from EA 1271 * @sub: updated with subordinate bus number from EA 1272 * 1273 * If @dev is a bridge with EA capability that specifies valid secondary 1274 * and subordinate bus numbers, return true with the bus numbers in @sec 1275 * and @sub. Otherwise return false. 1276 */ 1277 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1278 { 1279 int ea, offset; 1280 u32 dw; 1281 u8 ea_sec, ea_sub; 1282 1283 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1284 return false; 1285 1286 /* find PCI EA capability in list */ 1287 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1288 if (!ea) 1289 return false; 1290 1291 offset = ea + PCI_EA_FIRST_ENT; 1292 pci_read_config_dword(dev, offset, &dw); 1293 ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw); 1294 ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw); 1295 if (ea_sec == 0 || ea_sub < ea_sec) 1296 return false; 1297 1298 *sec = ea_sec; 1299 *sub = ea_sub; 1300 return true; 1301 } 1302 1303 /* 1304 * pci_scan_bridge_extend() - Scan buses behind a bridge 1305 * @bus: Parent bus the bridge is on 1306 * @dev: Bridge itself 1307 * @max: Starting subordinate number of buses behind this bridge 1308 * @available_buses: Total number of buses available for this bridge and 1309 * the devices below. After the minimal bus space has 1310 * been allocated the remaining buses will be 1311 * distributed equally between hotplug-capable bridges. 1312 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1313 * that need to be reconfigured. 1314 * 1315 * If it's a bridge, configure it and scan the bus behind it. 1316 * For CardBus bridges, we don't scan behind as the devices will 1317 * be handled by the bridge driver itself. 1318 * 1319 * We need to process bridges in two passes -- first we scan those 1320 * already configured by the BIOS and after we are done with all of 1321 * them, we proceed to assigning numbers to the remaining buses in 1322 * order to avoid overlaps between old and new bus numbers. 1323 * 1324 * Return: New subordinate number covering all buses behind this bridge. 1325 */ 1326 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1327 int max, unsigned int available_buses, 1328 int pass) 1329 { 1330 struct pci_bus *child; 1331 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1332 u32 buses, i, j = 0; 1333 u16 bctl; 1334 u8 primary, secondary, subordinate; 1335 int broken = 0; 1336 bool fixed_buses; 1337 u8 fixed_sec, fixed_sub; 1338 int next_busnr; 1339 1340 /* 1341 * Make sure the bridge is powered on to be able to access config 1342 * space of devices below it. 1343 */ 1344 pm_runtime_get_sync(&dev->dev); 1345 1346 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1347 primary = buses & 0xFF; 1348 secondary = (buses >> 8) & 0xFF; 1349 subordinate = (buses >> 16) & 0xFF; 1350 1351 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1352 secondary, subordinate, pass); 1353 1354 if (!primary && (primary != bus->number) && secondary && subordinate) { 1355 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1356 primary = bus->number; 1357 } 1358 1359 /* Check if setup is sensible at all */ 1360 if (!pass && 1361 (primary != bus->number || secondary <= bus->number || 1362 secondary > subordinate)) { 1363 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1364 secondary, subordinate); 1365 broken = 1; 1366 } 1367 1368 /* 1369 * Disable Master-Abort Mode during probing to avoid reporting of 1370 * bus errors in some architectures. 1371 */ 1372 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1373 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1374 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1375 1376 pci_enable_rrs_sv(dev); 1377 1378 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1379 !is_cardbus && !broken) { 1380 unsigned int cmax, buses; 1381 1382 /* 1383 * Bus already configured by firmware, process it in the 1384 * first pass and just note the configuration. 1385 */ 1386 if (pass) 1387 goto out; 1388 1389 /* 1390 * The bus might already exist for two reasons: Either we 1391 * are rescanning the bus or the bus is reachable through 1392 * more than one bridge. The second case can happen with 1393 * the i450NX chipset. 1394 */ 1395 child = pci_find_bus(pci_domain_nr(bus), secondary); 1396 if (!child) { 1397 child = pci_add_new_bus(bus, dev, secondary); 1398 if (!child) 1399 goto out; 1400 child->primary = primary; 1401 pci_bus_insert_busn_res(child, secondary, subordinate); 1402 child->bridge_ctl = bctl; 1403 } 1404 1405 buses = subordinate - secondary; 1406 cmax = pci_scan_child_bus_extend(child, buses); 1407 if (cmax > subordinate) 1408 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1409 subordinate, cmax); 1410 1411 /* Subordinate should equal child->busn_res.end */ 1412 if (subordinate > max) 1413 max = subordinate; 1414 } else { 1415 1416 /* 1417 * We need to assign a number to this bus which we always 1418 * do in the second pass. 1419 */ 1420 if (!pass) { 1421 if (pcibios_assign_all_busses() || broken || is_cardbus) 1422 1423 /* 1424 * Temporarily disable forwarding of the 1425 * configuration cycles on all bridges in 1426 * this bus segment to avoid possible 1427 * conflicts in the second pass between two 1428 * bridges programmed with overlapping bus 1429 * ranges. 1430 */ 1431 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1432 buses & ~0xffffff); 1433 goto out; 1434 } 1435 1436 /* Clear errors */ 1437 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1438 1439 /* Read bus numbers from EA Capability (if present) */ 1440 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1441 if (fixed_buses) 1442 next_busnr = fixed_sec; 1443 else 1444 next_busnr = max + 1; 1445 1446 /* 1447 * Prevent assigning a bus number that already exists. 1448 * This can happen when a bridge is hot-plugged, so in this 1449 * case we only re-scan this bus. 1450 */ 1451 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1452 if (!child) { 1453 child = pci_add_new_bus(bus, dev, next_busnr); 1454 if (!child) 1455 goto out; 1456 pci_bus_insert_busn_res(child, next_busnr, 1457 bus->busn_res.end); 1458 } 1459 max++; 1460 if (available_buses) 1461 available_buses--; 1462 1463 buses = (buses & 0xff000000) 1464 | ((unsigned int)(child->primary) << 0) 1465 | ((unsigned int)(child->busn_res.start) << 8) 1466 | ((unsigned int)(child->busn_res.end) << 16); 1467 1468 /* 1469 * yenta.c forces a secondary latency timer of 176. 1470 * Copy that behaviour here. 1471 */ 1472 if (is_cardbus) { 1473 buses &= ~0xff000000; 1474 buses |= CARDBUS_LATENCY_TIMER << 24; 1475 } 1476 1477 /* We need to blast all three values with a single write */ 1478 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1479 1480 if (!is_cardbus) { 1481 child->bridge_ctl = bctl; 1482 max = pci_scan_child_bus_extend(child, available_buses); 1483 } else { 1484 1485 /* 1486 * For CardBus bridges, we leave 4 bus numbers as 1487 * cards with a PCI-to-PCI bridge can be inserted 1488 * later. 1489 */ 1490 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1491 struct pci_bus *parent = bus; 1492 if (pci_find_bus(pci_domain_nr(bus), 1493 max+i+1)) 1494 break; 1495 while (parent->parent) { 1496 if ((!pcibios_assign_all_busses()) && 1497 (parent->busn_res.end > max) && 1498 (parent->busn_res.end <= max+i)) { 1499 j = 1; 1500 } 1501 parent = parent->parent; 1502 } 1503 if (j) { 1504 1505 /* 1506 * Often, there are two CardBus 1507 * bridges -- try to leave one 1508 * valid bus number for each one. 1509 */ 1510 i /= 2; 1511 break; 1512 } 1513 } 1514 max += i; 1515 } 1516 1517 /* 1518 * Set subordinate bus number to its real value. 1519 * If fixed subordinate bus number exists from EA 1520 * capability then use it. 1521 */ 1522 if (fixed_buses) 1523 max = fixed_sub; 1524 pci_bus_update_busn_res_end(child, max); 1525 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1526 } 1527 1528 sprintf(child->name, 1529 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1530 pci_domain_nr(bus), child->number); 1531 1532 /* Check that all devices are accessible */ 1533 while (bus->parent) { 1534 if ((child->busn_res.end > bus->busn_res.end) || 1535 (child->number > bus->busn_res.end) || 1536 (child->number < bus->number) || 1537 (child->busn_res.end < bus->number)) { 1538 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1539 &child->busn_res); 1540 break; 1541 } 1542 bus = bus->parent; 1543 } 1544 1545 out: 1546 /* Clear errors in the Secondary Status Register */ 1547 pci_write_config_word(dev, PCI_SEC_STATUS, 0xffff); 1548 1549 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1550 1551 pm_runtime_put(&dev->dev); 1552 1553 return max; 1554 } 1555 1556 /* 1557 * pci_scan_bridge() - Scan buses behind a bridge 1558 * @bus: Parent bus the bridge is on 1559 * @dev: Bridge itself 1560 * @max: Starting subordinate number of buses behind this bridge 1561 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1562 * that need to be reconfigured. 1563 * 1564 * If it's a bridge, configure it and scan the bus behind it. 1565 * For CardBus bridges, we don't scan behind as the devices will 1566 * be handled by the bridge driver itself. 1567 * 1568 * We need to process bridges in two passes -- first we scan those 1569 * already configured by the BIOS and after we are done with all of 1570 * them, we proceed to assigning numbers to the remaining buses in 1571 * order to avoid overlaps between old and new bus numbers. 1572 * 1573 * Return: New subordinate number covering all buses behind this bridge. 1574 */ 1575 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1576 { 1577 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1578 } 1579 EXPORT_SYMBOL(pci_scan_bridge); 1580 1581 /* 1582 * Read interrupt line and base address registers. 1583 * The architecture-dependent code can tweak these, of course. 1584 */ 1585 static void pci_read_irq(struct pci_dev *dev) 1586 { 1587 unsigned char irq; 1588 1589 /* VFs are not allowed to use INTx, so skip the config reads */ 1590 if (dev->is_virtfn) { 1591 dev->pin = 0; 1592 dev->irq = 0; 1593 return; 1594 } 1595 1596 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1597 dev->pin = irq; 1598 if (irq) 1599 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1600 dev->irq = irq; 1601 } 1602 1603 void set_pcie_port_type(struct pci_dev *pdev) 1604 { 1605 int pos; 1606 u16 reg16; 1607 u32 reg32; 1608 int type; 1609 struct pci_dev *parent; 1610 1611 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1612 if (!pos) 1613 return; 1614 1615 pdev->pcie_cap = pos; 1616 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1617 pdev->pcie_flags_reg = reg16; 1618 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1619 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1620 1621 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); 1622 if (reg32 & PCI_EXP_LNKCAP_DLLLARC) 1623 pdev->link_active_reporting = 1; 1624 1625 parent = pci_upstream_bridge(pdev); 1626 if (!parent) 1627 return; 1628 1629 /* 1630 * Some systems do not identify their upstream/downstream ports 1631 * correctly so detect impossible configurations here and correct 1632 * the port type accordingly. 1633 */ 1634 type = pci_pcie_type(pdev); 1635 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1636 /* 1637 * If pdev claims to be downstream port but the parent 1638 * device is also downstream port assume pdev is actually 1639 * upstream port. 1640 */ 1641 if (pcie_downstream_port(parent)) { 1642 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1643 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1644 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1645 } 1646 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1647 /* 1648 * If pdev claims to be upstream port but the parent 1649 * device is also upstream port assume pdev is actually 1650 * downstream port. 1651 */ 1652 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1653 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1654 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1655 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1656 } 1657 } 1658 } 1659 1660 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1661 { 1662 u32 reg32; 1663 1664 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1665 if (reg32 & PCI_EXP_SLTCAP_HPC) 1666 pdev->is_hotplug_bridge = 1; 1667 } 1668 1669 static void set_pcie_thunderbolt(struct pci_dev *dev) 1670 { 1671 u16 vsec; 1672 1673 /* Is the device part of a Thunderbolt controller? */ 1674 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); 1675 if (vsec) 1676 dev->is_thunderbolt = 1; 1677 } 1678 1679 static void set_pcie_untrusted(struct pci_dev *dev) 1680 { 1681 struct pci_dev *parent = pci_upstream_bridge(dev); 1682 1683 if (!parent) 1684 return; 1685 /* 1686 * If the upstream bridge is untrusted we treat this device as 1687 * untrusted as well. 1688 */ 1689 if (parent->untrusted) { 1690 dev->untrusted = true; 1691 return; 1692 } 1693 1694 if (arch_pci_dev_is_removable(dev)) { 1695 pci_dbg(dev, "marking as untrusted\n"); 1696 dev->untrusted = true; 1697 } 1698 } 1699 1700 static void pci_set_removable(struct pci_dev *dev) 1701 { 1702 struct pci_dev *parent = pci_upstream_bridge(dev); 1703 1704 if (!parent) 1705 return; 1706 /* 1707 * We (only) consider everything tunneled below an external_facing 1708 * device to be removable by the user. We're mainly concerned with 1709 * consumer platforms with user accessible thunderbolt ports that are 1710 * vulnerable to DMA attacks, and we expect those ports to be marked by 1711 * the firmware as external_facing. Devices in traditional hotplug 1712 * slots can technically be removed, but the expectation is that unless 1713 * the port is marked with external_facing, such devices are less 1714 * accessible to user / may not be removed by end user, and thus not 1715 * exposed as "removable" to userspace. 1716 */ 1717 if (dev_is_removable(&parent->dev)) { 1718 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1719 return; 1720 } 1721 1722 if (arch_pci_dev_is_removable(dev)) { 1723 pci_dbg(dev, "marking as removable\n"); 1724 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1725 } 1726 } 1727 1728 /** 1729 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1730 * @dev: PCI device 1731 * 1732 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1733 * when forwarding a type1 configuration request the bridge must check that 1734 * the extended register address field is zero. The bridge is not permitted 1735 * to forward the transactions and must handle it as an Unsupported Request. 1736 * Some bridges do not follow this rule and simply drop the extended register 1737 * bits, resulting in the standard config space being aliased, every 256 1738 * bytes across the entire configuration space. Test for this condition by 1739 * comparing the first dword of each potential alias to the vendor/device ID. 1740 * Known offenders: 1741 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1742 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1743 */ 1744 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1745 { 1746 #ifdef CONFIG_PCI_QUIRKS 1747 int pos, ret; 1748 u32 header, tmp; 1749 1750 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1751 1752 for (pos = PCI_CFG_SPACE_SIZE; 1753 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1754 ret = pci_read_config_dword(dev, pos, &tmp); 1755 if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp)) 1756 return false; 1757 } 1758 1759 return true; 1760 #else 1761 return false; 1762 #endif 1763 } 1764 1765 /** 1766 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1767 * @dev: PCI device 1768 * 1769 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1770 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1771 * access it. Maybe we don't have a way to generate extended config space 1772 * accesses, or the device is behind a reverse Express bridge. So we try 1773 * reading the dword at 0x100 which must either be 0 or a valid extended 1774 * capability header. 1775 */ 1776 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1777 { 1778 u32 status; 1779 int pos = PCI_CFG_SPACE_SIZE; 1780 1781 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1782 return PCI_CFG_SPACE_SIZE; 1783 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) 1784 return PCI_CFG_SPACE_SIZE; 1785 1786 return PCI_CFG_SPACE_EXP_SIZE; 1787 } 1788 1789 int pci_cfg_space_size(struct pci_dev *dev) 1790 { 1791 int pos; 1792 u32 status; 1793 u16 class; 1794 1795 #ifdef CONFIG_PCI_IOV 1796 /* 1797 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1798 * implement a PCIe capability and therefore must implement extended 1799 * config space. We can skip the NO_EXTCFG test below and the 1800 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1801 * the fact that the SR-IOV capability on the PF resides in extended 1802 * config space and must be accessible and non-aliased to have enabled 1803 * support for this VF. This is a micro performance optimization for 1804 * systems supporting many VFs. 1805 */ 1806 if (dev->is_virtfn) 1807 return PCI_CFG_SPACE_EXP_SIZE; 1808 #endif 1809 1810 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1811 return PCI_CFG_SPACE_SIZE; 1812 1813 class = dev->class >> 8; 1814 if (class == PCI_CLASS_BRIDGE_HOST) 1815 return pci_cfg_space_size_ext(dev); 1816 1817 if (pci_is_pcie(dev)) 1818 return pci_cfg_space_size_ext(dev); 1819 1820 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1821 if (!pos) 1822 return PCI_CFG_SPACE_SIZE; 1823 1824 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1825 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1826 return pci_cfg_space_size_ext(dev); 1827 1828 return PCI_CFG_SPACE_SIZE; 1829 } 1830 1831 static u32 pci_class(struct pci_dev *dev) 1832 { 1833 u32 class; 1834 1835 #ifdef CONFIG_PCI_IOV 1836 if (dev->is_virtfn) 1837 return dev->physfn->sriov->class; 1838 #endif 1839 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1840 return class; 1841 } 1842 1843 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1844 { 1845 #ifdef CONFIG_PCI_IOV 1846 if (dev->is_virtfn) { 1847 *vendor = dev->physfn->sriov->subsystem_vendor; 1848 *device = dev->physfn->sriov->subsystem_device; 1849 return; 1850 } 1851 #endif 1852 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1853 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1854 } 1855 1856 static u8 pci_hdr_type(struct pci_dev *dev) 1857 { 1858 u8 hdr_type; 1859 1860 #ifdef CONFIG_PCI_IOV 1861 if (dev->is_virtfn) 1862 return dev->physfn->sriov->hdr_type; 1863 #endif 1864 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1865 return hdr_type; 1866 } 1867 1868 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1869 1870 /** 1871 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1872 * @dev: PCI device 1873 * 1874 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1875 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1876 */ 1877 static int pci_intx_mask_broken(struct pci_dev *dev) 1878 { 1879 u16 orig, toggle, new; 1880 1881 pci_read_config_word(dev, PCI_COMMAND, &orig); 1882 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1883 pci_write_config_word(dev, PCI_COMMAND, toggle); 1884 pci_read_config_word(dev, PCI_COMMAND, &new); 1885 1886 pci_write_config_word(dev, PCI_COMMAND, orig); 1887 1888 /* 1889 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1890 * r2.3, so strictly speaking, a device is not *broken* if it's not 1891 * writable. But we'll live with the misnomer for now. 1892 */ 1893 if (new != toggle) 1894 return 1; 1895 return 0; 1896 } 1897 1898 static void early_dump_pci_device(struct pci_dev *pdev) 1899 { 1900 u32 value[256 / 4]; 1901 int i; 1902 1903 pci_info(pdev, "config space:\n"); 1904 1905 for (i = 0; i < 256; i += 4) 1906 pci_read_config_dword(pdev, i, &value[i / 4]); 1907 1908 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1909 value, 256, false); 1910 } 1911 1912 static const char *pci_type_str(struct pci_dev *dev) 1913 { 1914 static const char * const str[] = { 1915 "PCIe Endpoint", 1916 "PCIe Legacy Endpoint", 1917 "PCIe unknown", 1918 "PCIe unknown", 1919 "PCIe Root Port", 1920 "PCIe Switch Upstream Port", 1921 "PCIe Switch Downstream Port", 1922 "PCIe to PCI/PCI-X bridge", 1923 "PCI/PCI-X to PCIe bridge", 1924 "PCIe Root Complex Integrated Endpoint", 1925 "PCIe Root Complex Event Collector", 1926 }; 1927 int type; 1928 1929 if (pci_is_pcie(dev)) { 1930 type = pci_pcie_type(dev); 1931 if (type < ARRAY_SIZE(str)) 1932 return str[type]; 1933 1934 return "PCIe unknown"; 1935 } 1936 1937 switch (dev->hdr_type) { 1938 case PCI_HEADER_TYPE_NORMAL: 1939 return "conventional PCI endpoint"; 1940 case PCI_HEADER_TYPE_BRIDGE: 1941 return "conventional PCI bridge"; 1942 case PCI_HEADER_TYPE_CARDBUS: 1943 return "CardBus bridge"; 1944 default: 1945 return "conventional PCI"; 1946 } 1947 } 1948 1949 /** 1950 * pci_setup_device - Fill in class and map information of a device 1951 * @dev: the device structure to fill 1952 * 1953 * Initialize the device structure with information about the device's 1954 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1955 * Called at initialisation of the PCI subsystem and by CardBus services. 1956 * Returns 0 on success and negative if unknown type of device (not normal, 1957 * bridge or CardBus). 1958 */ 1959 int pci_setup_device(struct pci_dev *dev) 1960 { 1961 u32 class; 1962 u16 cmd; 1963 u8 hdr_type; 1964 int err, pos = 0; 1965 struct pci_bus_region region; 1966 struct resource *res; 1967 1968 hdr_type = pci_hdr_type(dev); 1969 1970 dev->sysdata = dev->bus->sysdata; 1971 dev->dev.parent = dev->bus->bridge; 1972 dev->dev.bus = &pci_bus_type; 1973 dev->hdr_type = hdr_type & 0x7f; 1974 dev->multifunction = !!(hdr_type & 0x80); 1975 dev->error_state = pci_channel_io_normal; 1976 set_pcie_port_type(dev); 1977 1978 err = pci_set_of_node(dev); 1979 if (err) 1980 return err; 1981 pci_set_acpi_fwnode(dev); 1982 1983 pci_dev_assign_slot(dev); 1984 1985 /* 1986 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1987 * set this higher, assuming the system even supports it. 1988 */ 1989 dev->dma_mask = 0xffffffff; 1990 1991 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1992 dev->bus->number, PCI_SLOT(dev->devfn), 1993 PCI_FUNC(dev->devfn)); 1994 1995 class = pci_class(dev); 1996 1997 dev->revision = class & 0xff; 1998 dev->class = class >> 8; /* upper 3 bytes */ 1999 2000 if (pci_early_dump) 2001 early_dump_pci_device(dev); 2002 2003 /* Need to have dev->class ready */ 2004 dev->cfg_size = pci_cfg_space_size(dev); 2005 2006 /* Need to have dev->cfg_size ready */ 2007 set_pcie_thunderbolt(dev); 2008 2009 set_pcie_untrusted(dev); 2010 2011 if (pci_is_pcie(dev)) 2012 dev->supported_speeds = pcie_get_supported_speeds(dev); 2013 2014 /* "Unknown power state" */ 2015 dev->current_state = PCI_UNKNOWN; 2016 2017 /* Early fixups, before probing the BARs */ 2018 pci_fixup_device(pci_fixup_early, dev); 2019 2020 pci_set_removable(dev); 2021 2022 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n", 2023 dev->vendor, dev->device, dev->hdr_type, dev->class, 2024 pci_type_str(dev)); 2025 2026 /* Device class may be changed after fixup */ 2027 class = dev->class >> 8; 2028 2029 if (dev->non_compliant_bars && !dev->mmio_always_on) { 2030 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2031 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 2032 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 2033 cmd &= ~PCI_COMMAND_IO; 2034 cmd &= ~PCI_COMMAND_MEMORY; 2035 pci_write_config_word(dev, PCI_COMMAND, cmd); 2036 } 2037 } 2038 2039 dev->broken_intx_masking = pci_intx_mask_broken(dev); 2040 2041 switch (dev->hdr_type) { /* header type */ 2042 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 2043 if (class == PCI_CLASS_BRIDGE_PCI) 2044 goto bad; 2045 pci_read_irq(dev); 2046 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 2047 2048 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 2049 2050 /* 2051 * Do the ugly legacy mode stuff here rather than broken chip 2052 * quirk code. Legacy mode ATA controllers have fixed 2053 * addresses. These are not always echoed in BAR0-3, and 2054 * BAR0-3 in a few cases contain junk! 2055 */ 2056 if (class == PCI_CLASS_STORAGE_IDE) { 2057 u8 progif; 2058 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 2059 if ((progif & 1) == 0) { 2060 region.start = 0x1F0; 2061 region.end = 0x1F7; 2062 res = &dev->resource[0]; 2063 res->flags = LEGACY_IO_RESOURCE; 2064 pcibios_bus_to_resource(dev->bus, res, ®ion); 2065 pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n", 2066 res); 2067 region.start = 0x3F6; 2068 region.end = 0x3F6; 2069 res = &dev->resource[1]; 2070 res->flags = LEGACY_IO_RESOURCE; 2071 pcibios_bus_to_resource(dev->bus, res, ®ion); 2072 pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n", 2073 res); 2074 } 2075 if ((progif & 4) == 0) { 2076 region.start = 0x170; 2077 region.end = 0x177; 2078 res = &dev->resource[2]; 2079 res->flags = LEGACY_IO_RESOURCE; 2080 pcibios_bus_to_resource(dev->bus, res, ®ion); 2081 pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n", 2082 res); 2083 region.start = 0x376; 2084 region.end = 0x376; 2085 res = &dev->resource[3]; 2086 res->flags = LEGACY_IO_RESOURCE; 2087 pcibios_bus_to_resource(dev->bus, res, ®ion); 2088 pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n", 2089 res); 2090 } 2091 } 2092 break; 2093 2094 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 2095 /* 2096 * The PCI-to-PCI bridge spec requires that subtractive 2097 * decoding (i.e. transparent) bridge must have programming 2098 * interface code of 0x01. 2099 */ 2100 pci_read_irq(dev); 2101 dev->transparent = ((dev->class & 0xff) == 1); 2102 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 2103 pci_read_bridge_windows(dev); 2104 set_pcie_hotplug_bridge(dev); 2105 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 2106 if (pos) { 2107 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 2108 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 2109 } 2110 break; 2111 2112 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 2113 if (class != PCI_CLASS_BRIDGE_CARDBUS) 2114 goto bad; 2115 pci_read_irq(dev); 2116 pci_read_bases(dev, 1, 0); 2117 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 2118 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 2119 break; 2120 2121 default: /* unknown header */ 2122 pci_err(dev, "unknown header type %02x, ignoring device\n", 2123 dev->hdr_type); 2124 pci_release_of_node(dev); 2125 return -EIO; 2126 2127 bad: 2128 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 2129 dev->class, dev->hdr_type); 2130 dev->class = PCI_CLASS_NOT_DEFINED << 8; 2131 } 2132 2133 /* We found a fine healthy device, go go go... */ 2134 return 0; 2135 } 2136 2137 static void pci_configure_mps(struct pci_dev *dev) 2138 { 2139 struct pci_dev *bridge = pci_upstream_bridge(dev); 2140 int mps, mpss, p_mps, rc; 2141 2142 if (!pci_is_pcie(dev)) 2143 return; 2144 2145 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 2146 if (dev->is_virtfn) 2147 return; 2148 2149 /* 2150 * For Root Complex Integrated Endpoints, program the maximum 2151 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 2152 */ 2153 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 2154 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2155 mps = 128; 2156 else 2157 mps = 128 << dev->pcie_mpss; 2158 rc = pcie_set_mps(dev, mps); 2159 if (rc) { 2160 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2161 mps); 2162 } 2163 return; 2164 } 2165 2166 if (!bridge || !pci_is_pcie(bridge)) 2167 return; 2168 2169 mps = pcie_get_mps(dev); 2170 p_mps = pcie_get_mps(bridge); 2171 2172 if (mps == p_mps) 2173 return; 2174 2175 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2176 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2177 mps, pci_name(bridge), p_mps); 2178 return; 2179 } 2180 2181 /* 2182 * Fancier MPS configuration is done later by 2183 * pcie_bus_configure_settings() 2184 */ 2185 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2186 return; 2187 2188 mpss = 128 << dev->pcie_mpss; 2189 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2190 pcie_set_mps(bridge, mpss); 2191 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2192 mpss, p_mps, 128 << bridge->pcie_mpss); 2193 p_mps = pcie_get_mps(bridge); 2194 } 2195 2196 rc = pcie_set_mps(dev, p_mps); 2197 if (rc) { 2198 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2199 p_mps); 2200 return; 2201 } 2202 2203 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2204 p_mps, mps, mpss); 2205 } 2206 2207 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2208 { 2209 struct pci_host_bridge *host; 2210 u32 cap; 2211 u16 ctl; 2212 int ret; 2213 2214 if (!pci_is_pcie(dev)) 2215 return 0; 2216 2217 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2218 if (ret) 2219 return 0; 2220 2221 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2222 return 0; 2223 2224 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2225 if (ret) 2226 return 0; 2227 2228 host = pci_find_host_bridge(dev->bus); 2229 if (!host) 2230 return 0; 2231 2232 /* 2233 * If some device in the hierarchy doesn't handle Extended Tags 2234 * correctly, make sure they're disabled. 2235 */ 2236 if (host->no_ext_tags) { 2237 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2238 pci_info(dev, "disabling Extended Tags\n"); 2239 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2240 PCI_EXP_DEVCTL_EXT_TAG); 2241 } 2242 return 0; 2243 } 2244 2245 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2246 pci_info(dev, "enabling Extended Tags\n"); 2247 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2248 PCI_EXP_DEVCTL_EXT_TAG); 2249 } 2250 return 0; 2251 } 2252 2253 /** 2254 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2255 * @dev: PCI device to query 2256 * 2257 * Returns true if the device has enabled relaxed ordering attribute. 2258 */ 2259 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2260 { 2261 u16 v; 2262 2263 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2264 2265 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2266 } 2267 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2268 2269 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2270 { 2271 struct pci_dev *root; 2272 2273 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */ 2274 if (dev->is_virtfn) 2275 return; 2276 2277 if (!pcie_relaxed_ordering_enabled(dev)) 2278 return; 2279 2280 /* 2281 * For now, we only deal with Relaxed Ordering issues with Root 2282 * Ports. Peer-to-Peer DMA is another can of worms. 2283 */ 2284 root = pcie_find_root_port(dev); 2285 if (!root) 2286 return; 2287 2288 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2289 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2290 PCI_EXP_DEVCTL_RELAX_EN); 2291 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2292 } 2293 } 2294 2295 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2296 { 2297 struct pci_dev *bridge; 2298 unsigned int eetlp_max; 2299 int pcie_type; 2300 u32 cap; 2301 2302 if (!pci_is_pcie(dev)) 2303 return; 2304 2305 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2306 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2307 return; 2308 2309 pcie_type = pci_pcie_type(dev); 2310 2311 eetlp_max = FIELD_GET(PCI_EXP_DEVCAP2_EE_PREFIX_MAX, cap); 2312 /* 00b means 4 */ 2313 eetlp_max = eetlp_max ?: 4; 2314 2315 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2316 pcie_type == PCI_EXP_TYPE_RC_END) 2317 dev->eetlp_prefix_max = eetlp_max; 2318 else { 2319 bridge = pci_upstream_bridge(dev); 2320 if (bridge && bridge->eetlp_prefix_max) 2321 dev->eetlp_prefix_max = eetlp_max; 2322 } 2323 } 2324 2325 static void pci_configure_serr(struct pci_dev *dev) 2326 { 2327 u16 control; 2328 2329 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2330 2331 /* 2332 * A bridge will not forward ERR_ messages coming from an 2333 * endpoint unless SERR# forwarding is enabled. 2334 */ 2335 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2336 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2337 control |= PCI_BRIDGE_CTL_SERR; 2338 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2339 } 2340 } 2341 } 2342 2343 static void pci_configure_device(struct pci_dev *dev) 2344 { 2345 pci_configure_mps(dev); 2346 pci_configure_extended_tags(dev, NULL); 2347 pci_configure_relaxed_ordering(dev); 2348 pci_configure_ltr(dev); 2349 pci_configure_aspm_l1ss(dev); 2350 pci_configure_eetlp_prefix(dev); 2351 pci_configure_serr(dev); 2352 2353 pci_acpi_program_hp_params(dev); 2354 } 2355 2356 static void pci_release_capabilities(struct pci_dev *dev) 2357 { 2358 pci_aer_exit(dev); 2359 pci_rcec_exit(dev); 2360 pci_iov_release(dev); 2361 pci_free_cap_save_buffers(dev); 2362 } 2363 2364 /** 2365 * pci_release_dev - Free a PCI device structure when all users of it are 2366 * finished 2367 * @dev: device that's been disconnected 2368 * 2369 * Will be called only by the device core when all users of this PCI device are 2370 * done. 2371 */ 2372 static void pci_release_dev(struct device *dev) 2373 { 2374 struct pci_dev *pci_dev; 2375 2376 pci_dev = to_pci_dev(dev); 2377 pci_release_capabilities(pci_dev); 2378 pci_release_of_node(pci_dev); 2379 pcibios_release_device(pci_dev); 2380 pci_bus_put(pci_dev->bus); 2381 kfree(pci_dev->driver_override); 2382 bitmap_free(pci_dev->dma_alias_mask); 2383 dev_dbg(dev, "device released\n"); 2384 kfree(pci_dev); 2385 } 2386 2387 static const struct device_type pci_dev_type = { 2388 .groups = pci_dev_attr_groups, 2389 }; 2390 2391 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2392 { 2393 struct pci_dev *dev; 2394 2395 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2396 if (!dev) 2397 return NULL; 2398 2399 INIT_LIST_HEAD(&dev->bus_list); 2400 dev->dev.type = &pci_dev_type; 2401 dev->bus = pci_bus_get(bus); 2402 dev->driver_exclusive_resource = (struct resource) { 2403 .name = "PCI Exclusive", 2404 .start = 0, 2405 .end = -1, 2406 }; 2407 2408 spin_lock_init(&dev->pcie_cap_lock); 2409 #ifdef CONFIG_PCI_MSI 2410 raw_spin_lock_init(&dev->msi_lock); 2411 #endif 2412 return dev; 2413 } 2414 EXPORT_SYMBOL(pci_alloc_dev); 2415 2416 static bool pci_bus_wait_rrs(struct pci_bus *bus, int devfn, u32 *l, 2417 int timeout) 2418 { 2419 int delay = 1; 2420 2421 if (!pci_bus_rrs_vendor_id(*l)) 2422 return true; /* not a Configuration RRS completion */ 2423 2424 if (!timeout) 2425 return false; /* RRS, but caller doesn't want to wait */ 2426 2427 /* 2428 * We got the reserved Vendor ID that indicates a completion with 2429 * Configuration Request Retry Status (RRS). Retry until we get a 2430 * valid Vendor ID or we time out. 2431 */ 2432 while (pci_bus_rrs_vendor_id(*l)) { 2433 if (delay > timeout) { 2434 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2435 pci_domain_nr(bus), bus->number, 2436 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2437 2438 return false; 2439 } 2440 if (delay >= 1000) 2441 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2442 pci_domain_nr(bus), bus->number, 2443 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2444 2445 msleep(delay); 2446 delay *= 2; 2447 2448 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2449 return false; 2450 } 2451 2452 if (delay >= 1000) 2453 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2454 pci_domain_nr(bus), bus->number, 2455 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2456 2457 return true; 2458 } 2459 2460 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2461 int timeout) 2462 { 2463 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2464 return false; 2465 2466 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ 2467 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || 2468 *l == 0x0000ffff || *l == 0xffff0000) 2469 return false; 2470 2471 if (pci_bus_rrs_vendor_id(*l)) 2472 return pci_bus_wait_rrs(bus, devfn, l, timeout); 2473 2474 return true; 2475 } 2476 2477 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2478 int timeout) 2479 { 2480 #ifdef CONFIG_PCI_QUIRKS 2481 struct pci_dev *bridge = bus->self; 2482 2483 /* 2484 * Certain IDT switches have an issue where they improperly trigger 2485 * ACS Source Validation errors on completions for config reads. 2486 */ 2487 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2488 bridge->device == 0x80b5) 2489 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2490 #endif 2491 2492 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2493 } 2494 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2495 2496 /* 2497 * Read the config data for a PCI device, sanity-check it, 2498 * and fill in the dev structure. 2499 */ 2500 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2501 { 2502 struct pci_dev *dev; 2503 u32 l; 2504 2505 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2506 return NULL; 2507 2508 dev = pci_alloc_dev(bus); 2509 if (!dev) 2510 return NULL; 2511 2512 dev->devfn = devfn; 2513 dev->vendor = l & 0xffff; 2514 dev->device = (l >> 16) & 0xffff; 2515 2516 if (pci_setup_device(dev)) { 2517 pci_bus_put(dev->bus); 2518 kfree(dev); 2519 return NULL; 2520 } 2521 2522 return dev; 2523 } 2524 2525 void pcie_report_downtraining(struct pci_dev *dev) 2526 { 2527 if (!pci_is_pcie(dev)) 2528 return; 2529 2530 /* Look from the device up to avoid downstream ports with no devices */ 2531 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2532 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2533 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2534 return; 2535 2536 /* Multi-function PCIe devices share the same link/status */ 2537 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2538 return; 2539 2540 /* Print link status only if the device is constrained by the fabric */ 2541 __pcie_print_link_status(dev, false); 2542 } 2543 2544 static void pci_init_capabilities(struct pci_dev *dev) 2545 { 2546 pci_ea_init(dev); /* Enhanced Allocation */ 2547 pci_msi_init(dev); /* Disable MSI */ 2548 pci_msix_init(dev); /* Disable MSI-X */ 2549 2550 /* Buffers for saving PCIe and PCI-X capabilities */ 2551 pci_allocate_cap_save_buffers(dev); 2552 2553 pci_pm_init(dev); /* Power Management */ 2554 pci_vpd_init(dev); /* Vital Product Data */ 2555 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2556 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2557 pci_ats_init(dev); /* Address Translation Services */ 2558 pci_pri_init(dev); /* Page Request Interface */ 2559 pci_pasid_init(dev); /* Process Address Space ID */ 2560 pci_acs_init(dev); /* Access Control Services */ 2561 pci_ptm_init(dev); /* Precision Time Measurement */ 2562 pci_aer_init(dev); /* Advanced Error Reporting */ 2563 pci_dpc_init(dev); /* Downstream Port Containment */ 2564 pci_rcec_init(dev); /* Root Complex Event Collector */ 2565 pci_doe_init(dev); /* Data Object Exchange */ 2566 pci_tph_init(dev); /* TLP Processing Hints */ 2567 2568 pcie_report_downtraining(dev); 2569 pci_init_reset_methods(dev); 2570 } 2571 2572 /* 2573 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2574 * devices. Firmware interfaces that can select the MSI domain on a 2575 * per-device basis should be called from here. 2576 */ 2577 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2578 { 2579 struct irq_domain *d; 2580 2581 /* 2582 * If a domain has been set through the pcibios_device_add() 2583 * callback, then this is the one (platform code knows best). 2584 */ 2585 d = dev_get_msi_domain(&dev->dev); 2586 if (d) 2587 return d; 2588 2589 /* 2590 * Let's see if we have a firmware interface able to provide 2591 * the domain. 2592 */ 2593 d = pci_msi_get_device_domain(dev); 2594 if (d) 2595 return d; 2596 2597 return NULL; 2598 } 2599 2600 static void pci_set_msi_domain(struct pci_dev *dev) 2601 { 2602 struct irq_domain *d; 2603 2604 /* 2605 * If the platform or firmware interfaces cannot supply a 2606 * device-specific MSI domain, then inherit the default domain 2607 * from the host bridge itself. 2608 */ 2609 d = pci_dev_msi_domain(dev); 2610 if (!d) 2611 d = dev_get_msi_domain(&dev->bus->dev); 2612 2613 dev_set_msi_domain(&dev->dev, d); 2614 } 2615 2616 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2617 { 2618 int ret; 2619 2620 pci_configure_device(dev); 2621 2622 device_initialize(&dev->dev); 2623 dev->dev.release = pci_release_dev; 2624 2625 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2626 dev->dev.dma_mask = &dev->dma_mask; 2627 dev->dev.dma_parms = &dev->dma_parms; 2628 dev->dev.coherent_dma_mask = 0xffffffffull; 2629 2630 dma_set_max_seg_size(&dev->dev, 65536); 2631 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2632 2633 pcie_failed_link_retrain(dev); 2634 2635 /* Fix up broken headers */ 2636 pci_fixup_device(pci_fixup_header, dev); 2637 2638 pci_reassigndev_resource_alignment(dev); 2639 2640 dev->state_saved = false; 2641 2642 pci_init_capabilities(dev); 2643 2644 /* 2645 * Add the device to our list of discovered devices 2646 * and the bus list for fixup functions, etc. 2647 */ 2648 down_write(&pci_bus_sem); 2649 list_add_tail(&dev->bus_list, &bus->devices); 2650 up_write(&pci_bus_sem); 2651 2652 ret = pcibios_device_add(dev); 2653 WARN_ON(ret < 0); 2654 2655 /* Set up MSI IRQ domain */ 2656 pci_set_msi_domain(dev); 2657 2658 /* Notifier could use PCI capabilities */ 2659 dev->match_driver = false; 2660 ret = device_add(&dev->dev); 2661 WARN_ON(ret < 0); 2662 2663 pci_npem_create(dev); 2664 } 2665 2666 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2667 { 2668 struct pci_dev *dev; 2669 2670 dev = pci_get_slot(bus, devfn); 2671 if (dev) { 2672 pci_dev_put(dev); 2673 return dev; 2674 } 2675 2676 dev = pci_scan_device(bus, devfn); 2677 if (!dev) 2678 return NULL; 2679 2680 pci_device_add(dev, bus); 2681 2682 return dev; 2683 } 2684 EXPORT_SYMBOL(pci_scan_single_device); 2685 2686 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2687 { 2688 int pos; 2689 u16 cap = 0; 2690 unsigned int next_fn; 2691 2692 if (!dev) 2693 return -ENODEV; 2694 2695 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2696 if (!pos) 2697 return -ENODEV; 2698 2699 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2700 next_fn = PCI_ARI_CAP_NFN(cap); 2701 if (next_fn <= fn) 2702 return -ENODEV; /* protect against malformed list */ 2703 2704 return next_fn; 2705 } 2706 2707 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2708 { 2709 if (pci_ari_enabled(bus)) 2710 return next_ari_fn(bus, dev, fn); 2711 2712 if (fn >= 7) 2713 return -ENODEV; 2714 /* only multifunction devices may have more functions */ 2715 if (dev && !dev->multifunction) 2716 return -ENODEV; 2717 2718 return fn + 1; 2719 } 2720 2721 static int only_one_child(struct pci_bus *bus) 2722 { 2723 struct pci_dev *bridge = bus->self; 2724 2725 /* 2726 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2727 * we scan for all possible devices, not just Device 0. 2728 */ 2729 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2730 return 0; 2731 2732 /* 2733 * A PCIe Downstream Port normally leads to a Link with only Device 2734 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2735 * only for Device 0 in that situation. 2736 */ 2737 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2738 return 1; 2739 2740 return 0; 2741 } 2742 2743 /** 2744 * pci_scan_slot - Scan a PCI slot on a bus for devices 2745 * @bus: PCI bus to scan 2746 * @devfn: slot number to scan (must have zero function) 2747 * 2748 * Scan a PCI slot on the specified PCI bus for devices, adding 2749 * discovered devices to the @bus->devices list. New devices 2750 * will not have is_added set. 2751 * 2752 * Returns the number of new devices found. 2753 */ 2754 int pci_scan_slot(struct pci_bus *bus, int devfn) 2755 { 2756 struct pci_dev *dev; 2757 int fn = 0, nr = 0; 2758 2759 if (only_one_child(bus) && (devfn > 0)) 2760 return 0; /* Already scanned the entire slot */ 2761 2762 do { 2763 dev = pci_scan_single_device(bus, devfn + fn); 2764 if (dev) { 2765 if (!pci_dev_is_added(dev)) 2766 nr++; 2767 if (fn > 0) 2768 dev->multifunction = 1; 2769 } else if (fn == 0) { 2770 /* 2771 * Function 0 is required unless we are running on 2772 * a hypervisor that passes through individual PCI 2773 * functions. 2774 */ 2775 if (!hypervisor_isolated_pci_functions()) 2776 break; 2777 } 2778 fn = next_fn(bus, dev, fn); 2779 } while (fn >= 0); 2780 2781 /* Only one slot has PCIe device */ 2782 if (bus->self && nr) 2783 pcie_aspm_init_link_state(bus->self); 2784 2785 return nr; 2786 } 2787 EXPORT_SYMBOL(pci_scan_slot); 2788 2789 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2790 { 2791 u8 *smpss = data; 2792 2793 if (!pci_is_pcie(dev)) 2794 return 0; 2795 2796 /* 2797 * We don't have a way to change MPS settings on devices that have 2798 * drivers attached. A hot-added device might support only the minimum 2799 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2800 * where devices may be hot-added, we limit the fabric MPS to 128 so 2801 * hot-added devices will work correctly. 2802 * 2803 * However, if we hot-add a device to a slot directly below a Root 2804 * Port, it's impossible for there to be other existing devices below 2805 * the port. We don't limit the MPS in this case because we can 2806 * reconfigure MPS on both the Root Port and the hot-added device, 2807 * and there are no other devices involved. 2808 * 2809 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2810 */ 2811 if (dev->is_hotplug_bridge && 2812 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2813 *smpss = 0; 2814 2815 if (*smpss > dev->pcie_mpss) 2816 *smpss = dev->pcie_mpss; 2817 2818 return 0; 2819 } 2820 2821 static void pcie_write_mps(struct pci_dev *dev, int mps) 2822 { 2823 int rc; 2824 2825 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2826 mps = 128 << dev->pcie_mpss; 2827 2828 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2829 dev->bus->self) 2830 2831 /* 2832 * For "Performance", the assumption is made that 2833 * downstream communication will never be larger than 2834 * the MRRS. So, the MPS only needs to be configured 2835 * for the upstream communication. This being the case, 2836 * walk from the top down and set the MPS of the child 2837 * to that of the parent bus. 2838 * 2839 * Configure the device MPS with the smaller of the 2840 * device MPSS or the bridge MPS (which is assumed to be 2841 * properly configured at this point to the largest 2842 * allowable MPS based on its parent bus). 2843 */ 2844 mps = min(mps, pcie_get_mps(dev->bus->self)); 2845 } 2846 2847 rc = pcie_set_mps(dev, mps); 2848 if (rc) 2849 pci_err(dev, "Failed attempting to set the MPS\n"); 2850 } 2851 2852 static void pcie_write_mrrs(struct pci_dev *dev) 2853 { 2854 int rc, mrrs; 2855 2856 /* 2857 * In the "safe" case, do not configure the MRRS. There appear to be 2858 * issues with setting MRRS to 0 on a number of devices. 2859 */ 2860 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2861 return; 2862 2863 /* 2864 * For max performance, the MRRS must be set to the largest supported 2865 * value. However, it cannot be configured larger than the MPS the 2866 * device or the bus can support. This should already be properly 2867 * configured by a prior call to pcie_write_mps(). 2868 */ 2869 mrrs = pcie_get_mps(dev); 2870 2871 /* 2872 * MRRS is a R/W register. Invalid values can be written, but a 2873 * subsequent read will verify if the value is acceptable or not. 2874 * If the MRRS value provided is not acceptable (e.g., too large), 2875 * shrink the value until it is acceptable to the HW. 2876 */ 2877 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2878 rc = pcie_set_readrq(dev, mrrs); 2879 if (!rc) 2880 break; 2881 2882 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2883 mrrs /= 2; 2884 } 2885 2886 if (mrrs < 128) 2887 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2888 } 2889 2890 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2891 { 2892 int mps, orig_mps; 2893 2894 if (!pci_is_pcie(dev)) 2895 return 0; 2896 2897 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2898 pcie_bus_config == PCIE_BUS_DEFAULT) 2899 return 0; 2900 2901 mps = 128 << *(u8 *)data; 2902 orig_mps = pcie_get_mps(dev); 2903 2904 pcie_write_mps(dev, mps); 2905 pcie_write_mrrs(dev); 2906 2907 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2908 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2909 orig_mps, pcie_get_readrq(dev)); 2910 2911 return 0; 2912 } 2913 2914 /* 2915 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2916 * parents then children fashion. If this changes, then this code will not 2917 * work as designed. 2918 */ 2919 void pcie_bus_configure_settings(struct pci_bus *bus) 2920 { 2921 u8 smpss = 0; 2922 2923 if (!bus->self) 2924 return; 2925 2926 if (!pci_is_pcie(bus->self)) 2927 return; 2928 2929 /* 2930 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2931 * to be aware of the MPS of the destination. To work around this, 2932 * simply force the MPS of the entire system to the smallest possible. 2933 */ 2934 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2935 smpss = 0; 2936 2937 if (pcie_bus_config == PCIE_BUS_SAFE) { 2938 smpss = bus->self->pcie_mpss; 2939 2940 pcie_find_smpss(bus->self, &smpss); 2941 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2942 } 2943 2944 pcie_bus_configure_set(bus->self, &smpss); 2945 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2946 } 2947 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2948 2949 /* 2950 * Called after each bus is probed, but before its children are examined. This 2951 * is marked as __weak because multiple architectures define it. 2952 */ 2953 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2954 { 2955 /* nothing to do, expected to be removed in the future */ 2956 } 2957 2958 /** 2959 * pci_scan_child_bus_extend() - Scan devices below a bus 2960 * @bus: Bus to scan for devices 2961 * @available_buses: Total number of buses available (%0 does not try to 2962 * extend beyond the minimal) 2963 * 2964 * Scans devices below @bus including subordinate buses. Returns new 2965 * subordinate number including all the found devices. Passing 2966 * @available_buses causes the remaining bus space to be distributed 2967 * equally between hotplug-capable bridges to allow future extension of the 2968 * hierarchy. 2969 */ 2970 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2971 unsigned int available_buses) 2972 { 2973 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2974 unsigned int start = bus->busn_res.start; 2975 unsigned int devfn, cmax, max = start; 2976 struct pci_dev *dev; 2977 2978 dev_dbg(&bus->dev, "scanning bus\n"); 2979 2980 /* Go find them, Rover! */ 2981 for (devfn = 0; devfn < 256; devfn += 8) 2982 pci_scan_slot(bus, devfn); 2983 2984 /* Reserve buses for SR-IOV capability */ 2985 used_buses = pci_iov_bus_range(bus); 2986 max += used_buses; 2987 2988 /* 2989 * After performing arch-dependent fixup of the bus, look behind 2990 * all PCI-to-PCI bridges on this bus. 2991 */ 2992 if (!bus->is_added) { 2993 dev_dbg(&bus->dev, "fixups for bus\n"); 2994 pcibios_fixup_bus(bus); 2995 bus->is_added = 1; 2996 } 2997 2998 /* 2999 * Calculate how many hotplug bridges and normal bridges there 3000 * are on this bus. We will distribute the additional available 3001 * buses between hotplug bridges. 3002 */ 3003 for_each_pci_bridge(dev, bus) { 3004 if (dev->is_hotplug_bridge) 3005 hotplug_bridges++; 3006 else 3007 normal_bridges++; 3008 } 3009 3010 /* 3011 * Scan bridges that are already configured. We don't touch them 3012 * unless they are misconfigured (which will be done in the second 3013 * scan below). 3014 */ 3015 for_each_pci_bridge(dev, bus) { 3016 cmax = max; 3017 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 3018 3019 /* 3020 * Reserve one bus for each bridge now to avoid extending 3021 * hotplug bridges too much during the second scan below. 3022 */ 3023 used_buses++; 3024 if (max - cmax > 1) 3025 used_buses += max - cmax - 1; 3026 } 3027 3028 /* Scan bridges that need to be reconfigured */ 3029 for_each_pci_bridge(dev, bus) { 3030 unsigned int buses = 0; 3031 3032 if (!hotplug_bridges && normal_bridges == 1) { 3033 /* 3034 * There is only one bridge on the bus (upstream 3035 * port) so it gets all available buses which it 3036 * can then distribute to the possible hotplug 3037 * bridges below. 3038 */ 3039 buses = available_buses; 3040 } else if (dev->is_hotplug_bridge) { 3041 /* 3042 * Distribute the extra buses between hotplug 3043 * bridges if any. 3044 */ 3045 buses = available_buses / hotplug_bridges; 3046 buses = min(buses, available_buses - used_buses + 1); 3047 } 3048 3049 cmax = max; 3050 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 3051 /* One bus is already accounted so don't add it again */ 3052 if (max - cmax > 1) 3053 used_buses += max - cmax - 1; 3054 } 3055 3056 /* 3057 * Make sure a hotplug bridge has at least the minimum requested 3058 * number of buses but allow it to grow up to the maximum available 3059 * bus number if there is room. 3060 */ 3061 if (bus->self && bus->self->is_hotplug_bridge) { 3062 used_buses = max_t(unsigned int, available_buses, 3063 pci_hotplug_bus_size - 1); 3064 if (max - start < used_buses) { 3065 max = start + used_buses; 3066 3067 /* Do not allocate more buses than we have room left */ 3068 if (max > bus->busn_res.end) 3069 max = bus->busn_res.end; 3070 3071 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 3072 &bus->busn_res, max - start); 3073 } 3074 } 3075 3076 /* 3077 * We've scanned the bus and so we know all about what's on 3078 * the other side of any bridges that may be on this bus plus 3079 * any devices. 3080 * 3081 * Return how far we've got finding sub-buses. 3082 */ 3083 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 3084 return max; 3085 } 3086 3087 /** 3088 * pci_scan_child_bus() - Scan devices below a bus 3089 * @bus: Bus to scan for devices 3090 * 3091 * Scans devices below @bus including subordinate buses. Returns new 3092 * subordinate number including all the found devices. 3093 */ 3094 unsigned int pci_scan_child_bus(struct pci_bus *bus) 3095 { 3096 return pci_scan_child_bus_extend(bus, 0); 3097 } 3098 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3099 3100 /** 3101 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3102 * @bridge: Host bridge to set up 3103 * 3104 * Default empty implementation. Replace with an architecture-specific setup 3105 * routine, if necessary. 3106 */ 3107 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3108 { 3109 return 0; 3110 } 3111 3112 void __weak pcibios_add_bus(struct pci_bus *bus) 3113 { 3114 } 3115 3116 void __weak pcibios_remove_bus(struct pci_bus *bus) 3117 { 3118 } 3119 3120 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3121 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3122 { 3123 int error; 3124 struct pci_host_bridge *bridge; 3125 3126 bridge = pci_alloc_host_bridge(0); 3127 if (!bridge) 3128 return NULL; 3129 3130 bridge->dev.parent = parent; 3131 3132 list_splice_init(resources, &bridge->windows); 3133 bridge->sysdata = sysdata; 3134 bridge->busnr = bus; 3135 bridge->ops = ops; 3136 3137 error = pci_register_host_bridge(bridge); 3138 if (error < 0) 3139 goto err_out; 3140 3141 return bridge->bus; 3142 3143 err_out: 3144 put_device(&bridge->dev); 3145 return NULL; 3146 } 3147 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3148 3149 int pci_host_probe(struct pci_host_bridge *bridge) 3150 { 3151 struct pci_bus *bus, *child; 3152 int ret; 3153 3154 pci_lock_rescan_remove(); 3155 ret = pci_scan_root_bus_bridge(bridge); 3156 pci_unlock_rescan_remove(); 3157 if (ret < 0) { 3158 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3159 return ret; 3160 } 3161 3162 bus = bridge->bus; 3163 3164 /* If we must preserve the resource configuration, claim now */ 3165 if (bridge->preserve_config) 3166 pci_bus_claim_resources(bus); 3167 3168 /* 3169 * Assign whatever was left unassigned. If we didn't claim above, 3170 * this will reassign everything. 3171 */ 3172 pci_assign_unassigned_root_bus_resources(bus); 3173 3174 list_for_each_entry(child, &bus->children, node) 3175 pcie_bus_configure_settings(child); 3176 3177 pci_lock_rescan_remove(); 3178 pci_bus_add_devices(bus); 3179 pci_unlock_rescan_remove(); 3180 3181 /* 3182 * Ensure pm_runtime_enable() is called for the controller drivers 3183 * before calling pci_host_probe(). The PM framework expects that 3184 * if the parent device supports runtime PM, it will be enabled 3185 * before child runtime PM is enabled. 3186 */ 3187 pm_runtime_set_active(&bridge->dev); 3188 pm_runtime_no_callbacks(&bridge->dev); 3189 devm_pm_runtime_enable(&bridge->dev); 3190 3191 return 0; 3192 } 3193 EXPORT_SYMBOL_GPL(pci_host_probe); 3194 3195 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3196 { 3197 struct resource *res = &b->busn_res; 3198 struct resource *parent_res, *conflict; 3199 3200 res->start = bus; 3201 res->end = bus_max; 3202 res->flags = IORESOURCE_BUS; 3203 3204 if (!pci_is_root_bus(b)) 3205 parent_res = &b->parent->busn_res; 3206 else { 3207 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3208 res->flags |= IORESOURCE_PCI_FIXED; 3209 } 3210 3211 conflict = request_resource_conflict(parent_res, res); 3212 3213 if (conflict) 3214 dev_info(&b->dev, 3215 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3216 res, pci_is_root_bus(b) ? "domain " : "", 3217 parent_res, conflict->name, conflict); 3218 3219 return conflict == NULL; 3220 } 3221 3222 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3223 { 3224 struct resource *res = &b->busn_res; 3225 struct resource old_res = *res; 3226 resource_size_t size; 3227 int ret; 3228 3229 if (res->start > bus_max) 3230 return -EINVAL; 3231 3232 size = bus_max - res->start + 1; 3233 ret = adjust_resource(res, res->start, size); 3234 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3235 &old_res, ret ? "can not be" : "is", bus_max); 3236 3237 if (!ret && !res->parent) 3238 pci_bus_insert_busn_res(b, res->start, res->end); 3239 3240 return ret; 3241 } 3242 3243 void pci_bus_release_busn_res(struct pci_bus *b) 3244 { 3245 struct resource *res = &b->busn_res; 3246 int ret; 3247 3248 if (!res->flags || !res->parent) 3249 return; 3250 3251 ret = release_resource(res); 3252 dev_info(&b->dev, "busn_res: %pR %s released\n", 3253 res, ret ? "can not be" : "is"); 3254 } 3255 3256 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3257 { 3258 struct resource_entry *window; 3259 bool found = false; 3260 struct pci_bus *b; 3261 int max, bus, ret; 3262 3263 if (!bridge) 3264 return -EINVAL; 3265 3266 resource_list_for_each_entry(window, &bridge->windows) 3267 if (window->res->flags & IORESOURCE_BUS) { 3268 bridge->busnr = window->res->start; 3269 found = true; 3270 break; 3271 } 3272 3273 ret = pci_register_host_bridge(bridge); 3274 if (ret < 0) 3275 return ret; 3276 3277 b = bridge->bus; 3278 bus = bridge->busnr; 3279 3280 if (!found) { 3281 dev_info(&b->dev, 3282 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3283 bus); 3284 pci_bus_insert_busn_res(b, bus, 255); 3285 } 3286 3287 max = pci_scan_child_bus(b); 3288 3289 if (!found) 3290 pci_bus_update_busn_res_end(b, max); 3291 3292 return 0; 3293 } 3294 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3295 3296 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3297 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3298 { 3299 struct resource_entry *window; 3300 bool found = false; 3301 struct pci_bus *b; 3302 int max; 3303 3304 resource_list_for_each_entry(window, resources) 3305 if (window->res->flags & IORESOURCE_BUS) { 3306 found = true; 3307 break; 3308 } 3309 3310 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3311 if (!b) 3312 return NULL; 3313 3314 if (!found) { 3315 dev_info(&b->dev, 3316 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3317 bus); 3318 pci_bus_insert_busn_res(b, bus, 255); 3319 } 3320 3321 max = pci_scan_child_bus(b); 3322 3323 if (!found) 3324 pci_bus_update_busn_res_end(b, max); 3325 3326 return b; 3327 } 3328 EXPORT_SYMBOL(pci_scan_root_bus); 3329 3330 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3331 void *sysdata) 3332 { 3333 LIST_HEAD(resources); 3334 struct pci_bus *b; 3335 3336 pci_add_resource(&resources, &ioport_resource); 3337 pci_add_resource(&resources, &iomem_resource); 3338 pci_add_resource(&resources, &busn_resource); 3339 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3340 if (b) { 3341 pci_scan_child_bus(b); 3342 } else { 3343 pci_free_resource_list(&resources); 3344 } 3345 return b; 3346 } 3347 EXPORT_SYMBOL(pci_scan_bus); 3348 3349 /** 3350 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3351 * @bridge: PCI bridge for the bus to scan 3352 * 3353 * Scan a PCI bus and child buses for new devices, add them, 3354 * and enable them, resizing bridge mmio/io resource if necessary 3355 * and possible. The caller must ensure the child devices are already 3356 * removed for resizing to occur. 3357 * 3358 * Returns the max number of subordinate bus discovered. 3359 */ 3360 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3361 { 3362 unsigned int max; 3363 struct pci_bus *bus = bridge->subordinate; 3364 3365 max = pci_scan_child_bus(bus); 3366 3367 pci_assign_unassigned_bridge_resources(bridge); 3368 3369 pci_bus_add_devices(bus); 3370 3371 return max; 3372 } 3373 3374 /** 3375 * pci_rescan_bus - Scan a PCI bus for devices 3376 * @bus: PCI bus to scan 3377 * 3378 * Scan a PCI bus and child buses for new devices, add them, 3379 * and enable them. 3380 * 3381 * Returns the max number of subordinate bus discovered. 3382 */ 3383 unsigned int pci_rescan_bus(struct pci_bus *bus) 3384 { 3385 unsigned int max; 3386 3387 max = pci_scan_child_bus(bus); 3388 pci_assign_unassigned_bus_resources(bus); 3389 pci_bus_add_devices(bus); 3390 3391 return max; 3392 } 3393 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3394 3395 /* 3396 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3397 * routines should always be executed under this mutex. 3398 */ 3399 static DEFINE_MUTEX(pci_rescan_remove_lock); 3400 3401 void pci_lock_rescan_remove(void) 3402 { 3403 mutex_lock(&pci_rescan_remove_lock); 3404 } 3405 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3406 3407 void pci_unlock_rescan_remove(void) 3408 { 3409 mutex_unlock(&pci_rescan_remove_lock); 3410 } 3411 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3412 3413 static int __init pci_sort_bf_cmp(const struct device *d_a, 3414 const struct device *d_b) 3415 { 3416 const struct pci_dev *a = to_pci_dev(d_a); 3417 const struct pci_dev *b = to_pci_dev(d_b); 3418 3419 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3420 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3421 3422 if (a->bus->number < b->bus->number) return -1; 3423 else if (a->bus->number > b->bus->number) return 1; 3424 3425 if (a->devfn < b->devfn) return -1; 3426 else if (a->devfn > b->devfn) return 1; 3427 3428 return 0; 3429 } 3430 3431 void __init pci_sort_breadthfirst(void) 3432 { 3433 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3434 } 3435 3436 int pci_hp_add_bridge(struct pci_dev *dev) 3437 { 3438 struct pci_bus *parent = dev->bus; 3439 int busnr, start = parent->busn_res.start; 3440 unsigned int available_buses = 0; 3441 int end = parent->busn_res.end; 3442 3443 for (busnr = start; busnr <= end; busnr++) { 3444 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3445 break; 3446 } 3447 if (busnr-- > end) { 3448 pci_err(dev, "No bus number available for hot-added bridge\n"); 3449 return -1; 3450 } 3451 3452 /* Scan bridges that are already configured */ 3453 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3454 3455 /* 3456 * Distribute the available bus numbers between hotplug-capable 3457 * bridges to make extending the chain later possible. 3458 */ 3459 available_buses = end - busnr; 3460 3461 /* Scan bridges that need to be reconfigured */ 3462 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3463 3464 if (!dev->subordinate) 3465 return -1; 3466 3467 return 0; 3468 } 3469 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3470