1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_pci.h> 12 #include <linux/pci_hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/cpumask.h> 16 #include <linux/aer.h> 17 #include <linux/acpi.h> 18 #include <linux/hypervisor.h> 19 #include <linux/irqdomain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/bitfield.h> 22 #include "pci.h" 23 24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 25 #define CARDBUS_RESERVE_BUSNR 3 26 27 static struct resource busn_resource = { 28 .name = "PCI busn", 29 .start = 0, 30 .end = 255, 31 .flags = IORESOURCE_BUS, 32 }; 33 34 /* Ugh. Need to stop exporting this to modules. */ 35 LIST_HEAD(pci_root_buses); 36 EXPORT_SYMBOL(pci_root_buses); 37 38 static LIST_HEAD(pci_domain_busn_res_list); 39 40 struct pci_domain_busn_res { 41 struct list_head list; 42 struct resource res; 43 int domain_nr; 44 }; 45 46 static struct resource *get_pci_domain_busn_res(int domain_nr) 47 { 48 struct pci_domain_busn_res *r; 49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list) 51 if (r->domain_nr == domain_nr) 52 return &r->res; 53 54 r = kzalloc(sizeof(*r), GFP_KERNEL); 55 if (!r) 56 return NULL; 57 58 r->domain_nr = domain_nr; 59 r->res.start = 0; 60 r->res.end = 0xff; 61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 62 63 list_add_tail(&r->list, &pci_domain_busn_res_list); 64 65 return &r->res; 66 } 67 68 /* 69 * Some device drivers need know if PCI is initiated. 70 * Basically, we think PCI is not initiated when there 71 * is no device to be found on the pci_bus_type. 72 */ 73 int no_pci_devices(void) 74 { 75 struct device *dev; 76 int no_devices; 77 78 dev = bus_find_next_device(&pci_bus_type, NULL); 79 no_devices = (dev == NULL); 80 put_device(dev); 81 return no_devices; 82 } 83 EXPORT_SYMBOL(no_pci_devices); 84 85 /* 86 * PCI Bus Class 87 */ 88 static void release_pcibus_dev(struct device *dev) 89 { 90 struct pci_bus *pci_bus = to_pci_bus(dev); 91 92 put_device(pci_bus->bridge); 93 pci_bus_remove_resources(pci_bus); 94 pci_release_bus_of_node(pci_bus); 95 kfree(pci_bus); 96 } 97 98 static struct class pcibus_class = { 99 .name = "pci_bus", 100 .dev_release = &release_pcibus_dev, 101 .dev_groups = pcibus_groups, 102 }; 103 104 static int __init pcibus_class_init(void) 105 { 106 return class_register(&pcibus_class); 107 } 108 postcore_initcall(pcibus_class_init); 109 110 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 111 { 112 u64 size = mask & maxbase; /* Find the significant bits */ 113 if (!size) 114 return 0; 115 116 /* 117 * Get the lowest of them to find the decode size, and from that 118 * the extent. 119 */ 120 size = size & ~(size-1); 121 122 /* 123 * base == maxbase can be valid only if the BAR has already been 124 * programmed with all 1s. 125 */ 126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 127 return 0; 128 129 return size; 130 } 131 132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 133 { 134 u32 mem_type; 135 unsigned long flags; 136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 139 flags |= IORESOURCE_IO; 140 return flags; 141 } 142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 144 flags |= IORESOURCE_MEM; 145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 146 flags |= IORESOURCE_PREFETCH; 147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 149 switch (mem_type) { 150 case PCI_BASE_ADDRESS_MEM_TYPE_32: 151 break; 152 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 153 /* 1M mem BAR treated as 32-bit BAR */ 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_64: 156 flags |= IORESOURCE_MEM_64; 157 break; 158 default: 159 /* mem unknown type treated as 32-bit BAR */ 160 break; 161 } 162 return flags; 163 } 164 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 167 /** 168 * __pci_read_base - Read a PCI BAR 169 * @dev: the PCI device 170 * @type: type of the BAR 171 * @res: resource buffer to be filled in 172 * @pos: BAR position in the config space 173 * 174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 175 */ 176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 177 struct resource *res, unsigned int pos) 178 { 179 u32 l = 0, sz = 0, mask; 180 u64 l64, sz64, mask64; 181 u16 orig_cmd; 182 struct pci_bus_region region, inverted_region; 183 184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 185 186 /* No printks while decoding is disabled! */ 187 if (!dev->mmio_always_on) { 188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 190 pci_write_config_word(dev, PCI_COMMAND, 191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 192 } 193 } 194 195 res->name = pci_name(dev); 196 197 pci_read_config_dword(dev, pos, &l); 198 pci_write_config_dword(dev, pos, l | mask); 199 pci_read_config_dword(dev, pos, &sz); 200 pci_write_config_dword(dev, pos, l); 201 202 /* 203 * All bits set in sz means the device isn't working properly. 204 * If the BAR isn't implemented, all bits must be 0. If it's a 205 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 206 * 1 must be clear. 207 */ 208 if (PCI_POSSIBLE_ERROR(sz)) 209 sz = 0; 210 211 /* 212 * I don't know how l can have all bits set. Copied from old code. 213 * Maybe it fixes a bug on some ancient platform. 214 */ 215 if (PCI_POSSIBLE_ERROR(l)) 216 l = 0; 217 218 if (type == pci_bar_unknown) { 219 res->flags = decode_bar(dev, l); 220 res->flags |= IORESOURCE_SIZEALIGN; 221 if (res->flags & IORESOURCE_IO) { 222 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 225 } else { 226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 229 } 230 } else { 231 if (l & PCI_ROM_ADDRESS_ENABLE) 232 res->flags |= IORESOURCE_ROM_ENABLE; 233 l64 = l & PCI_ROM_ADDRESS_MASK; 234 sz64 = sz & PCI_ROM_ADDRESS_MASK; 235 mask64 = PCI_ROM_ADDRESS_MASK; 236 } 237 238 if (res->flags & IORESOURCE_MEM_64) { 239 pci_read_config_dword(dev, pos + 4, &l); 240 pci_write_config_dword(dev, pos + 4, ~0); 241 pci_read_config_dword(dev, pos + 4, &sz); 242 pci_write_config_dword(dev, pos + 4, l); 243 244 l64 |= ((u64)l << 32); 245 sz64 |= ((u64)sz << 32); 246 mask64 |= ((u64)~0 << 32); 247 } 248 249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 251 252 if (!sz64) 253 goto fail; 254 255 sz64 = pci_size(l64, sz64, mask64); 256 if (!sz64) { 257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", 258 pos); 259 goto fail; 260 } 261 262 if (res->flags & IORESOURCE_MEM_64) { 263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 264 && sz64 > 0x100000000ULL) { 265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 266 res->start = 0; 267 res->end = 0; 268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", 269 pos, (unsigned long long)sz64); 270 goto out; 271 } 272 273 if ((sizeof(pci_bus_addr_t) < 8) && l) { 274 /* Above 32-bit boundary; try to reallocate */ 275 res->flags |= IORESOURCE_UNSET; 276 res->start = 0; 277 res->end = sz64 - 1; 278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", 279 pos, (unsigned long long)l64); 280 goto out; 281 } 282 } 283 284 region.start = l64; 285 region.end = l64 + sz64 - 1; 286 287 pcibios_bus_to_resource(dev->bus, res, ®ion); 288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 289 290 /* 291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 292 * the corresponding resource address (the physical address used by 293 * the CPU. Converting that resource address back to a bus address 294 * should yield the original BAR value: 295 * 296 * resource_to_bus(bus_to_resource(A)) == A 297 * 298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 299 * be claimed by the device. 300 */ 301 if (inverted_region.start != region.start) { 302 res->flags |= IORESOURCE_UNSET; 303 res->start = 0; 304 res->end = region.end - region.start; 305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", 306 pos, (unsigned long long)region.start); 307 } 308 309 goto out; 310 311 312 fail: 313 res->flags = 0; 314 out: 315 if (res->flags) 316 pci_info(dev, "reg 0x%x: %pR\n", pos, res); 317 318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 319 } 320 321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 322 { 323 unsigned int pos, reg; 324 325 if (dev->non_compliant_bars) 326 return; 327 328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 329 if (dev->is_virtfn) 330 return; 331 332 for (pos = 0; pos < howmany; pos++) { 333 struct resource *res = &dev->resource[pos]; 334 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 336 } 337 338 if (rom) { 339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 340 dev->rom_base_reg = rom; 341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 343 __pci_read_base(dev, pci_bar_mem32, res, rom); 344 } 345 } 346 347 static void pci_read_bridge_windows(struct pci_dev *bridge) 348 { 349 u16 io; 350 u32 pmem, tmp; 351 352 pci_read_config_word(bridge, PCI_IO_BASE, &io); 353 if (!io) { 354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 355 pci_read_config_word(bridge, PCI_IO_BASE, &io); 356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 357 } 358 if (io) 359 bridge->io_window = 1; 360 361 /* 362 * DECchip 21050 pass 2 errata: the bridge may miss an address 363 * disconnect boundary by one PCI data phase. Workaround: do not 364 * use prefetching on this device. 365 */ 366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 367 return; 368 369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 370 if (!pmem) { 371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 372 0xffe0fff0); 373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 375 } 376 if (!pmem) 377 return; 378 379 bridge->pref_window = 1; 380 381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 382 383 /* 384 * Bridge claims to have a 64-bit prefetchable memory 385 * window; verify that the upper bits are actually 386 * writable. 387 */ 388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 390 0xffffffff); 391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 393 if (tmp) 394 bridge->pref_64_window = 1; 395 } 396 } 397 398 static void pci_read_bridge_io(struct pci_bus *child) 399 { 400 struct pci_dev *dev = child->self; 401 u8 io_base_lo, io_limit_lo; 402 unsigned long io_mask, io_granularity, base, limit; 403 struct pci_bus_region region; 404 struct resource *res; 405 406 io_mask = PCI_IO_RANGE_MASK; 407 io_granularity = 0x1000; 408 if (dev->io_window_1k) { 409 /* Support 1K I/O space granularity */ 410 io_mask = PCI_IO_1K_RANGE_MASK; 411 io_granularity = 0x400; 412 } 413 414 res = child->resource[0]; 415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 417 base = (io_base_lo & io_mask) << 8; 418 limit = (io_limit_lo & io_mask) << 8; 419 420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 421 u16 io_base_hi, io_limit_hi; 422 423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 425 base |= ((unsigned long) io_base_hi << 16); 426 limit |= ((unsigned long) io_limit_hi << 16); 427 } 428 429 if (base <= limit) { 430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 431 region.start = base; 432 region.end = limit + io_granularity - 1; 433 pcibios_bus_to_resource(dev->bus, res, ®ion); 434 pci_info(dev, " bridge window %pR\n", res); 435 } 436 } 437 438 static void pci_read_bridge_mmio(struct pci_bus *child) 439 { 440 struct pci_dev *dev = child->self; 441 u16 mem_base_lo, mem_limit_lo; 442 unsigned long base, limit; 443 struct pci_bus_region region; 444 struct resource *res; 445 446 res = child->resource[1]; 447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 451 if (base <= limit) { 452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 453 region.start = base; 454 region.end = limit + 0xfffff; 455 pcibios_bus_to_resource(dev->bus, res, ®ion); 456 pci_info(dev, " bridge window %pR\n", res); 457 } 458 } 459 460 static void pci_read_bridge_mmio_pref(struct pci_bus *child) 461 { 462 struct pci_dev *dev = child->self; 463 u16 mem_base_lo, mem_limit_lo; 464 u64 base64, limit64; 465 pci_bus_addr_t base, limit; 466 struct pci_bus_region region; 467 struct resource *res; 468 469 res = child->resource[2]; 470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 474 475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 476 u32 mem_base_hi, mem_limit_hi; 477 478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 480 481 /* 482 * Some bridges set the base > limit by default, and some 483 * (broken) BIOSes do not initialize them. If we find 484 * this, just assume they are not being used. 485 */ 486 if (mem_base_hi <= mem_limit_hi) { 487 base64 |= (u64) mem_base_hi << 32; 488 limit64 |= (u64) mem_limit_hi << 32; 489 } 490 } 491 492 base = (pci_bus_addr_t) base64; 493 limit = (pci_bus_addr_t) limit64; 494 495 if (base != base64) { 496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 497 (unsigned long long) base64); 498 return; 499 } 500 501 if (base <= limit) { 502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 503 IORESOURCE_MEM | IORESOURCE_PREFETCH; 504 if (res->flags & PCI_PREF_RANGE_TYPE_64) 505 res->flags |= IORESOURCE_MEM_64; 506 region.start = base; 507 region.end = limit + 0xfffff; 508 pcibios_bus_to_resource(dev->bus, res, ®ion); 509 pci_info(dev, " bridge window %pR\n", res); 510 } 511 } 512 513 void pci_read_bridge_bases(struct pci_bus *child) 514 { 515 struct pci_dev *dev = child->self; 516 struct resource *res; 517 int i; 518 519 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 520 return; 521 522 pci_info(dev, "PCI bridge to %pR%s\n", 523 &child->busn_res, 524 dev->transparent ? " (subtractive decode)" : ""); 525 526 pci_bus_remove_resources(child); 527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 529 530 pci_read_bridge_io(child); 531 pci_read_bridge_mmio(child); 532 pci_read_bridge_mmio_pref(child); 533 534 if (dev->transparent) { 535 pci_bus_for_each_resource(child->parent, res) { 536 if (res && res->flags) { 537 pci_bus_add_resource(child, res, 538 PCI_SUBTRACTIVE_DECODE); 539 pci_info(dev, " bridge window %pR (subtractive decode)\n", 540 res); 541 } 542 } 543 } 544 } 545 546 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 547 { 548 struct pci_bus *b; 549 550 b = kzalloc(sizeof(*b), GFP_KERNEL); 551 if (!b) 552 return NULL; 553 554 INIT_LIST_HEAD(&b->node); 555 INIT_LIST_HEAD(&b->children); 556 INIT_LIST_HEAD(&b->devices); 557 INIT_LIST_HEAD(&b->slots); 558 INIT_LIST_HEAD(&b->resources); 559 b->max_bus_speed = PCI_SPEED_UNKNOWN; 560 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 561 #ifdef CONFIG_PCI_DOMAINS_GENERIC 562 if (parent) 563 b->domain_nr = parent->domain_nr; 564 #endif 565 return b; 566 } 567 568 static void pci_release_host_bridge_dev(struct device *dev) 569 { 570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 571 572 if (bridge->release_fn) 573 bridge->release_fn(bridge); 574 575 pci_free_resource_list(&bridge->windows); 576 pci_free_resource_list(&bridge->dma_ranges); 577 kfree(bridge); 578 } 579 580 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 581 { 582 INIT_LIST_HEAD(&bridge->windows); 583 INIT_LIST_HEAD(&bridge->dma_ranges); 584 585 /* 586 * We assume we can manage these PCIe features. Some systems may 587 * reserve these for use by the platform itself, e.g., an ACPI BIOS 588 * may implement its own AER handling and use _OSC to prevent the 589 * OS from interfering. 590 */ 591 bridge->native_aer = 1; 592 bridge->native_pcie_hotplug = 1; 593 bridge->native_shpc_hotplug = 1; 594 bridge->native_pme = 1; 595 bridge->native_ltr = 1; 596 bridge->native_dpc = 1; 597 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 598 bridge->native_cxl_error = 1; 599 600 device_initialize(&bridge->dev); 601 } 602 603 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 604 { 605 struct pci_host_bridge *bridge; 606 607 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 608 if (!bridge) 609 return NULL; 610 611 pci_init_host_bridge(bridge); 612 bridge->dev.release = pci_release_host_bridge_dev; 613 614 return bridge; 615 } 616 EXPORT_SYMBOL(pci_alloc_host_bridge); 617 618 static void devm_pci_alloc_host_bridge_release(void *data) 619 { 620 pci_free_host_bridge(data); 621 } 622 623 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 624 size_t priv) 625 { 626 int ret; 627 struct pci_host_bridge *bridge; 628 629 bridge = pci_alloc_host_bridge(priv); 630 if (!bridge) 631 return NULL; 632 633 bridge->dev.parent = dev; 634 635 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 636 bridge); 637 if (ret) 638 return NULL; 639 640 ret = devm_of_pci_bridge_init(dev, bridge); 641 if (ret) 642 return NULL; 643 644 return bridge; 645 } 646 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 647 648 void pci_free_host_bridge(struct pci_host_bridge *bridge) 649 { 650 put_device(&bridge->dev); 651 } 652 EXPORT_SYMBOL(pci_free_host_bridge); 653 654 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 655 static const unsigned char pcix_bus_speed[] = { 656 PCI_SPEED_UNKNOWN, /* 0 */ 657 PCI_SPEED_66MHz_PCIX, /* 1 */ 658 PCI_SPEED_100MHz_PCIX, /* 2 */ 659 PCI_SPEED_133MHz_PCIX, /* 3 */ 660 PCI_SPEED_UNKNOWN, /* 4 */ 661 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 662 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 663 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 664 PCI_SPEED_UNKNOWN, /* 8 */ 665 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 666 PCI_SPEED_100MHz_PCIX_266, /* A */ 667 PCI_SPEED_133MHz_PCIX_266, /* B */ 668 PCI_SPEED_UNKNOWN, /* C */ 669 PCI_SPEED_66MHz_PCIX_533, /* D */ 670 PCI_SPEED_100MHz_PCIX_533, /* E */ 671 PCI_SPEED_133MHz_PCIX_533 /* F */ 672 }; 673 674 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 675 const unsigned char pcie_link_speed[] = { 676 PCI_SPEED_UNKNOWN, /* 0 */ 677 PCIE_SPEED_2_5GT, /* 1 */ 678 PCIE_SPEED_5_0GT, /* 2 */ 679 PCIE_SPEED_8_0GT, /* 3 */ 680 PCIE_SPEED_16_0GT, /* 4 */ 681 PCIE_SPEED_32_0GT, /* 5 */ 682 PCIE_SPEED_64_0GT, /* 6 */ 683 PCI_SPEED_UNKNOWN, /* 7 */ 684 PCI_SPEED_UNKNOWN, /* 8 */ 685 PCI_SPEED_UNKNOWN, /* 9 */ 686 PCI_SPEED_UNKNOWN, /* A */ 687 PCI_SPEED_UNKNOWN, /* B */ 688 PCI_SPEED_UNKNOWN, /* C */ 689 PCI_SPEED_UNKNOWN, /* D */ 690 PCI_SPEED_UNKNOWN, /* E */ 691 PCI_SPEED_UNKNOWN /* F */ 692 }; 693 EXPORT_SYMBOL_GPL(pcie_link_speed); 694 695 const char *pci_speed_string(enum pci_bus_speed speed) 696 { 697 /* Indexed by the pci_bus_speed enum */ 698 static const char *speed_strings[] = { 699 "33 MHz PCI", /* 0x00 */ 700 "66 MHz PCI", /* 0x01 */ 701 "66 MHz PCI-X", /* 0x02 */ 702 "100 MHz PCI-X", /* 0x03 */ 703 "133 MHz PCI-X", /* 0x04 */ 704 NULL, /* 0x05 */ 705 NULL, /* 0x06 */ 706 NULL, /* 0x07 */ 707 NULL, /* 0x08 */ 708 "66 MHz PCI-X 266", /* 0x09 */ 709 "100 MHz PCI-X 266", /* 0x0a */ 710 "133 MHz PCI-X 266", /* 0x0b */ 711 "Unknown AGP", /* 0x0c */ 712 "1x AGP", /* 0x0d */ 713 "2x AGP", /* 0x0e */ 714 "4x AGP", /* 0x0f */ 715 "8x AGP", /* 0x10 */ 716 "66 MHz PCI-X 533", /* 0x11 */ 717 "100 MHz PCI-X 533", /* 0x12 */ 718 "133 MHz PCI-X 533", /* 0x13 */ 719 "2.5 GT/s PCIe", /* 0x14 */ 720 "5.0 GT/s PCIe", /* 0x15 */ 721 "8.0 GT/s PCIe", /* 0x16 */ 722 "16.0 GT/s PCIe", /* 0x17 */ 723 "32.0 GT/s PCIe", /* 0x18 */ 724 "64.0 GT/s PCIe", /* 0x19 */ 725 }; 726 727 if (speed < ARRAY_SIZE(speed_strings)) 728 return speed_strings[speed]; 729 return "Unknown"; 730 } 731 EXPORT_SYMBOL_GPL(pci_speed_string); 732 733 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 734 { 735 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 736 } 737 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 738 739 static unsigned char agp_speeds[] = { 740 AGP_UNKNOWN, 741 AGP_1X, 742 AGP_2X, 743 AGP_4X, 744 AGP_8X 745 }; 746 747 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 748 { 749 int index = 0; 750 751 if (agpstat & 4) 752 index = 3; 753 else if (agpstat & 2) 754 index = 2; 755 else if (agpstat & 1) 756 index = 1; 757 else 758 goto out; 759 760 if (agp3) { 761 index += 2; 762 if (index == 5) 763 index = 0; 764 } 765 766 out: 767 return agp_speeds[index]; 768 } 769 770 static void pci_set_bus_speed(struct pci_bus *bus) 771 { 772 struct pci_dev *bridge = bus->self; 773 int pos; 774 775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 776 if (!pos) 777 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 778 if (pos) { 779 u32 agpstat, agpcmd; 780 781 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 782 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 783 784 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 785 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 786 } 787 788 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 789 if (pos) { 790 u16 status; 791 enum pci_bus_speed max; 792 793 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 794 &status); 795 796 if (status & PCI_X_SSTATUS_533MHZ) { 797 max = PCI_SPEED_133MHz_PCIX_533; 798 } else if (status & PCI_X_SSTATUS_266MHZ) { 799 max = PCI_SPEED_133MHz_PCIX_266; 800 } else if (status & PCI_X_SSTATUS_133MHZ) { 801 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 802 max = PCI_SPEED_133MHz_PCIX_ECC; 803 else 804 max = PCI_SPEED_133MHz_PCIX; 805 } else { 806 max = PCI_SPEED_66MHz_PCIX; 807 } 808 809 bus->max_bus_speed = max; 810 bus->cur_bus_speed = pcix_bus_speed[ 811 (status & PCI_X_SSTATUS_FREQ) >> 6]; 812 813 return; 814 } 815 816 if (pci_is_pcie(bridge)) { 817 u32 linkcap; 818 u16 linksta; 819 820 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 821 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 822 823 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 824 pcie_update_link_speed(bus, linksta); 825 } 826 } 827 828 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 829 { 830 struct irq_domain *d; 831 832 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 833 d = dev_get_msi_domain(bus->bridge); 834 835 /* 836 * Any firmware interface that can resolve the msi_domain 837 * should be called from here. 838 */ 839 if (!d) 840 d = pci_host_bridge_of_msi_domain(bus); 841 if (!d) 842 d = pci_host_bridge_acpi_msi_domain(bus); 843 844 /* 845 * If no IRQ domain was found via the OF tree, try looking it up 846 * directly through the fwnode_handle. 847 */ 848 if (!d) { 849 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 850 851 if (fwnode) 852 d = irq_find_matching_fwnode(fwnode, 853 DOMAIN_BUS_PCI_MSI); 854 } 855 856 return d; 857 } 858 859 static void pci_set_bus_msi_domain(struct pci_bus *bus) 860 { 861 struct irq_domain *d; 862 struct pci_bus *b; 863 864 /* 865 * The bus can be a root bus, a subordinate bus, or a virtual bus 866 * created by an SR-IOV device. Walk up to the first bridge device 867 * found or derive the domain from the host bridge. 868 */ 869 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 870 if (b->self) 871 d = dev_get_msi_domain(&b->self->dev); 872 } 873 874 if (!d) 875 d = pci_host_bridge_msi_domain(b); 876 877 dev_set_msi_domain(&bus->dev, d); 878 } 879 880 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 881 { 882 struct device *parent = bridge->dev.parent; 883 struct resource_entry *window, *next, *n; 884 struct pci_bus *bus, *b; 885 resource_size_t offset, next_offset; 886 LIST_HEAD(resources); 887 struct resource *res, *next_res; 888 char addr[64], *fmt; 889 const char *name; 890 int err; 891 892 bus = pci_alloc_bus(NULL); 893 if (!bus) 894 return -ENOMEM; 895 896 bridge->bus = bus; 897 898 bus->sysdata = bridge->sysdata; 899 bus->ops = bridge->ops; 900 bus->number = bus->busn_res.start = bridge->busnr; 901 #ifdef CONFIG_PCI_DOMAINS_GENERIC 902 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 903 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 904 else 905 bus->domain_nr = bridge->domain_nr; 906 if (bus->domain_nr < 0) { 907 err = bus->domain_nr; 908 goto free; 909 } 910 #endif 911 912 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 913 if (b) { 914 /* Ignore it if we already got here via a different bridge */ 915 dev_dbg(&b->dev, "bus already known\n"); 916 err = -EEXIST; 917 goto free; 918 } 919 920 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 921 bridge->busnr); 922 923 err = pcibios_root_bridge_prepare(bridge); 924 if (err) 925 goto free; 926 927 /* Temporarily move resources off the list */ 928 list_splice_init(&bridge->windows, &resources); 929 err = device_add(&bridge->dev); 930 if (err) { 931 put_device(&bridge->dev); 932 goto free; 933 } 934 bus->bridge = get_device(&bridge->dev); 935 device_enable_async_suspend(bus->bridge); 936 pci_set_bus_of_node(bus); 937 pci_set_bus_msi_domain(bus); 938 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 939 !pci_host_of_has_msi_map(parent)) 940 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 941 942 if (!parent) 943 set_dev_node(bus->bridge, pcibus_to_node(bus)); 944 945 bus->dev.class = &pcibus_class; 946 bus->dev.parent = bus->bridge; 947 948 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 949 name = dev_name(&bus->dev); 950 951 err = device_register(&bus->dev); 952 if (err) 953 goto unregister; 954 955 pcibios_add_bus(bus); 956 957 if (bus->ops->add_bus) { 958 err = bus->ops->add_bus(bus); 959 if (WARN_ON(err < 0)) 960 dev_err(&bus->dev, "failed to add bus: %d\n", err); 961 } 962 963 /* Create legacy_io and legacy_mem files for this bus */ 964 pci_create_legacy_files(bus); 965 966 if (parent) 967 dev_info(parent, "PCI host bridge to bus %s\n", name); 968 else 969 pr_info("PCI host bridge to bus %s\n", name); 970 971 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 972 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 973 974 /* Coalesce contiguous windows */ 975 resource_list_for_each_entry_safe(window, n, &resources) { 976 if (list_is_last(&window->node, &resources)) 977 break; 978 979 next = list_next_entry(window, node); 980 offset = window->offset; 981 res = window->res; 982 next_offset = next->offset; 983 next_res = next->res; 984 985 if (res->flags != next_res->flags || offset != next_offset) 986 continue; 987 988 if (res->end + 1 == next_res->start) { 989 next_res->start = res->start; 990 res->flags = res->start = res->end = 0; 991 } 992 } 993 994 /* Add initial resources to the bus */ 995 resource_list_for_each_entry_safe(window, n, &resources) { 996 offset = window->offset; 997 res = window->res; 998 if (!res->flags && !res->start && !res->end) { 999 release_resource(res); 1000 continue; 1001 } 1002 1003 list_move_tail(&window->node, &bridge->windows); 1004 1005 if (res->flags & IORESOURCE_BUS) 1006 pci_bus_insert_busn_res(bus, bus->number, res->end); 1007 else 1008 pci_bus_add_resource(bus, res, 0); 1009 1010 if (offset) { 1011 if (resource_type(res) == IORESOURCE_IO) 1012 fmt = " (bus address [%#06llx-%#06llx])"; 1013 else 1014 fmt = " (bus address [%#010llx-%#010llx])"; 1015 1016 snprintf(addr, sizeof(addr), fmt, 1017 (unsigned long long)(res->start - offset), 1018 (unsigned long long)(res->end - offset)); 1019 } else 1020 addr[0] = '\0'; 1021 1022 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 1023 } 1024 1025 down_write(&pci_bus_sem); 1026 list_add_tail(&bus->node, &pci_root_buses); 1027 up_write(&pci_bus_sem); 1028 1029 return 0; 1030 1031 unregister: 1032 put_device(&bridge->dev); 1033 device_del(&bridge->dev); 1034 1035 free: 1036 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1037 pci_bus_release_domain_nr(bus, parent); 1038 #endif 1039 kfree(bus); 1040 return err; 1041 } 1042 1043 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1044 { 1045 int pos; 1046 u32 status; 1047 1048 /* 1049 * If extended config space isn't accessible on a bridge's primary 1050 * bus, we certainly can't access it on the secondary bus. 1051 */ 1052 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1053 return false; 1054 1055 /* 1056 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1057 * extended config space is accessible on the primary, it's also 1058 * accessible on the secondary. 1059 */ 1060 if (pci_is_pcie(bridge) && 1061 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1062 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1063 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1064 return true; 1065 1066 /* 1067 * For the other bridge types: 1068 * - PCI-to-PCI bridges 1069 * - PCIe-to-PCI/PCI-X forward bridges 1070 * - PCI/PCI-X-to-PCIe reverse bridges 1071 * extended config space on the secondary side is only accessible 1072 * if the bridge supports PCI-X Mode 2. 1073 */ 1074 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1075 if (!pos) 1076 return false; 1077 1078 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1079 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1080 } 1081 1082 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1083 struct pci_dev *bridge, int busnr) 1084 { 1085 struct pci_bus *child; 1086 struct pci_host_bridge *host; 1087 int i; 1088 int ret; 1089 1090 /* Allocate a new bus and inherit stuff from the parent */ 1091 child = pci_alloc_bus(parent); 1092 if (!child) 1093 return NULL; 1094 1095 child->parent = parent; 1096 child->sysdata = parent->sysdata; 1097 child->bus_flags = parent->bus_flags; 1098 1099 host = pci_find_host_bridge(parent); 1100 if (host->child_ops) 1101 child->ops = host->child_ops; 1102 else 1103 child->ops = parent->ops; 1104 1105 /* 1106 * Initialize some portions of the bus device, but don't register 1107 * it now as the parent is not properly set up yet. 1108 */ 1109 child->dev.class = &pcibus_class; 1110 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1111 1112 /* Set up the primary, secondary and subordinate bus numbers */ 1113 child->number = child->busn_res.start = busnr; 1114 child->primary = parent->busn_res.start; 1115 child->busn_res.end = 0xff; 1116 1117 if (!bridge) { 1118 child->dev.parent = parent->bridge; 1119 goto add_dev; 1120 } 1121 1122 child->self = bridge; 1123 child->bridge = get_device(&bridge->dev); 1124 child->dev.parent = child->bridge; 1125 pci_set_bus_of_node(child); 1126 pci_set_bus_speed(child); 1127 1128 /* 1129 * Check whether extended config space is accessible on the child 1130 * bus. Note that we currently assume it is always accessible on 1131 * the root bus. 1132 */ 1133 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1134 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1135 pci_info(child, "extended config space not accessible\n"); 1136 } 1137 1138 /* Set up default resource pointers and names */ 1139 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1140 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1141 child->resource[i]->name = child->name; 1142 } 1143 bridge->subordinate = child; 1144 1145 add_dev: 1146 pci_set_bus_msi_domain(child); 1147 ret = device_register(&child->dev); 1148 WARN_ON(ret < 0); 1149 1150 pcibios_add_bus(child); 1151 1152 if (child->ops->add_bus) { 1153 ret = child->ops->add_bus(child); 1154 if (WARN_ON(ret < 0)) 1155 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1156 } 1157 1158 /* Create legacy_io and legacy_mem files for this bus */ 1159 pci_create_legacy_files(child); 1160 1161 return child; 1162 } 1163 1164 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1165 int busnr) 1166 { 1167 struct pci_bus *child; 1168 1169 child = pci_alloc_child_bus(parent, dev, busnr); 1170 if (child) { 1171 down_write(&pci_bus_sem); 1172 list_add_tail(&child->node, &parent->children); 1173 up_write(&pci_bus_sem); 1174 } 1175 return child; 1176 } 1177 EXPORT_SYMBOL(pci_add_new_bus); 1178 1179 static void pci_enable_crs(struct pci_dev *pdev) 1180 { 1181 u16 root_cap = 0; 1182 1183 /* Enable CRS Software Visibility if supported */ 1184 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1185 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1186 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1187 PCI_EXP_RTCTL_CRSSVE); 1188 } 1189 1190 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1191 unsigned int available_buses); 1192 /** 1193 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1194 * numbers from EA capability. 1195 * @dev: Bridge 1196 * @sec: updated with secondary bus number from EA 1197 * @sub: updated with subordinate bus number from EA 1198 * 1199 * If @dev is a bridge with EA capability that specifies valid secondary 1200 * and subordinate bus numbers, return true with the bus numbers in @sec 1201 * and @sub. Otherwise return false. 1202 */ 1203 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1204 { 1205 int ea, offset; 1206 u32 dw; 1207 u8 ea_sec, ea_sub; 1208 1209 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1210 return false; 1211 1212 /* find PCI EA capability in list */ 1213 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1214 if (!ea) 1215 return false; 1216 1217 offset = ea + PCI_EA_FIRST_ENT; 1218 pci_read_config_dword(dev, offset, &dw); 1219 ea_sec = dw & PCI_EA_SEC_BUS_MASK; 1220 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; 1221 if (ea_sec == 0 || ea_sub < ea_sec) 1222 return false; 1223 1224 *sec = ea_sec; 1225 *sub = ea_sub; 1226 return true; 1227 } 1228 1229 /* 1230 * pci_scan_bridge_extend() - Scan buses behind a bridge 1231 * @bus: Parent bus the bridge is on 1232 * @dev: Bridge itself 1233 * @max: Starting subordinate number of buses behind this bridge 1234 * @available_buses: Total number of buses available for this bridge and 1235 * the devices below. After the minimal bus space has 1236 * been allocated the remaining buses will be 1237 * distributed equally between hotplug-capable bridges. 1238 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1239 * that need to be reconfigured. 1240 * 1241 * If it's a bridge, configure it and scan the bus behind it. 1242 * For CardBus bridges, we don't scan behind as the devices will 1243 * be handled by the bridge driver itself. 1244 * 1245 * We need to process bridges in two passes -- first we scan those 1246 * already configured by the BIOS and after we are done with all of 1247 * them, we proceed to assigning numbers to the remaining buses in 1248 * order to avoid overlaps between old and new bus numbers. 1249 * 1250 * Return: New subordinate number covering all buses behind this bridge. 1251 */ 1252 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1253 int max, unsigned int available_buses, 1254 int pass) 1255 { 1256 struct pci_bus *child; 1257 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1258 u32 buses, i, j = 0; 1259 u16 bctl; 1260 u8 primary, secondary, subordinate; 1261 int broken = 0; 1262 bool fixed_buses; 1263 u8 fixed_sec, fixed_sub; 1264 int next_busnr; 1265 1266 /* 1267 * Make sure the bridge is powered on to be able to access config 1268 * space of devices below it. 1269 */ 1270 pm_runtime_get_sync(&dev->dev); 1271 1272 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1273 primary = buses & 0xFF; 1274 secondary = (buses >> 8) & 0xFF; 1275 subordinate = (buses >> 16) & 0xFF; 1276 1277 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1278 secondary, subordinate, pass); 1279 1280 if (!primary && (primary != bus->number) && secondary && subordinate) { 1281 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1282 primary = bus->number; 1283 } 1284 1285 /* Check if setup is sensible at all */ 1286 if (!pass && 1287 (primary != bus->number || secondary <= bus->number || 1288 secondary > subordinate)) { 1289 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1290 secondary, subordinate); 1291 broken = 1; 1292 } 1293 1294 /* 1295 * Disable Master-Abort Mode during probing to avoid reporting of 1296 * bus errors in some architectures. 1297 */ 1298 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1299 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1300 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1301 1302 pci_enable_crs(dev); 1303 1304 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1305 !is_cardbus && !broken) { 1306 unsigned int cmax, buses; 1307 1308 /* 1309 * Bus already configured by firmware, process it in the 1310 * first pass and just note the configuration. 1311 */ 1312 if (pass) 1313 goto out; 1314 1315 /* 1316 * The bus might already exist for two reasons: Either we 1317 * are rescanning the bus or the bus is reachable through 1318 * more than one bridge. The second case can happen with 1319 * the i450NX chipset. 1320 */ 1321 child = pci_find_bus(pci_domain_nr(bus), secondary); 1322 if (!child) { 1323 child = pci_add_new_bus(bus, dev, secondary); 1324 if (!child) 1325 goto out; 1326 child->primary = primary; 1327 pci_bus_insert_busn_res(child, secondary, subordinate); 1328 child->bridge_ctl = bctl; 1329 } 1330 1331 buses = subordinate - secondary; 1332 cmax = pci_scan_child_bus_extend(child, buses); 1333 if (cmax > subordinate) 1334 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1335 subordinate, cmax); 1336 1337 /* Subordinate should equal child->busn_res.end */ 1338 if (subordinate > max) 1339 max = subordinate; 1340 } else { 1341 1342 /* 1343 * We need to assign a number to this bus which we always 1344 * do in the second pass. 1345 */ 1346 if (!pass) { 1347 if (pcibios_assign_all_busses() || broken || is_cardbus) 1348 1349 /* 1350 * Temporarily disable forwarding of the 1351 * configuration cycles on all bridges in 1352 * this bus segment to avoid possible 1353 * conflicts in the second pass between two 1354 * bridges programmed with overlapping bus 1355 * ranges. 1356 */ 1357 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1358 buses & ~0xffffff); 1359 goto out; 1360 } 1361 1362 /* Clear errors */ 1363 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1364 1365 /* Read bus numbers from EA Capability (if present) */ 1366 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1367 if (fixed_buses) 1368 next_busnr = fixed_sec; 1369 else 1370 next_busnr = max + 1; 1371 1372 /* 1373 * Prevent assigning a bus number that already exists. 1374 * This can happen when a bridge is hot-plugged, so in this 1375 * case we only re-scan this bus. 1376 */ 1377 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1378 if (!child) { 1379 child = pci_add_new_bus(bus, dev, next_busnr); 1380 if (!child) 1381 goto out; 1382 pci_bus_insert_busn_res(child, next_busnr, 1383 bus->busn_res.end); 1384 } 1385 max++; 1386 if (available_buses) 1387 available_buses--; 1388 1389 buses = (buses & 0xff000000) 1390 | ((unsigned int)(child->primary) << 0) 1391 | ((unsigned int)(child->busn_res.start) << 8) 1392 | ((unsigned int)(child->busn_res.end) << 16); 1393 1394 /* 1395 * yenta.c forces a secondary latency timer of 176. 1396 * Copy that behaviour here. 1397 */ 1398 if (is_cardbus) { 1399 buses &= ~0xff000000; 1400 buses |= CARDBUS_LATENCY_TIMER << 24; 1401 } 1402 1403 /* We need to blast all three values with a single write */ 1404 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1405 1406 if (!is_cardbus) { 1407 child->bridge_ctl = bctl; 1408 max = pci_scan_child_bus_extend(child, available_buses); 1409 } else { 1410 1411 /* 1412 * For CardBus bridges, we leave 4 bus numbers as 1413 * cards with a PCI-to-PCI bridge can be inserted 1414 * later. 1415 */ 1416 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1417 struct pci_bus *parent = bus; 1418 if (pci_find_bus(pci_domain_nr(bus), 1419 max+i+1)) 1420 break; 1421 while (parent->parent) { 1422 if ((!pcibios_assign_all_busses()) && 1423 (parent->busn_res.end > max) && 1424 (parent->busn_res.end <= max+i)) { 1425 j = 1; 1426 } 1427 parent = parent->parent; 1428 } 1429 if (j) { 1430 1431 /* 1432 * Often, there are two CardBus 1433 * bridges -- try to leave one 1434 * valid bus number for each one. 1435 */ 1436 i /= 2; 1437 break; 1438 } 1439 } 1440 max += i; 1441 } 1442 1443 /* 1444 * Set subordinate bus number to its real value. 1445 * If fixed subordinate bus number exists from EA 1446 * capability then use it. 1447 */ 1448 if (fixed_buses) 1449 max = fixed_sub; 1450 pci_bus_update_busn_res_end(child, max); 1451 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1452 } 1453 1454 sprintf(child->name, 1455 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1456 pci_domain_nr(bus), child->number); 1457 1458 /* Check that all devices are accessible */ 1459 while (bus->parent) { 1460 if ((child->busn_res.end > bus->busn_res.end) || 1461 (child->number > bus->busn_res.end) || 1462 (child->number < bus->number) || 1463 (child->busn_res.end < bus->number)) { 1464 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1465 &child->busn_res); 1466 break; 1467 } 1468 bus = bus->parent; 1469 } 1470 1471 out: 1472 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1473 1474 pm_runtime_put(&dev->dev); 1475 1476 return max; 1477 } 1478 1479 /* 1480 * pci_scan_bridge() - Scan buses behind a bridge 1481 * @bus: Parent bus the bridge is on 1482 * @dev: Bridge itself 1483 * @max: Starting subordinate number of buses behind this bridge 1484 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1485 * that need to be reconfigured. 1486 * 1487 * If it's a bridge, configure it and scan the bus behind it. 1488 * For CardBus bridges, we don't scan behind as the devices will 1489 * be handled by the bridge driver itself. 1490 * 1491 * We need to process bridges in two passes -- first we scan those 1492 * already configured by the BIOS and after we are done with all of 1493 * them, we proceed to assigning numbers to the remaining buses in 1494 * order to avoid overlaps between old and new bus numbers. 1495 * 1496 * Return: New subordinate number covering all buses behind this bridge. 1497 */ 1498 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1499 { 1500 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1501 } 1502 EXPORT_SYMBOL(pci_scan_bridge); 1503 1504 /* 1505 * Read interrupt line and base address registers. 1506 * The architecture-dependent code can tweak these, of course. 1507 */ 1508 static void pci_read_irq(struct pci_dev *dev) 1509 { 1510 unsigned char irq; 1511 1512 /* VFs are not allowed to use INTx, so skip the config reads */ 1513 if (dev->is_virtfn) { 1514 dev->pin = 0; 1515 dev->irq = 0; 1516 return; 1517 } 1518 1519 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1520 dev->pin = irq; 1521 if (irq) 1522 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1523 dev->irq = irq; 1524 } 1525 1526 void set_pcie_port_type(struct pci_dev *pdev) 1527 { 1528 int pos; 1529 u16 reg16; 1530 u32 reg32; 1531 int type; 1532 struct pci_dev *parent; 1533 1534 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1535 if (!pos) 1536 return; 1537 1538 pdev->pcie_cap = pos; 1539 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1540 pdev->pcie_flags_reg = reg16; 1541 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1542 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1543 1544 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); 1545 if (reg32 & PCI_EXP_LNKCAP_DLLLARC) 1546 pdev->link_active_reporting = 1; 1547 1548 parent = pci_upstream_bridge(pdev); 1549 if (!parent) 1550 return; 1551 1552 /* 1553 * Some systems do not identify their upstream/downstream ports 1554 * correctly so detect impossible configurations here and correct 1555 * the port type accordingly. 1556 */ 1557 type = pci_pcie_type(pdev); 1558 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1559 /* 1560 * If pdev claims to be downstream port but the parent 1561 * device is also downstream port assume pdev is actually 1562 * upstream port. 1563 */ 1564 if (pcie_downstream_port(parent)) { 1565 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1566 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1567 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1568 } 1569 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1570 /* 1571 * If pdev claims to be upstream port but the parent 1572 * device is also upstream port assume pdev is actually 1573 * downstream port. 1574 */ 1575 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1576 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1577 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1578 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1579 } 1580 } 1581 } 1582 1583 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1584 { 1585 u32 reg32; 1586 1587 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1588 if (reg32 & PCI_EXP_SLTCAP_HPC) 1589 pdev->is_hotplug_bridge = 1; 1590 } 1591 1592 static void set_pcie_thunderbolt(struct pci_dev *dev) 1593 { 1594 u16 vsec; 1595 1596 /* Is the device part of a Thunderbolt controller? */ 1597 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); 1598 if (vsec) 1599 dev->is_thunderbolt = 1; 1600 } 1601 1602 static void set_pcie_untrusted(struct pci_dev *dev) 1603 { 1604 struct pci_dev *parent; 1605 1606 /* 1607 * If the upstream bridge is untrusted we treat this device 1608 * untrusted as well. 1609 */ 1610 parent = pci_upstream_bridge(dev); 1611 if (parent && (parent->untrusted || parent->external_facing)) 1612 dev->untrusted = true; 1613 } 1614 1615 static void pci_set_removable(struct pci_dev *dev) 1616 { 1617 struct pci_dev *parent = pci_upstream_bridge(dev); 1618 1619 /* 1620 * We (only) consider everything downstream from an external_facing 1621 * device to be removable by the user. We're mainly concerned with 1622 * consumer platforms with user accessible thunderbolt ports that are 1623 * vulnerable to DMA attacks, and we expect those ports to be marked by 1624 * the firmware as external_facing. Devices in traditional hotplug 1625 * slots can technically be removed, but the expectation is that unless 1626 * the port is marked with external_facing, such devices are less 1627 * accessible to user / may not be removed by end user, and thus not 1628 * exposed as "removable" to userspace. 1629 */ 1630 if (parent && 1631 (parent->external_facing || dev_is_removable(&parent->dev))) 1632 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1633 } 1634 1635 /** 1636 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1637 * @dev: PCI device 1638 * 1639 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1640 * when forwarding a type1 configuration request the bridge must check that 1641 * the extended register address field is zero. The bridge is not permitted 1642 * to forward the transactions and must handle it as an Unsupported Request. 1643 * Some bridges do not follow this rule and simply drop the extended register 1644 * bits, resulting in the standard config space being aliased, every 256 1645 * bytes across the entire configuration space. Test for this condition by 1646 * comparing the first dword of each potential alias to the vendor/device ID. 1647 * Known offenders: 1648 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1649 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1650 */ 1651 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1652 { 1653 #ifdef CONFIG_PCI_QUIRKS 1654 int pos; 1655 u32 header, tmp; 1656 1657 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1658 1659 for (pos = PCI_CFG_SPACE_SIZE; 1660 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1661 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL 1662 || header != tmp) 1663 return false; 1664 } 1665 1666 return true; 1667 #else 1668 return false; 1669 #endif 1670 } 1671 1672 /** 1673 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1674 * @dev: PCI device 1675 * 1676 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1677 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1678 * access it. Maybe we don't have a way to generate extended config space 1679 * accesses, or the device is behind a reverse Express bridge. So we try 1680 * reading the dword at 0x100 which must either be 0 or a valid extended 1681 * capability header. 1682 */ 1683 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1684 { 1685 u32 status; 1686 int pos = PCI_CFG_SPACE_SIZE; 1687 1688 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1689 return PCI_CFG_SPACE_SIZE; 1690 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) 1691 return PCI_CFG_SPACE_SIZE; 1692 1693 return PCI_CFG_SPACE_EXP_SIZE; 1694 } 1695 1696 int pci_cfg_space_size(struct pci_dev *dev) 1697 { 1698 int pos; 1699 u32 status; 1700 u16 class; 1701 1702 #ifdef CONFIG_PCI_IOV 1703 /* 1704 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1705 * implement a PCIe capability and therefore must implement extended 1706 * config space. We can skip the NO_EXTCFG test below and the 1707 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1708 * the fact that the SR-IOV capability on the PF resides in extended 1709 * config space and must be accessible and non-aliased to have enabled 1710 * support for this VF. This is a micro performance optimization for 1711 * systems supporting many VFs. 1712 */ 1713 if (dev->is_virtfn) 1714 return PCI_CFG_SPACE_EXP_SIZE; 1715 #endif 1716 1717 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1718 return PCI_CFG_SPACE_SIZE; 1719 1720 class = dev->class >> 8; 1721 if (class == PCI_CLASS_BRIDGE_HOST) 1722 return pci_cfg_space_size_ext(dev); 1723 1724 if (pci_is_pcie(dev)) 1725 return pci_cfg_space_size_ext(dev); 1726 1727 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1728 if (!pos) 1729 return PCI_CFG_SPACE_SIZE; 1730 1731 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1732 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1733 return pci_cfg_space_size_ext(dev); 1734 1735 return PCI_CFG_SPACE_SIZE; 1736 } 1737 1738 static u32 pci_class(struct pci_dev *dev) 1739 { 1740 u32 class; 1741 1742 #ifdef CONFIG_PCI_IOV 1743 if (dev->is_virtfn) 1744 return dev->physfn->sriov->class; 1745 #endif 1746 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1747 return class; 1748 } 1749 1750 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1751 { 1752 #ifdef CONFIG_PCI_IOV 1753 if (dev->is_virtfn) { 1754 *vendor = dev->physfn->sriov->subsystem_vendor; 1755 *device = dev->physfn->sriov->subsystem_device; 1756 return; 1757 } 1758 #endif 1759 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1760 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1761 } 1762 1763 static u8 pci_hdr_type(struct pci_dev *dev) 1764 { 1765 u8 hdr_type; 1766 1767 #ifdef CONFIG_PCI_IOV 1768 if (dev->is_virtfn) 1769 return dev->physfn->sriov->hdr_type; 1770 #endif 1771 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1772 return hdr_type; 1773 } 1774 1775 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1776 1777 /** 1778 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1779 * @dev: PCI device 1780 * 1781 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1782 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1783 */ 1784 static int pci_intx_mask_broken(struct pci_dev *dev) 1785 { 1786 u16 orig, toggle, new; 1787 1788 pci_read_config_word(dev, PCI_COMMAND, &orig); 1789 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1790 pci_write_config_word(dev, PCI_COMMAND, toggle); 1791 pci_read_config_word(dev, PCI_COMMAND, &new); 1792 1793 pci_write_config_word(dev, PCI_COMMAND, orig); 1794 1795 /* 1796 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1797 * r2.3, so strictly speaking, a device is not *broken* if it's not 1798 * writable. But we'll live with the misnomer for now. 1799 */ 1800 if (new != toggle) 1801 return 1; 1802 return 0; 1803 } 1804 1805 static void early_dump_pci_device(struct pci_dev *pdev) 1806 { 1807 u32 value[256 / 4]; 1808 int i; 1809 1810 pci_info(pdev, "config space:\n"); 1811 1812 for (i = 0; i < 256; i += 4) 1813 pci_read_config_dword(pdev, i, &value[i / 4]); 1814 1815 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1816 value, 256, false); 1817 } 1818 1819 /** 1820 * pci_setup_device - Fill in class and map information of a device 1821 * @dev: the device structure to fill 1822 * 1823 * Initialize the device structure with information about the device's 1824 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1825 * Called at initialisation of the PCI subsystem and by CardBus services. 1826 * Returns 0 on success and negative if unknown type of device (not normal, 1827 * bridge or CardBus). 1828 */ 1829 int pci_setup_device(struct pci_dev *dev) 1830 { 1831 u32 class; 1832 u16 cmd; 1833 u8 hdr_type; 1834 int err, pos = 0; 1835 struct pci_bus_region region; 1836 struct resource *res; 1837 1838 hdr_type = pci_hdr_type(dev); 1839 1840 dev->sysdata = dev->bus->sysdata; 1841 dev->dev.parent = dev->bus->bridge; 1842 dev->dev.bus = &pci_bus_type; 1843 dev->hdr_type = hdr_type & 0x7f; 1844 dev->multifunction = !!(hdr_type & 0x80); 1845 dev->error_state = pci_channel_io_normal; 1846 set_pcie_port_type(dev); 1847 1848 err = pci_set_of_node(dev); 1849 if (err) 1850 return err; 1851 pci_set_acpi_fwnode(dev); 1852 1853 pci_dev_assign_slot(dev); 1854 1855 /* 1856 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1857 * set this higher, assuming the system even supports it. 1858 */ 1859 dev->dma_mask = 0xffffffff; 1860 1861 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1862 dev->bus->number, PCI_SLOT(dev->devfn), 1863 PCI_FUNC(dev->devfn)); 1864 1865 class = pci_class(dev); 1866 1867 dev->revision = class & 0xff; 1868 dev->class = class >> 8; /* upper 3 bytes */ 1869 1870 if (pci_early_dump) 1871 early_dump_pci_device(dev); 1872 1873 /* Need to have dev->class ready */ 1874 dev->cfg_size = pci_cfg_space_size(dev); 1875 1876 /* Need to have dev->cfg_size ready */ 1877 set_pcie_thunderbolt(dev); 1878 1879 set_pcie_untrusted(dev); 1880 1881 /* "Unknown power state" */ 1882 dev->current_state = PCI_UNKNOWN; 1883 1884 /* Early fixups, before probing the BARs */ 1885 pci_fixup_device(pci_fixup_early, dev); 1886 1887 pci_set_removable(dev); 1888 1889 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 1890 dev->vendor, dev->device, dev->hdr_type, dev->class); 1891 1892 /* Device class may be changed after fixup */ 1893 class = dev->class >> 8; 1894 1895 if (dev->non_compliant_bars && !dev->mmio_always_on) { 1896 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1897 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1898 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1899 cmd &= ~PCI_COMMAND_IO; 1900 cmd &= ~PCI_COMMAND_MEMORY; 1901 pci_write_config_word(dev, PCI_COMMAND, cmd); 1902 } 1903 } 1904 1905 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1906 1907 switch (dev->hdr_type) { /* header type */ 1908 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1909 if (class == PCI_CLASS_BRIDGE_PCI) 1910 goto bad; 1911 pci_read_irq(dev); 1912 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1913 1914 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1915 1916 /* 1917 * Do the ugly legacy mode stuff here rather than broken chip 1918 * quirk code. Legacy mode ATA controllers have fixed 1919 * addresses. These are not always echoed in BAR0-3, and 1920 * BAR0-3 in a few cases contain junk! 1921 */ 1922 if (class == PCI_CLASS_STORAGE_IDE) { 1923 u8 progif; 1924 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1925 if ((progif & 1) == 0) { 1926 region.start = 0x1F0; 1927 region.end = 0x1F7; 1928 res = &dev->resource[0]; 1929 res->flags = LEGACY_IO_RESOURCE; 1930 pcibios_bus_to_resource(dev->bus, res, ®ion); 1931 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1932 res); 1933 region.start = 0x3F6; 1934 region.end = 0x3F6; 1935 res = &dev->resource[1]; 1936 res->flags = LEGACY_IO_RESOURCE; 1937 pcibios_bus_to_resource(dev->bus, res, ®ion); 1938 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1939 res); 1940 } 1941 if ((progif & 4) == 0) { 1942 region.start = 0x170; 1943 region.end = 0x177; 1944 res = &dev->resource[2]; 1945 res->flags = LEGACY_IO_RESOURCE; 1946 pcibios_bus_to_resource(dev->bus, res, ®ion); 1947 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1948 res); 1949 region.start = 0x376; 1950 region.end = 0x376; 1951 res = &dev->resource[3]; 1952 res->flags = LEGACY_IO_RESOURCE; 1953 pcibios_bus_to_resource(dev->bus, res, ®ion); 1954 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1955 res); 1956 } 1957 } 1958 break; 1959 1960 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1961 /* 1962 * The PCI-to-PCI bridge spec requires that subtractive 1963 * decoding (i.e. transparent) bridge must have programming 1964 * interface code of 0x01. 1965 */ 1966 pci_read_irq(dev); 1967 dev->transparent = ((dev->class & 0xff) == 1); 1968 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1969 pci_read_bridge_windows(dev); 1970 set_pcie_hotplug_bridge(dev); 1971 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1972 if (pos) { 1973 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1974 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1975 } 1976 break; 1977 1978 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1979 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1980 goto bad; 1981 pci_read_irq(dev); 1982 pci_read_bases(dev, 1, 0); 1983 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1984 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1985 break; 1986 1987 default: /* unknown header */ 1988 pci_err(dev, "unknown header type %02x, ignoring device\n", 1989 dev->hdr_type); 1990 pci_release_of_node(dev); 1991 return -EIO; 1992 1993 bad: 1994 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1995 dev->class, dev->hdr_type); 1996 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1997 } 1998 1999 /* We found a fine healthy device, go go go... */ 2000 return 0; 2001 } 2002 2003 static void pci_configure_mps(struct pci_dev *dev) 2004 { 2005 struct pci_dev *bridge = pci_upstream_bridge(dev); 2006 int mps, mpss, p_mps, rc; 2007 2008 if (!pci_is_pcie(dev)) 2009 return; 2010 2011 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 2012 if (dev->is_virtfn) 2013 return; 2014 2015 /* 2016 * For Root Complex Integrated Endpoints, program the maximum 2017 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 2018 */ 2019 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 2020 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2021 mps = 128; 2022 else 2023 mps = 128 << dev->pcie_mpss; 2024 rc = pcie_set_mps(dev, mps); 2025 if (rc) { 2026 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2027 mps); 2028 } 2029 return; 2030 } 2031 2032 if (!bridge || !pci_is_pcie(bridge)) 2033 return; 2034 2035 mps = pcie_get_mps(dev); 2036 p_mps = pcie_get_mps(bridge); 2037 2038 if (mps == p_mps) 2039 return; 2040 2041 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2042 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2043 mps, pci_name(bridge), p_mps); 2044 return; 2045 } 2046 2047 /* 2048 * Fancier MPS configuration is done later by 2049 * pcie_bus_configure_settings() 2050 */ 2051 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2052 return; 2053 2054 mpss = 128 << dev->pcie_mpss; 2055 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2056 pcie_set_mps(bridge, mpss); 2057 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2058 mpss, p_mps, 128 << bridge->pcie_mpss); 2059 p_mps = pcie_get_mps(bridge); 2060 } 2061 2062 rc = pcie_set_mps(dev, p_mps); 2063 if (rc) { 2064 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2065 p_mps); 2066 return; 2067 } 2068 2069 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2070 p_mps, mps, mpss); 2071 } 2072 2073 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2074 { 2075 struct pci_host_bridge *host; 2076 u32 cap; 2077 u16 ctl; 2078 int ret; 2079 2080 if (!pci_is_pcie(dev)) 2081 return 0; 2082 2083 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2084 if (ret) 2085 return 0; 2086 2087 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2088 return 0; 2089 2090 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2091 if (ret) 2092 return 0; 2093 2094 host = pci_find_host_bridge(dev->bus); 2095 if (!host) 2096 return 0; 2097 2098 /* 2099 * If some device in the hierarchy doesn't handle Extended Tags 2100 * correctly, make sure they're disabled. 2101 */ 2102 if (host->no_ext_tags) { 2103 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2104 pci_info(dev, "disabling Extended Tags\n"); 2105 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2106 PCI_EXP_DEVCTL_EXT_TAG); 2107 } 2108 return 0; 2109 } 2110 2111 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2112 pci_info(dev, "enabling Extended Tags\n"); 2113 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2114 PCI_EXP_DEVCTL_EXT_TAG); 2115 } 2116 return 0; 2117 } 2118 2119 /** 2120 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2121 * @dev: PCI device to query 2122 * 2123 * Returns true if the device has enabled relaxed ordering attribute. 2124 */ 2125 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2126 { 2127 u16 v; 2128 2129 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2130 2131 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2132 } 2133 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2134 2135 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2136 { 2137 struct pci_dev *root; 2138 2139 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */ 2140 if (dev->is_virtfn) 2141 return; 2142 2143 if (!pcie_relaxed_ordering_enabled(dev)) 2144 return; 2145 2146 /* 2147 * For now, we only deal with Relaxed Ordering issues with Root 2148 * Ports. Peer-to-Peer DMA is another can of worms. 2149 */ 2150 root = pcie_find_root_port(dev); 2151 if (!root) 2152 return; 2153 2154 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2155 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2156 PCI_EXP_DEVCTL_RELAX_EN); 2157 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2158 } 2159 } 2160 2161 static void pci_configure_ltr(struct pci_dev *dev) 2162 { 2163 #ifdef CONFIG_PCIEASPM 2164 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 2165 struct pci_dev *bridge; 2166 u32 cap, ctl; 2167 2168 if (!pci_is_pcie(dev)) 2169 return; 2170 2171 /* Read L1 PM substate capabilities */ 2172 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); 2173 2174 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2175 if (!(cap & PCI_EXP_DEVCAP2_LTR)) 2176 return; 2177 2178 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); 2179 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { 2180 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2181 dev->ltr_path = 1; 2182 return; 2183 } 2184 2185 bridge = pci_upstream_bridge(dev); 2186 if (bridge && bridge->ltr_path) 2187 dev->ltr_path = 1; 2188 2189 return; 2190 } 2191 2192 if (!host->native_ltr) 2193 return; 2194 2195 /* 2196 * Software must not enable LTR in an Endpoint unless the Root 2197 * Complex and all intermediate Switches indicate support for LTR. 2198 * PCIe r4.0, sec 6.18. 2199 */ 2200 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2201 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2202 PCI_EXP_DEVCTL2_LTR_EN); 2203 dev->ltr_path = 1; 2204 return; 2205 } 2206 2207 /* 2208 * If we're configuring a hot-added device, LTR was likely 2209 * disabled in the upstream bridge, so re-enable it before enabling 2210 * it in the new device. 2211 */ 2212 bridge = pci_upstream_bridge(dev); 2213 if (bridge && bridge->ltr_path) { 2214 pci_bridge_reconfigure_ltr(dev); 2215 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2216 PCI_EXP_DEVCTL2_LTR_EN); 2217 dev->ltr_path = 1; 2218 } 2219 #endif 2220 } 2221 2222 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2223 { 2224 #ifdef CONFIG_PCI_PASID 2225 struct pci_dev *bridge; 2226 int pcie_type; 2227 u32 cap; 2228 2229 if (!pci_is_pcie(dev)) 2230 return; 2231 2232 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2233 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2234 return; 2235 2236 pcie_type = pci_pcie_type(dev); 2237 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2238 pcie_type == PCI_EXP_TYPE_RC_END) 2239 dev->eetlp_prefix_path = 1; 2240 else { 2241 bridge = pci_upstream_bridge(dev); 2242 if (bridge && bridge->eetlp_prefix_path) 2243 dev->eetlp_prefix_path = 1; 2244 } 2245 #endif 2246 } 2247 2248 static void pci_configure_serr(struct pci_dev *dev) 2249 { 2250 u16 control; 2251 2252 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2253 2254 /* 2255 * A bridge will not forward ERR_ messages coming from an 2256 * endpoint unless SERR# forwarding is enabled. 2257 */ 2258 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2259 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2260 control |= PCI_BRIDGE_CTL_SERR; 2261 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2262 } 2263 } 2264 } 2265 2266 static void pci_configure_device(struct pci_dev *dev) 2267 { 2268 pci_configure_mps(dev); 2269 pci_configure_extended_tags(dev, NULL); 2270 pci_configure_relaxed_ordering(dev); 2271 pci_configure_ltr(dev); 2272 pci_configure_eetlp_prefix(dev); 2273 pci_configure_serr(dev); 2274 2275 pci_acpi_program_hp_params(dev); 2276 } 2277 2278 static void pci_release_capabilities(struct pci_dev *dev) 2279 { 2280 pci_aer_exit(dev); 2281 pci_rcec_exit(dev); 2282 pci_iov_release(dev); 2283 pci_free_cap_save_buffers(dev); 2284 } 2285 2286 /** 2287 * pci_release_dev - Free a PCI device structure when all users of it are 2288 * finished 2289 * @dev: device that's been disconnected 2290 * 2291 * Will be called only by the device core when all users of this PCI device are 2292 * done. 2293 */ 2294 static void pci_release_dev(struct device *dev) 2295 { 2296 struct pci_dev *pci_dev; 2297 2298 pci_dev = to_pci_dev(dev); 2299 pci_release_capabilities(pci_dev); 2300 pci_release_of_node(pci_dev); 2301 pcibios_release_device(pci_dev); 2302 pci_bus_put(pci_dev->bus); 2303 kfree(pci_dev->driver_override); 2304 bitmap_free(pci_dev->dma_alias_mask); 2305 dev_dbg(dev, "device released\n"); 2306 kfree(pci_dev); 2307 } 2308 2309 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2310 { 2311 struct pci_dev *dev; 2312 2313 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2314 if (!dev) 2315 return NULL; 2316 2317 INIT_LIST_HEAD(&dev->bus_list); 2318 dev->dev.type = &pci_dev_type; 2319 dev->bus = pci_bus_get(bus); 2320 dev->driver_exclusive_resource = (struct resource) { 2321 .name = "PCI Exclusive", 2322 .start = 0, 2323 .end = -1, 2324 }; 2325 2326 spin_lock_init(&dev->pcie_cap_lock); 2327 #ifdef CONFIG_PCI_MSI 2328 raw_spin_lock_init(&dev->msi_lock); 2329 #endif 2330 return dev; 2331 } 2332 EXPORT_SYMBOL(pci_alloc_dev); 2333 2334 static bool pci_bus_crs_vendor_id(u32 l) 2335 { 2336 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 2337 } 2338 2339 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2340 int timeout) 2341 { 2342 int delay = 1; 2343 2344 if (!pci_bus_crs_vendor_id(*l)) 2345 return true; /* not a CRS completion */ 2346 2347 if (!timeout) 2348 return false; /* CRS, but caller doesn't want to wait */ 2349 2350 /* 2351 * We got the reserved Vendor ID that indicates a completion with 2352 * Configuration Request Retry Status (CRS). Retry until we get a 2353 * valid Vendor ID or we time out. 2354 */ 2355 while (pci_bus_crs_vendor_id(*l)) { 2356 if (delay > timeout) { 2357 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2358 pci_domain_nr(bus), bus->number, 2359 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2360 2361 return false; 2362 } 2363 if (delay >= 1000) 2364 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2365 pci_domain_nr(bus), bus->number, 2366 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2367 2368 msleep(delay); 2369 delay *= 2; 2370 2371 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2372 return false; 2373 } 2374 2375 if (delay >= 1000) 2376 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2377 pci_domain_nr(bus), bus->number, 2378 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2379 2380 return true; 2381 } 2382 2383 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2384 int timeout) 2385 { 2386 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2387 return false; 2388 2389 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ 2390 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || 2391 *l == 0x0000ffff || *l == 0xffff0000) 2392 return false; 2393 2394 if (pci_bus_crs_vendor_id(*l)) 2395 return pci_bus_wait_crs(bus, devfn, l, timeout); 2396 2397 return true; 2398 } 2399 2400 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2401 int timeout) 2402 { 2403 #ifdef CONFIG_PCI_QUIRKS 2404 struct pci_dev *bridge = bus->self; 2405 2406 /* 2407 * Certain IDT switches have an issue where they improperly trigger 2408 * ACS Source Validation errors on completions for config reads. 2409 */ 2410 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2411 bridge->device == 0x80b5) 2412 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2413 #endif 2414 2415 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2416 } 2417 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2418 2419 /* 2420 * Read the config data for a PCI device, sanity-check it, 2421 * and fill in the dev structure. 2422 */ 2423 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2424 { 2425 struct pci_dev *dev; 2426 u32 l; 2427 2428 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2429 return NULL; 2430 2431 dev = pci_alloc_dev(bus); 2432 if (!dev) 2433 return NULL; 2434 2435 dev->devfn = devfn; 2436 dev->vendor = l & 0xffff; 2437 dev->device = (l >> 16) & 0xffff; 2438 2439 if (pci_setup_device(dev)) { 2440 pci_bus_put(dev->bus); 2441 kfree(dev); 2442 return NULL; 2443 } 2444 2445 return dev; 2446 } 2447 2448 void pcie_report_downtraining(struct pci_dev *dev) 2449 { 2450 if (!pci_is_pcie(dev)) 2451 return; 2452 2453 /* Look from the device up to avoid downstream ports with no devices */ 2454 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2455 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2456 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2457 return; 2458 2459 /* Multi-function PCIe devices share the same link/status */ 2460 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2461 return; 2462 2463 /* Print link status only if the device is constrained by the fabric */ 2464 __pcie_print_link_status(dev, false); 2465 } 2466 2467 static void pci_init_capabilities(struct pci_dev *dev) 2468 { 2469 pci_ea_init(dev); /* Enhanced Allocation */ 2470 pci_msi_init(dev); /* Disable MSI */ 2471 pci_msix_init(dev); /* Disable MSI-X */ 2472 2473 /* Buffers for saving PCIe and PCI-X capabilities */ 2474 pci_allocate_cap_save_buffers(dev); 2475 2476 pci_pm_init(dev); /* Power Management */ 2477 pci_vpd_init(dev); /* Vital Product Data */ 2478 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2479 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2480 pci_ats_init(dev); /* Address Translation Services */ 2481 pci_pri_init(dev); /* Page Request Interface */ 2482 pci_pasid_init(dev); /* Process Address Space ID */ 2483 pci_acs_init(dev); /* Access Control Services */ 2484 pci_ptm_init(dev); /* Precision Time Measurement */ 2485 pci_aer_init(dev); /* Advanced Error Reporting */ 2486 pci_dpc_init(dev); /* Downstream Port Containment */ 2487 pci_rcec_init(dev); /* Root Complex Event Collector */ 2488 pci_doe_init(dev); /* Data Object Exchange */ 2489 2490 pcie_report_downtraining(dev); 2491 pci_init_reset_methods(dev); 2492 } 2493 2494 /* 2495 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2496 * devices. Firmware interfaces that can select the MSI domain on a 2497 * per-device basis should be called from here. 2498 */ 2499 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2500 { 2501 struct irq_domain *d; 2502 2503 /* 2504 * If a domain has been set through the pcibios_device_add() 2505 * callback, then this is the one (platform code knows best). 2506 */ 2507 d = dev_get_msi_domain(&dev->dev); 2508 if (d) 2509 return d; 2510 2511 /* 2512 * Let's see if we have a firmware interface able to provide 2513 * the domain. 2514 */ 2515 d = pci_msi_get_device_domain(dev); 2516 if (d) 2517 return d; 2518 2519 return NULL; 2520 } 2521 2522 static void pci_set_msi_domain(struct pci_dev *dev) 2523 { 2524 struct irq_domain *d; 2525 2526 /* 2527 * If the platform or firmware interfaces cannot supply a 2528 * device-specific MSI domain, then inherit the default domain 2529 * from the host bridge itself. 2530 */ 2531 d = pci_dev_msi_domain(dev); 2532 if (!d) 2533 d = dev_get_msi_domain(&dev->bus->dev); 2534 2535 dev_set_msi_domain(&dev->dev, d); 2536 } 2537 2538 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2539 { 2540 int ret; 2541 2542 pci_configure_device(dev); 2543 2544 device_initialize(&dev->dev); 2545 dev->dev.release = pci_release_dev; 2546 2547 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2548 dev->dev.dma_mask = &dev->dma_mask; 2549 dev->dev.dma_parms = &dev->dma_parms; 2550 dev->dev.coherent_dma_mask = 0xffffffffull; 2551 2552 dma_set_max_seg_size(&dev->dev, 65536); 2553 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2554 2555 pcie_failed_link_retrain(dev); 2556 2557 /* Fix up broken headers */ 2558 pci_fixup_device(pci_fixup_header, dev); 2559 2560 pci_reassigndev_resource_alignment(dev); 2561 2562 dev->state_saved = false; 2563 2564 pci_init_capabilities(dev); 2565 2566 /* 2567 * Add the device to our list of discovered devices 2568 * and the bus list for fixup functions, etc. 2569 */ 2570 down_write(&pci_bus_sem); 2571 list_add_tail(&dev->bus_list, &bus->devices); 2572 up_write(&pci_bus_sem); 2573 2574 ret = pcibios_device_add(dev); 2575 WARN_ON(ret < 0); 2576 2577 /* Set up MSI IRQ domain */ 2578 pci_set_msi_domain(dev); 2579 2580 /* Notifier could use PCI capabilities */ 2581 dev->match_driver = false; 2582 ret = device_add(&dev->dev); 2583 WARN_ON(ret < 0); 2584 } 2585 2586 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2587 { 2588 struct pci_dev *dev; 2589 2590 dev = pci_get_slot(bus, devfn); 2591 if (dev) { 2592 pci_dev_put(dev); 2593 return dev; 2594 } 2595 2596 dev = pci_scan_device(bus, devfn); 2597 if (!dev) 2598 return NULL; 2599 2600 pci_device_add(dev, bus); 2601 2602 return dev; 2603 } 2604 EXPORT_SYMBOL(pci_scan_single_device); 2605 2606 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2607 { 2608 int pos; 2609 u16 cap = 0; 2610 unsigned int next_fn; 2611 2612 if (!dev) 2613 return -ENODEV; 2614 2615 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2616 if (!pos) 2617 return -ENODEV; 2618 2619 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2620 next_fn = PCI_ARI_CAP_NFN(cap); 2621 if (next_fn <= fn) 2622 return -ENODEV; /* protect against malformed list */ 2623 2624 return next_fn; 2625 } 2626 2627 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2628 { 2629 if (pci_ari_enabled(bus)) 2630 return next_ari_fn(bus, dev, fn); 2631 2632 if (fn >= 7) 2633 return -ENODEV; 2634 /* only multifunction devices may have more functions */ 2635 if (dev && !dev->multifunction) 2636 return -ENODEV; 2637 2638 return fn + 1; 2639 } 2640 2641 static int only_one_child(struct pci_bus *bus) 2642 { 2643 struct pci_dev *bridge = bus->self; 2644 2645 /* 2646 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2647 * we scan for all possible devices, not just Device 0. 2648 */ 2649 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2650 return 0; 2651 2652 /* 2653 * A PCIe Downstream Port normally leads to a Link with only Device 2654 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2655 * only for Device 0 in that situation. 2656 */ 2657 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2658 return 1; 2659 2660 return 0; 2661 } 2662 2663 /** 2664 * pci_scan_slot - Scan a PCI slot on a bus for devices 2665 * @bus: PCI bus to scan 2666 * @devfn: slot number to scan (must have zero function) 2667 * 2668 * Scan a PCI slot on the specified PCI bus for devices, adding 2669 * discovered devices to the @bus->devices list. New devices 2670 * will not have is_added set. 2671 * 2672 * Returns the number of new devices found. 2673 */ 2674 int pci_scan_slot(struct pci_bus *bus, int devfn) 2675 { 2676 struct pci_dev *dev; 2677 int fn = 0, nr = 0; 2678 2679 if (only_one_child(bus) && (devfn > 0)) 2680 return 0; /* Already scanned the entire slot */ 2681 2682 do { 2683 dev = pci_scan_single_device(bus, devfn + fn); 2684 if (dev) { 2685 if (!pci_dev_is_added(dev)) 2686 nr++; 2687 if (fn > 0) 2688 dev->multifunction = 1; 2689 } else if (fn == 0) { 2690 /* 2691 * Function 0 is required unless we are running on 2692 * a hypervisor that passes through individual PCI 2693 * functions. 2694 */ 2695 if (!hypervisor_isolated_pci_functions()) 2696 break; 2697 } 2698 fn = next_fn(bus, dev, fn); 2699 } while (fn >= 0); 2700 2701 /* Only one slot has PCIe device */ 2702 if (bus->self && nr) 2703 pcie_aspm_init_link_state(bus->self); 2704 2705 return nr; 2706 } 2707 EXPORT_SYMBOL(pci_scan_slot); 2708 2709 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2710 { 2711 u8 *smpss = data; 2712 2713 if (!pci_is_pcie(dev)) 2714 return 0; 2715 2716 /* 2717 * We don't have a way to change MPS settings on devices that have 2718 * drivers attached. A hot-added device might support only the minimum 2719 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2720 * where devices may be hot-added, we limit the fabric MPS to 128 so 2721 * hot-added devices will work correctly. 2722 * 2723 * However, if we hot-add a device to a slot directly below a Root 2724 * Port, it's impossible for there to be other existing devices below 2725 * the port. We don't limit the MPS in this case because we can 2726 * reconfigure MPS on both the Root Port and the hot-added device, 2727 * and there are no other devices involved. 2728 * 2729 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2730 */ 2731 if (dev->is_hotplug_bridge && 2732 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2733 *smpss = 0; 2734 2735 if (*smpss > dev->pcie_mpss) 2736 *smpss = dev->pcie_mpss; 2737 2738 return 0; 2739 } 2740 2741 static void pcie_write_mps(struct pci_dev *dev, int mps) 2742 { 2743 int rc; 2744 2745 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2746 mps = 128 << dev->pcie_mpss; 2747 2748 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2749 dev->bus->self) 2750 2751 /* 2752 * For "Performance", the assumption is made that 2753 * downstream communication will never be larger than 2754 * the MRRS. So, the MPS only needs to be configured 2755 * for the upstream communication. This being the case, 2756 * walk from the top down and set the MPS of the child 2757 * to that of the parent bus. 2758 * 2759 * Configure the device MPS with the smaller of the 2760 * device MPSS or the bridge MPS (which is assumed to be 2761 * properly configured at this point to the largest 2762 * allowable MPS based on its parent bus). 2763 */ 2764 mps = min(mps, pcie_get_mps(dev->bus->self)); 2765 } 2766 2767 rc = pcie_set_mps(dev, mps); 2768 if (rc) 2769 pci_err(dev, "Failed attempting to set the MPS\n"); 2770 } 2771 2772 static void pcie_write_mrrs(struct pci_dev *dev) 2773 { 2774 int rc, mrrs; 2775 2776 /* 2777 * In the "safe" case, do not configure the MRRS. There appear to be 2778 * issues with setting MRRS to 0 on a number of devices. 2779 */ 2780 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2781 return; 2782 2783 /* 2784 * For max performance, the MRRS must be set to the largest supported 2785 * value. However, it cannot be configured larger than the MPS the 2786 * device or the bus can support. This should already be properly 2787 * configured by a prior call to pcie_write_mps(). 2788 */ 2789 mrrs = pcie_get_mps(dev); 2790 2791 /* 2792 * MRRS is a R/W register. Invalid values can be written, but a 2793 * subsequent read will verify if the value is acceptable or not. 2794 * If the MRRS value provided is not acceptable (e.g., too large), 2795 * shrink the value until it is acceptable to the HW. 2796 */ 2797 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2798 rc = pcie_set_readrq(dev, mrrs); 2799 if (!rc) 2800 break; 2801 2802 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2803 mrrs /= 2; 2804 } 2805 2806 if (mrrs < 128) 2807 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2808 } 2809 2810 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2811 { 2812 int mps, orig_mps; 2813 2814 if (!pci_is_pcie(dev)) 2815 return 0; 2816 2817 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2818 pcie_bus_config == PCIE_BUS_DEFAULT) 2819 return 0; 2820 2821 mps = 128 << *(u8 *)data; 2822 orig_mps = pcie_get_mps(dev); 2823 2824 pcie_write_mps(dev, mps); 2825 pcie_write_mrrs(dev); 2826 2827 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2828 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2829 orig_mps, pcie_get_readrq(dev)); 2830 2831 return 0; 2832 } 2833 2834 /* 2835 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2836 * parents then children fashion. If this changes, then this code will not 2837 * work as designed. 2838 */ 2839 void pcie_bus_configure_settings(struct pci_bus *bus) 2840 { 2841 u8 smpss = 0; 2842 2843 if (!bus->self) 2844 return; 2845 2846 if (!pci_is_pcie(bus->self)) 2847 return; 2848 2849 /* 2850 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2851 * to be aware of the MPS of the destination. To work around this, 2852 * simply force the MPS of the entire system to the smallest possible. 2853 */ 2854 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2855 smpss = 0; 2856 2857 if (pcie_bus_config == PCIE_BUS_SAFE) { 2858 smpss = bus->self->pcie_mpss; 2859 2860 pcie_find_smpss(bus->self, &smpss); 2861 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2862 } 2863 2864 pcie_bus_configure_set(bus->self, &smpss); 2865 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2866 } 2867 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2868 2869 /* 2870 * Called after each bus is probed, but before its children are examined. This 2871 * is marked as __weak because multiple architectures define it. 2872 */ 2873 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2874 { 2875 /* nothing to do, expected to be removed in the future */ 2876 } 2877 2878 /** 2879 * pci_scan_child_bus_extend() - Scan devices below a bus 2880 * @bus: Bus to scan for devices 2881 * @available_buses: Total number of buses available (%0 does not try to 2882 * extend beyond the minimal) 2883 * 2884 * Scans devices below @bus including subordinate buses. Returns new 2885 * subordinate number including all the found devices. Passing 2886 * @available_buses causes the remaining bus space to be distributed 2887 * equally between hotplug-capable bridges to allow future extension of the 2888 * hierarchy. 2889 */ 2890 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2891 unsigned int available_buses) 2892 { 2893 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2894 unsigned int start = bus->busn_res.start; 2895 unsigned int devfn, cmax, max = start; 2896 struct pci_dev *dev; 2897 2898 dev_dbg(&bus->dev, "scanning bus\n"); 2899 2900 /* Go find them, Rover! */ 2901 for (devfn = 0; devfn < 256; devfn += 8) 2902 pci_scan_slot(bus, devfn); 2903 2904 /* Reserve buses for SR-IOV capability */ 2905 used_buses = pci_iov_bus_range(bus); 2906 max += used_buses; 2907 2908 /* 2909 * After performing arch-dependent fixup of the bus, look behind 2910 * all PCI-to-PCI bridges on this bus. 2911 */ 2912 if (!bus->is_added) { 2913 dev_dbg(&bus->dev, "fixups for bus\n"); 2914 pcibios_fixup_bus(bus); 2915 bus->is_added = 1; 2916 } 2917 2918 /* 2919 * Calculate how many hotplug bridges and normal bridges there 2920 * are on this bus. We will distribute the additional available 2921 * buses between hotplug bridges. 2922 */ 2923 for_each_pci_bridge(dev, bus) { 2924 if (dev->is_hotplug_bridge) 2925 hotplug_bridges++; 2926 else 2927 normal_bridges++; 2928 } 2929 2930 /* 2931 * Scan bridges that are already configured. We don't touch them 2932 * unless they are misconfigured (which will be done in the second 2933 * scan below). 2934 */ 2935 for_each_pci_bridge(dev, bus) { 2936 cmax = max; 2937 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2938 2939 /* 2940 * Reserve one bus for each bridge now to avoid extending 2941 * hotplug bridges too much during the second scan below. 2942 */ 2943 used_buses++; 2944 if (max - cmax > 1) 2945 used_buses += max - cmax - 1; 2946 } 2947 2948 /* Scan bridges that need to be reconfigured */ 2949 for_each_pci_bridge(dev, bus) { 2950 unsigned int buses = 0; 2951 2952 if (!hotplug_bridges && normal_bridges == 1) { 2953 /* 2954 * There is only one bridge on the bus (upstream 2955 * port) so it gets all available buses which it 2956 * can then distribute to the possible hotplug 2957 * bridges below. 2958 */ 2959 buses = available_buses; 2960 } else if (dev->is_hotplug_bridge) { 2961 /* 2962 * Distribute the extra buses between hotplug 2963 * bridges if any. 2964 */ 2965 buses = available_buses / hotplug_bridges; 2966 buses = min(buses, available_buses - used_buses + 1); 2967 } 2968 2969 cmax = max; 2970 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2971 /* One bus is already accounted so don't add it again */ 2972 if (max - cmax > 1) 2973 used_buses += max - cmax - 1; 2974 } 2975 2976 /* 2977 * Make sure a hotplug bridge has at least the minimum requested 2978 * number of buses but allow it to grow up to the maximum available 2979 * bus number if there is room. 2980 */ 2981 if (bus->self && bus->self->is_hotplug_bridge) { 2982 used_buses = max_t(unsigned int, available_buses, 2983 pci_hotplug_bus_size - 1); 2984 if (max - start < used_buses) { 2985 max = start + used_buses; 2986 2987 /* Do not allocate more buses than we have room left */ 2988 if (max > bus->busn_res.end) 2989 max = bus->busn_res.end; 2990 2991 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 2992 &bus->busn_res, max - start); 2993 } 2994 } 2995 2996 /* 2997 * We've scanned the bus and so we know all about what's on 2998 * the other side of any bridges that may be on this bus plus 2999 * any devices. 3000 * 3001 * Return how far we've got finding sub-buses. 3002 */ 3003 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 3004 return max; 3005 } 3006 3007 /** 3008 * pci_scan_child_bus() - Scan devices below a bus 3009 * @bus: Bus to scan for devices 3010 * 3011 * Scans devices below @bus including subordinate buses. Returns new 3012 * subordinate number including all the found devices. 3013 */ 3014 unsigned int pci_scan_child_bus(struct pci_bus *bus) 3015 { 3016 return pci_scan_child_bus_extend(bus, 0); 3017 } 3018 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3019 3020 /** 3021 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3022 * @bridge: Host bridge to set up 3023 * 3024 * Default empty implementation. Replace with an architecture-specific setup 3025 * routine, if necessary. 3026 */ 3027 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3028 { 3029 return 0; 3030 } 3031 3032 void __weak pcibios_add_bus(struct pci_bus *bus) 3033 { 3034 } 3035 3036 void __weak pcibios_remove_bus(struct pci_bus *bus) 3037 { 3038 } 3039 3040 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3041 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3042 { 3043 int error; 3044 struct pci_host_bridge *bridge; 3045 3046 bridge = pci_alloc_host_bridge(0); 3047 if (!bridge) 3048 return NULL; 3049 3050 bridge->dev.parent = parent; 3051 3052 list_splice_init(resources, &bridge->windows); 3053 bridge->sysdata = sysdata; 3054 bridge->busnr = bus; 3055 bridge->ops = ops; 3056 3057 error = pci_register_host_bridge(bridge); 3058 if (error < 0) 3059 goto err_out; 3060 3061 return bridge->bus; 3062 3063 err_out: 3064 put_device(&bridge->dev); 3065 return NULL; 3066 } 3067 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3068 3069 int pci_host_probe(struct pci_host_bridge *bridge) 3070 { 3071 struct pci_bus *bus, *child; 3072 int ret; 3073 3074 ret = pci_scan_root_bus_bridge(bridge); 3075 if (ret < 0) { 3076 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3077 return ret; 3078 } 3079 3080 bus = bridge->bus; 3081 3082 /* 3083 * We insert PCI resources into the iomem_resource and 3084 * ioport_resource trees in either pci_bus_claim_resources() 3085 * or pci_bus_assign_resources(). 3086 */ 3087 if (pci_has_flag(PCI_PROBE_ONLY)) { 3088 pci_bus_claim_resources(bus); 3089 } else { 3090 pci_bus_size_bridges(bus); 3091 pci_bus_assign_resources(bus); 3092 3093 list_for_each_entry(child, &bus->children, node) 3094 pcie_bus_configure_settings(child); 3095 } 3096 3097 pci_bus_add_devices(bus); 3098 return 0; 3099 } 3100 EXPORT_SYMBOL_GPL(pci_host_probe); 3101 3102 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3103 { 3104 struct resource *res = &b->busn_res; 3105 struct resource *parent_res, *conflict; 3106 3107 res->start = bus; 3108 res->end = bus_max; 3109 res->flags = IORESOURCE_BUS; 3110 3111 if (!pci_is_root_bus(b)) 3112 parent_res = &b->parent->busn_res; 3113 else { 3114 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3115 res->flags |= IORESOURCE_PCI_FIXED; 3116 } 3117 3118 conflict = request_resource_conflict(parent_res, res); 3119 3120 if (conflict) 3121 dev_info(&b->dev, 3122 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3123 res, pci_is_root_bus(b) ? "domain " : "", 3124 parent_res, conflict->name, conflict); 3125 3126 return conflict == NULL; 3127 } 3128 3129 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3130 { 3131 struct resource *res = &b->busn_res; 3132 struct resource old_res = *res; 3133 resource_size_t size; 3134 int ret; 3135 3136 if (res->start > bus_max) 3137 return -EINVAL; 3138 3139 size = bus_max - res->start + 1; 3140 ret = adjust_resource(res, res->start, size); 3141 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3142 &old_res, ret ? "can not be" : "is", bus_max); 3143 3144 if (!ret && !res->parent) 3145 pci_bus_insert_busn_res(b, res->start, res->end); 3146 3147 return ret; 3148 } 3149 3150 void pci_bus_release_busn_res(struct pci_bus *b) 3151 { 3152 struct resource *res = &b->busn_res; 3153 int ret; 3154 3155 if (!res->flags || !res->parent) 3156 return; 3157 3158 ret = release_resource(res); 3159 dev_info(&b->dev, "busn_res: %pR %s released\n", 3160 res, ret ? "can not be" : "is"); 3161 } 3162 3163 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3164 { 3165 struct resource_entry *window; 3166 bool found = false; 3167 struct pci_bus *b; 3168 int max, bus, ret; 3169 3170 if (!bridge) 3171 return -EINVAL; 3172 3173 resource_list_for_each_entry(window, &bridge->windows) 3174 if (window->res->flags & IORESOURCE_BUS) { 3175 bridge->busnr = window->res->start; 3176 found = true; 3177 break; 3178 } 3179 3180 ret = pci_register_host_bridge(bridge); 3181 if (ret < 0) 3182 return ret; 3183 3184 b = bridge->bus; 3185 bus = bridge->busnr; 3186 3187 if (!found) { 3188 dev_info(&b->dev, 3189 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3190 bus); 3191 pci_bus_insert_busn_res(b, bus, 255); 3192 } 3193 3194 max = pci_scan_child_bus(b); 3195 3196 if (!found) 3197 pci_bus_update_busn_res_end(b, max); 3198 3199 return 0; 3200 } 3201 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3202 3203 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3204 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3205 { 3206 struct resource_entry *window; 3207 bool found = false; 3208 struct pci_bus *b; 3209 int max; 3210 3211 resource_list_for_each_entry(window, resources) 3212 if (window->res->flags & IORESOURCE_BUS) { 3213 found = true; 3214 break; 3215 } 3216 3217 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3218 if (!b) 3219 return NULL; 3220 3221 if (!found) { 3222 dev_info(&b->dev, 3223 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3224 bus); 3225 pci_bus_insert_busn_res(b, bus, 255); 3226 } 3227 3228 max = pci_scan_child_bus(b); 3229 3230 if (!found) 3231 pci_bus_update_busn_res_end(b, max); 3232 3233 return b; 3234 } 3235 EXPORT_SYMBOL(pci_scan_root_bus); 3236 3237 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3238 void *sysdata) 3239 { 3240 LIST_HEAD(resources); 3241 struct pci_bus *b; 3242 3243 pci_add_resource(&resources, &ioport_resource); 3244 pci_add_resource(&resources, &iomem_resource); 3245 pci_add_resource(&resources, &busn_resource); 3246 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3247 if (b) { 3248 pci_scan_child_bus(b); 3249 } else { 3250 pci_free_resource_list(&resources); 3251 } 3252 return b; 3253 } 3254 EXPORT_SYMBOL(pci_scan_bus); 3255 3256 /** 3257 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3258 * @bridge: PCI bridge for the bus to scan 3259 * 3260 * Scan a PCI bus and child buses for new devices, add them, 3261 * and enable them, resizing bridge mmio/io resource if necessary 3262 * and possible. The caller must ensure the child devices are already 3263 * removed for resizing to occur. 3264 * 3265 * Returns the max number of subordinate bus discovered. 3266 */ 3267 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3268 { 3269 unsigned int max; 3270 struct pci_bus *bus = bridge->subordinate; 3271 3272 max = pci_scan_child_bus(bus); 3273 3274 pci_assign_unassigned_bridge_resources(bridge); 3275 3276 pci_bus_add_devices(bus); 3277 3278 return max; 3279 } 3280 3281 /** 3282 * pci_rescan_bus - Scan a PCI bus for devices 3283 * @bus: PCI bus to scan 3284 * 3285 * Scan a PCI bus and child buses for new devices, add them, 3286 * and enable them. 3287 * 3288 * Returns the max number of subordinate bus discovered. 3289 */ 3290 unsigned int pci_rescan_bus(struct pci_bus *bus) 3291 { 3292 unsigned int max; 3293 3294 max = pci_scan_child_bus(bus); 3295 pci_assign_unassigned_bus_resources(bus); 3296 pci_bus_add_devices(bus); 3297 3298 return max; 3299 } 3300 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3301 3302 /* 3303 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3304 * routines should always be executed under this mutex. 3305 */ 3306 static DEFINE_MUTEX(pci_rescan_remove_lock); 3307 3308 void pci_lock_rescan_remove(void) 3309 { 3310 mutex_lock(&pci_rescan_remove_lock); 3311 } 3312 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3313 3314 void pci_unlock_rescan_remove(void) 3315 { 3316 mutex_unlock(&pci_rescan_remove_lock); 3317 } 3318 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3319 3320 static int __init pci_sort_bf_cmp(const struct device *d_a, 3321 const struct device *d_b) 3322 { 3323 const struct pci_dev *a = to_pci_dev(d_a); 3324 const struct pci_dev *b = to_pci_dev(d_b); 3325 3326 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3327 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3328 3329 if (a->bus->number < b->bus->number) return -1; 3330 else if (a->bus->number > b->bus->number) return 1; 3331 3332 if (a->devfn < b->devfn) return -1; 3333 else if (a->devfn > b->devfn) return 1; 3334 3335 return 0; 3336 } 3337 3338 void __init pci_sort_breadthfirst(void) 3339 { 3340 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3341 } 3342 3343 int pci_hp_add_bridge(struct pci_dev *dev) 3344 { 3345 struct pci_bus *parent = dev->bus; 3346 int busnr, start = parent->busn_res.start; 3347 unsigned int available_buses = 0; 3348 int end = parent->busn_res.end; 3349 3350 for (busnr = start; busnr <= end; busnr++) { 3351 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3352 break; 3353 } 3354 if (busnr-- > end) { 3355 pci_err(dev, "No bus number available for hot-added bridge\n"); 3356 return -1; 3357 } 3358 3359 /* Scan bridges that are already configured */ 3360 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3361 3362 /* 3363 * Distribute the available bus numbers between hotplug-capable 3364 * bridges to make extending the chain later possible. 3365 */ 3366 available_buses = end - busnr; 3367 3368 /* Scan bridges that need to be reconfigured */ 3369 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3370 3371 if (!dev->subordinate) 3372 return -1; 3373 3374 return 0; 3375 } 3376 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3377