1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_device.h> 12 #include <linux/of_pci.h> 13 #include <linux/pci_hotplug.h> 14 #include <linux/slab.h> 15 #include <linux/module.h> 16 #include <linux/cpumask.h> 17 #include <linux/aer.h> 18 #include <linux/acpi.h> 19 #include <linux/hypervisor.h> 20 #include <linux/irqdomain.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/bitfield.h> 23 #include "pci.h" 24 25 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 26 #define CARDBUS_RESERVE_BUSNR 3 27 28 static struct resource busn_resource = { 29 .name = "PCI busn", 30 .start = 0, 31 .end = 255, 32 .flags = IORESOURCE_BUS, 33 }; 34 35 /* Ugh. Need to stop exporting this to modules. */ 36 LIST_HEAD(pci_root_buses); 37 EXPORT_SYMBOL(pci_root_buses); 38 39 static LIST_HEAD(pci_domain_busn_res_list); 40 41 struct pci_domain_busn_res { 42 struct list_head list; 43 struct resource res; 44 int domain_nr; 45 }; 46 47 static struct resource *get_pci_domain_busn_res(int domain_nr) 48 { 49 struct pci_domain_busn_res *r; 50 51 list_for_each_entry(r, &pci_domain_busn_res_list, list) 52 if (r->domain_nr == domain_nr) 53 return &r->res; 54 55 r = kzalloc(sizeof(*r), GFP_KERNEL); 56 if (!r) 57 return NULL; 58 59 r->domain_nr = domain_nr; 60 r->res.start = 0; 61 r->res.end = 0xff; 62 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 63 64 list_add_tail(&r->list, &pci_domain_busn_res_list); 65 66 return &r->res; 67 } 68 69 /* 70 * Some device drivers need know if PCI is initiated. 71 * Basically, we think PCI is not initiated when there 72 * is no device to be found on the pci_bus_type. 73 */ 74 int no_pci_devices(void) 75 { 76 struct device *dev; 77 int no_devices; 78 79 dev = bus_find_next_device(&pci_bus_type, NULL); 80 no_devices = (dev == NULL); 81 put_device(dev); 82 return no_devices; 83 } 84 EXPORT_SYMBOL(no_pci_devices); 85 86 /* 87 * PCI Bus Class 88 */ 89 static void release_pcibus_dev(struct device *dev) 90 { 91 struct pci_bus *pci_bus = to_pci_bus(dev); 92 93 put_device(pci_bus->bridge); 94 pci_bus_remove_resources(pci_bus); 95 pci_release_bus_of_node(pci_bus); 96 kfree(pci_bus); 97 } 98 99 static struct class pcibus_class = { 100 .name = "pci_bus", 101 .dev_release = &release_pcibus_dev, 102 .dev_groups = pcibus_groups, 103 }; 104 105 static int __init pcibus_class_init(void) 106 { 107 return class_register(&pcibus_class); 108 } 109 postcore_initcall(pcibus_class_init); 110 111 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 112 { 113 u64 size = mask & maxbase; /* Find the significant bits */ 114 if (!size) 115 return 0; 116 117 /* 118 * Get the lowest of them to find the decode size, and from that 119 * the extent. 120 */ 121 size = size & ~(size-1); 122 123 /* 124 * base == maxbase can be valid only if the BAR has already been 125 * programmed with all 1s. 126 */ 127 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 128 return 0; 129 130 return size; 131 } 132 133 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 134 { 135 u32 mem_type; 136 unsigned long flags; 137 138 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 139 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 140 flags |= IORESOURCE_IO; 141 return flags; 142 } 143 144 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 145 flags |= IORESOURCE_MEM; 146 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 147 flags |= IORESOURCE_PREFETCH; 148 149 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 150 switch (mem_type) { 151 case PCI_BASE_ADDRESS_MEM_TYPE_32: 152 break; 153 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 154 /* 1M mem BAR treated as 32-bit BAR */ 155 break; 156 case PCI_BASE_ADDRESS_MEM_TYPE_64: 157 flags |= IORESOURCE_MEM_64; 158 break; 159 default: 160 /* mem unknown type treated as 32-bit BAR */ 161 break; 162 } 163 return flags; 164 } 165 166 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 167 168 /** 169 * __pci_read_base - Read a PCI BAR 170 * @dev: the PCI device 171 * @type: type of the BAR 172 * @res: resource buffer to be filled in 173 * @pos: BAR position in the config space 174 * 175 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 176 */ 177 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 178 struct resource *res, unsigned int pos) 179 { 180 u32 l = 0, sz = 0, mask; 181 u64 l64, sz64, mask64; 182 u16 orig_cmd; 183 struct pci_bus_region region, inverted_region; 184 185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 186 187 /* No printks while decoding is disabled! */ 188 if (!dev->mmio_always_on) { 189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 191 pci_write_config_word(dev, PCI_COMMAND, 192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 193 } 194 } 195 196 res->name = pci_name(dev); 197 198 pci_read_config_dword(dev, pos, &l); 199 pci_write_config_dword(dev, pos, l | mask); 200 pci_read_config_dword(dev, pos, &sz); 201 pci_write_config_dword(dev, pos, l); 202 203 /* 204 * All bits set in sz means the device isn't working properly. 205 * If the BAR isn't implemented, all bits must be 0. If it's a 206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 207 * 1 must be clear. 208 */ 209 if (sz == 0xffffffff) 210 sz = 0; 211 212 /* 213 * I don't know how l can have all bits set. Copied from old code. 214 * Maybe it fixes a bug on some ancient platform. 215 */ 216 if (l == 0xffffffff) 217 l = 0; 218 219 if (type == pci_bar_unknown) { 220 res->flags = decode_bar(dev, l); 221 res->flags |= IORESOURCE_SIZEALIGN; 222 if (res->flags & IORESOURCE_IO) { 223 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 226 } else { 227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 230 } 231 } else { 232 if (l & PCI_ROM_ADDRESS_ENABLE) 233 res->flags |= IORESOURCE_ROM_ENABLE; 234 l64 = l & PCI_ROM_ADDRESS_MASK; 235 sz64 = sz & PCI_ROM_ADDRESS_MASK; 236 mask64 = PCI_ROM_ADDRESS_MASK; 237 } 238 239 if (res->flags & IORESOURCE_MEM_64) { 240 pci_read_config_dword(dev, pos + 4, &l); 241 pci_write_config_dword(dev, pos + 4, ~0); 242 pci_read_config_dword(dev, pos + 4, &sz); 243 pci_write_config_dword(dev, pos + 4, l); 244 245 l64 |= ((u64)l << 32); 246 sz64 |= ((u64)sz << 32); 247 mask64 |= ((u64)~0 << 32); 248 } 249 250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 252 253 if (!sz64) 254 goto fail; 255 256 sz64 = pci_size(l64, sz64, mask64); 257 if (!sz64) { 258 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", 259 pos); 260 goto fail; 261 } 262 263 if (res->flags & IORESOURCE_MEM_64) { 264 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 265 && sz64 > 0x100000000ULL) { 266 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 267 res->start = 0; 268 res->end = 0; 269 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", 270 pos, (unsigned long long)sz64); 271 goto out; 272 } 273 274 if ((sizeof(pci_bus_addr_t) < 8) && l) { 275 /* Above 32-bit boundary; try to reallocate */ 276 res->flags |= IORESOURCE_UNSET; 277 res->start = 0; 278 res->end = sz64 - 1; 279 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", 280 pos, (unsigned long long)l64); 281 goto out; 282 } 283 } 284 285 region.start = l64; 286 region.end = l64 + sz64 - 1; 287 288 pcibios_bus_to_resource(dev->bus, res, ®ion); 289 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 290 291 /* 292 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 293 * the corresponding resource address (the physical address used by 294 * the CPU. Converting that resource address back to a bus address 295 * should yield the original BAR value: 296 * 297 * resource_to_bus(bus_to_resource(A)) == A 298 * 299 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 300 * be claimed by the device. 301 */ 302 if (inverted_region.start != region.start) { 303 res->flags |= IORESOURCE_UNSET; 304 res->start = 0; 305 res->end = region.end - region.start; 306 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", 307 pos, (unsigned long long)region.start); 308 } 309 310 goto out; 311 312 313 fail: 314 res->flags = 0; 315 out: 316 if (res->flags) 317 pci_info(dev, "reg 0x%x: %pR\n", pos, res); 318 319 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 320 } 321 322 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 323 { 324 unsigned int pos, reg; 325 326 if (dev->non_compliant_bars) 327 return; 328 329 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 330 if (dev->is_virtfn) 331 return; 332 333 for (pos = 0; pos < howmany; pos++) { 334 struct resource *res = &dev->resource[pos]; 335 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 336 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 337 } 338 339 if (rom) { 340 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 341 dev->rom_base_reg = rom; 342 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 343 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 344 __pci_read_base(dev, pci_bar_mem32, res, rom); 345 } 346 } 347 348 static void pci_read_bridge_windows(struct pci_dev *bridge) 349 { 350 u16 io; 351 u32 pmem, tmp; 352 353 pci_read_config_word(bridge, PCI_IO_BASE, &io); 354 if (!io) { 355 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 356 pci_read_config_word(bridge, PCI_IO_BASE, &io); 357 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 358 } 359 if (io) 360 bridge->io_window = 1; 361 362 /* 363 * DECchip 21050 pass 2 errata: the bridge may miss an address 364 * disconnect boundary by one PCI data phase. Workaround: do not 365 * use prefetching on this device. 366 */ 367 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 368 return; 369 370 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 371 if (!pmem) { 372 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 373 0xffe0fff0); 374 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 375 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 376 } 377 if (!pmem) 378 return; 379 380 bridge->pref_window = 1; 381 382 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 383 384 /* 385 * Bridge claims to have a 64-bit prefetchable memory 386 * window; verify that the upper bits are actually 387 * writable. 388 */ 389 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 390 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 391 0xffffffff); 392 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 393 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 394 if (tmp) 395 bridge->pref_64_window = 1; 396 } 397 } 398 399 static void pci_read_bridge_io(struct pci_bus *child) 400 { 401 struct pci_dev *dev = child->self; 402 u8 io_base_lo, io_limit_lo; 403 unsigned long io_mask, io_granularity, base, limit; 404 struct pci_bus_region region; 405 struct resource *res; 406 407 io_mask = PCI_IO_RANGE_MASK; 408 io_granularity = 0x1000; 409 if (dev->io_window_1k) { 410 /* Support 1K I/O space granularity */ 411 io_mask = PCI_IO_1K_RANGE_MASK; 412 io_granularity = 0x400; 413 } 414 415 res = child->resource[0]; 416 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 417 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 418 base = (io_base_lo & io_mask) << 8; 419 limit = (io_limit_lo & io_mask) << 8; 420 421 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 422 u16 io_base_hi, io_limit_hi; 423 424 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 425 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 426 base |= ((unsigned long) io_base_hi << 16); 427 limit |= ((unsigned long) io_limit_hi << 16); 428 } 429 430 if (base <= limit) { 431 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 432 region.start = base; 433 region.end = limit + io_granularity - 1; 434 pcibios_bus_to_resource(dev->bus, res, ®ion); 435 pci_info(dev, " bridge window %pR\n", res); 436 } 437 } 438 439 static void pci_read_bridge_mmio(struct pci_bus *child) 440 { 441 struct pci_dev *dev = child->self; 442 u16 mem_base_lo, mem_limit_lo; 443 unsigned long base, limit; 444 struct pci_bus_region region; 445 struct resource *res; 446 447 res = child->resource[1]; 448 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 449 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 450 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 451 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 452 if (base <= limit) { 453 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 454 region.start = base; 455 region.end = limit + 0xfffff; 456 pcibios_bus_to_resource(dev->bus, res, ®ion); 457 pci_info(dev, " bridge window %pR\n", res); 458 } 459 } 460 461 static void pci_read_bridge_mmio_pref(struct pci_bus *child) 462 { 463 struct pci_dev *dev = child->self; 464 u16 mem_base_lo, mem_limit_lo; 465 u64 base64, limit64; 466 pci_bus_addr_t base, limit; 467 struct pci_bus_region region; 468 struct resource *res; 469 470 res = child->resource[2]; 471 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 472 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 473 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 474 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 475 476 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 477 u32 mem_base_hi, mem_limit_hi; 478 479 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 480 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 481 482 /* 483 * Some bridges set the base > limit by default, and some 484 * (broken) BIOSes do not initialize them. If we find 485 * this, just assume they are not being used. 486 */ 487 if (mem_base_hi <= mem_limit_hi) { 488 base64 |= (u64) mem_base_hi << 32; 489 limit64 |= (u64) mem_limit_hi << 32; 490 } 491 } 492 493 base = (pci_bus_addr_t) base64; 494 limit = (pci_bus_addr_t) limit64; 495 496 if (base != base64) { 497 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 498 (unsigned long long) base64); 499 return; 500 } 501 502 if (base <= limit) { 503 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 504 IORESOURCE_MEM | IORESOURCE_PREFETCH; 505 if (res->flags & PCI_PREF_RANGE_TYPE_64) 506 res->flags |= IORESOURCE_MEM_64; 507 region.start = base; 508 region.end = limit + 0xfffff; 509 pcibios_bus_to_resource(dev->bus, res, ®ion); 510 pci_info(dev, " bridge window %pR\n", res); 511 } 512 } 513 514 void pci_read_bridge_bases(struct pci_bus *child) 515 { 516 struct pci_dev *dev = child->self; 517 struct resource *res; 518 int i; 519 520 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 521 return; 522 523 pci_info(dev, "PCI bridge to %pR%s\n", 524 &child->busn_res, 525 dev->transparent ? " (subtractive decode)" : ""); 526 527 pci_bus_remove_resources(child); 528 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 529 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 530 531 pci_read_bridge_io(child); 532 pci_read_bridge_mmio(child); 533 pci_read_bridge_mmio_pref(child); 534 535 if (dev->transparent) { 536 pci_bus_for_each_resource(child->parent, res, i) { 537 if (res && res->flags) { 538 pci_bus_add_resource(child, res, 539 PCI_SUBTRACTIVE_DECODE); 540 pci_info(dev, " bridge window %pR (subtractive decode)\n", 541 res); 542 } 543 } 544 } 545 } 546 547 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 548 { 549 struct pci_bus *b; 550 551 b = kzalloc(sizeof(*b), GFP_KERNEL); 552 if (!b) 553 return NULL; 554 555 INIT_LIST_HEAD(&b->node); 556 INIT_LIST_HEAD(&b->children); 557 INIT_LIST_HEAD(&b->devices); 558 INIT_LIST_HEAD(&b->slots); 559 INIT_LIST_HEAD(&b->resources); 560 b->max_bus_speed = PCI_SPEED_UNKNOWN; 561 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 562 #ifdef CONFIG_PCI_DOMAINS_GENERIC 563 if (parent) 564 b->domain_nr = parent->domain_nr; 565 #endif 566 return b; 567 } 568 569 static void pci_release_host_bridge_dev(struct device *dev) 570 { 571 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 572 573 if (bridge->release_fn) 574 bridge->release_fn(bridge); 575 576 pci_free_resource_list(&bridge->windows); 577 pci_free_resource_list(&bridge->dma_ranges); 578 kfree(bridge); 579 } 580 581 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 582 { 583 INIT_LIST_HEAD(&bridge->windows); 584 INIT_LIST_HEAD(&bridge->dma_ranges); 585 586 /* 587 * We assume we can manage these PCIe features. Some systems may 588 * reserve these for use by the platform itself, e.g., an ACPI BIOS 589 * may implement its own AER handling and use _OSC to prevent the 590 * OS from interfering. 591 */ 592 bridge->native_aer = 1; 593 bridge->native_pcie_hotplug = 1; 594 bridge->native_shpc_hotplug = 1; 595 bridge->native_pme = 1; 596 bridge->native_ltr = 1; 597 bridge->native_dpc = 1; 598 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 599 600 device_initialize(&bridge->dev); 601 } 602 603 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 604 { 605 struct pci_host_bridge *bridge; 606 607 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 608 if (!bridge) 609 return NULL; 610 611 pci_init_host_bridge(bridge); 612 bridge->dev.release = pci_release_host_bridge_dev; 613 614 return bridge; 615 } 616 EXPORT_SYMBOL(pci_alloc_host_bridge); 617 618 static void devm_pci_alloc_host_bridge_release(void *data) 619 { 620 pci_free_host_bridge(data); 621 } 622 623 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 624 size_t priv) 625 { 626 int ret; 627 struct pci_host_bridge *bridge; 628 629 bridge = pci_alloc_host_bridge(priv); 630 if (!bridge) 631 return NULL; 632 633 bridge->dev.parent = dev; 634 635 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 636 bridge); 637 if (ret) 638 return NULL; 639 640 ret = devm_of_pci_bridge_init(dev, bridge); 641 if (ret) 642 return NULL; 643 644 return bridge; 645 } 646 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 647 648 void pci_free_host_bridge(struct pci_host_bridge *bridge) 649 { 650 put_device(&bridge->dev); 651 } 652 EXPORT_SYMBOL(pci_free_host_bridge); 653 654 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 655 static const unsigned char pcix_bus_speed[] = { 656 PCI_SPEED_UNKNOWN, /* 0 */ 657 PCI_SPEED_66MHz_PCIX, /* 1 */ 658 PCI_SPEED_100MHz_PCIX, /* 2 */ 659 PCI_SPEED_133MHz_PCIX, /* 3 */ 660 PCI_SPEED_UNKNOWN, /* 4 */ 661 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 662 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 663 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 664 PCI_SPEED_UNKNOWN, /* 8 */ 665 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 666 PCI_SPEED_100MHz_PCIX_266, /* A */ 667 PCI_SPEED_133MHz_PCIX_266, /* B */ 668 PCI_SPEED_UNKNOWN, /* C */ 669 PCI_SPEED_66MHz_PCIX_533, /* D */ 670 PCI_SPEED_100MHz_PCIX_533, /* E */ 671 PCI_SPEED_133MHz_PCIX_533 /* F */ 672 }; 673 674 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 675 const unsigned char pcie_link_speed[] = { 676 PCI_SPEED_UNKNOWN, /* 0 */ 677 PCIE_SPEED_2_5GT, /* 1 */ 678 PCIE_SPEED_5_0GT, /* 2 */ 679 PCIE_SPEED_8_0GT, /* 3 */ 680 PCIE_SPEED_16_0GT, /* 4 */ 681 PCIE_SPEED_32_0GT, /* 5 */ 682 PCIE_SPEED_64_0GT, /* 6 */ 683 PCI_SPEED_UNKNOWN, /* 7 */ 684 PCI_SPEED_UNKNOWN, /* 8 */ 685 PCI_SPEED_UNKNOWN, /* 9 */ 686 PCI_SPEED_UNKNOWN, /* A */ 687 PCI_SPEED_UNKNOWN, /* B */ 688 PCI_SPEED_UNKNOWN, /* C */ 689 PCI_SPEED_UNKNOWN, /* D */ 690 PCI_SPEED_UNKNOWN, /* E */ 691 PCI_SPEED_UNKNOWN /* F */ 692 }; 693 EXPORT_SYMBOL_GPL(pcie_link_speed); 694 695 const char *pci_speed_string(enum pci_bus_speed speed) 696 { 697 /* Indexed by the pci_bus_speed enum */ 698 static const char *speed_strings[] = { 699 "33 MHz PCI", /* 0x00 */ 700 "66 MHz PCI", /* 0x01 */ 701 "66 MHz PCI-X", /* 0x02 */ 702 "100 MHz PCI-X", /* 0x03 */ 703 "133 MHz PCI-X", /* 0x04 */ 704 NULL, /* 0x05 */ 705 NULL, /* 0x06 */ 706 NULL, /* 0x07 */ 707 NULL, /* 0x08 */ 708 "66 MHz PCI-X 266", /* 0x09 */ 709 "100 MHz PCI-X 266", /* 0x0a */ 710 "133 MHz PCI-X 266", /* 0x0b */ 711 "Unknown AGP", /* 0x0c */ 712 "1x AGP", /* 0x0d */ 713 "2x AGP", /* 0x0e */ 714 "4x AGP", /* 0x0f */ 715 "8x AGP", /* 0x10 */ 716 "66 MHz PCI-X 533", /* 0x11 */ 717 "100 MHz PCI-X 533", /* 0x12 */ 718 "133 MHz PCI-X 533", /* 0x13 */ 719 "2.5 GT/s PCIe", /* 0x14 */ 720 "5.0 GT/s PCIe", /* 0x15 */ 721 "8.0 GT/s PCIe", /* 0x16 */ 722 "16.0 GT/s PCIe", /* 0x17 */ 723 "32.0 GT/s PCIe", /* 0x18 */ 724 "64.0 GT/s PCIe", /* 0x19 */ 725 }; 726 727 if (speed < ARRAY_SIZE(speed_strings)) 728 return speed_strings[speed]; 729 return "Unknown"; 730 } 731 EXPORT_SYMBOL_GPL(pci_speed_string); 732 733 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 734 { 735 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 736 } 737 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 738 739 static unsigned char agp_speeds[] = { 740 AGP_UNKNOWN, 741 AGP_1X, 742 AGP_2X, 743 AGP_4X, 744 AGP_8X 745 }; 746 747 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 748 { 749 int index = 0; 750 751 if (agpstat & 4) 752 index = 3; 753 else if (agpstat & 2) 754 index = 2; 755 else if (agpstat & 1) 756 index = 1; 757 else 758 goto out; 759 760 if (agp3) { 761 index += 2; 762 if (index == 5) 763 index = 0; 764 } 765 766 out: 767 return agp_speeds[index]; 768 } 769 770 static void pci_set_bus_speed(struct pci_bus *bus) 771 { 772 struct pci_dev *bridge = bus->self; 773 int pos; 774 775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 776 if (!pos) 777 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 778 if (pos) { 779 u32 agpstat, agpcmd; 780 781 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 782 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 783 784 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 785 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 786 } 787 788 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 789 if (pos) { 790 u16 status; 791 enum pci_bus_speed max; 792 793 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 794 &status); 795 796 if (status & PCI_X_SSTATUS_533MHZ) { 797 max = PCI_SPEED_133MHz_PCIX_533; 798 } else if (status & PCI_X_SSTATUS_266MHZ) { 799 max = PCI_SPEED_133MHz_PCIX_266; 800 } else if (status & PCI_X_SSTATUS_133MHZ) { 801 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 802 max = PCI_SPEED_133MHz_PCIX_ECC; 803 else 804 max = PCI_SPEED_133MHz_PCIX; 805 } else { 806 max = PCI_SPEED_66MHz_PCIX; 807 } 808 809 bus->max_bus_speed = max; 810 bus->cur_bus_speed = pcix_bus_speed[ 811 (status & PCI_X_SSTATUS_FREQ) >> 6]; 812 813 return; 814 } 815 816 if (pci_is_pcie(bridge)) { 817 u32 linkcap; 818 u16 linksta; 819 820 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 821 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 822 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); 823 824 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 825 pcie_update_link_speed(bus, linksta); 826 } 827 } 828 829 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 830 { 831 struct irq_domain *d; 832 833 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 834 d = dev_get_msi_domain(bus->bridge); 835 836 /* 837 * Any firmware interface that can resolve the msi_domain 838 * should be called from here. 839 */ 840 if (!d) 841 d = pci_host_bridge_of_msi_domain(bus); 842 if (!d) 843 d = pci_host_bridge_acpi_msi_domain(bus); 844 845 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN 846 /* 847 * If no IRQ domain was found via the OF tree, try looking it up 848 * directly through the fwnode_handle. 849 */ 850 if (!d) { 851 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 852 853 if (fwnode) 854 d = irq_find_matching_fwnode(fwnode, 855 DOMAIN_BUS_PCI_MSI); 856 } 857 #endif 858 859 return d; 860 } 861 862 static void pci_set_bus_msi_domain(struct pci_bus *bus) 863 { 864 struct irq_domain *d; 865 struct pci_bus *b; 866 867 /* 868 * The bus can be a root bus, a subordinate bus, or a virtual bus 869 * created by an SR-IOV device. Walk up to the first bridge device 870 * found or derive the domain from the host bridge. 871 */ 872 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 873 if (b->self) 874 d = dev_get_msi_domain(&b->self->dev); 875 } 876 877 if (!d) 878 d = pci_host_bridge_msi_domain(b); 879 880 dev_set_msi_domain(&bus->dev, d); 881 } 882 883 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 884 { 885 struct device *parent = bridge->dev.parent; 886 struct resource_entry *window, *n; 887 struct pci_bus *bus, *b; 888 resource_size_t offset; 889 LIST_HEAD(resources); 890 struct resource *res; 891 char addr[64], *fmt; 892 const char *name; 893 int err; 894 895 bus = pci_alloc_bus(NULL); 896 if (!bus) 897 return -ENOMEM; 898 899 bridge->bus = bus; 900 901 /* Temporarily move resources off the list */ 902 list_splice_init(&bridge->windows, &resources); 903 bus->sysdata = bridge->sysdata; 904 bus->ops = bridge->ops; 905 bus->number = bus->busn_res.start = bridge->busnr; 906 #ifdef CONFIG_PCI_DOMAINS_GENERIC 907 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 908 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 909 else 910 bus->domain_nr = bridge->domain_nr; 911 #endif 912 913 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 914 if (b) { 915 /* Ignore it if we already got here via a different bridge */ 916 dev_dbg(&b->dev, "bus already known\n"); 917 err = -EEXIST; 918 goto free; 919 } 920 921 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 922 bridge->busnr); 923 924 err = pcibios_root_bridge_prepare(bridge); 925 if (err) 926 goto free; 927 928 err = device_add(&bridge->dev); 929 if (err) { 930 put_device(&bridge->dev); 931 goto free; 932 } 933 bus->bridge = get_device(&bridge->dev); 934 device_enable_async_suspend(bus->bridge); 935 pci_set_bus_of_node(bus); 936 pci_set_bus_msi_domain(bus); 937 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 938 !pci_host_of_has_msi_map(parent)) 939 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 940 941 if (!parent) 942 set_dev_node(bus->bridge, pcibus_to_node(bus)); 943 944 bus->dev.class = &pcibus_class; 945 bus->dev.parent = bus->bridge; 946 947 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 948 name = dev_name(&bus->dev); 949 950 err = device_register(&bus->dev); 951 if (err) 952 goto unregister; 953 954 pcibios_add_bus(bus); 955 956 if (bus->ops->add_bus) { 957 err = bus->ops->add_bus(bus); 958 if (WARN_ON(err < 0)) 959 dev_err(&bus->dev, "failed to add bus: %d\n", err); 960 } 961 962 /* Create legacy_io and legacy_mem files for this bus */ 963 pci_create_legacy_files(bus); 964 965 if (parent) 966 dev_info(parent, "PCI host bridge to bus %s\n", name); 967 else 968 pr_info("PCI host bridge to bus %s\n", name); 969 970 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 971 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 972 973 /* Add initial resources to the bus */ 974 resource_list_for_each_entry_safe(window, n, &resources) { 975 list_move_tail(&window->node, &bridge->windows); 976 offset = window->offset; 977 res = window->res; 978 979 if (res->flags & IORESOURCE_BUS) 980 pci_bus_insert_busn_res(bus, bus->number, res->end); 981 else 982 pci_bus_add_resource(bus, res, 0); 983 984 if (offset) { 985 if (resource_type(res) == IORESOURCE_IO) 986 fmt = " (bus address [%#06llx-%#06llx])"; 987 else 988 fmt = " (bus address [%#010llx-%#010llx])"; 989 990 snprintf(addr, sizeof(addr), fmt, 991 (unsigned long long)(res->start - offset), 992 (unsigned long long)(res->end - offset)); 993 } else 994 addr[0] = '\0'; 995 996 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 997 } 998 999 down_write(&pci_bus_sem); 1000 list_add_tail(&bus->node, &pci_root_buses); 1001 up_write(&pci_bus_sem); 1002 1003 return 0; 1004 1005 unregister: 1006 put_device(&bridge->dev); 1007 device_del(&bridge->dev); 1008 1009 free: 1010 kfree(bus); 1011 return err; 1012 } 1013 1014 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1015 { 1016 int pos; 1017 u32 status; 1018 1019 /* 1020 * If extended config space isn't accessible on a bridge's primary 1021 * bus, we certainly can't access it on the secondary bus. 1022 */ 1023 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1024 return false; 1025 1026 /* 1027 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1028 * extended config space is accessible on the primary, it's also 1029 * accessible on the secondary. 1030 */ 1031 if (pci_is_pcie(bridge) && 1032 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1033 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1034 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1035 return true; 1036 1037 /* 1038 * For the other bridge types: 1039 * - PCI-to-PCI bridges 1040 * - PCIe-to-PCI/PCI-X forward bridges 1041 * - PCI/PCI-X-to-PCIe reverse bridges 1042 * extended config space on the secondary side is only accessible 1043 * if the bridge supports PCI-X Mode 2. 1044 */ 1045 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1046 if (!pos) 1047 return false; 1048 1049 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1050 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1051 } 1052 1053 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1054 struct pci_dev *bridge, int busnr) 1055 { 1056 struct pci_bus *child; 1057 struct pci_host_bridge *host; 1058 int i; 1059 int ret; 1060 1061 /* Allocate a new bus and inherit stuff from the parent */ 1062 child = pci_alloc_bus(parent); 1063 if (!child) 1064 return NULL; 1065 1066 child->parent = parent; 1067 child->sysdata = parent->sysdata; 1068 child->bus_flags = parent->bus_flags; 1069 1070 host = pci_find_host_bridge(parent); 1071 if (host->child_ops) 1072 child->ops = host->child_ops; 1073 else 1074 child->ops = parent->ops; 1075 1076 /* 1077 * Initialize some portions of the bus device, but don't register 1078 * it now as the parent is not properly set up yet. 1079 */ 1080 child->dev.class = &pcibus_class; 1081 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1082 1083 /* Set up the primary, secondary and subordinate bus numbers */ 1084 child->number = child->busn_res.start = busnr; 1085 child->primary = parent->busn_res.start; 1086 child->busn_res.end = 0xff; 1087 1088 if (!bridge) { 1089 child->dev.parent = parent->bridge; 1090 goto add_dev; 1091 } 1092 1093 child->self = bridge; 1094 child->bridge = get_device(&bridge->dev); 1095 child->dev.parent = child->bridge; 1096 pci_set_bus_of_node(child); 1097 pci_set_bus_speed(child); 1098 1099 /* 1100 * Check whether extended config space is accessible on the child 1101 * bus. Note that we currently assume it is always accessible on 1102 * the root bus. 1103 */ 1104 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1105 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1106 pci_info(child, "extended config space not accessible\n"); 1107 } 1108 1109 /* Set up default resource pointers and names */ 1110 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1111 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1112 child->resource[i]->name = child->name; 1113 } 1114 bridge->subordinate = child; 1115 1116 add_dev: 1117 pci_set_bus_msi_domain(child); 1118 ret = device_register(&child->dev); 1119 WARN_ON(ret < 0); 1120 1121 pcibios_add_bus(child); 1122 1123 if (child->ops->add_bus) { 1124 ret = child->ops->add_bus(child); 1125 if (WARN_ON(ret < 0)) 1126 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1127 } 1128 1129 /* Create legacy_io and legacy_mem files for this bus */ 1130 pci_create_legacy_files(child); 1131 1132 return child; 1133 } 1134 1135 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1136 int busnr) 1137 { 1138 struct pci_bus *child; 1139 1140 child = pci_alloc_child_bus(parent, dev, busnr); 1141 if (child) { 1142 down_write(&pci_bus_sem); 1143 list_add_tail(&child->node, &parent->children); 1144 up_write(&pci_bus_sem); 1145 } 1146 return child; 1147 } 1148 EXPORT_SYMBOL(pci_add_new_bus); 1149 1150 static void pci_enable_crs(struct pci_dev *pdev) 1151 { 1152 u16 root_cap = 0; 1153 1154 /* Enable CRS Software Visibility if supported */ 1155 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1156 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1157 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1158 PCI_EXP_RTCTL_CRSSVE); 1159 } 1160 1161 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1162 unsigned int available_buses); 1163 /** 1164 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1165 * numbers from EA capability. 1166 * @dev: Bridge 1167 * @sec: updated with secondary bus number from EA 1168 * @sub: updated with subordinate bus number from EA 1169 * 1170 * If @dev is a bridge with EA capability that specifies valid secondary 1171 * and subordinate bus numbers, return true with the bus numbers in @sec 1172 * and @sub. Otherwise return false. 1173 */ 1174 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1175 { 1176 int ea, offset; 1177 u32 dw; 1178 u8 ea_sec, ea_sub; 1179 1180 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1181 return false; 1182 1183 /* find PCI EA capability in list */ 1184 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1185 if (!ea) 1186 return false; 1187 1188 offset = ea + PCI_EA_FIRST_ENT; 1189 pci_read_config_dword(dev, offset, &dw); 1190 ea_sec = dw & PCI_EA_SEC_BUS_MASK; 1191 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; 1192 if (ea_sec == 0 || ea_sub < ea_sec) 1193 return false; 1194 1195 *sec = ea_sec; 1196 *sub = ea_sub; 1197 return true; 1198 } 1199 1200 /* 1201 * pci_scan_bridge_extend() - Scan buses behind a bridge 1202 * @bus: Parent bus the bridge is on 1203 * @dev: Bridge itself 1204 * @max: Starting subordinate number of buses behind this bridge 1205 * @available_buses: Total number of buses available for this bridge and 1206 * the devices below. After the minimal bus space has 1207 * been allocated the remaining buses will be 1208 * distributed equally between hotplug-capable bridges. 1209 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1210 * that need to be reconfigured. 1211 * 1212 * If it's a bridge, configure it and scan the bus behind it. 1213 * For CardBus bridges, we don't scan behind as the devices will 1214 * be handled by the bridge driver itself. 1215 * 1216 * We need to process bridges in two passes -- first we scan those 1217 * already configured by the BIOS and after we are done with all of 1218 * them, we proceed to assigning numbers to the remaining buses in 1219 * order to avoid overlaps between old and new bus numbers. 1220 * 1221 * Return: New subordinate number covering all buses behind this bridge. 1222 */ 1223 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1224 int max, unsigned int available_buses, 1225 int pass) 1226 { 1227 struct pci_bus *child; 1228 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1229 u32 buses, i, j = 0; 1230 u16 bctl; 1231 u8 primary, secondary, subordinate; 1232 int broken = 0; 1233 bool fixed_buses; 1234 u8 fixed_sec, fixed_sub; 1235 int next_busnr; 1236 1237 /* 1238 * Make sure the bridge is powered on to be able to access config 1239 * space of devices below it. 1240 */ 1241 pm_runtime_get_sync(&dev->dev); 1242 1243 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1244 primary = buses & 0xFF; 1245 secondary = (buses >> 8) & 0xFF; 1246 subordinate = (buses >> 16) & 0xFF; 1247 1248 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1249 secondary, subordinate, pass); 1250 1251 if (!primary && (primary != bus->number) && secondary && subordinate) { 1252 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1253 primary = bus->number; 1254 } 1255 1256 /* Check if setup is sensible at all */ 1257 if (!pass && 1258 (primary != bus->number || secondary <= bus->number || 1259 secondary > subordinate)) { 1260 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1261 secondary, subordinate); 1262 broken = 1; 1263 } 1264 1265 /* 1266 * Disable Master-Abort Mode during probing to avoid reporting of 1267 * bus errors in some architectures. 1268 */ 1269 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1270 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1271 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1272 1273 pci_enable_crs(dev); 1274 1275 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1276 !is_cardbus && !broken) { 1277 unsigned int cmax; 1278 1279 /* 1280 * Bus already configured by firmware, process it in the 1281 * first pass and just note the configuration. 1282 */ 1283 if (pass) 1284 goto out; 1285 1286 /* 1287 * The bus might already exist for two reasons: Either we 1288 * are rescanning the bus or the bus is reachable through 1289 * more than one bridge. The second case can happen with 1290 * the i450NX chipset. 1291 */ 1292 child = pci_find_bus(pci_domain_nr(bus), secondary); 1293 if (!child) { 1294 child = pci_add_new_bus(bus, dev, secondary); 1295 if (!child) 1296 goto out; 1297 child->primary = primary; 1298 pci_bus_insert_busn_res(child, secondary, subordinate); 1299 child->bridge_ctl = bctl; 1300 } 1301 1302 cmax = pci_scan_child_bus(child); 1303 if (cmax > subordinate) 1304 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1305 subordinate, cmax); 1306 1307 /* Subordinate should equal child->busn_res.end */ 1308 if (subordinate > max) 1309 max = subordinate; 1310 } else { 1311 1312 /* 1313 * We need to assign a number to this bus which we always 1314 * do in the second pass. 1315 */ 1316 if (!pass) { 1317 if (pcibios_assign_all_busses() || broken || is_cardbus) 1318 1319 /* 1320 * Temporarily disable forwarding of the 1321 * configuration cycles on all bridges in 1322 * this bus segment to avoid possible 1323 * conflicts in the second pass between two 1324 * bridges programmed with overlapping bus 1325 * ranges. 1326 */ 1327 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1328 buses & ~0xffffff); 1329 goto out; 1330 } 1331 1332 /* Clear errors */ 1333 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1334 1335 /* Read bus numbers from EA Capability (if present) */ 1336 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1337 if (fixed_buses) 1338 next_busnr = fixed_sec; 1339 else 1340 next_busnr = max + 1; 1341 1342 /* 1343 * Prevent assigning a bus number that already exists. 1344 * This can happen when a bridge is hot-plugged, so in this 1345 * case we only re-scan this bus. 1346 */ 1347 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1348 if (!child) { 1349 child = pci_add_new_bus(bus, dev, next_busnr); 1350 if (!child) 1351 goto out; 1352 pci_bus_insert_busn_res(child, next_busnr, 1353 bus->busn_res.end); 1354 } 1355 max++; 1356 if (available_buses) 1357 available_buses--; 1358 1359 buses = (buses & 0xff000000) 1360 | ((unsigned int)(child->primary) << 0) 1361 | ((unsigned int)(child->busn_res.start) << 8) 1362 | ((unsigned int)(child->busn_res.end) << 16); 1363 1364 /* 1365 * yenta.c forces a secondary latency timer of 176. 1366 * Copy that behaviour here. 1367 */ 1368 if (is_cardbus) { 1369 buses &= ~0xff000000; 1370 buses |= CARDBUS_LATENCY_TIMER << 24; 1371 } 1372 1373 /* We need to blast all three values with a single write */ 1374 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1375 1376 if (!is_cardbus) { 1377 child->bridge_ctl = bctl; 1378 max = pci_scan_child_bus_extend(child, available_buses); 1379 } else { 1380 1381 /* 1382 * For CardBus bridges, we leave 4 bus numbers as 1383 * cards with a PCI-to-PCI bridge can be inserted 1384 * later. 1385 */ 1386 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1387 struct pci_bus *parent = bus; 1388 if (pci_find_bus(pci_domain_nr(bus), 1389 max+i+1)) 1390 break; 1391 while (parent->parent) { 1392 if ((!pcibios_assign_all_busses()) && 1393 (parent->busn_res.end > max) && 1394 (parent->busn_res.end <= max+i)) { 1395 j = 1; 1396 } 1397 parent = parent->parent; 1398 } 1399 if (j) { 1400 1401 /* 1402 * Often, there are two CardBus 1403 * bridges -- try to leave one 1404 * valid bus number for each one. 1405 */ 1406 i /= 2; 1407 break; 1408 } 1409 } 1410 max += i; 1411 } 1412 1413 /* 1414 * Set subordinate bus number to its real value. 1415 * If fixed subordinate bus number exists from EA 1416 * capability then use it. 1417 */ 1418 if (fixed_buses) 1419 max = fixed_sub; 1420 pci_bus_update_busn_res_end(child, max); 1421 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1422 } 1423 1424 sprintf(child->name, 1425 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1426 pci_domain_nr(bus), child->number); 1427 1428 /* Check that all devices are accessible */ 1429 while (bus->parent) { 1430 if ((child->busn_res.end > bus->busn_res.end) || 1431 (child->number > bus->busn_res.end) || 1432 (child->number < bus->number) || 1433 (child->busn_res.end < bus->number)) { 1434 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1435 &child->busn_res); 1436 break; 1437 } 1438 bus = bus->parent; 1439 } 1440 1441 out: 1442 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1443 1444 pm_runtime_put(&dev->dev); 1445 1446 return max; 1447 } 1448 1449 /* 1450 * pci_scan_bridge() - Scan buses behind a bridge 1451 * @bus: Parent bus the bridge is on 1452 * @dev: Bridge itself 1453 * @max: Starting subordinate number of buses behind this bridge 1454 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1455 * that need to be reconfigured. 1456 * 1457 * If it's a bridge, configure it and scan the bus behind it. 1458 * For CardBus bridges, we don't scan behind as the devices will 1459 * be handled by the bridge driver itself. 1460 * 1461 * We need to process bridges in two passes -- first we scan those 1462 * already configured by the BIOS and after we are done with all of 1463 * them, we proceed to assigning numbers to the remaining buses in 1464 * order to avoid overlaps between old and new bus numbers. 1465 * 1466 * Return: New subordinate number covering all buses behind this bridge. 1467 */ 1468 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1469 { 1470 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1471 } 1472 EXPORT_SYMBOL(pci_scan_bridge); 1473 1474 /* 1475 * Read interrupt line and base address registers. 1476 * The architecture-dependent code can tweak these, of course. 1477 */ 1478 static void pci_read_irq(struct pci_dev *dev) 1479 { 1480 unsigned char irq; 1481 1482 /* VFs are not allowed to use INTx, so skip the config reads */ 1483 if (dev->is_virtfn) { 1484 dev->pin = 0; 1485 dev->irq = 0; 1486 return; 1487 } 1488 1489 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1490 dev->pin = irq; 1491 if (irq) 1492 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1493 dev->irq = irq; 1494 } 1495 1496 void set_pcie_port_type(struct pci_dev *pdev) 1497 { 1498 int pos; 1499 u16 reg16; 1500 int type; 1501 struct pci_dev *parent; 1502 1503 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1504 if (!pos) 1505 return; 1506 1507 pdev->pcie_cap = pos; 1508 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1509 pdev->pcie_flags_reg = reg16; 1510 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1511 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1512 1513 parent = pci_upstream_bridge(pdev); 1514 if (!parent) 1515 return; 1516 1517 /* 1518 * Some systems do not identify their upstream/downstream ports 1519 * correctly so detect impossible configurations here and correct 1520 * the port type accordingly. 1521 */ 1522 type = pci_pcie_type(pdev); 1523 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1524 /* 1525 * If pdev claims to be downstream port but the parent 1526 * device is also downstream port assume pdev is actually 1527 * upstream port. 1528 */ 1529 if (pcie_downstream_port(parent)) { 1530 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1531 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1532 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1533 } 1534 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1535 /* 1536 * If pdev claims to be upstream port but the parent 1537 * device is also upstream port assume pdev is actually 1538 * downstream port. 1539 */ 1540 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1541 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1542 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1543 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1544 } 1545 } 1546 } 1547 1548 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1549 { 1550 u32 reg32; 1551 1552 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1553 if (reg32 & PCI_EXP_SLTCAP_HPC) 1554 pdev->is_hotplug_bridge = 1; 1555 } 1556 1557 static void set_pcie_thunderbolt(struct pci_dev *dev) 1558 { 1559 int vsec = 0; 1560 u32 header; 1561 1562 while ((vsec = pci_find_next_ext_capability(dev, vsec, 1563 PCI_EXT_CAP_ID_VNDR))) { 1564 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header); 1565 1566 /* Is the device part of a Thunderbolt controller? */ 1567 if (dev->vendor == PCI_VENDOR_ID_INTEL && 1568 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) { 1569 dev->is_thunderbolt = 1; 1570 return; 1571 } 1572 } 1573 } 1574 1575 static void set_pcie_untrusted(struct pci_dev *dev) 1576 { 1577 struct pci_dev *parent; 1578 1579 /* 1580 * If the upstream bridge is untrusted we treat this device 1581 * untrusted as well. 1582 */ 1583 parent = pci_upstream_bridge(dev); 1584 if (parent && (parent->untrusted || parent->external_facing)) 1585 dev->untrusted = true; 1586 } 1587 1588 static void pci_set_removable(struct pci_dev *dev) 1589 { 1590 struct pci_dev *parent = pci_upstream_bridge(dev); 1591 1592 /* 1593 * We (only) consider everything downstream from an external_facing 1594 * device to be removable by the user. We're mainly concerned with 1595 * consumer platforms with user accessible thunderbolt ports that are 1596 * vulnerable to DMA attacks, and we expect those ports to be marked by 1597 * the firmware as external_facing. Devices in traditional hotplug 1598 * slots can technically be removed, but the expectation is that unless 1599 * the port is marked with external_facing, such devices are less 1600 * accessible to user / may not be removed by end user, and thus not 1601 * exposed as "removable" to userspace. 1602 */ 1603 if (parent && 1604 (parent->external_facing || dev_is_removable(&parent->dev))) 1605 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1606 } 1607 1608 /** 1609 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1610 * @dev: PCI device 1611 * 1612 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1613 * when forwarding a type1 configuration request the bridge must check that 1614 * the extended register address field is zero. The bridge is not permitted 1615 * to forward the transactions and must handle it as an Unsupported Request. 1616 * Some bridges do not follow this rule and simply drop the extended register 1617 * bits, resulting in the standard config space being aliased, every 256 1618 * bytes across the entire configuration space. Test for this condition by 1619 * comparing the first dword of each potential alias to the vendor/device ID. 1620 * Known offenders: 1621 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1622 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1623 */ 1624 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1625 { 1626 #ifdef CONFIG_PCI_QUIRKS 1627 int pos; 1628 u32 header, tmp; 1629 1630 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1631 1632 for (pos = PCI_CFG_SPACE_SIZE; 1633 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1634 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL 1635 || header != tmp) 1636 return false; 1637 } 1638 1639 return true; 1640 #else 1641 return false; 1642 #endif 1643 } 1644 1645 /** 1646 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1647 * @dev: PCI device 1648 * 1649 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1650 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1651 * access it. Maybe we don't have a way to generate extended config space 1652 * accesses, or the device is behind a reverse Express bridge. So we try 1653 * reading the dword at 0x100 which must either be 0 or a valid extended 1654 * capability header. 1655 */ 1656 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1657 { 1658 u32 status; 1659 int pos = PCI_CFG_SPACE_SIZE; 1660 1661 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1662 return PCI_CFG_SPACE_SIZE; 1663 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) 1664 return PCI_CFG_SPACE_SIZE; 1665 1666 return PCI_CFG_SPACE_EXP_SIZE; 1667 } 1668 1669 int pci_cfg_space_size(struct pci_dev *dev) 1670 { 1671 int pos; 1672 u32 status; 1673 u16 class; 1674 1675 #ifdef CONFIG_PCI_IOV 1676 /* 1677 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1678 * implement a PCIe capability and therefore must implement extended 1679 * config space. We can skip the NO_EXTCFG test below and the 1680 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1681 * the fact that the SR-IOV capability on the PF resides in extended 1682 * config space and must be accessible and non-aliased to have enabled 1683 * support for this VF. This is a micro performance optimization for 1684 * systems supporting many VFs. 1685 */ 1686 if (dev->is_virtfn) 1687 return PCI_CFG_SPACE_EXP_SIZE; 1688 #endif 1689 1690 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1691 return PCI_CFG_SPACE_SIZE; 1692 1693 class = dev->class >> 8; 1694 if (class == PCI_CLASS_BRIDGE_HOST) 1695 return pci_cfg_space_size_ext(dev); 1696 1697 if (pci_is_pcie(dev)) 1698 return pci_cfg_space_size_ext(dev); 1699 1700 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1701 if (!pos) 1702 return PCI_CFG_SPACE_SIZE; 1703 1704 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1705 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1706 return pci_cfg_space_size_ext(dev); 1707 1708 return PCI_CFG_SPACE_SIZE; 1709 } 1710 1711 static u32 pci_class(struct pci_dev *dev) 1712 { 1713 u32 class; 1714 1715 #ifdef CONFIG_PCI_IOV 1716 if (dev->is_virtfn) 1717 return dev->physfn->sriov->class; 1718 #endif 1719 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1720 return class; 1721 } 1722 1723 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1724 { 1725 #ifdef CONFIG_PCI_IOV 1726 if (dev->is_virtfn) { 1727 *vendor = dev->physfn->sriov->subsystem_vendor; 1728 *device = dev->physfn->sriov->subsystem_device; 1729 return; 1730 } 1731 #endif 1732 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1733 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1734 } 1735 1736 static u8 pci_hdr_type(struct pci_dev *dev) 1737 { 1738 u8 hdr_type; 1739 1740 #ifdef CONFIG_PCI_IOV 1741 if (dev->is_virtfn) 1742 return dev->physfn->sriov->hdr_type; 1743 #endif 1744 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1745 return hdr_type; 1746 } 1747 1748 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1749 1750 /** 1751 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1752 * @dev: PCI device 1753 * 1754 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1755 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1756 */ 1757 static int pci_intx_mask_broken(struct pci_dev *dev) 1758 { 1759 u16 orig, toggle, new; 1760 1761 pci_read_config_word(dev, PCI_COMMAND, &orig); 1762 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1763 pci_write_config_word(dev, PCI_COMMAND, toggle); 1764 pci_read_config_word(dev, PCI_COMMAND, &new); 1765 1766 pci_write_config_word(dev, PCI_COMMAND, orig); 1767 1768 /* 1769 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1770 * r2.3, so strictly speaking, a device is not *broken* if it's not 1771 * writable. But we'll live with the misnomer for now. 1772 */ 1773 if (new != toggle) 1774 return 1; 1775 return 0; 1776 } 1777 1778 static void early_dump_pci_device(struct pci_dev *pdev) 1779 { 1780 u32 value[256 / 4]; 1781 int i; 1782 1783 pci_info(pdev, "config space:\n"); 1784 1785 for (i = 0; i < 256; i += 4) 1786 pci_read_config_dword(pdev, i, &value[i / 4]); 1787 1788 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1789 value, 256, false); 1790 } 1791 1792 /** 1793 * pci_setup_device - Fill in class and map information of a device 1794 * @dev: the device structure to fill 1795 * 1796 * Initialize the device structure with information about the device's 1797 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1798 * Called at initialisation of the PCI subsystem and by CardBus services. 1799 * Returns 0 on success and negative if unknown type of device (not normal, 1800 * bridge or CardBus). 1801 */ 1802 int pci_setup_device(struct pci_dev *dev) 1803 { 1804 u32 class; 1805 u16 cmd; 1806 u8 hdr_type; 1807 int pos = 0; 1808 struct pci_bus_region region; 1809 struct resource *res; 1810 1811 hdr_type = pci_hdr_type(dev); 1812 1813 dev->sysdata = dev->bus->sysdata; 1814 dev->dev.parent = dev->bus->bridge; 1815 dev->dev.bus = &pci_bus_type; 1816 dev->hdr_type = hdr_type & 0x7f; 1817 dev->multifunction = !!(hdr_type & 0x80); 1818 dev->error_state = pci_channel_io_normal; 1819 set_pcie_port_type(dev); 1820 1821 pci_set_of_node(dev); 1822 pci_set_acpi_fwnode(dev); 1823 1824 pci_dev_assign_slot(dev); 1825 1826 /* 1827 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1828 * set this higher, assuming the system even supports it. 1829 */ 1830 dev->dma_mask = 0xffffffff; 1831 1832 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1833 dev->bus->number, PCI_SLOT(dev->devfn), 1834 PCI_FUNC(dev->devfn)); 1835 1836 class = pci_class(dev); 1837 1838 dev->revision = class & 0xff; 1839 dev->class = class >> 8; /* upper 3 bytes */ 1840 1841 if (pci_early_dump) 1842 early_dump_pci_device(dev); 1843 1844 /* Need to have dev->class ready */ 1845 dev->cfg_size = pci_cfg_space_size(dev); 1846 1847 /* Need to have dev->cfg_size ready */ 1848 set_pcie_thunderbolt(dev); 1849 1850 set_pcie_untrusted(dev); 1851 1852 /* "Unknown power state" */ 1853 dev->current_state = PCI_UNKNOWN; 1854 1855 /* Early fixups, before probing the BARs */ 1856 pci_fixup_device(pci_fixup_early, dev); 1857 1858 pci_set_removable(dev); 1859 1860 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 1861 dev->vendor, dev->device, dev->hdr_type, dev->class); 1862 1863 /* Device class may be changed after fixup */ 1864 class = dev->class >> 8; 1865 1866 if (dev->non_compliant_bars && !dev->mmio_always_on) { 1867 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1868 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1869 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1870 cmd &= ~PCI_COMMAND_IO; 1871 cmd &= ~PCI_COMMAND_MEMORY; 1872 pci_write_config_word(dev, PCI_COMMAND, cmd); 1873 } 1874 } 1875 1876 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1877 1878 switch (dev->hdr_type) { /* header type */ 1879 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1880 if (class == PCI_CLASS_BRIDGE_PCI) 1881 goto bad; 1882 pci_read_irq(dev); 1883 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1884 1885 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1886 1887 /* 1888 * Do the ugly legacy mode stuff here rather than broken chip 1889 * quirk code. Legacy mode ATA controllers have fixed 1890 * addresses. These are not always echoed in BAR0-3, and 1891 * BAR0-3 in a few cases contain junk! 1892 */ 1893 if (class == PCI_CLASS_STORAGE_IDE) { 1894 u8 progif; 1895 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1896 if ((progif & 1) == 0) { 1897 region.start = 0x1F0; 1898 region.end = 0x1F7; 1899 res = &dev->resource[0]; 1900 res->flags = LEGACY_IO_RESOURCE; 1901 pcibios_bus_to_resource(dev->bus, res, ®ion); 1902 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1903 res); 1904 region.start = 0x3F6; 1905 region.end = 0x3F6; 1906 res = &dev->resource[1]; 1907 res->flags = LEGACY_IO_RESOURCE; 1908 pcibios_bus_to_resource(dev->bus, res, ®ion); 1909 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1910 res); 1911 } 1912 if ((progif & 4) == 0) { 1913 region.start = 0x170; 1914 region.end = 0x177; 1915 res = &dev->resource[2]; 1916 res->flags = LEGACY_IO_RESOURCE; 1917 pcibios_bus_to_resource(dev->bus, res, ®ion); 1918 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1919 res); 1920 region.start = 0x376; 1921 region.end = 0x376; 1922 res = &dev->resource[3]; 1923 res->flags = LEGACY_IO_RESOURCE; 1924 pcibios_bus_to_resource(dev->bus, res, ®ion); 1925 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1926 res); 1927 } 1928 } 1929 break; 1930 1931 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1932 /* 1933 * The PCI-to-PCI bridge spec requires that subtractive 1934 * decoding (i.e. transparent) bridge must have programming 1935 * interface code of 0x01. 1936 */ 1937 pci_read_irq(dev); 1938 dev->transparent = ((dev->class & 0xff) == 1); 1939 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1940 pci_read_bridge_windows(dev); 1941 set_pcie_hotplug_bridge(dev); 1942 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1943 if (pos) { 1944 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1945 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1946 } 1947 break; 1948 1949 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1950 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1951 goto bad; 1952 pci_read_irq(dev); 1953 pci_read_bases(dev, 1, 0); 1954 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1955 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1956 break; 1957 1958 default: /* unknown header */ 1959 pci_err(dev, "unknown header type %02x, ignoring device\n", 1960 dev->hdr_type); 1961 pci_release_of_node(dev); 1962 return -EIO; 1963 1964 bad: 1965 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1966 dev->class, dev->hdr_type); 1967 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1968 } 1969 1970 /* We found a fine healthy device, go go go... */ 1971 return 0; 1972 } 1973 1974 static void pci_configure_mps(struct pci_dev *dev) 1975 { 1976 struct pci_dev *bridge = pci_upstream_bridge(dev); 1977 int mps, mpss, p_mps, rc; 1978 1979 if (!pci_is_pcie(dev)) 1980 return; 1981 1982 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 1983 if (dev->is_virtfn) 1984 return; 1985 1986 /* 1987 * For Root Complex Integrated Endpoints, program the maximum 1988 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 1989 */ 1990 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 1991 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 1992 mps = 128; 1993 else 1994 mps = 128 << dev->pcie_mpss; 1995 rc = pcie_set_mps(dev, mps); 1996 if (rc) { 1997 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1998 mps); 1999 } 2000 return; 2001 } 2002 2003 if (!bridge || !pci_is_pcie(bridge)) 2004 return; 2005 2006 mps = pcie_get_mps(dev); 2007 p_mps = pcie_get_mps(bridge); 2008 2009 if (mps == p_mps) 2010 return; 2011 2012 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2013 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2014 mps, pci_name(bridge), p_mps); 2015 return; 2016 } 2017 2018 /* 2019 * Fancier MPS configuration is done later by 2020 * pcie_bus_configure_settings() 2021 */ 2022 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2023 return; 2024 2025 mpss = 128 << dev->pcie_mpss; 2026 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2027 pcie_set_mps(bridge, mpss); 2028 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2029 mpss, p_mps, 128 << bridge->pcie_mpss); 2030 p_mps = pcie_get_mps(bridge); 2031 } 2032 2033 rc = pcie_set_mps(dev, p_mps); 2034 if (rc) { 2035 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2036 p_mps); 2037 return; 2038 } 2039 2040 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2041 p_mps, mps, mpss); 2042 } 2043 2044 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2045 { 2046 struct pci_host_bridge *host; 2047 u32 cap; 2048 u16 ctl; 2049 int ret; 2050 2051 if (!pci_is_pcie(dev)) 2052 return 0; 2053 2054 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2055 if (ret) 2056 return 0; 2057 2058 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2059 return 0; 2060 2061 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2062 if (ret) 2063 return 0; 2064 2065 host = pci_find_host_bridge(dev->bus); 2066 if (!host) 2067 return 0; 2068 2069 /* 2070 * If some device in the hierarchy doesn't handle Extended Tags 2071 * correctly, make sure they're disabled. 2072 */ 2073 if (host->no_ext_tags) { 2074 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2075 pci_info(dev, "disabling Extended Tags\n"); 2076 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2077 PCI_EXP_DEVCTL_EXT_TAG); 2078 } 2079 return 0; 2080 } 2081 2082 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2083 pci_info(dev, "enabling Extended Tags\n"); 2084 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2085 PCI_EXP_DEVCTL_EXT_TAG); 2086 } 2087 return 0; 2088 } 2089 2090 /** 2091 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2092 * @dev: PCI device to query 2093 * 2094 * Returns true if the device has enabled relaxed ordering attribute. 2095 */ 2096 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2097 { 2098 u16 v; 2099 2100 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2101 2102 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2103 } 2104 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2105 2106 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2107 { 2108 struct pci_dev *root; 2109 2110 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ 2111 if (dev->is_virtfn) 2112 return; 2113 2114 if (!pcie_relaxed_ordering_enabled(dev)) 2115 return; 2116 2117 /* 2118 * For now, we only deal with Relaxed Ordering issues with Root 2119 * Ports. Peer-to-Peer DMA is another can of worms. 2120 */ 2121 root = pcie_find_root_port(dev); 2122 if (!root) 2123 return; 2124 2125 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2126 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2127 PCI_EXP_DEVCTL_RELAX_EN); 2128 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2129 } 2130 } 2131 2132 static void pci_configure_ltr(struct pci_dev *dev) 2133 { 2134 #ifdef CONFIG_PCIEASPM 2135 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 2136 struct pci_dev *bridge; 2137 u32 cap, ctl; 2138 2139 if (!pci_is_pcie(dev)) 2140 return; 2141 2142 /* Read L1 PM substate capabilities */ 2143 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); 2144 2145 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2146 if (!(cap & PCI_EXP_DEVCAP2_LTR)) 2147 return; 2148 2149 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); 2150 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { 2151 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2152 dev->ltr_path = 1; 2153 return; 2154 } 2155 2156 bridge = pci_upstream_bridge(dev); 2157 if (bridge && bridge->ltr_path) 2158 dev->ltr_path = 1; 2159 2160 return; 2161 } 2162 2163 if (!host->native_ltr) 2164 return; 2165 2166 /* 2167 * Software must not enable LTR in an Endpoint unless the Root 2168 * Complex and all intermediate Switches indicate support for LTR. 2169 * PCIe r4.0, sec 6.18. 2170 */ 2171 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 2172 ((bridge = pci_upstream_bridge(dev)) && 2173 bridge->ltr_path)) { 2174 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2175 PCI_EXP_DEVCTL2_LTR_EN); 2176 dev->ltr_path = 1; 2177 } 2178 #endif 2179 } 2180 2181 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2182 { 2183 #ifdef CONFIG_PCI_PASID 2184 struct pci_dev *bridge; 2185 int pcie_type; 2186 u32 cap; 2187 2188 if (!pci_is_pcie(dev)) 2189 return; 2190 2191 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2192 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2193 return; 2194 2195 pcie_type = pci_pcie_type(dev); 2196 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2197 pcie_type == PCI_EXP_TYPE_RC_END) 2198 dev->eetlp_prefix_path = 1; 2199 else { 2200 bridge = pci_upstream_bridge(dev); 2201 if (bridge && bridge->eetlp_prefix_path) 2202 dev->eetlp_prefix_path = 1; 2203 } 2204 #endif 2205 } 2206 2207 static void pci_configure_serr(struct pci_dev *dev) 2208 { 2209 u16 control; 2210 2211 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2212 2213 /* 2214 * A bridge will not forward ERR_ messages coming from an 2215 * endpoint unless SERR# forwarding is enabled. 2216 */ 2217 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2218 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2219 control |= PCI_BRIDGE_CTL_SERR; 2220 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2221 } 2222 } 2223 } 2224 2225 static void pci_configure_device(struct pci_dev *dev) 2226 { 2227 pci_configure_mps(dev); 2228 pci_configure_extended_tags(dev, NULL); 2229 pci_configure_relaxed_ordering(dev); 2230 pci_configure_ltr(dev); 2231 pci_configure_eetlp_prefix(dev); 2232 pci_configure_serr(dev); 2233 2234 pci_acpi_program_hp_params(dev); 2235 } 2236 2237 static void pci_release_capabilities(struct pci_dev *dev) 2238 { 2239 pci_aer_exit(dev); 2240 pci_rcec_exit(dev); 2241 pci_iov_release(dev); 2242 pci_free_cap_save_buffers(dev); 2243 } 2244 2245 /** 2246 * pci_release_dev - Free a PCI device structure when all users of it are 2247 * finished 2248 * @dev: device that's been disconnected 2249 * 2250 * Will be called only by the device core when all users of this PCI device are 2251 * done. 2252 */ 2253 static void pci_release_dev(struct device *dev) 2254 { 2255 struct pci_dev *pci_dev; 2256 2257 pci_dev = to_pci_dev(dev); 2258 pci_release_capabilities(pci_dev); 2259 pci_release_of_node(pci_dev); 2260 pcibios_release_device(pci_dev); 2261 pci_bus_put(pci_dev->bus); 2262 kfree(pci_dev->driver_override); 2263 bitmap_free(pci_dev->dma_alias_mask); 2264 dev_dbg(dev, "device released\n"); 2265 kfree(pci_dev); 2266 } 2267 2268 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2269 { 2270 struct pci_dev *dev; 2271 2272 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2273 if (!dev) 2274 return NULL; 2275 2276 INIT_LIST_HEAD(&dev->bus_list); 2277 dev->dev.type = &pci_dev_type; 2278 dev->bus = pci_bus_get(bus); 2279 2280 return dev; 2281 } 2282 EXPORT_SYMBOL(pci_alloc_dev); 2283 2284 static bool pci_bus_crs_vendor_id(u32 l) 2285 { 2286 return (l & 0xffff) == 0x0001; 2287 } 2288 2289 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2290 int timeout) 2291 { 2292 int delay = 1; 2293 2294 if (!pci_bus_crs_vendor_id(*l)) 2295 return true; /* not a CRS completion */ 2296 2297 if (!timeout) 2298 return false; /* CRS, but caller doesn't want to wait */ 2299 2300 /* 2301 * We got the reserved Vendor ID that indicates a completion with 2302 * Configuration Request Retry Status (CRS). Retry until we get a 2303 * valid Vendor ID or we time out. 2304 */ 2305 while (pci_bus_crs_vendor_id(*l)) { 2306 if (delay > timeout) { 2307 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2308 pci_domain_nr(bus), bus->number, 2309 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2310 2311 return false; 2312 } 2313 if (delay >= 1000) 2314 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2315 pci_domain_nr(bus), bus->number, 2316 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2317 2318 msleep(delay); 2319 delay *= 2; 2320 2321 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2322 return false; 2323 } 2324 2325 if (delay >= 1000) 2326 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2327 pci_domain_nr(bus), bus->number, 2328 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2329 2330 return true; 2331 } 2332 2333 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2334 int timeout) 2335 { 2336 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2337 return false; 2338 2339 /* Some broken boards return 0 or ~0 if a slot is empty: */ 2340 if (*l == 0xffffffff || *l == 0x00000000 || 2341 *l == 0x0000ffff || *l == 0xffff0000) 2342 return false; 2343 2344 if (pci_bus_crs_vendor_id(*l)) 2345 return pci_bus_wait_crs(bus, devfn, l, timeout); 2346 2347 return true; 2348 } 2349 2350 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2351 int timeout) 2352 { 2353 #ifdef CONFIG_PCI_QUIRKS 2354 struct pci_dev *bridge = bus->self; 2355 2356 /* 2357 * Certain IDT switches have an issue where they improperly trigger 2358 * ACS Source Validation errors on completions for config reads. 2359 */ 2360 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2361 bridge->device == 0x80b5) 2362 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2363 #endif 2364 2365 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2366 } 2367 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2368 2369 /* 2370 * Read the config data for a PCI device, sanity-check it, 2371 * and fill in the dev structure. 2372 */ 2373 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2374 { 2375 struct pci_dev *dev; 2376 u32 l; 2377 2378 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2379 return NULL; 2380 2381 dev = pci_alloc_dev(bus); 2382 if (!dev) 2383 return NULL; 2384 2385 dev->devfn = devfn; 2386 dev->vendor = l & 0xffff; 2387 dev->device = (l >> 16) & 0xffff; 2388 2389 if (pci_setup_device(dev)) { 2390 pci_bus_put(dev->bus); 2391 kfree(dev); 2392 return NULL; 2393 } 2394 2395 return dev; 2396 } 2397 2398 void pcie_report_downtraining(struct pci_dev *dev) 2399 { 2400 if (!pci_is_pcie(dev)) 2401 return; 2402 2403 /* Look from the device up to avoid downstream ports with no devices */ 2404 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2405 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2406 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2407 return; 2408 2409 /* Multi-function PCIe devices share the same link/status */ 2410 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2411 return; 2412 2413 /* Print link status only if the device is constrained by the fabric */ 2414 __pcie_print_link_status(dev, false); 2415 } 2416 2417 static void pci_init_capabilities(struct pci_dev *dev) 2418 { 2419 pci_ea_init(dev); /* Enhanced Allocation */ 2420 pci_msi_init(dev); /* Disable MSI */ 2421 pci_msix_init(dev); /* Disable MSI-X */ 2422 2423 /* Buffers for saving PCIe and PCI-X capabilities */ 2424 pci_allocate_cap_save_buffers(dev); 2425 2426 pci_pm_init(dev); /* Power Management */ 2427 pci_vpd_init(dev); /* Vital Product Data */ 2428 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2429 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2430 pci_ats_init(dev); /* Address Translation Services */ 2431 pci_pri_init(dev); /* Page Request Interface */ 2432 pci_pasid_init(dev); /* Process Address Space ID */ 2433 pci_acs_init(dev); /* Access Control Services */ 2434 pci_ptm_init(dev); /* Precision Time Measurement */ 2435 pci_aer_init(dev); /* Advanced Error Reporting */ 2436 pci_dpc_init(dev); /* Downstream Port Containment */ 2437 pci_rcec_init(dev); /* Root Complex Event Collector */ 2438 2439 pcie_report_downtraining(dev); 2440 pci_init_reset_methods(dev); 2441 } 2442 2443 /* 2444 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2445 * devices. Firmware interfaces that can select the MSI domain on a 2446 * per-device basis should be called from here. 2447 */ 2448 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2449 { 2450 struct irq_domain *d; 2451 2452 /* 2453 * If a domain has been set through the pcibios_add_device() 2454 * callback, then this is the one (platform code knows best). 2455 */ 2456 d = dev_get_msi_domain(&dev->dev); 2457 if (d) 2458 return d; 2459 2460 /* 2461 * Let's see if we have a firmware interface able to provide 2462 * the domain. 2463 */ 2464 d = pci_msi_get_device_domain(dev); 2465 if (d) 2466 return d; 2467 2468 return NULL; 2469 } 2470 2471 static void pci_set_msi_domain(struct pci_dev *dev) 2472 { 2473 struct irq_domain *d; 2474 2475 /* 2476 * If the platform or firmware interfaces cannot supply a 2477 * device-specific MSI domain, then inherit the default domain 2478 * from the host bridge itself. 2479 */ 2480 d = pci_dev_msi_domain(dev); 2481 if (!d) 2482 d = dev_get_msi_domain(&dev->bus->dev); 2483 2484 dev_set_msi_domain(&dev->dev, d); 2485 } 2486 2487 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2488 { 2489 int ret; 2490 2491 pci_configure_device(dev); 2492 2493 device_initialize(&dev->dev); 2494 dev->dev.release = pci_release_dev; 2495 2496 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2497 dev->dev.dma_mask = &dev->dma_mask; 2498 dev->dev.dma_parms = &dev->dma_parms; 2499 dev->dev.coherent_dma_mask = 0xffffffffull; 2500 2501 dma_set_max_seg_size(&dev->dev, 65536); 2502 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2503 2504 /* Fix up broken headers */ 2505 pci_fixup_device(pci_fixup_header, dev); 2506 2507 pci_reassigndev_resource_alignment(dev); 2508 2509 dev->state_saved = false; 2510 2511 pci_init_capabilities(dev); 2512 2513 /* 2514 * Add the device to our list of discovered devices 2515 * and the bus list for fixup functions, etc. 2516 */ 2517 down_write(&pci_bus_sem); 2518 list_add_tail(&dev->bus_list, &bus->devices); 2519 up_write(&pci_bus_sem); 2520 2521 ret = pcibios_add_device(dev); 2522 WARN_ON(ret < 0); 2523 2524 /* Set up MSI IRQ domain */ 2525 pci_set_msi_domain(dev); 2526 2527 /* Notifier could use PCI capabilities */ 2528 dev->match_driver = false; 2529 ret = device_add(&dev->dev); 2530 WARN_ON(ret < 0); 2531 } 2532 2533 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2534 { 2535 struct pci_dev *dev; 2536 2537 dev = pci_get_slot(bus, devfn); 2538 if (dev) { 2539 pci_dev_put(dev); 2540 return dev; 2541 } 2542 2543 dev = pci_scan_device(bus, devfn); 2544 if (!dev) 2545 return NULL; 2546 2547 pci_device_add(dev, bus); 2548 2549 return dev; 2550 } 2551 EXPORT_SYMBOL(pci_scan_single_device); 2552 2553 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) 2554 { 2555 int pos; 2556 u16 cap = 0; 2557 unsigned next_fn; 2558 2559 if (pci_ari_enabled(bus)) { 2560 if (!dev) 2561 return 0; 2562 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2563 if (!pos) 2564 return 0; 2565 2566 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2567 next_fn = PCI_ARI_CAP_NFN(cap); 2568 if (next_fn <= fn) 2569 return 0; /* protect against malformed list */ 2570 2571 return next_fn; 2572 } 2573 2574 /* dev may be NULL for non-contiguous multifunction devices */ 2575 if (!dev || dev->multifunction) 2576 return (fn + 1) % 8; 2577 2578 return 0; 2579 } 2580 2581 static int only_one_child(struct pci_bus *bus) 2582 { 2583 struct pci_dev *bridge = bus->self; 2584 2585 /* 2586 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2587 * we scan for all possible devices, not just Device 0. 2588 */ 2589 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2590 return 0; 2591 2592 /* 2593 * A PCIe Downstream Port normally leads to a Link with only Device 2594 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2595 * only for Device 0 in that situation. 2596 */ 2597 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2598 return 1; 2599 2600 return 0; 2601 } 2602 2603 /** 2604 * pci_scan_slot - Scan a PCI slot on a bus for devices 2605 * @bus: PCI bus to scan 2606 * @devfn: slot number to scan (must have zero function) 2607 * 2608 * Scan a PCI slot on the specified PCI bus for devices, adding 2609 * discovered devices to the @bus->devices list. New devices 2610 * will not have is_added set. 2611 * 2612 * Returns the number of new devices found. 2613 */ 2614 int pci_scan_slot(struct pci_bus *bus, int devfn) 2615 { 2616 unsigned fn, nr = 0; 2617 struct pci_dev *dev; 2618 2619 if (only_one_child(bus) && (devfn > 0)) 2620 return 0; /* Already scanned the entire slot */ 2621 2622 dev = pci_scan_single_device(bus, devfn); 2623 if (!dev) 2624 return 0; 2625 if (!pci_dev_is_added(dev)) 2626 nr++; 2627 2628 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { 2629 dev = pci_scan_single_device(bus, devfn + fn); 2630 if (dev) { 2631 if (!pci_dev_is_added(dev)) 2632 nr++; 2633 dev->multifunction = 1; 2634 } 2635 } 2636 2637 /* Only one slot has PCIe device */ 2638 if (bus->self && nr) 2639 pcie_aspm_init_link_state(bus->self); 2640 2641 return nr; 2642 } 2643 EXPORT_SYMBOL(pci_scan_slot); 2644 2645 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2646 { 2647 u8 *smpss = data; 2648 2649 if (!pci_is_pcie(dev)) 2650 return 0; 2651 2652 /* 2653 * We don't have a way to change MPS settings on devices that have 2654 * drivers attached. A hot-added device might support only the minimum 2655 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2656 * where devices may be hot-added, we limit the fabric MPS to 128 so 2657 * hot-added devices will work correctly. 2658 * 2659 * However, if we hot-add a device to a slot directly below a Root 2660 * Port, it's impossible for there to be other existing devices below 2661 * the port. We don't limit the MPS in this case because we can 2662 * reconfigure MPS on both the Root Port and the hot-added device, 2663 * and there are no other devices involved. 2664 * 2665 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2666 */ 2667 if (dev->is_hotplug_bridge && 2668 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2669 *smpss = 0; 2670 2671 if (*smpss > dev->pcie_mpss) 2672 *smpss = dev->pcie_mpss; 2673 2674 return 0; 2675 } 2676 2677 static void pcie_write_mps(struct pci_dev *dev, int mps) 2678 { 2679 int rc; 2680 2681 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2682 mps = 128 << dev->pcie_mpss; 2683 2684 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2685 dev->bus->self) 2686 2687 /* 2688 * For "Performance", the assumption is made that 2689 * downstream communication will never be larger than 2690 * the MRRS. So, the MPS only needs to be configured 2691 * for the upstream communication. This being the case, 2692 * walk from the top down and set the MPS of the child 2693 * to that of the parent bus. 2694 * 2695 * Configure the device MPS with the smaller of the 2696 * device MPSS or the bridge MPS (which is assumed to be 2697 * properly configured at this point to the largest 2698 * allowable MPS based on its parent bus). 2699 */ 2700 mps = min(mps, pcie_get_mps(dev->bus->self)); 2701 } 2702 2703 rc = pcie_set_mps(dev, mps); 2704 if (rc) 2705 pci_err(dev, "Failed attempting to set the MPS\n"); 2706 } 2707 2708 static void pcie_write_mrrs(struct pci_dev *dev) 2709 { 2710 int rc, mrrs; 2711 2712 /* 2713 * In the "safe" case, do not configure the MRRS. There appear to be 2714 * issues with setting MRRS to 0 on a number of devices. 2715 */ 2716 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2717 return; 2718 2719 /* 2720 * For max performance, the MRRS must be set to the largest supported 2721 * value. However, it cannot be configured larger than the MPS the 2722 * device or the bus can support. This should already be properly 2723 * configured by a prior call to pcie_write_mps(). 2724 */ 2725 mrrs = pcie_get_mps(dev); 2726 2727 /* 2728 * MRRS is a R/W register. Invalid values can be written, but a 2729 * subsequent read will verify if the value is acceptable or not. 2730 * If the MRRS value provided is not acceptable (e.g., too large), 2731 * shrink the value until it is acceptable to the HW. 2732 */ 2733 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2734 rc = pcie_set_readrq(dev, mrrs); 2735 if (!rc) 2736 break; 2737 2738 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2739 mrrs /= 2; 2740 } 2741 2742 if (mrrs < 128) 2743 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2744 } 2745 2746 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2747 { 2748 int mps, orig_mps; 2749 2750 if (!pci_is_pcie(dev)) 2751 return 0; 2752 2753 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2754 pcie_bus_config == PCIE_BUS_DEFAULT) 2755 return 0; 2756 2757 mps = 128 << *(u8 *)data; 2758 orig_mps = pcie_get_mps(dev); 2759 2760 pcie_write_mps(dev, mps); 2761 pcie_write_mrrs(dev); 2762 2763 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2764 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2765 orig_mps, pcie_get_readrq(dev)); 2766 2767 return 0; 2768 } 2769 2770 /* 2771 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2772 * parents then children fashion. If this changes, then this code will not 2773 * work as designed. 2774 */ 2775 void pcie_bus_configure_settings(struct pci_bus *bus) 2776 { 2777 u8 smpss = 0; 2778 2779 if (!bus->self) 2780 return; 2781 2782 if (!pci_is_pcie(bus->self)) 2783 return; 2784 2785 /* 2786 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2787 * to be aware of the MPS of the destination. To work around this, 2788 * simply force the MPS of the entire system to the smallest possible. 2789 */ 2790 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2791 smpss = 0; 2792 2793 if (pcie_bus_config == PCIE_BUS_SAFE) { 2794 smpss = bus->self->pcie_mpss; 2795 2796 pcie_find_smpss(bus->self, &smpss); 2797 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2798 } 2799 2800 pcie_bus_configure_set(bus->self, &smpss); 2801 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2802 } 2803 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2804 2805 /* 2806 * Called after each bus is probed, but before its children are examined. This 2807 * is marked as __weak because multiple architectures define it. 2808 */ 2809 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2810 { 2811 /* nothing to do, expected to be removed in the future */ 2812 } 2813 2814 /** 2815 * pci_scan_child_bus_extend() - Scan devices below a bus 2816 * @bus: Bus to scan for devices 2817 * @available_buses: Total number of buses available (%0 does not try to 2818 * extend beyond the minimal) 2819 * 2820 * Scans devices below @bus including subordinate buses. Returns new 2821 * subordinate number including all the found devices. Passing 2822 * @available_buses causes the remaining bus space to be distributed 2823 * equally between hotplug-capable bridges to allow future extension of the 2824 * hierarchy. 2825 */ 2826 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2827 unsigned int available_buses) 2828 { 2829 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2830 unsigned int start = bus->busn_res.start; 2831 unsigned int devfn, fn, cmax, max = start; 2832 struct pci_dev *dev; 2833 int nr_devs; 2834 2835 dev_dbg(&bus->dev, "scanning bus\n"); 2836 2837 /* Go find them, Rover! */ 2838 for (devfn = 0; devfn < 256; devfn += 8) { 2839 nr_devs = pci_scan_slot(bus, devfn); 2840 2841 /* 2842 * The Jailhouse hypervisor may pass individual functions of a 2843 * multi-function device to a guest without passing function 0. 2844 * Look for them as well. 2845 */ 2846 if (jailhouse_paravirt() && nr_devs == 0) { 2847 for (fn = 1; fn < 8; fn++) { 2848 dev = pci_scan_single_device(bus, devfn + fn); 2849 if (dev) 2850 dev->multifunction = 1; 2851 } 2852 } 2853 } 2854 2855 /* Reserve buses for SR-IOV capability */ 2856 used_buses = pci_iov_bus_range(bus); 2857 max += used_buses; 2858 2859 /* 2860 * After performing arch-dependent fixup of the bus, look behind 2861 * all PCI-to-PCI bridges on this bus. 2862 */ 2863 if (!bus->is_added) { 2864 dev_dbg(&bus->dev, "fixups for bus\n"); 2865 pcibios_fixup_bus(bus); 2866 bus->is_added = 1; 2867 } 2868 2869 /* 2870 * Calculate how many hotplug bridges and normal bridges there 2871 * are on this bus. We will distribute the additional available 2872 * buses between hotplug bridges. 2873 */ 2874 for_each_pci_bridge(dev, bus) { 2875 if (dev->is_hotplug_bridge) 2876 hotplug_bridges++; 2877 else 2878 normal_bridges++; 2879 } 2880 2881 /* 2882 * Scan bridges that are already configured. We don't touch them 2883 * unless they are misconfigured (which will be done in the second 2884 * scan below). 2885 */ 2886 for_each_pci_bridge(dev, bus) { 2887 cmax = max; 2888 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2889 2890 /* 2891 * Reserve one bus for each bridge now to avoid extending 2892 * hotplug bridges too much during the second scan below. 2893 */ 2894 used_buses++; 2895 if (cmax - max > 1) 2896 used_buses += cmax - max - 1; 2897 } 2898 2899 /* Scan bridges that need to be reconfigured */ 2900 for_each_pci_bridge(dev, bus) { 2901 unsigned int buses = 0; 2902 2903 if (!hotplug_bridges && normal_bridges == 1) { 2904 2905 /* 2906 * There is only one bridge on the bus (upstream 2907 * port) so it gets all available buses which it 2908 * can then distribute to the possible hotplug 2909 * bridges below. 2910 */ 2911 buses = available_buses; 2912 } else if (dev->is_hotplug_bridge) { 2913 2914 /* 2915 * Distribute the extra buses between hotplug 2916 * bridges if any. 2917 */ 2918 buses = available_buses / hotplug_bridges; 2919 buses = min(buses, available_buses - used_buses + 1); 2920 } 2921 2922 cmax = max; 2923 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2924 /* One bus is already accounted so don't add it again */ 2925 if (max - cmax > 1) 2926 used_buses += max - cmax - 1; 2927 } 2928 2929 /* 2930 * Make sure a hotplug bridge has at least the minimum requested 2931 * number of buses but allow it to grow up to the maximum available 2932 * bus number of there is room. 2933 */ 2934 if (bus->self && bus->self->is_hotplug_bridge) { 2935 used_buses = max_t(unsigned int, available_buses, 2936 pci_hotplug_bus_size - 1); 2937 if (max - start < used_buses) { 2938 max = start + used_buses; 2939 2940 /* Do not allocate more buses than we have room left */ 2941 if (max > bus->busn_res.end) 2942 max = bus->busn_res.end; 2943 2944 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 2945 &bus->busn_res, max - start); 2946 } 2947 } 2948 2949 /* 2950 * We've scanned the bus and so we know all about what's on 2951 * the other side of any bridges that may be on this bus plus 2952 * any devices. 2953 * 2954 * Return how far we've got finding sub-buses. 2955 */ 2956 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 2957 return max; 2958 } 2959 2960 /** 2961 * pci_scan_child_bus() - Scan devices below a bus 2962 * @bus: Bus to scan for devices 2963 * 2964 * Scans devices below @bus including subordinate buses. Returns new 2965 * subordinate number including all the found devices. 2966 */ 2967 unsigned int pci_scan_child_bus(struct pci_bus *bus) 2968 { 2969 return pci_scan_child_bus_extend(bus, 0); 2970 } 2971 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 2972 2973 /** 2974 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 2975 * @bridge: Host bridge to set up 2976 * 2977 * Default empty implementation. Replace with an architecture-specific setup 2978 * routine, if necessary. 2979 */ 2980 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 2981 { 2982 return 0; 2983 } 2984 2985 void __weak pcibios_add_bus(struct pci_bus *bus) 2986 { 2987 } 2988 2989 void __weak pcibios_remove_bus(struct pci_bus *bus) 2990 { 2991 } 2992 2993 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 2994 struct pci_ops *ops, void *sysdata, struct list_head *resources) 2995 { 2996 int error; 2997 struct pci_host_bridge *bridge; 2998 2999 bridge = pci_alloc_host_bridge(0); 3000 if (!bridge) 3001 return NULL; 3002 3003 bridge->dev.parent = parent; 3004 3005 list_splice_init(resources, &bridge->windows); 3006 bridge->sysdata = sysdata; 3007 bridge->busnr = bus; 3008 bridge->ops = ops; 3009 3010 error = pci_register_host_bridge(bridge); 3011 if (error < 0) 3012 goto err_out; 3013 3014 return bridge->bus; 3015 3016 err_out: 3017 put_device(&bridge->dev); 3018 return NULL; 3019 } 3020 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3021 3022 int pci_host_probe(struct pci_host_bridge *bridge) 3023 { 3024 struct pci_bus *bus, *child; 3025 int ret; 3026 3027 ret = pci_scan_root_bus_bridge(bridge); 3028 if (ret < 0) { 3029 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3030 return ret; 3031 } 3032 3033 bus = bridge->bus; 3034 3035 /* 3036 * We insert PCI resources into the iomem_resource and 3037 * ioport_resource trees in either pci_bus_claim_resources() 3038 * or pci_bus_assign_resources(). 3039 */ 3040 if (pci_has_flag(PCI_PROBE_ONLY)) { 3041 pci_bus_claim_resources(bus); 3042 } else { 3043 pci_bus_size_bridges(bus); 3044 pci_bus_assign_resources(bus); 3045 3046 list_for_each_entry(child, &bus->children, node) 3047 pcie_bus_configure_settings(child); 3048 } 3049 3050 pci_bus_add_devices(bus); 3051 return 0; 3052 } 3053 EXPORT_SYMBOL_GPL(pci_host_probe); 3054 3055 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3056 { 3057 struct resource *res = &b->busn_res; 3058 struct resource *parent_res, *conflict; 3059 3060 res->start = bus; 3061 res->end = bus_max; 3062 res->flags = IORESOURCE_BUS; 3063 3064 if (!pci_is_root_bus(b)) 3065 parent_res = &b->parent->busn_res; 3066 else { 3067 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3068 res->flags |= IORESOURCE_PCI_FIXED; 3069 } 3070 3071 conflict = request_resource_conflict(parent_res, res); 3072 3073 if (conflict) 3074 dev_info(&b->dev, 3075 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3076 res, pci_is_root_bus(b) ? "domain " : "", 3077 parent_res, conflict->name, conflict); 3078 3079 return conflict == NULL; 3080 } 3081 3082 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3083 { 3084 struct resource *res = &b->busn_res; 3085 struct resource old_res = *res; 3086 resource_size_t size; 3087 int ret; 3088 3089 if (res->start > bus_max) 3090 return -EINVAL; 3091 3092 size = bus_max - res->start + 1; 3093 ret = adjust_resource(res, res->start, size); 3094 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3095 &old_res, ret ? "can not be" : "is", bus_max); 3096 3097 if (!ret && !res->parent) 3098 pci_bus_insert_busn_res(b, res->start, res->end); 3099 3100 return ret; 3101 } 3102 3103 void pci_bus_release_busn_res(struct pci_bus *b) 3104 { 3105 struct resource *res = &b->busn_res; 3106 int ret; 3107 3108 if (!res->flags || !res->parent) 3109 return; 3110 3111 ret = release_resource(res); 3112 dev_info(&b->dev, "busn_res: %pR %s released\n", 3113 res, ret ? "can not be" : "is"); 3114 } 3115 3116 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3117 { 3118 struct resource_entry *window; 3119 bool found = false; 3120 struct pci_bus *b; 3121 int max, bus, ret; 3122 3123 if (!bridge) 3124 return -EINVAL; 3125 3126 resource_list_for_each_entry(window, &bridge->windows) 3127 if (window->res->flags & IORESOURCE_BUS) { 3128 bridge->busnr = window->res->start; 3129 found = true; 3130 break; 3131 } 3132 3133 ret = pci_register_host_bridge(bridge); 3134 if (ret < 0) 3135 return ret; 3136 3137 b = bridge->bus; 3138 bus = bridge->busnr; 3139 3140 if (!found) { 3141 dev_info(&b->dev, 3142 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3143 bus); 3144 pci_bus_insert_busn_res(b, bus, 255); 3145 } 3146 3147 max = pci_scan_child_bus(b); 3148 3149 if (!found) 3150 pci_bus_update_busn_res_end(b, max); 3151 3152 return 0; 3153 } 3154 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3155 3156 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3157 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3158 { 3159 struct resource_entry *window; 3160 bool found = false; 3161 struct pci_bus *b; 3162 int max; 3163 3164 resource_list_for_each_entry(window, resources) 3165 if (window->res->flags & IORESOURCE_BUS) { 3166 found = true; 3167 break; 3168 } 3169 3170 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3171 if (!b) 3172 return NULL; 3173 3174 if (!found) { 3175 dev_info(&b->dev, 3176 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3177 bus); 3178 pci_bus_insert_busn_res(b, bus, 255); 3179 } 3180 3181 max = pci_scan_child_bus(b); 3182 3183 if (!found) 3184 pci_bus_update_busn_res_end(b, max); 3185 3186 return b; 3187 } 3188 EXPORT_SYMBOL(pci_scan_root_bus); 3189 3190 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3191 void *sysdata) 3192 { 3193 LIST_HEAD(resources); 3194 struct pci_bus *b; 3195 3196 pci_add_resource(&resources, &ioport_resource); 3197 pci_add_resource(&resources, &iomem_resource); 3198 pci_add_resource(&resources, &busn_resource); 3199 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3200 if (b) { 3201 pci_scan_child_bus(b); 3202 } else { 3203 pci_free_resource_list(&resources); 3204 } 3205 return b; 3206 } 3207 EXPORT_SYMBOL(pci_scan_bus); 3208 3209 /** 3210 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3211 * @bridge: PCI bridge for the bus to scan 3212 * 3213 * Scan a PCI bus and child buses for new devices, add them, 3214 * and enable them, resizing bridge mmio/io resource if necessary 3215 * and possible. The caller must ensure the child devices are already 3216 * removed for resizing to occur. 3217 * 3218 * Returns the max number of subordinate bus discovered. 3219 */ 3220 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3221 { 3222 unsigned int max; 3223 struct pci_bus *bus = bridge->subordinate; 3224 3225 max = pci_scan_child_bus(bus); 3226 3227 pci_assign_unassigned_bridge_resources(bridge); 3228 3229 pci_bus_add_devices(bus); 3230 3231 return max; 3232 } 3233 3234 /** 3235 * pci_rescan_bus - Scan a PCI bus for devices 3236 * @bus: PCI bus to scan 3237 * 3238 * Scan a PCI bus and child buses for new devices, add them, 3239 * and enable them. 3240 * 3241 * Returns the max number of subordinate bus discovered. 3242 */ 3243 unsigned int pci_rescan_bus(struct pci_bus *bus) 3244 { 3245 unsigned int max; 3246 3247 max = pci_scan_child_bus(bus); 3248 pci_assign_unassigned_bus_resources(bus); 3249 pci_bus_add_devices(bus); 3250 3251 return max; 3252 } 3253 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3254 3255 /* 3256 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3257 * routines should always be executed under this mutex. 3258 */ 3259 static DEFINE_MUTEX(pci_rescan_remove_lock); 3260 3261 void pci_lock_rescan_remove(void) 3262 { 3263 mutex_lock(&pci_rescan_remove_lock); 3264 } 3265 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3266 3267 void pci_unlock_rescan_remove(void) 3268 { 3269 mutex_unlock(&pci_rescan_remove_lock); 3270 } 3271 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3272 3273 static int __init pci_sort_bf_cmp(const struct device *d_a, 3274 const struct device *d_b) 3275 { 3276 const struct pci_dev *a = to_pci_dev(d_a); 3277 const struct pci_dev *b = to_pci_dev(d_b); 3278 3279 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3280 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3281 3282 if (a->bus->number < b->bus->number) return -1; 3283 else if (a->bus->number > b->bus->number) return 1; 3284 3285 if (a->devfn < b->devfn) return -1; 3286 else if (a->devfn > b->devfn) return 1; 3287 3288 return 0; 3289 } 3290 3291 void __init pci_sort_breadthfirst(void) 3292 { 3293 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3294 } 3295 3296 int pci_hp_add_bridge(struct pci_dev *dev) 3297 { 3298 struct pci_bus *parent = dev->bus; 3299 int busnr, start = parent->busn_res.start; 3300 unsigned int available_buses = 0; 3301 int end = parent->busn_res.end; 3302 3303 for (busnr = start; busnr <= end; busnr++) { 3304 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3305 break; 3306 } 3307 if (busnr-- > end) { 3308 pci_err(dev, "No bus number available for hot-added bridge\n"); 3309 return -1; 3310 } 3311 3312 /* Scan bridges that are already configured */ 3313 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3314 3315 /* 3316 * Distribute the available bus numbers between hotplug-capable 3317 * bridges to make extending the chain later possible. 3318 */ 3319 available_buses = end - busnr; 3320 3321 /* Scan bridges that need to be reconfigured */ 3322 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3323 3324 if (!dev->subordinate) 3325 return -1; 3326 3327 return 0; 3328 } 3329 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3330