1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_pci.h> 12 #include <linux/pci_hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/cpumask.h> 16 #include <linux/aer.h> 17 #include <linux/acpi.h> 18 #include <linux/hypervisor.h> 19 #include <linux/irqdomain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/bitfield.h> 22 #include "pci.h" 23 24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 25 #define CARDBUS_RESERVE_BUSNR 3 26 27 static struct resource busn_resource = { 28 .name = "PCI busn", 29 .start = 0, 30 .end = 255, 31 .flags = IORESOURCE_BUS, 32 }; 33 34 /* Ugh. Need to stop exporting this to modules. */ 35 LIST_HEAD(pci_root_buses); 36 EXPORT_SYMBOL(pci_root_buses); 37 38 static LIST_HEAD(pci_domain_busn_res_list); 39 40 struct pci_domain_busn_res { 41 struct list_head list; 42 struct resource res; 43 int domain_nr; 44 }; 45 46 static struct resource *get_pci_domain_busn_res(int domain_nr) 47 { 48 struct pci_domain_busn_res *r; 49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list) 51 if (r->domain_nr == domain_nr) 52 return &r->res; 53 54 r = kzalloc(sizeof(*r), GFP_KERNEL); 55 if (!r) 56 return NULL; 57 58 r->domain_nr = domain_nr; 59 r->res.start = 0; 60 r->res.end = 0xff; 61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 62 63 list_add_tail(&r->list, &pci_domain_busn_res_list); 64 65 return &r->res; 66 } 67 68 /* 69 * Some device drivers need know if PCI is initiated. 70 * Basically, we think PCI is not initiated when there 71 * is no device to be found on the pci_bus_type. 72 */ 73 int no_pci_devices(void) 74 { 75 struct device *dev; 76 int no_devices; 77 78 dev = bus_find_next_device(&pci_bus_type, NULL); 79 no_devices = (dev == NULL); 80 put_device(dev); 81 return no_devices; 82 } 83 EXPORT_SYMBOL(no_pci_devices); 84 85 /* 86 * PCI Bus Class 87 */ 88 static void release_pcibus_dev(struct device *dev) 89 { 90 struct pci_bus *pci_bus = to_pci_bus(dev); 91 92 put_device(pci_bus->bridge); 93 pci_bus_remove_resources(pci_bus); 94 pci_release_bus_of_node(pci_bus); 95 kfree(pci_bus); 96 } 97 98 static const struct class pcibus_class = { 99 .name = "pci_bus", 100 .dev_release = &release_pcibus_dev, 101 .dev_groups = pcibus_groups, 102 }; 103 104 static int __init pcibus_class_init(void) 105 { 106 return class_register(&pcibus_class); 107 } 108 postcore_initcall(pcibus_class_init); 109 110 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 111 { 112 u64 size = mask & maxbase; /* Find the significant bits */ 113 if (!size) 114 return 0; 115 116 /* 117 * Get the lowest of them to find the decode size, and from that 118 * the extent. 119 */ 120 size = size & ~(size-1); 121 122 /* 123 * base == maxbase can be valid only if the BAR has already been 124 * programmed with all 1s. 125 */ 126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 127 return 0; 128 129 return size; 130 } 131 132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 133 { 134 u32 mem_type; 135 unsigned long flags; 136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 139 flags |= IORESOURCE_IO; 140 return flags; 141 } 142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 144 flags |= IORESOURCE_MEM; 145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 146 flags |= IORESOURCE_PREFETCH; 147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 149 switch (mem_type) { 150 case PCI_BASE_ADDRESS_MEM_TYPE_32: 151 break; 152 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 153 /* 1M mem BAR treated as 32-bit BAR */ 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_64: 156 flags |= IORESOURCE_MEM_64; 157 break; 158 default: 159 /* mem unknown type treated as 32-bit BAR */ 160 break; 161 } 162 return flags; 163 } 164 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 167 /** 168 * __pci_size_bars - Read the raw BAR mask for a range of PCI BARs 169 * @dev: the PCI device 170 * @count: number of BARs to size 171 * @pos: starting config space position 172 * @sizes: array to store mask values 173 * @rom: indicate whether to use ROM mask, which avoids enabling ROM BARs 174 * 175 * Provided @sizes array must be sufficiently sized to store results for 176 * @count u32 BARs. Caller is responsible for disabling decode to specified 177 * BAR range around calling this function. This function is intended to avoid 178 * disabling decode around sizing each BAR individually, which can result in 179 * non-trivial overhead in virtualized environments with very large PCI BARs. 180 */ 181 static void __pci_size_bars(struct pci_dev *dev, int count, 182 unsigned int pos, u32 *sizes, bool rom) 183 { 184 u32 orig, mask = rom ? PCI_ROM_ADDRESS_MASK : ~0; 185 int i; 186 187 for (i = 0; i < count; i++, pos += 4, sizes++) { 188 pci_read_config_dword(dev, pos, &orig); 189 pci_write_config_dword(dev, pos, mask); 190 pci_read_config_dword(dev, pos, sizes); 191 pci_write_config_dword(dev, pos, orig); 192 } 193 } 194 195 void __pci_size_stdbars(struct pci_dev *dev, int count, 196 unsigned int pos, u32 *sizes) 197 { 198 __pci_size_bars(dev, count, pos, sizes, false); 199 } 200 201 static void __pci_size_rom(struct pci_dev *dev, unsigned int pos, u32 *sizes) 202 { 203 __pci_size_bars(dev, 1, pos, sizes, true); 204 } 205 206 /** 207 * __pci_read_base - Read a PCI BAR 208 * @dev: the PCI device 209 * @type: type of the BAR 210 * @res: resource buffer to be filled in 211 * @pos: BAR position in the config space 212 * @sizes: array of one or more pre-read BAR masks 213 * 214 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 215 */ 216 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 217 struct resource *res, unsigned int pos, u32 *sizes) 218 { 219 u32 l = 0, sz; 220 u64 l64, sz64, mask64; 221 struct pci_bus_region region, inverted_region; 222 const char *res_name = pci_resource_name(dev, res - dev->resource); 223 224 res->name = pci_name(dev); 225 226 pci_read_config_dword(dev, pos, &l); 227 sz = sizes[0]; 228 229 /* 230 * All bits set in sz means the device isn't working properly. 231 * If the BAR isn't implemented, all bits must be 0. If it's a 232 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 233 * 1 must be clear. 234 */ 235 if (PCI_POSSIBLE_ERROR(sz)) 236 sz = 0; 237 238 /* 239 * I don't know how l can have all bits set. Copied from old code. 240 * Maybe it fixes a bug on some ancient platform. 241 */ 242 if (PCI_POSSIBLE_ERROR(l)) 243 l = 0; 244 245 if (type == pci_bar_unknown) { 246 res->flags = decode_bar(dev, l); 247 res->flags |= IORESOURCE_SIZEALIGN; 248 if (res->flags & IORESOURCE_IO) { 249 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 250 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 251 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 252 } else { 253 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 254 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 255 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 256 } 257 } else { 258 if (l & PCI_ROM_ADDRESS_ENABLE) 259 res->flags |= IORESOURCE_ROM_ENABLE; 260 l64 = l & PCI_ROM_ADDRESS_MASK; 261 sz64 = sz & PCI_ROM_ADDRESS_MASK; 262 mask64 = PCI_ROM_ADDRESS_MASK; 263 } 264 265 if (res->flags & IORESOURCE_MEM_64) { 266 pci_read_config_dword(dev, pos + 4, &l); 267 sz = sizes[1]; 268 269 l64 |= ((u64)l << 32); 270 sz64 |= ((u64)sz << 32); 271 mask64 |= ((u64)~0 << 32); 272 } 273 274 if (!sz64) 275 goto fail; 276 277 sz64 = pci_size(l64, sz64, mask64); 278 if (!sz64) { 279 pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name); 280 goto fail; 281 } 282 283 if (res->flags & IORESOURCE_MEM_64) { 284 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 285 && sz64 > 0x100000000ULL) { 286 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 287 res->start = 0; 288 res->end = 0; 289 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n", 290 res_name, (unsigned long long)sz64); 291 goto out; 292 } 293 294 if ((sizeof(pci_bus_addr_t) < 8) && l) { 295 /* Above 32-bit boundary; try to reallocate */ 296 res->flags |= IORESOURCE_UNSET; 297 res->start = 0; 298 res->end = sz64 - 1; 299 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n", 300 res_name, (unsigned long long)l64); 301 goto out; 302 } 303 } 304 305 region.start = l64; 306 region.end = l64 + sz64 - 1; 307 308 pcibios_bus_to_resource(dev->bus, res, ®ion); 309 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 310 311 /* 312 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 313 * the corresponding resource address (the physical address used by 314 * the CPU. Converting that resource address back to a bus address 315 * should yield the original BAR value: 316 * 317 * resource_to_bus(bus_to_resource(A)) == A 318 * 319 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 320 * be claimed by the device. 321 */ 322 if (inverted_region.start != region.start) { 323 res->flags |= IORESOURCE_UNSET; 324 res->start = 0; 325 res->end = region.end - region.start; 326 pci_info(dev, "%s: initial BAR value %#010llx invalid\n", 327 res_name, (unsigned long long)region.start); 328 } 329 330 goto out; 331 332 333 fail: 334 res->flags = 0; 335 out: 336 if (res->flags) 337 pci_info(dev, "%s %pR\n", res_name, res); 338 339 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 340 } 341 342 static __always_inline void pci_read_bases(struct pci_dev *dev, 343 unsigned int howmany, int rom) 344 { 345 u32 rombar, stdbars[PCI_STD_NUM_BARS]; 346 unsigned int pos, reg; 347 u16 orig_cmd; 348 349 BUILD_BUG_ON(statically_true(howmany > PCI_STD_NUM_BARS)); 350 351 if (dev->non_compliant_bars) 352 return; 353 354 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 355 if (dev->is_virtfn) 356 return; 357 358 /* No printks while decoding is disabled! */ 359 if (!dev->mmio_always_on) { 360 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 361 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 362 pci_write_config_word(dev, PCI_COMMAND, 363 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 364 } 365 } 366 367 __pci_size_stdbars(dev, howmany, PCI_BASE_ADDRESS_0, stdbars); 368 if (rom) 369 __pci_size_rom(dev, rom, &rombar); 370 371 if (!dev->mmio_always_on && 372 (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 373 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 374 375 for (pos = 0; pos < howmany; pos++) { 376 struct resource *res = &dev->resource[pos]; 377 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 378 pos += __pci_read_base(dev, pci_bar_unknown, 379 res, reg, &stdbars[pos]); 380 } 381 382 if (rom) { 383 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 384 dev->rom_base_reg = rom; 385 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 386 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 387 __pci_read_base(dev, pci_bar_mem32, res, rom, &rombar); 388 } 389 } 390 391 static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res, 392 bool log) 393 { 394 u8 io_base_lo, io_limit_lo; 395 unsigned long io_mask, io_granularity, base, limit; 396 struct pci_bus_region region; 397 398 io_mask = PCI_IO_RANGE_MASK; 399 io_granularity = 0x1000; 400 if (dev->io_window_1k) { 401 /* Support 1K I/O space granularity */ 402 io_mask = PCI_IO_1K_RANGE_MASK; 403 io_granularity = 0x400; 404 } 405 406 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 407 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 408 base = (io_base_lo & io_mask) << 8; 409 limit = (io_limit_lo & io_mask) << 8; 410 411 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 412 u16 io_base_hi, io_limit_hi; 413 414 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 415 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 416 base |= ((unsigned long) io_base_hi << 16); 417 limit |= ((unsigned long) io_limit_hi << 16); 418 } 419 420 if (base <= limit) { 421 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 422 region.start = base; 423 region.end = limit + io_granularity - 1; 424 pcibios_bus_to_resource(dev->bus, res, ®ion); 425 if (log) 426 pci_info(dev, " bridge window %pR\n", res); 427 } 428 } 429 430 static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res, 431 bool log) 432 { 433 u16 mem_base_lo, mem_limit_lo; 434 unsigned long base, limit; 435 struct pci_bus_region region; 436 437 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 438 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 439 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 440 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 441 if (base <= limit) { 442 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 443 region.start = base; 444 region.end = limit + 0xfffff; 445 pcibios_bus_to_resource(dev->bus, res, ®ion); 446 if (log) 447 pci_info(dev, " bridge window %pR\n", res); 448 } 449 } 450 451 static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res, 452 bool log) 453 { 454 u16 mem_base_lo, mem_limit_lo; 455 u64 base64, limit64; 456 pci_bus_addr_t base, limit; 457 struct pci_bus_region region; 458 459 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 460 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 461 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 462 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 463 464 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 465 u32 mem_base_hi, mem_limit_hi; 466 467 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 468 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 469 470 /* 471 * Some bridges set the base > limit by default, and some 472 * (broken) BIOSes do not initialize them. If we find 473 * this, just assume they are not being used. 474 */ 475 if (mem_base_hi <= mem_limit_hi) { 476 base64 |= (u64) mem_base_hi << 32; 477 limit64 |= (u64) mem_limit_hi << 32; 478 } 479 } 480 481 base = (pci_bus_addr_t) base64; 482 limit = (pci_bus_addr_t) limit64; 483 484 if (base != base64) { 485 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 486 (unsigned long long) base64); 487 return; 488 } 489 490 if (base <= limit) { 491 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 492 IORESOURCE_MEM | IORESOURCE_PREFETCH; 493 if (res->flags & PCI_PREF_RANGE_TYPE_64) 494 res->flags |= IORESOURCE_MEM_64; 495 region.start = base; 496 region.end = limit + 0xfffff; 497 pcibios_bus_to_resource(dev->bus, res, ®ion); 498 if (log) 499 pci_info(dev, " bridge window %pR\n", res); 500 } 501 } 502 503 static void pci_read_bridge_windows(struct pci_dev *bridge) 504 { 505 u32 buses; 506 u16 io; 507 u32 pmem, tmp; 508 struct resource res; 509 510 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses); 511 res.flags = IORESOURCE_BUS; 512 res.start = (buses >> 8) & 0xff; 513 res.end = (buses >> 16) & 0xff; 514 pci_info(bridge, "PCI bridge to %pR%s\n", &res, 515 bridge->transparent ? " (subtractive decode)" : ""); 516 517 pci_read_config_word(bridge, PCI_IO_BASE, &io); 518 if (!io) { 519 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 520 pci_read_config_word(bridge, PCI_IO_BASE, &io); 521 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 522 } 523 if (io) { 524 bridge->io_window = 1; 525 pci_read_bridge_io(bridge, &res, true); 526 } 527 528 pci_read_bridge_mmio(bridge, &res, true); 529 530 /* 531 * DECchip 21050 pass 2 errata: the bridge may miss an address 532 * disconnect boundary by one PCI data phase. Workaround: do not 533 * use prefetching on this device. 534 */ 535 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 536 return; 537 538 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 539 if (!pmem) { 540 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 541 0xffe0fff0); 542 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 543 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 544 } 545 if (!pmem) 546 return; 547 548 bridge->pref_window = 1; 549 550 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 551 552 /* 553 * Bridge claims to have a 64-bit prefetchable memory 554 * window; verify that the upper bits are actually 555 * writable. 556 */ 557 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 558 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 559 0xffffffff); 560 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 561 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 562 if (tmp) 563 bridge->pref_64_window = 1; 564 } 565 566 pci_read_bridge_mmio_pref(bridge, &res, true); 567 } 568 569 void pci_read_bridge_bases(struct pci_bus *child) 570 { 571 struct pci_dev *dev = child->self; 572 struct resource *res; 573 int i; 574 575 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 576 return; 577 578 pci_info(dev, "PCI bridge to %pR%s\n", 579 &child->busn_res, 580 dev->transparent ? " (subtractive decode)" : ""); 581 582 pci_bus_remove_resources(child); 583 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 584 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 585 586 pci_read_bridge_io(child->self, child->resource[0], false); 587 pci_read_bridge_mmio(child->self, child->resource[1], false); 588 pci_read_bridge_mmio_pref(child->self, child->resource[2], false); 589 590 if (!dev->transparent) 591 return; 592 593 pci_bus_for_each_resource(child->parent, res) { 594 if (!res || !res->flags) 595 continue; 596 597 pci_bus_add_resource(child, res); 598 pci_info(dev, " bridge window %pR (subtractive decode)\n", res); 599 } 600 } 601 602 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 603 { 604 struct pci_bus *b; 605 606 b = kzalloc(sizeof(*b), GFP_KERNEL); 607 if (!b) 608 return NULL; 609 610 INIT_LIST_HEAD(&b->node); 611 INIT_LIST_HEAD(&b->children); 612 INIT_LIST_HEAD(&b->devices); 613 INIT_LIST_HEAD(&b->slots); 614 INIT_LIST_HEAD(&b->resources); 615 b->max_bus_speed = PCI_SPEED_UNKNOWN; 616 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 617 #ifdef CONFIG_PCI_DOMAINS_GENERIC 618 if (parent) 619 b->domain_nr = parent->domain_nr; 620 #endif 621 return b; 622 } 623 624 static void pci_release_host_bridge_dev(struct device *dev) 625 { 626 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 627 628 if (bridge->release_fn) 629 bridge->release_fn(bridge); 630 631 pci_free_resource_list(&bridge->windows); 632 pci_free_resource_list(&bridge->dma_ranges); 633 kfree(bridge); 634 } 635 636 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 637 { 638 INIT_LIST_HEAD(&bridge->windows); 639 INIT_LIST_HEAD(&bridge->dma_ranges); 640 641 /* 642 * We assume we can manage these PCIe features. Some systems may 643 * reserve these for use by the platform itself, e.g., an ACPI BIOS 644 * may implement its own AER handling and use _OSC to prevent the 645 * OS from interfering. 646 */ 647 bridge->native_aer = 1; 648 bridge->native_pcie_hotplug = 1; 649 bridge->native_shpc_hotplug = 1; 650 bridge->native_pme = 1; 651 bridge->native_ltr = 1; 652 bridge->native_dpc = 1; 653 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 654 bridge->native_cxl_error = 1; 655 656 device_initialize(&bridge->dev); 657 } 658 659 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 660 { 661 struct pci_host_bridge *bridge; 662 663 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 664 if (!bridge) 665 return NULL; 666 667 pci_init_host_bridge(bridge); 668 bridge->dev.release = pci_release_host_bridge_dev; 669 670 return bridge; 671 } 672 EXPORT_SYMBOL(pci_alloc_host_bridge); 673 674 static void devm_pci_alloc_host_bridge_release(void *data) 675 { 676 pci_free_host_bridge(data); 677 } 678 679 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 680 size_t priv) 681 { 682 int ret; 683 struct pci_host_bridge *bridge; 684 685 bridge = pci_alloc_host_bridge(priv); 686 if (!bridge) 687 return NULL; 688 689 bridge->dev.parent = dev; 690 691 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 692 bridge); 693 if (ret) 694 return NULL; 695 696 ret = devm_of_pci_bridge_init(dev, bridge); 697 if (ret) 698 return NULL; 699 700 return bridge; 701 } 702 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 703 704 void pci_free_host_bridge(struct pci_host_bridge *bridge) 705 { 706 put_device(&bridge->dev); 707 } 708 EXPORT_SYMBOL(pci_free_host_bridge); 709 710 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 711 static const unsigned char pcix_bus_speed[] = { 712 PCI_SPEED_UNKNOWN, /* 0 */ 713 PCI_SPEED_66MHz_PCIX, /* 1 */ 714 PCI_SPEED_100MHz_PCIX, /* 2 */ 715 PCI_SPEED_133MHz_PCIX, /* 3 */ 716 PCI_SPEED_UNKNOWN, /* 4 */ 717 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 718 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 719 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 720 PCI_SPEED_UNKNOWN, /* 8 */ 721 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 722 PCI_SPEED_100MHz_PCIX_266, /* A */ 723 PCI_SPEED_133MHz_PCIX_266, /* B */ 724 PCI_SPEED_UNKNOWN, /* C */ 725 PCI_SPEED_66MHz_PCIX_533, /* D */ 726 PCI_SPEED_100MHz_PCIX_533, /* E */ 727 PCI_SPEED_133MHz_PCIX_533 /* F */ 728 }; 729 730 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 731 const unsigned char pcie_link_speed[] = { 732 PCI_SPEED_UNKNOWN, /* 0 */ 733 PCIE_SPEED_2_5GT, /* 1 */ 734 PCIE_SPEED_5_0GT, /* 2 */ 735 PCIE_SPEED_8_0GT, /* 3 */ 736 PCIE_SPEED_16_0GT, /* 4 */ 737 PCIE_SPEED_32_0GT, /* 5 */ 738 PCIE_SPEED_64_0GT, /* 6 */ 739 PCI_SPEED_UNKNOWN, /* 7 */ 740 PCI_SPEED_UNKNOWN, /* 8 */ 741 PCI_SPEED_UNKNOWN, /* 9 */ 742 PCI_SPEED_UNKNOWN, /* A */ 743 PCI_SPEED_UNKNOWN, /* B */ 744 PCI_SPEED_UNKNOWN, /* C */ 745 PCI_SPEED_UNKNOWN, /* D */ 746 PCI_SPEED_UNKNOWN, /* E */ 747 PCI_SPEED_UNKNOWN /* F */ 748 }; 749 EXPORT_SYMBOL_GPL(pcie_link_speed); 750 751 const char *pci_speed_string(enum pci_bus_speed speed) 752 { 753 /* Indexed by the pci_bus_speed enum */ 754 static const char *speed_strings[] = { 755 "33 MHz PCI", /* 0x00 */ 756 "66 MHz PCI", /* 0x01 */ 757 "66 MHz PCI-X", /* 0x02 */ 758 "100 MHz PCI-X", /* 0x03 */ 759 "133 MHz PCI-X", /* 0x04 */ 760 NULL, /* 0x05 */ 761 NULL, /* 0x06 */ 762 NULL, /* 0x07 */ 763 NULL, /* 0x08 */ 764 "66 MHz PCI-X 266", /* 0x09 */ 765 "100 MHz PCI-X 266", /* 0x0a */ 766 "133 MHz PCI-X 266", /* 0x0b */ 767 "Unknown AGP", /* 0x0c */ 768 "1x AGP", /* 0x0d */ 769 "2x AGP", /* 0x0e */ 770 "4x AGP", /* 0x0f */ 771 "8x AGP", /* 0x10 */ 772 "66 MHz PCI-X 533", /* 0x11 */ 773 "100 MHz PCI-X 533", /* 0x12 */ 774 "133 MHz PCI-X 533", /* 0x13 */ 775 "2.5 GT/s PCIe", /* 0x14 */ 776 "5.0 GT/s PCIe", /* 0x15 */ 777 "8.0 GT/s PCIe", /* 0x16 */ 778 "16.0 GT/s PCIe", /* 0x17 */ 779 "32.0 GT/s PCIe", /* 0x18 */ 780 "64.0 GT/s PCIe", /* 0x19 */ 781 }; 782 783 if (speed < ARRAY_SIZE(speed_strings)) 784 return speed_strings[speed]; 785 return "Unknown"; 786 } 787 EXPORT_SYMBOL_GPL(pci_speed_string); 788 789 void pcie_update_link_speed(struct pci_bus *bus) 790 { 791 struct pci_dev *bridge = bus->self; 792 u16 linksta; 793 794 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 795 __pcie_update_link_speed(bus, linksta); 796 } 797 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 798 799 static unsigned char agp_speeds[] = { 800 AGP_UNKNOWN, 801 AGP_1X, 802 AGP_2X, 803 AGP_4X, 804 AGP_8X 805 }; 806 807 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 808 { 809 int index = 0; 810 811 if (agpstat & 4) 812 index = 3; 813 else if (agpstat & 2) 814 index = 2; 815 else if (agpstat & 1) 816 index = 1; 817 else 818 goto out; 819 820 if (agp3) { 821 index += 2; 822 if (index == 5) 823 index = 0; 824 } 825 826 out: 827 return agp_speeds[index]; 828 } 829 830 static void pci_set_bus_speed(struct pci_bus *bus) 831 { 832 struct pci_dev *bridge = bus->self; 833 int pos; 834 835 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 836 if (!pos) 837 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 838 if (pos) { 839 u32 agpstat, agpcmd; 840 841 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 842 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 843 844 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 845 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 846 } 847 848 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 849 if (pos) { 850 u16 status; 851 enum pci_bus_speed max; 852 853 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 854 &status); 855 856 if (status & PCI_X_SSTATUS_533MHZ) { 857 max = PCI_SPEED_133MHz_PCIX_533; 858 } else if (status & PCI_X_SSTATUS_266MHZ) { 859 max = PCI_SPEED_133MHz_PCIX_266; 860 } else if (status & PCI_X_SSTATUS_133MHZ) { 861 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 862 max = PCI_SPEED_133MHz_PCIX_ECC; 863 else 864 max = PCI_SPEED_133MHz_PCIX; 865 } else { 866 max = PCI_SPEED_66MHz_PCIX; 867 } 868 869 bus->max_bus_speed = max; 870 bus->cur_bus_speed = 871 pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)]; 872 873 return; 874 } 875 876 if (pci_is_pcie(bridge)) { 877 u32 linkcap; 878 879 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 880 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 881 882 pcie_update_link_speed(bus); 883 } 884 } 885 886 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 887 { 888 struct irq_domain *d; 889 890 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 891 d = dev_get_msi_domain(bus->bridge); 892 893 /* 894 * Any firmware interface that can resolve the msi_domain 895 * should be called from here. 896 */ 897 if (!d) 898 d = pci_host_bridge_of_msi_domain(bus); 899 if (!d) 900 d = pci_host_bridge_acpi_msi_domain(bus); 901 902 /* 903 * If no IRQ domain was found via the OF tree, try looking it up 904 * directly through the fwnode_handle. 905 */ 906 if (!d) { 907 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 908 909 if (fwnode) 910 d = irq_find_matching_fwnode(fwnode, 911 DOMAIN_BUS_PCI_MSI); 912 } 913 914 return d; 915 } 916 917 static void pci_set_bus_msi_domain(struct pci_bus *bus) 918 { 919 struct irq_domain *d; 920 struct pci_bus *b; 921 922 /* 923 * The bus can be a root bus, a subordinate bus, or a virtual bus 924 * created by an SR-IOV device. Walk up to the first bridge device 925 * found or derive the domain from the host bridge. 926 */ 927 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 928 if (b->self) 929 d = dev_get_msi_domain(&b->self->dev); 930 } 931 932 if (!d) 933 d = pci_host_bridge_msi_domain(b); 934 935 dev_set_msi_domain(&bus->dev, d); 936 } 937 938 static bool pci_preserve_config(struct pci_host_bridge *host_bridge) 939 { 940 if (pci_acpi_preserve_config(host_bridge)) 941 return true; 942 943 if (host_bridge->dev.parent && host_bridge->dev.parent->of_node) 944 return of_pci_preserve_config(host_bridge->dev.parent->of_node); 945 946 return false; 947 } 948 949 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 950 { 951 struct device *parent = bridge->dev.parent; 952 struct resource_entry *window, *next, *n; 953 struct pci_bus *bus, *b; 954 resource_size_t offset, next_offset; 955 LIST_HEAD(resources); 956 struct resource *res, *next_res; 957 char addr[64], *fmt; 958 const char *name; 959 int err; 960 961 bus = pci_alloc_bus(NULL); 962 if (!bus) 963 return -ENOMEM; 964 965 bridge->bus = bus; 966 967 bus->sysdata = bridge->sysdata; 968 bus->ops = bridge->ops; 969 bus->number = bus->busn_res.start = bridge->busnr; 970 #ifdef CONFIG_PCI_DOMAINS_GENERIC 971 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 972 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 973 else 974 bus->domain_nr = bridge->domain_nr; 975 if (bus->domain_nr < 0) { 976 err = bus->domain_nr; 977 goto free; 978 } 979 #endif 980 981 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 982 if (b) { 983 /* Ignore it if we already got here via a different bridge */ 984 dev_dbg(&b->dev, "bus already known\n"); 985 err = -EEXIST; 986 goto free; 987 } 988 989 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 990 bridge->busnr); 991 992 err = pcibios_root_bridge_prepare(bridge); 993 if (err) 994 goto free; 995 996 /* Temporarily move resources off the list */ 997 list_splice_init(&bridge->windows, &resources); 998 err = device_add(&bridge->dev); 999 if (err) { 1000 put_device(&bridge->dev); 1001 goto free; 1002 } 1003 bus->bridge = get_device(&bridge->dev); 1004 device_enable_async_suspend(bus->bridge); 1005 pci_set_bus_of_node(bus); 1006 pci_set_bus_msi_domain(bus); 1007 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 1008 !pci_host_of_has_msi_map(parent)) 1009 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1010 1011 if (!parent) 1012 set_dev_node(bus->bridge, pcibus_to_node(bus)); 1013 1014 bus->dev.class = &pcibus_class; 1015 bus->dev.parent = bus->bridge; 1016 1017 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 1018 name = dev_name(&bus->dev); 1019 1020 err = device_register(&bus->dev); 1021 if (err) 1022 goto unregister; 1023 1024 pcibios_add_bus(bus); 1025 1026 if (bus->ops->add_bus) { 1027 err = bus->ops->add_bus(bus); 1028 if (WARN_ON(err < 0)) 1029 dev_err(&bus->dev, "failed to add bus: %d\n", err); 1030 } 1031 1032 /* Create legacy_io and legacy_mem files for this bus */ 1033 pci_create_legacy_files(bus); 1034 1035 if (parent) 1036 dev_info(parent, "PCI host bridge to bus %s\n", name); 1037 else 1038 pr_info("PCI host bridge to bus %s\n", name); 1039 1040 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 1041 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 1042 1043 /* Check if the boot configuration by FW needs to be preserved */ 1044 bridge->preserve_config = pci_preserve_config(bridge); 1045 1046 /* Coalesce contiguous windows */ 1047 resource_list_for_each_entry_safe(window, n, &resources) { 1048 if (list_is_last(&window->node, &resources)) 1049 break; 1050 1051 next = list_next_entry(window, node); 1052 offset = window->offset; 1053 res = window->res; 1054 next_offset = next->offset; 1055 next_res = next->res; 1056 1057 if (res->flags != next_res->flags || offset != next_offset) 1058 continue; 1059 1060 if (res->end + 1 == next_res->start) { 1061 next_res->start = res->start; 1062 res->flags = res->start = res->end = 0; 1063 } 1064 } 1065 1066 /* Add initial resources to the bus */ 1067 resource_list_for_each_entry_safe(window, n, &resources) { 1068 offset = window->offset; 1069 res = window->res; 1070 if (!res->flags && !res->start && !res->end) { 1071 release_resource(res); 1072 resource_list_destroy_entry(window); 1073 continue; 1074 } 1075 1076 list_move_tail(&window->node, &bridge->windows); 1077 1078 if (res->flags & IORESOURCE_BUS) 1079 pci_bus_insert_busn_res(bus, bus->number, res->end); 1080 else 1081 pci_bus_add_resource(bus, res); 1082 1083 if (offset) { 1084 if (resource_type(res) == IORESOURCE_IO) 1085 fmt = " (bus address [%#06llx-%#06llx])"; 1086 else 1087 fmt = " (bus address [%#010llx-%#010llx])"; 1088 1089 snprintf(addr, sizeof(addr), fmt, 1090 (unsigned long long)(res->start - offset), 1091 (unsigned long long)(res->end - offset)); 1092 } else 1093 addr[0] = '\0'; 1094 1095 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 1096 } 1097 1098 down_write(&pci_bus_sem); 1099 list_add_tail(&bus->node, &pci_root_buses); 1100 up_write(&pci_bus_sem); 1101 1102 return 0; 1103 1104 unregister: 1105 put_device(&bridge->dev); 1106 device_del(&bridge->dev); 1107 1108 free: 1109 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1110 pci_bus_release_domain_nr(parent, bus->domain_nr); 1111 #endif 1112 kfree(bus); 1113 return err; 1114 } 1115 1116 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1117 { 1118 int pos; 1119 u32 status; 1120 1121 /* 1122 * If extended config space isn't accessible on a bridge's primary 1123 * bus, we certainly can't access it on the secondary bus. 1124 */ 1125 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1126 return false; 1127 1128 /* 1129 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1130 * extended config space is accessible on the primary, it's also 1131 * accessible on the secondary. 1132 */ 1133 if (pci_is_pcie(bridge) && 1134 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1135 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1136 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1137 return true; 1138 1139 /* 1140 * For the other bridge types: 1141 * - PCI-to-PCI bridges 1142 * - PCIe-to-PCI/PCI-X forward bridges 1143 * - PCI/PCI-X-to-PCIe reverse bridges 1144 * extended config space on the secondary side is only accessible 1145 * if the bridge supports PCI-X Mode 2. 1146 */ 1147 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1148 if (!pos) 1149 return false; 1150 1151 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1152 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1153 } 1154 1155 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1156 struct pci_dev *bridge, int busnr) 1157 { 1158 struct pci_bus *child; 1159 struct pci_host_bridge *host; 1160 int i; 1161 int ret; 1162 1163 /* Allocate a new bus and inherit stuff from the parent */ 1164 child = pci_alloc_bus(parent); 1165 if (!child) 1166 return NULL; 1167 1168 child->parent = parent; 1169 child->sysdata = parent->sysdata; 1170 child->bus_flags = parent->bus_flags; 1171 1172 host = pci_find_host_bridge(parent); 1173 if (host->child_ops) 1174 child->ops = host->child_ops; 1175 else 1176 child->ops = parent->ops; 1177 1178 /* 1179 * Initialize some portions of the bus device, but don't register 1180 * it now as the parent is not properly set up yet. 1181 */ 1182 child->dev.class = &pcibus_class; 1183 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1184 1185 /* Set up the primary, secondary and subordinate bus numbers */ 1186 child->number = child->busn_res.start = busnr; 1187 child->primary = parent->busn_res.start; 1188 child->busn_res.end = 0xff; 1189 1190 if (!bridge) { 1191 child->dev.parent = parent->bridge; 1192 goto add_dev; 1193 } 1194 1195 child->self = bridge; 1196 child->bridge = get_device(&bridge->dev); 1197 child->dev.parent = child->bridge; 1198 pci_set_bus_of_node(child); 1199 pci_set_bus_speed(child); 1200 1201 /* 1202 * Check whether extended config space is accessible on the child 1203 * bus. Note that we currently assume it is always accessible on 1204 * the root bus. 1205 */ 1206 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1207 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1208 pci_info(child, "extended config space not accessible\n"); 1209 } 1210 1211 /* Set up default resource pointers and names */ 1212 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1213 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1214 child->resource[i]->name = child->name; 1215 } 1216 bridge->subordinate = child; 1217 1218 add_dev: 1219 pci_set_bus_msi_domain(child); 1220 ret = device_register(&child->dev); 1221 WARN_ON(ret < 0); 1222 1223 pcibios_add_bus(child); 1224 1225 if (child->ops->add_bus) { 1226 ret = child->ops->add_bus(child); 1227 if (WARN_ON(ret < 0)) 1228 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1229 } 1230 1231 /* Create legacy_io and legacy_mem files for this bus */ 1232 pci_create_legacy_files(child); 1233 1234 return child; 1235 } 1236 1237 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1238 int busnr) 1239 { 1240 struct pci_bus *child; 1241 1242 child = pci_alloc_child_bus(parent, dev, busnr); 1243 if (child) { 1244 down_write(&pci_bus_sem); 1245 list_add_tail(&child->node, &parent->children); 1246 up_write(&pci_bus_sem); 1247 } 1248 return child; 1249 } 1250 EXPORT_SYMBOL(pci_add_new_bus); 1251 1252 static void pci_enable_rrs_sv(struct pci_dev *pdev) 1253 { 1254 u16 root_cap = 0; 1255 1256 /* Enable Configuration RRS Software Visibility if supported */ 1257 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1258 if (root_cap & PCI_EXP_RTCAP_RRS_SV) { 1259 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1260 PCI_EXP_RTCTL_RRS_SVE); 1261 pdev->config_rrs_sv = 1; 1262 } 1263 } 1264 1265 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1266 unsigned int available_buses); 1267 /** 1268 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1269 * numbers from EA capability. 1270 * @dev: Bridge 1271 * @sec: updated with secondary bus number from EA 1272 * @sub: updated with subordinate bus number from EA 1273 * 1274 * If @dev is a bridge with EA capability that specifies valid secondary 1275 * and subordinate bus numbers, return true with the bus numbers in @sec 1276 * and @sub. Otherwise return false. 1277 */ 1278 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1279 { 1280 int ea, offset; 1281 u32 dw; 1282 u8 ea_sec, ea_sub; 1283 1284 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1285 return false; 1286 1287 /* find PCI EA capability in list */ 1288 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1289 if (!ea) 1290 return false; 1291 1292 offset = ea + PCI_EA_FIRST_ENT; 1293 pci_read_config_dword(dev, offset, &dw); 1294 ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw); 1295 ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw); 1296 if (ea_sec == 0 || ea_sub < ea_sec) 1297 return false; 1298 1299 *sec = ea_sec; 1300 *sub = ea_sub; 1301 return true; 1302 } 1303 1304 /* 1305 * pci_scan_bridge_extend() - Scan buses behind a bridge 1306 * @bus: Parent bus the bridge is on 1307 * @dev: Bridge itself 1308 * @max: Starting subordinate number of buses behind this bridge 1309 * @available_buses: Total number of buses available for this bridge and 1310 * the devices below. After the minimal bus space has 1311 * been allocated the remaining buses will be 1312 * distributed equally between hotplug-capable bridges. 1313 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1314 * that need to be reconfigured. 1315 * 1316 * If it's a bridge, configure it and scan the bus behind it. 1317 * For CardBus bridges, we don't scan behind as the devices will 1318 * be handled by the bridge driver itself. 1319 * 1320 * We need to process bridges in two passes -- first we scan those 1321 * already configured by the BIOS and after we are done with all of 1322 * them, we proceed to assigning numbers to the remaining buses in 1323 * order to avoid overlaps between old and new bus numbers. 1324 * 1325 * Return: New subordinate number covering all buses behind this bridge. 1326 */ 1327 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1328 int max, unsigned int available_buses, 1329 int pass) 1330 { 1331 struct pci_bus *child; 1332 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1333 u32 buses, i, j = 0; 1334 u16 bctl; 1335 u8 primary, secondary, subordinate; 1336 int broken = 0; 1337 bool fixed_buses; 1338 u8 fixed_sec, fixed_sub; 1339 int next_busnr; 1340 1341 /* 1342 * Make sure the bridge is powered on to be able to access config 1343 * space of devices below it. 1344 */ 1345 pm_runtime_get_sync(&dev->dev); 1346 1347 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1348 primary = buses & 0xFF; 1349 secondary = (buses >> 8) & 0xFF; 1350 subordinate = (buses >> 16) & 0xFF; 1351 1352 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1353 secondary, subordinate, pass); 1354 1355 if (!primary && (primary != bus->number) && secondary && subordinate) { 1356 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1357 primary = bus->number; 1358 } 1359 1360 /* Check if setup is sensible at all */ 1361 if (!pass && 1362 (primary != bus->number || secondary <= bus->number || 1363 secondary > subordinate)) { 1364 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1365 secondary, subordinate); 1366 broken = 1; 1367 } 1368 1369 /* 1370 * Disable Master-Abort Mode during probing to avoid reporting of 1371 * bus errors in some architectures. 1372 */ 1373 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1374 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1375 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1376 1377 pci_enable_rrs_sv(dev); 1378 1379 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1380 !is_cardbus && !broken) { 1381 unsigned int cmax, buses; 1382 1383 /* 1384 * Bus already configured by firmware, process it in the 1385 * first pass and just note the configuration. 1386 */ 1387 if (pass) 1388 goto out; 1389 1390 /* 1391 * The bus might already exist for two reasons: Either we 1392 * are rescanning the bus or the bus is reachable through 1393 * more than one bridge. The second case can happen with 1394 * the i450NX chipset. 1395 */ 1396 child = pci_find_bus(pci_domain_nr(bus), secondary); 1397 if (!child) { 1398 child = pci_add_new_bus(bus, dev, secondary); 1399 if (!child) 1400 goto out; 1401 child->primary = primary; 1402 pci_bus_insert_busn_res(child, secondary, subordinate); 1403 child->bridge_ctl = bctl; 1404 } 1405 1406 buses = subordinate - secondary; 1407 cmax = pci_scan_child_bus_extend(child, buses); 1408 if (cmax > subordinate) 1409 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1410 subordinate, cmax); 1411 1412 /* Subordinate should equal child->busn_res.end */ 1413 if (subordinate > max) 1414 max = subordinate; 1415 } else { 1416 1417 /* 1418 * We need to assign a number to this bus which we always 1419 * do in the second pass. 1420 */ 1421 if (!pass) { 1422 if (pcibios_assign_all_busses() || broken || is_cardbus) 1423 1424 /* 1425 * Temporarily disable forwarding of the 1426 * configuration cycles on all bridges in 1427 * this bus segment to avoid possible 1428 * conflicts in the second pass between two 1429 * bridges programmed with overlapping bus 1430 * ranges. 1431 */ 1432 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1433 buses & ~0xffffff); 1434 goto out; 1435 } 1436 1437 /* Clear errors */ 1438 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1439 1440 /* Read bus numbers from EA Capability (if present) */ 1441 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1442 if (fixed_buses) 1443 next_busnr = fixed_sec; 1444 else 1445 next_busnr = max + 1; 1446 1447 /* 1448 * Prevent assigning a bus number that already exists. 1449 * This can happen when a bridge is hot-plugged, so in this 1450 * case we only re-scan this bus. 1451 */ 1452 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1453 if (!child) { 1454 child = pci_add_new_bus(bus, dev, next_busnr); 1455 if (!child) 1456 goto out; 1457 pci_bus_insert_busn_res(child, next_busnr, 1458 bus->busn_res.end); 1459 } 1460 max++; 1461 if (available_buses) 1462 available_buses--; 1463 1464 buses = (buses & 0xff000000) 1465 | ((unsigned int)(child->primary) << 0) 1466 | ((unsigned int)(child->busn_res.start) << 8) 1467 | ((unsigned int)(child->busn_res.end) << 16); 1468 1469 /* 1470 * yenta.c forces a secondary latency timer of 176. 1471 * Copy that behaviour here. 1472 */ 1473 if (is_cardbus) { 1474 buses &= ~0xff000000; 1475 buses |= CARDBUS_LATENCY_TIMER << 24; 1476 } 1477 1478 /* We need to blast all three values with a single write */ 1479 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1480 1481 if (!is_cardbus) { 1482 child->bridge_ctl = bctl; 1483 max = pci_scan_child_bus_extend(child, available_buses); 1484 } else { 1485 1486 /* 1487 * For CardBus bridges, we leave 4 bus numbers as 1488 * cards with a PCI-to-PCI bridge can be inserted 1489 * later. 1490 */ 1491 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1492 struct pci_bus *parent = bus; 1493 if (pci_find_bus(pci_domain_nr(bus), 1494 max+i+1)) 1495 break; 1496 while (parent->parent) { 1497 if ((!pcibios_assign_all_busses()) && 1498 (parent->busn_res.end > max) && 1499 (parent->busn_res.end <= max+i)) { 1500 j = 1; 1501 } 1502 parent = parent->parent; 1503 } 1504 if (j) { 1505 1506 /* 1507 * Often, there are two CardBus 1508 * bridges -- try to leave one 1509 * valid bus number for each one. 1510 */ 1511 i /= 2; 1512 break; 1513 } 1514 } 1515 max += i; 1516 } 1517 1518 /* 1519 * Set subordinate bus number to its real value. 1520 * If fixed subordinate bus number exists from EA 1521 * capability then use it. 1522 */ 1523 if (fixed_buses) 1524 max = fixed_sub; 1525 pci_bus_update_busn_res_end(child, max); 1526 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1527 } 1528 1529 sprintf(child->name, 1530 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1531 pci_domain_nr(bus), child->number); 1532 1533 /* Check that all devices are accessible */ 1534 while (bus->parent) { 1535 if ((child->busn_res.end > bus->busn_res.end) || 1536 (child->number > bus->busn_res.end) || 1537 (child->number < bus->number) || 1538 (child->busn_res.end < bus->number)) { 1539 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1540 &child->busn_res); 1541 break; 1542 } 1543 bus = bus->parent; 1544 } 1545 1546 out: 1547 /* Clear errors in the Secondary Status Register */ 1548 pci_write_config_word(dev, PCI_SEC_STATUS, 0xffff); 1549 1550 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1551 1552 pm_runtime_put(&dev->dev); 1553 1554 return max; 1555 } 1556 1557 /* 1558 * pci_scan_bridge() - Scan buses behind a bridge 1559 * @bus: Parent bus the bridge is on 1560 * @dev: Bridge itself 1561 * @max: Starting subordinate number of buses behind this bridge 1562 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1563 * that need to be reconfigured. 1564 * 1565 * If it's a bridge, configure it and scan the bus behind it. 1566 * For CardBus bridges, we don't scan behind as the devices will 1567 * be handled by the bridge driver itself. 1568 * 1569 * We need to process bridges in two passes -- first we scan those 1570 * already configured by the BIOS and after we are done with all of 1571 * them, we proceed to assigning numbers to the remaining buses in 1572 * order to avoid overlaps between old and new bus numbers. 1573 * 1574 * Return: New subordinate number covering all buses behind this bridge. 1575 */ 1576 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1577 { 1578 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1579 } 1580 EXPORT_SYMBOL(pci_scan_bridge); 1581 1582 /* 1583 * Read interrupt line and base address registers. 1584 * The architecture-dependent code can tweak these, of course. 1585 */ 1586 static void pci_read_irq(struct pci_dev *dev) 1587 { 1588 unsigned char irq; 1589 1590 /* VFs are not allowed to use INTx, so skip the config reads */ 1591 if (dev->is_virtfn) { 1592 dev->pin = 0; 1593 dev->irq = 0; 1594 return; 1595 } 1596 1597 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1598 dev->pin = irq; 1599 if (irq) 1600 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1601 dev->irq = irq; 1602 } 1603 1604 void set_pcie_port_type(struct pci_dev *pdev) 1605 { 1606 int pos; 1607 u16 reg16; 1608 u32 reg32; 1609 int type; 1610 struct pci_dev *parent; 1611 1612 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1613 if (!pos) 1614 return; 1615 1616 pdev->pcie_cap = pos; 1617 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1618 pdev->pcie_flags_reg = reg16; 1619 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1620 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1621 1622 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); 1623 if (reg32 & PCI_EXP_LNKCAP_DLLLARC) 1624 pdev->link_active_reporting = 1; 1625 1626 parent = pci_upstream_bridge(pdev); 1627 if (!parent) 1628 return; 1629 1630 /* 1631 * Some systems do not identify their upstream/downstream ports 1632 * correctly so detect impossible configurations here and correct 1633 * the port type accordingly. 1634 */ 1635 type = pci_pcie_type(pdev); 1636 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1637 /* 1638 * If pdev claims to be downstream port but the parent 1639 * device is also downstream port assume pdev is actually 1640 * upstream port. 1641 */ 1642 if (pcie_downstream_port(parent)) { 1643 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1644 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1645 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1646 } 1647 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1648 /* 1649 * If pdev claims to be upstream port but the parent 1650 * device is also upstream port assume pdev is actually 1651 * downstream port. 1652 */ 1653 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1654 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1655 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1656 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1657 } 1658 } 1659 } 1660 1661 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1662 { 1663 u32 reg32; 1664 1665 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1666 if (reg32 & PCI_EXP_SLTCAP_HPC) 1667 pdev->is_hotplug_bridge = 1; 1668 } 1669 1670 static void set_pcie_thunderbolt(struct pci_dev *dev) 1671 { 1672 u16 vsec; 1673 1674 /* Is the device part of a Thunderbolt controller? */ 1675 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); 1676 if (vsec) 1677 dev->is_thunderbolt = 1; 1678 } 1679 1680 static void set_pcie_untrusted(struct pci_dev *dev) 1681 { 1682 struct pci_dev *parent = pci_upstream_bridge(dev); 1683 1684 if (!parent) 1685 return; 1686 /* 1687 * If the upstream bridge is untrusted we treat this device as 1688 * untrusted as well. 1689 */ 1690 if (parent->untrusted) { 1691 dev->untrusted = true; 1692 return; 1693 } 1694 1695 if (arch_pci_dev_is_removable(dev)) { 1696 pci_dbg(dev, "marking as untrusted\n"); 1697 dev->untrusted = true; 1698 } 1699 } 1700 1701 static void pci_set_removable(struct pci_dev *dev) 1702 { 1703 struct pci_dev *parent = pci_upstream_bridge(dev); 1704 1705 if (!parent) 1706 return; 1707 /* 1708 * We (only) consider everything tunneled below an external_facing 1709 * device to be removable by the user. We're mainly concerned with 1710 * consumer platforms with user accessible thunderbolt ports that are 1711 * vulnerable to DMA attacks, and we expect those ports to be marked by 1712 * the firmware as external_facing. Devices in traditional hotplug 1713 * slots can technically be removed, but the expectation is that unless 1714 * the port is marked with external_facing, such devices are less 1715 * accessible to user / may not be removed by end user, and thus not 1716 * exposed as "removable" to userspace. 1717 */ 1718 if (dev_is_removable(&parent->dev)) { 1719 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1720 return; 1721 } 1722 1723 if (arch_pci_dev_is_removable(dev)) { 1724 pci_dbg(dev, "marking as removable\n"); 1725 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1726 } 1727 } 1728 1729 /** 1730 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1731 * @dev: PCI device 1732 * 1733 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1734 * when forwarding a type1 configuration request the bridge must check that 1735 * the extended register address field is zero. The bridge is not permitted 1736 * to forward the transactions and must handle it as an Unsupported Request. 1737 * Some bridges do not follow this rule and simply drop the extended register 1738 * bits, resulting in the standard config space being aliased, every 256 1739 * bytes across the entire configuration space. Test for this condition by 1740 * comparing the first dword of each potential alias to the vendor/device ID. 1741 * Known offenders: 1742 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1743 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1744 */ 1745 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1746 { 1747 #ifdef CONFIG_PCI_QUIRKS 1748 int pos, ret; 1749 u32 header, tmp; 1750 1751 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1752 1753 for (pos = PCI_CFG_SPACE_SIZE; 1754 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1755 ret = pci_read_config_dword(dev, pos, &tmp); 1756 if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp)) 1757 return false; 1758 } 1759 1760 return true; 1761 #else 1762 return false; 1763 #endif 1764 } 1765 1766 /** 1767 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1768 * @dev: PCI device 1769 * 1770 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1771 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1772 * access it. Maybe we don't have a way to generate extended config space 1773 * accesses, or the device is behind a reverse Express bridge. So we try 1774 * reading the dword at 0x100 which must either be 0 or a valid extended 1775 * capability header. 1776 */ 1777 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1778 { 1779 u32 status; 1780 int pos = PCI_CFG_SPACE_SIZE; 1781 1782 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1783 return PCI_CFG_SPACE_SIZE; 1784 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) 1785 return PCI_CFG_SPACE_SIZE; 1786 1787 return PCI_CFG_SPACE_EXP_SIZE; 1788 } 1789 1790 int pci_cfg_space_size(struct pci_dev *dev) 1791 { 1792 int pos; 1793 u32 status; 1794 u16 class; 1795 1796 #ifdef CONFIG_PCI_IOV 1797 /* 1798 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1799 * implement a PCIe capability and therefore must implement extended 1800 * config space. We can skip the NO_EXTCFG test below and the 1801 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1802 * the fact that the SR-IOV capability on the PF resides in extended 1803 * config space and must be accessible and non-aliased to have enabled 1804 * support for this VF. This is a micro performance optimization for 1805 * systems supporting many VFs. 1806 */ 1807 if (dev->is_virtfn) 1808 return PCI_CFG_SPACE_EXP_SIZE; 1809 #endif 1810 1811 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1812 return PCI_CFG_SPACE_SIZE; 1813 1814 class = dev->class >> 8; 1815 if (class == PCI_CLASS_BRIDGE_HOST) 1816 return pci_cfg_space_size_ext(dev); 1817 1818 if (pci_is_pcie(dev)) 1819 return pci_cfg_space_size_ext(dev); 1820 1821 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1822 if (!pos) 1823 return PCI_CFG_SPACE_SIZE; 1824 1825 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1826 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1827 return pci_cfg_space_size_ext(dev); 1828 1829 return PCI_CFG_SPACE_SIZE; 1830 } 1831 1832 static u32 pci_class(struct pci_dev *dev) 1833 { 1834 u32 class; 1835 1836 #ifdef CONFIG_PCI_IOV 1837 if (dev->is_virtfn) 1838 return dev->physfn->sriov->class; 1839 #endif 1840 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1841 return class; 1842 } 1843 1844 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1845 { 1846 #ifdef CONFIG_PCI_IOV 1847 if (dev->is_virtfn) { 1848 *vendor = dev->physfn->sriov->subsystem_vendor; 1849 *device = dev->physfn->sriov->subsystem_device; 1850 return; 1851 } 1852 #endif 1853 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1854 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1855 } 1856 1857 static u8 pci_hdr_type(struct pci_dev *dev) 1858 { 1859 u8 hdr_type; 1860 1861 #ifdef CONFIG_PCI_IOV 1862 if (dev->is_virtfn) 1863 return dev->physfn->sriov->hdr_type; 1864 #endif 1865 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1866 return hdr_type; 1867 } 1868 1869 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1870 1871 /** 1872 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1873 * @dev: PCI device 1874 * 1875 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1876 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1877 */ 1878 static int pci_intx_mask_broken(struct pci_dev *dev) 1879 { 1880 u16 orig, toggle, new; 1881 1882 pci_read_config_word(dev, PCI_COMMAND, &orig); 1883 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1884 pci_write_config_word(dev, PCI_COMMAND, toggle); 1885 pci_read_config_word(dev, PCI_COMMAND, &new); 1886 1887 pci_write_config_word(dev, PCI_COMMAND, orig); 1888 1889 /* 1890 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1891 * r2.3, so strictly speaking, a device is not *broken* if it's not 1892 * writable. But we'll live with the misnomer for now. 1893 */ 1894 if (new != toggle) 1895 return 1; 1896 return 0; 1897 } 1898 1899 static void early_dump_pci_device(struct pci_dev *pdev) 1900 { 1901 u32 value[256 / 4]; 1902 int i; 1903 1904 pci_info(pdev, "config space:\n"); 1905 1906 for (i = 0; i < 256; i += 4) 1907 pci_read_config_dword(pdev, i, &value[i / 4]); 1908 1909 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1910 value, 256, false); 1911 } 1912 1913 static const char *pci_type_str(struct pci_dev *dev) 1914 { 1915 static const char * const str[] = { 1916 "PCIe Endpoint", 1917 "PCIe Legacy Endpoint", 1918 "PCIe unknown", 1919 "PCIe unknown", 1920 "PCIe Root Port", 1921 "PCIe Switch Upstream Port", 1922 "PCIe Switch Downstream Port", 1923 "PCIe to PCI/PCI-X bridge", 1924 "PCI/PCI-X to PCIe bridge", 1925 "PCIe Root Complex Integrated Endpoint", 1926 "PCIe Root Complex Event Collector", 1927 }; 1928 int type; 1929 1930 if (pci_is_pcie(dev)) { 1931 type = pci_pcie_type(dev); 1932 if (type < ARRAY_SIZE(str)) 1933 return str[type]; 1934 1935 return "PCIe unknown"; 1936 } 1937 1938 switch (dev->hdr_type) { 1939 case PCI_HEADER_TYPE_NORMAL: 1940 return "conventional PCI endpoint"; 1941 case PCI_HEADER_TYPE_BRIDGE: 1942 return "conventional PCI bridge"; 1943 case PCI_HEADER_TYPE_CARDBUS: 1944 return "CardBus bridge"; 1945 default: 1946 return "conventional PCI"; 1947 } 1948 } 1949 1950 /** 1951 * pci_setup_device - Fill in class and map information of a device 1952 * @dev: the device structure to fill 1953 * 1954 * Initialize the device structure with information about the device's 1955 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1956 * Called at initialisation of the PCI subsystem and by CardBus services. 1957 * Returns 0 on success and negative if unknown type of device (not normal, 1958 * bridge or CardBus). 1959 */ 1960 int pci_setup_device(struct pci_dev *dev) 1961 { 1962 u32 class; 1963 u16 cmd; 1964 u8 hdr_type; 1965 int err, pos = 0; 1966 struct pci_bus_region region; 1967 struct resource *res; 1968 1969 hdr_type = pci_hdr_type(dev); 1970 1971 dev->sysdata = dev->bus->sysdata; 1972 dev->dev.parent = dev->bus->bridge; 1973 dev->dev.bus = &pci_bus_type; 1974 dev->hdr_type = hdr_type & 0x7f; 1975 dev->multifunction = !!(hdr_type & 0x80); 1976 dev->error_state = pci_channel_io_normal; 1977 set_pcie_port_type(dev); 1978 1979 err = pci_set_of_node(dev); 1980 if (err) 1981 return err; 1982 pci_set_acpi_fwnode(dev); 1983 1984 pci_dev_assign_slot(dev); 1985 1986 /* 1987 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1988 * set this higher, assuming the system even supports it. 1989 */ 1990 dev->dma_mask = 0xffffffff; 1991 1992 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1993 dev->bus->number, PCI_SLOT(dev->devfn), 1994 PCI_FUNC(dev->devfn)); 1995 1996 class = pci_class(dev); 1997 1998 dev->revision = class & 0xff; 1999 dev->class = class >> 8; /* upper 3 bytes */ 2000 2001 if (pci_early_dump) 2002 early_dump_pci_device(dev); 2003 2004 /* Need to have dev->class ready */ 2005 dev->cfg_size = pci_cfg_space_size(dev); 2006 2007 /* Need to have dev->cfg_size ready */ 2008 set_pcie_thunderbolt(dev); 2009 2010 set_pcie_untrusted(dev); 2011 2012 if (pci_is_pcie(dev)) 2013 dev->supported_speeds = pcie_get_supported_speeds(dev); 2014 2015 /* "Unknown power state" */ 2016 dev->current_state = PCI_UNKNOWN; 2017 2018 /* Early fixups, before probing the BARs */ 2019 pci_fixup_device(pci_fixup_early, dev); 2020 2021 pci_set_removable(dev); 2022 2023 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n", 2024 dev->vendor, dev->device, dev->hdr_type, dev->class, 2025 pci_type_str(dev)); 2026 2027 /* Device class may be changed after fixup */ 2028 class = dev->class >> 8; 2029 2030 if (dev->non_compliant_bars && !dev->mmio_always_on) { 2031 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2032 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 2033 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 2034 cmd &= ~PCI_COMMAND_IO; 2035 cmd &= ~PCI_COMMAND_MEMORY; 2036 pci_write_config_word(dev, PCI_COMMAND, cmd); 2037 } 2038 } 2039 2040 dev->broken_intx_masking = pci_intx_mask_broken(dev); 2041 2042 switch (dev->hdr_type) { /* header type */ 2043 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 2044 if (class == PCI_CLASS_BRIDGE_PCI) 2045 goto bad; 2046 pci_read_irq(dev); 2047 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 2048 2049 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 2050 2051 /* 2052 * Do the ugly legacy mode stuff here rather than broken chip 2053 * quirk code. Legacy mode ATA controllers have fixed 2054 * addresses. These are not always echoed in BAR0-3, and 2055 * BAR0-3 in a few cases contain junk! 2056 */ 2057 if (class == PCI_CLASS_STORAGE_IDE) { 2058 u8 progif; 2059 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 2060 if ((progif & 1) == 0) { 2061 region.start = 0x1F0; 2062 region.end = 0x1F7; 2063 res = &dev->resource[0]; 2064 res->flags = LEGACY_IO_RESOURCE; 2065 pcibios_bus_to_resource(dev->bus, res, ®ion); 2066 pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n", 2067 res); 2068 region.start = 0x3F6; 2069 region.end = 0x3F6; 2070 res = &dev->resource[1]; 2071 res->flags = LEGACY_IO_RESOURCE; 2072 pcibios_bus_to_resource(dev->bus, res, ®ion); 2073 pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n", 2074 res); 2075 } 2076 if ((progif & 4) == 0) { 2077 region.start = 0x170; 2078 region.end = 0x177; 2079 res = &dev->resource[2]; 2080 res->flags = LEGACY_IO_RESOURCE; 2081 pcibios_bus_to_resource(dev->bus, res, ®ion); 2082 pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n", 2083 res); 2084 region.start = 0x376; 2085 region.end = 0x376; 2086 res = &dev->resource[3]; 2087 res->flags = LEGACY_IO_RESOURCE; 2088 pcibios_bus_to_resource(dev->bus, res, ®ion); 2089 pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n", 2090 res); 2091 } 2092 } 2093 break; 2094 2095 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 2096 /* 2097 * The PCI-to-PCI bridge spec requires that subtractive 2098 * decoding (i.e. transparent) bridge must have programming 2099 * interface code of 0x01. 2100 */ 2101 pci_read_irq(dev); 2102 dev->transparent = ((dev->class & 0xff) == 1); 2103 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 2104 pci_read_bridge_windows(dev); 2105 set_pcie_hotplug_bridge(dev); 2106 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 2107 if (pos) { 2108 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 2109 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 2110 } 2111 break; 2112 2113 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 2114 if (class != PCI_CLASS_BRIDGE_CARDBUS) 2115 goto bad; 2116 pci_read_irq(dev); 2117 pci_read_bases(dev, 1, 0); 2118 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 2119 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 2120 break; 2121 2122 default: /* unknown header */ 2123 pci_err(dev, "unknown header type %02x, ignoring device\n", 2124 dev->hdr_type); 2125 pci_release_of_node(dev); 2126 return -EIO; 2127 2128 bad: 2129 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 2130 dev->class, dev->hdr_type); 2131 dev->class = PCI_CLASS_NOT_DEFINED << 8; 2132 } 2133 2134 /* We found a fine healthy device, go go go... */ 2135 return 0; 2136 } 2137 2138 static void pci_configure_mps(struct pci_dev *dev) 2139 { 2140 struct pci_dev *bridge = pci_upstream_bridge(dev); 2141 int mps, mpss, p_mps, rc; 2142 2143 if (!pci_is_pcie(dev)) 2144 return; 2145 2146 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 2147 if (dev->is_virtfn) 2148 return; 2149 2150 /* 2151 * For Root Complex Integrated Endpoints, program the maximum 2152 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 2153 */ 2154 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 2155 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2156 mps = 128; 2157 else 2158 mps = 128 << dev->pcie_mpss; 2159 rc = pcie_set_mps(dev, mps); 2160 if (rc) { 2161 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2162 mps); 2163 } 2164 return; 2165 } 2166 2167 if (!bridge || !pci_is_pcie(bridge)) 2168 return; 2169 2170 mps = pcie_get_mps(dev); 2171 p_mps = pcie_get_mps(bridge); 2172 2173 if (mps == p_mps) 2174 return; 2175 2176 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2177 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2178 mps, pci_name(bridge), p_mps); 2179 return; 2180 } 2181 2182 /* 2183 * Fancier MPS configuration is done later by 2184 * pcie_bus_configure_settings() 2185 */ 2186 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2187 return; 2188 2189 mpss = 128 << dev->pcie_mpss; 2190 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2191 pcie_set_mps(bridge, mpss); 2192 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2193 mpss, p_mps, 128 << bridge->pcie_mpss); 2194 p_mps = pcie_get_mps(bridge); 2195 } 2196 2197 rc = pcie_set_mps(dev, p_mps); 2198 if (rc) { 2199 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2200 p_mps); 2201 return; 2202 } 2203 2204 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2205 p_mps, mps, mpss); 2206 } 2207 2208 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2209 { 2210 struct pci_host_bridge *host; 2211 u32 cap; 2212 u16 ctl; 2213 int ret; 2214 2215 if (!pci_is_pcie(dev)) 2216 return 0; 2217 2218 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2219 if (ret) 2220 return 0; 2221 2222 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2223 return 0; 2224 2225 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2226 if (ret) 2227 return 0; 2228 2229 host = pci_find_host_bridge(dev->bus); 2230 if (!host) 2231 return 0; 2232 2233 /* 2234 * If some device in the hierarchy doesn't handle Extended Tags 2235 * correctly, make sure they're disabled. 2236 */ 2237 if (host->no_ext_tags) { 2238 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2239 pci_info(dev, "disabling Extended Tags\n"); 2240 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2241 PCI_EXP_DEVCTL_EXT_TAG); 2242 } 2243 return 0; 2244 } 2245 2246 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2247 pci_info(dev, "enabling Extended Tags\n"); 2248 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2249 PCI_EXP_DEVCTL_EXT_TAG); 2250 } 2251 return 0; 2252 } 2253 2254 /** 2255 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2256 * @dev: PCI device to query 2257 * 2258 * Returns true if the device has enabled relaxed ordering attribute. 2259 */ 2260 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2261 { 2262 u16 v; 2263 2264 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2265 2266 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2267 } 2268 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2269 2270 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2271 { 2272 struct pci_dev *root; 2273 2274 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */ 2275 if (dev->is_virtfn) 2276 return; 2277 2278 if (!pcie_relaxed_ordering_enabled(dev)) 2279 return; 2280 2281 /* 2282 * For now, we only deal with Relaxed Ordering issues with Root 2283 * Ports. Peer-to-Peer DMA is another can of worms. 2284 */ 2285 root = pcie_find_root_port(dev); 2286 if (!root) 2287 return; 2288 2289 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2290 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2291 PCI_EXP_DEVCTL_RELAX_EN); 2292 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2293 } 2294 } 2295 2296 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2297 { 2298 struct pci_dev *bridge; 2299 unsigned int eetlp_max; 2300 int pcie_type; 2301 u32 cap; 2302 2303 if (!pci_is_pcie(dev)) 2304 return; 2305 2306 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2307 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2308 return; 2309 2310 pcie_type = pci_pcie_type(dev); 2311 2312 eetlp_max = FIELD_GET(PCI_EXP_DEVCAP2_EE_PREFIX_MAX, cap); 2313 /* 00b means 4 */ 2314 eetlp_max = eetlp_max ?: 4; 2315 2316 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2317 pcie_type == PCI_EXP_TYPE_RC_END) 2318 dev->eetlp_prefix_max = eetlp_max; 2319 else { 2320 bridge = pci_upstream_bridge(dev); 2321 if (bridge && bridge->eetlp_prefix_max) 2322 dev->eetlp_prefix_max = eetlp_max; 2323 } 2324 } 2325 2326 static void pci_configure_serr(struct pci_dev *dev) 2327 { 2328 u16 control; 2329 2330 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2331 2332 /* 2333 * A bridge will not forward ERR_ messages coming from an 2334 * endpoint unless SERR# forwarding is enabled. 2335 */ 2336 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2337 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2338 control |= PCI_BRIDGE_CTL_SERR; 2339 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2340 } 2341 } 2342 } 2343 2344 static void pci_configure_device(struct pci_dev *dev) 2345 { 2346 pci_configure_mps(dev); 2347 pci_configure_extended_tags(dev, NULL); 2348 pci_configure_relaxed_ordering(dev); 2349 pci_configure_ltr(dev); 2350 pci_configure_aspm_l1ss(dev); 2351 pci_configure_eetlp_prefix(dev); 2352 pci_configure_serr(dev); 2353 2354 pci_acpi_program_hp_params(dev); 2355 } 2356 2357 static void pci_release_capabilities(struct pci_dev *dev) 2358 { 2359 pci_aer_exit(dev); 2360 pci_rcec_exit(dev); 2361 pci_iov_release(dev); 2362 pci_free_cap_save_buffers(dev); 2363 } 2364 2365 /** 2366 * pci_release_dev - Free a PCI device structure when all users of it are 2367 * finished 2368 * @dev: device that's been disconnected 2369 * 2370 * Will be called only by the device core when all users of this PCI device are 2371 * done. 2372 */ 2373 static void pci_release_dev(struct device *dev) 2374 { 2375 struct pci_dev *pci_dev; 2376 2377 pci_dev = to_pci_dev(dev); 2378 pci_release_capabilities(pci_dev); 2379 pci_release_of_node(pci_dev); 2380 pcibios_release_device(pci_dev); 2381 pci_bus_put(pci_dev->bus); 2382 kfree(pci_dev->driver_override); 2383 bitmap_free(pci_dev->dma_alias_mask); 2384 dev_dbg(dev, "device released\n"); 2385 kfree(pci_dev); 2386 } 2387 2388 static const struct device_type pci_dev_type = { 2389 .groups = pci_dev_attr_groups, 2390 }; 2391 2392 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2393 { 2394 struct pci_dev *dev; 2395 2396 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2397 if (!dev) 2398 return NULL; 2399 2400 INIT_LIST_HEAD(&dev->bus_list); 2401 dev->dev.type = &pci_dev_type; 2402 dev->bus = pci_bus_get(bus); 2403 dev->driver_exclusive_resource = (struct resource) { 2404 .name = "PCI Exclusive", 2405 .start = 0, 2406 .end = -1, 2407 }; 2408 2409 spin_lock_init(&dev->pcie_cap_lock); 2410 #ifdef CONFIG_PCI_MSI 2411 raw_spin_lock_init(&dev->msi_lock); 2412 #endif 2413 return dev; 2414 } 2415 EXPORT_SYMBOL(pci_alloc_dev); 2416 2417 static bool pci_bus_wait_rrs(struct pci_bus *bus, int devfn, u32 *l, 2418 int timeout) 2419 { 2420 int delay = 1; 2421 2422 if (!pci_bus_rrs_vendor_id(*l)) 2423 return true; /* not a Configuration RRS completion */ 2424 2425 if (!timeout) 2426 return false; /* RRS, but caller doesn't want to wait */ 2427 2428 /* 2429 * We got the reserved Vendor ID that indicates a completion with 2430 * Configuration Request Retry Status (RRS). Retry until we get a 2431 * valid Vendor ID or we time out. 2432 */ 2433 while (pci_bus_rrs_vendor_id(*l)) { 2434 if (delay > timeout) { 2435 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2436 pci_domain_nr(bus), bus->number, 2437 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2438 2439 return false; 2440 } 2441 if (delay >= 1000) 2442 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2443 pci_domain_nr(bus), bus->number, 2444 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2445 2446 msleep(delay); 2447 delay *= 2; 2448 2449 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2450 return false; 2451 } 2452 2453 if (delay >= 1000) 2454 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2455 pci_domain_nr(bus), bus->number, 2456 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2457 2458 return true; 2459 } 2460 2461 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2462 int timeout) 2463 { 2464 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2465 return false; 2466 2467 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ 2468 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || 2469 *l == 0x0000ffff || *l == 0xffff0000) 2470 return false; 2471 2472 if (pci_bus_rrs_vendor_id(*l)) 2473 return pci_bus_wait_rrs(bus, devfn, l, timeout); 2474 2475 return true; 2476 } 2477 2478 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2479 int timeout) 2480 { 2481 #ifdef CONFIG_PCI_QUIRKS 2482 struct pci_dev *bridge = bus->self; 2483 2484 /* 2485 * Certain IDT switches have an issue where they improperly trigger 2486 * ACS Source Validation errors on completions for config reads. 2487 */ 2488 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2489 bridge->device == 0x80b5) 2490 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2491 #endif 2492 2493 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2494 } 2495 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2496 2497 /* 2498 * Read the config data for a PCI device, sanity-check it, 2499 * and fill in the dev structure. 2500 */ 2501 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2502 { 2503 struct pci_dev *dev; 2504 u32 l; 2505 2506 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2507 return NULL; 2508 2509 dev = pci_alloc_dev(bus); 2510 if (!dev) 2511 return NULL; 2512 2513 dev->devfn = devfn; 2514 dev->vendor = l & 0xffff; 2515 dev->device = (l >> 16) & 0xffff; 2516 2517 if (pci_setup_device(dev)) { 2518 pci_bus_put(dev->bus); 2519 kfree(dev); 2520 return NULL; 2521 } 2522 2523 return dev; 2524 } 2525 2526 void pcie_report_downtraining(struct pci_dev *dev) 2527 { 2528 if (!pci_is_pcie(dev)) 2529 return; 2530 2531 /* Look from the device up to avoid downstream ports with no devices */ 2532 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2533 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2534 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2535 return; 2536 2537 /* Multi-function PCIe devices share the same link/status */ 2538 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2539 return; 2540 2541 /* Print link status only if the device is constrained by the fabric */ 2542 __pcie_print_link_status(dev, false); 2543 } 2544 2545 static void pci_init_capabilities(struct pci_dev *dev) 2546 { 2547 pci_ea_init(dev); /* Enhanced Allocation */ 2548 pci_msi_init(dev); /* Disable MSI */ 2549 pci_msix_init(dev); /* Disable MSI-X */ 2550 2551 /* Buffers for saving PCIe and PCI-X capabilities */ 2552 pci_allocate_cap_save_buffers(dev); 2553 2554 pci_pm_init(dev); /* Power Management */ 2555 pci_vpd_init(dev); /* Vital Product Data */ 2556 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2557 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2558 pci_ats_init(dev); /* Address Translation Services */ 2559 pci_pri_init(dev); /* Page Request Interface */ 2560 pci_pasid_init(dev); /* Process Address Space ID */ 2561 pci_acs_init(dev); /* Access Control Services */ 2562 pci_ptm_init(dev); /* Precision Time Measurement */ 2563 pci_aer_init(dev); /* Advanced Error Reporting */ 2564 pci_dpc_init(dev); /* Downstream Port Containment */ 2565 pci_rcec_init(dev); /* Root Complex Event Collector */ 2566 pci_doe_init(dev); /* Data Object Exchange */ 2567 pci_tph_init(dev); /* TLP Processing Hints */ 2568 2569 pcie_report_downtraining(dev); 2570 pci_init_reset_methods(dev); 2571 } 2572 2573 /* 2574 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2575 * devices. Firmware interfaces that can select the MSI domain on a 2576 * per-device basis should be called from here. 2577 */ 2578 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2579 { 2580 struct irq_domain *d; 2581 2582 /* 2583 * If a domain has been set through the pcibios_device_add() 2584 * callback, then this is the one (platform code knows best). 2585 */ 2586 d = dev_get_msi_domain(&dev->dev); 2587 if (d) 2588 return d; 2589 2590 /* 2591 * Let's see if we have a firmware interface able to provide 2592 * the domain. 2593 */ 2594 d = pci_msi_get_device_domain(dev); 2595 if (d) 2596 return d; 2597 2598 return NULL; 2599 } 2600 2601 static void pci_set_msi_domain(struct pci_dev *dev) 2602 { 2603 struct irq_domain *d; 2604 2605 /* 2606 * If the platform or firmware interfaces cannot supply a 2607 * device-specific MSI domain, then inherit the default domain 2608 * from the host bridge itself. 2609 */ 2610 d = pci_dev_msi_domain(dev); 2611 if (!d) 2612 d = dev_get_msi_domain(&dev->bus->dev); 2613 2614 dev_set_msi_domain(&dev->dev, d); 2615 } 2616 2617 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2618 { 2619 int ret; 2620 2621 pci_configure_device(dev); 2622 2623 device_initialize(&dev->dev); 2624 dev->dev.release = pci_release_dev; 2625 2626 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2627 dev->dev.dma_mask = &dev->dma_mask; 2628 dev->dev.dma_parms = &dev->dma_parms; 2629 dev->dev.coherent_dma_mask = 0xffffffffull; 2630 2631 dma_set_max_seg_size(&dev->dev, 65536); 2632 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2633 2634 pcie_failed_link_retrain(dev); 2635 2636 /* Fix up broken headers */ 2637 pci_fixup_device(pci_fixup_header, dev); 2638 2639 pci_reassigndev_resource_alignment(dev); 2640 2641 dev->state_saved = false; 2642 2643 pci_init_capabilities(dev); 2644 2645 /* 2646 * Add the device to our list of discovered devices 2647 * and the bus list for fixup functions, etc. 2648 */ 2649 down_write(&pci_bus_sem); 2650 list_add_tail(&dev->bus_list, &bus->devices); 2651 up_write(&pci_bus_sem); 2652 2653 ret = pcibios_device_add(dev); 2654 WARN_ON(ret < 0); 2655 2656 /* Set up MSI IRQ domain */ 2657 pci_set_msi_domain(dev); 2658 2659 /* Notifier could use PCI capabilities */ 2660 dev->match_driver = false; 2661 ret = device_add(&dev->dev); 2662 WARN_ON(ret < 0); 2663 2664 pci_npem_create(dev); 2665 } 2666 2667 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2668 { 2669 struct pci_dev *dev; 2670 2671 dev = pci_get_slot(bus, devfn); 2672 if (dev) { 2673 pci_dev_put(dev); 2674 return dev; 2675 } 2676 2677 dev = pci_scan_device(bus, devfn); 2678 if (!dev) 2679 return NULL; 2680 2681 pci_device_add(dev, bus); 2682 2683 return dev; 2684 } 2685 EXPORT_SYMBOL(pci_scan_single_device); 2686 2687 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2688 { 2689 int pos; 2690 u16 cap = 0; 2691 unsigned int next_fn; 2692 2693 if (!dev) 2694 return -ENODEV; 2695 2696 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2697 if (!pos) 2698 return -ENODEV; 2699 2700 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2701 next_fn = PCI_ARI_CAP_NFN(cap); 2702 if (next_fn <= fn) 2703 return -ENODEV; /* protect against malformed list */ 2704 2705 return next_fn; 2706 } 2707 2708 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2709 { 2710 if (pci_ari_enabled(bus)) 2711 return next_ari_fn(bus, dev, fn); 2712 2713 if (fn >= 7) 2714 return -ENODEV; 2715 /* only multifunction devices may have more functions */ 2716 if (dev && !dev->multifunction) 2717 return -ENODEV; 2718 2719 return fn + 1; 2720 } 2721 2722 static int only_one_child(struct pci_bus *bus) 2723 { 2724 struct pci_dev *bridge = bus->self; 2725 2726 /* 2727 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2728 * we scan for all possible devices, not just Device 0. 2729 */ 2730 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2731 return 0; 2732 2733 /* 2734 * A PCIe Downstream Port normally leads to a Link with only Device 2735 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2736 * only for Device 0 in that situation. 2737 */ 2738 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2739 return 1; 2740 2741 return 0; 2742 } 2743 2744 /** 2745 * pci_scan_slot - Scan a PCI slot on a bus for devices 2746 * @bus: PCI bus to scan 2747 * @devfn: slot number to scan (must have zero function) 2748 * 2749 * Scan a PCI slot on the specified PCI bus for devices, adding 2750 * discovered devices to the @bus->devices list. New devices 2751 * will not have is_added set. 2752 * 2753 * Returns the number of new devices found. 2754 */ 2755 int pci_scan_slot(struct pci_bus *bus, int devfn) 2756 { 2757 struct pci_dev *dev; 2758 int fn = 0, nr = 0; 2759 2760 if (only_one_child(bus) && (devfn > 0)) 2761 return 0; /* Already scanned the entire slot */ 2762 2763 do { 2764 dev = pci_scan_single_device(bus, devfn + fn); 2765 if (dev) { 2766 if (!pci_dev_is_added(dev)) 2767 nr++; 2768 if (fn > 0) 2769 dev->multifunction = 1; 2770 } else if (fn == 0) { 2771 /* 2772 * Function 0 is required unless we are running on 2773 * a hypervisor that passes through individual PCI 2774 * functions. 2775 */ 2776 if (!hypervisor_isolated_pci_functions()) 2777 break; 2778 } 2779 fn = next_fn(bus, dev, fn); 2780 } while (fn >= 0); 2781 2782 /* Only one slot has PCIe device */ 2783 if (bus->self && nr) 2784 pcie_aspm_init_link_state(bus->self); 2785 2786 return nr; 2787 } 2788 EXPORT_SYMBOL(pci_scan_slot); 2789 2790 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2791 { 2792 u8 *smpss = data; 2793 2794 if (!pci_is_pcie(dev)) 2795 return 0; 2796 2797 /* 2798 * We don't have a way to change MPS settings on devices that have 2799 * drivers attached. A hot-added device might support only the minimum 2800 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2801 * where devices may be hot-added, we limit the fabric MPS to 128 so 2802 * hot-added devices will work correctly. 2803 * 2804 * However, if we hot-add a device to a slot directly below a Root 2805 * Port, it's impossible for there to be other existing devices below 2806 * the port. We don't limit the MPS in this case because we can 2807 * reconfigure MPS on both the Root Port and the hot-added device, 2808 * and there are no other devices involved. 2809 * 2810 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2811 */ 2812 if (dev->is_hotplug_bridge && 2813 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2814 *smpss = 0; 2815 2816 if (*smpss > dev->pcie_mpss) 2817 *smpss = dev->pcie_mpss; 2818 2819 return 0; 2820 } 2821 2822 static void pcie_write_mps(struct pci_dev *dev, int mps) 2823 { 2824 int rc; 2825 2826 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2827 mps = 128 << dev->pcie_mpss; 2828 2829 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2830 dev->bus->self) 2831 2832 /* 2833 * For "Performance", the assumption is made that 2834 * downstream communication will never be larger than 2835 * the MRRS. So, the MPS only needs to be configured 2836 * for the upstream communication. This being the case, 2837 * walk from the top down and set the MPS of the child 2838 * to that of the parent bus. 2839 * 2840 * Configure the device MPS with the smaller of the 2841 * device MPSS or the bridge MPS (which is assumed to be 2842 * properly configured at this point to the largest 2843 * allowable MPS based on its parent bus). 2844 */ 2845 mps = min(mps, pcie_get_mps(dev->bus->self)); 2846 } 2847 2848 rc = pcie_set_mps(dev, mps); 2849 if (rc) 2850 pci_err(dev, "Failed attempting to set the MPS\n"); 2851 } 2852 2853 static void pcie_write_mrrs(struct pci_dev *dev) 2854 { 2855 int rc, mrrs; 2856 2857 /* 2858 * In the "safe" case, do not configure the MRRS. There appear to be 2859 * issues with setting MRRS to 0 on a number of devices. 2860 */ 2861 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2862 return; 2863 2864 /* 2865 * For max performance, the MRRS must be set to the largest supported 2866 * value. However, it cannot be configured larger than the MPS the 2867 * device or the bus can support. This should already be properly 2868 * configured by a prior call to pcie_write_mps(). 2869 */ 2870 mrrs = pcie_get_mps(dev); 2871 2872 /* 2873 * MRRS is a R/W register. Invalid values can be written, but a 2874 * subsequent read will verify if the value is acceptable or not. 2875 * If the MRRS value provided is not acceptable (e.g., too large), 2876 * shrink the value until it is acceptable to the HW. 2877 */ 2878 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2879 rc = pcie_set_readrq(dev, mrrs); 2880 if (!rc) 2881 break; 2882 2883 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2884 mrrs /= 2; 2885 } 2886 2887 if (mrrs < 128) 2888 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2889 } 2890 2891 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2892 { 2893 int mps, orig_mps; 2894 2895 if (!pci_is_pcie(dev)) 2896 return 0; 2897 2898 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2899 pcie_bus_config == PCIE_BUS_DEFAULT) 2900 return 0; 2901 2902 mps = 128 << *(u8 *)data; 2903 orig_mps = pcie_get_mps(dev); 2904 2905 pcie_write_mps(dev, mps); 2906 pcie_write_mrrs(dev); 2907 2908 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2909 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2910 orig_mps, pcie_get_readrq(dev)); 2911 2912 return 0; 2913 } 2914 2915 /* 2916 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2917 * parents then children fashion. If this changes, then this code will not 2918 * work as designed. 2919 */ 2920 void pcie_bus_configure_settings(struct pci_bus *bus) 2921 { 2922 u8 smpss = 0; 2923 2924 if (!bus->self) 2925 return; 2926 2927 if (!pci_is_pcie(bus->self)) 2928 return; 2929 2930 /* 2931 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2932 * to be aware of the MPS of the destination. To work around this, 2933 * simply force the MPS of the entire system to the smallest possible. 2934 */ 2935 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2936 smpss = 0; 2937 2938 if (pcie_bus_config == PCIE_BUS_SAFE) { 2939 smpss = bus->self->pcie_mpss; 2940 2941 pcie_find_smpss(bus->self, &smpss); 2942 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2943 } 2944 2945 pcie_bus_configure_set(bus->self, &smpss); 2946 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2947 } 2948 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2949 2950 /* 2951 * Called after each bus is probed, but before its children are examined. This 2952 * is marked as __weak because multiple architectures define it. 2953 */ 2954 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2955 { 2956 /* nothing to do, expected to be removed in the future */ 2957 } 2958 2959 /** 2960 * pci_scan_child_bus_extend() - Scan devices below a bus 2961 * @bus: Bus to scan for devices 2962 * @available_buses: Total number of buses available (%0 does not try to 2963 * extend beyond the minimal) 2964 * 2965 * Scans devices below @bus including subordinate buses. Returns new 2966 * subordinate number including all the found devices. Passing 2967 * @available_buses causes the remaining bus space to be distributed 2968 * equally between hotplug-capable bridges to allow future extension of the 2969 * hierarchy. 2970 */ 2971 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2972 unsigned int available_buses) 2973 { 2974 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2975 unsigned int start = bus->busn_res.start; 2976 unsigned int devfn, cmax, max = start; 2977 struct pci_dev *dev; 2978 2979 dev_dbg(&bus->dev, "scanning bus\n"); 2980 2981 /* Go find them, Rover! */ 2982 for (devfn = 0; devfn < 256; devfn += 8) 2983 pci_scan_slot(bus, devfn); 2984 2985 /* Reserve buses for SR-IOV capability */ 2986 used_buses = pci_iov_bus_range(bus); 2987 max += used_buses; 2988 2989 /* 2990 * After performing arch-dependent fixup of the bus, look behind 2991 * all PCI-to-PCI bridges on this bus. 2992 */ 2993 if (!bus->is_added) { 2994 dev_dbg(&bus->dev, "fixups for bus\n"); 2995 pcibios_fixup_bus(bus); 2996 bus->is_added = 1; 2997 } 2998 2999 /* 3000 * Calculate how many hotplug bridges and normal bridges there 3001 * are on this bus. We will distribute the additional available 3002 * buses between hotplug bridges. 3003 */ 3004 for_each_pci_bridge(dev, bus) { 3005 if (dev->is_hotplug_bridge) 3006 hotplug_bridges++; 3007 else 3008 normal_bridges++; 3009 } 3010 3011 /* 3012 * Scan bridges that are already configured. We don't touch them 3013 * unless they are misconfigured (which will be done in the second 3014 * scan below). 3015 */ 3016 for_each_pci_bridge(dev, bus) { 3017 cmax = max; 3018 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 3019 3020 /* 3021 * Reserve one bus for each bridge now to avoid extending 3022 * hotplug bridges too much during the second scan below. 3023 */ 3024 used_buses++; 3025 if (max - cmax > 1) 3026 used_buses += max - cmax - 1; 3027 } 3028 3029 /* Scan bridges that need to be reconfigured */ 3030 for_each_pci_bridge(dev, bus) { 3031 unsigned int buses = 0; 3032 3033 if (!hotplug_bridges && normal_bridges == 1) { 3034 /* 3035 * There is only one bridge on the bus (upstream 3036 * port) so it gets all available buses which it 3037 * can then distribute to the possible hotplug 3038 * bridges below. 3039 */ 3040 buses = available_buses; 3041 } else if (dev->is_hotplug_bridge) { 3042 /* 3043 * Distribute the extra buses between hotplug 3044 * bridges if any. 3045 */ 3046 buses = available_buses / hotplug_bridges; 3047 buses = min(buses, available_buses - used_buses + 1); 3048 } 3049 3050 cmax = max; 3051 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 3052 /* One bus is already accounted so don't add it again */ 3053 if (max - cmax > 1) 3054 used_buses += max - cmax - 1; 3055 } 3056 3057 /* 3058 * Make sure a hotplug bridge has at least the minimum requested 3059 * number of buses but allow it to grow up to the maximum available 3060 * bus number if there is room. 3061 */ 3062 if (bus->self && bus->self->is_hotplug_bridge) { 3063 used_buses = max_t(unsigned int, available_buses, 3064 pci_hotplug_bus_size - 1); 3065 if (max - start < used_buses) { 3066 max = start + used_buses; 3067 3068 /* Do not allocate more buses than we have room left */ 3069 if (max > bus->busn_res.end) 3070 max = bus->busn_res.end; 3071 3072 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 3073 &bus->busn_res, max - start); 3074 } 3075 } 3076 3077 /* 3078 * We've scanned the bus and so we know all about what's on 3079 * the other side of any bridges that may be on this bus plus 3080 * any devices. 3081 * 3082 * Return how far we've got finding sub-buses. 3083 */ 3084 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 3085 return max; 3086 } 3087 3088 /** 3089 * pci_scan_child_bus() - Scan devices below a bus 3090 * @bus: Bus to scan for devices 3091 * 3092 * Scans devices below @bus including subordinate buses. Returns new 3093 * subordinate number including all the found devices. 3094 */ 3095 unsigned int pci_scan_child_bus(struct pci_bus *bus) 3096 { 3097 return pci_scan_child_bus_extend(bus, 0); 3098 } 3099 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3100 3101 /** 3102 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3103 * @bridge: Host bridge to set up 3104 * 3105 * Default empty implementation. Replace with an architecture-specific setup 3106 * routine, if necessary. 3107 */ 3108 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3109 { 3110 return 0; 3111 } 3112 3113 void __weak pcibios_add_bus(struct pci_bus *bus) 3114 { 3115 } 3116 3117 void __weak pcibios_remove_bus(struct pci_bus *bus) 3118 { 3119 } 3120 3121 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3122 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3123 { 3124 int error; 3125 struct pci_host_bridge *bridge; 3126 3127 bridge = pci_alloc_host_bridge(0); 3128 if (!bridge) 3129 return NULL; 3130 3131 bridge->dev.parent = parent; 3132 3133 list_splice_init(resources, &bridge->windows); 3134 bridge->sysdata = sysdata; 3135 bridge->busnr = bus; 3136 bridge->ops = ops; 3137 3138 error = pci_register_host_bridge(bridge); 3139 if (error < 0) 3140 goto err_out; 3141 3142 return bridge->bus; 3143 3144 err_out: 3145 put_device(&bridge->dev); 3146 return NULL; 3147 } 3148 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3149 3150 int pci_host_probe(struct pci_host_bridge *bridge) 3151 { 3152 struct pci_bus *bus, *child; 3153 int ret; 3154 3155 pci_lock_rescan_remove(); 3156 ret = pci_scan_root_bus_bridge(bridge); 3157 pci_unlock_rescan_remove(); 3158 if (ret < 0) { 3159 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3160 return ret; 3161 } 3162 3163 bus = bridge->bus; 3164 3165 /* If we must preserve the resource configuration, claim now */ 3166 if (bridge->preserve_config) 3167 pci_bus_claim_resources(bus); 3168 3169 /* 3170 * Assign whatever was left unassigned. If we didn't claim above, 3171 * this will reassign everything. 3172 */ 3173 pci_assign_unassigned_root_bus_resources(bus); 3174 3175 list_for_each_entry(child, &bus->children, node) 3176 pcie_bus_configure_settings(child); 3177 3178 pci_lock_rescan_remove(); 3179 pci_bus_add_devices(bus); 3180 pci_unlock_rescan_remove(); 3181 3182 /* 3183 * Ensure pm_runtime_enable() is called for the controller drivers 3184 * before calling pci_host_probe(). The PM framework expects that 3185 * if the parent device supports runtime PM, it will be enabled 3186 * before child runtime PM is enabled. 3187 */ 3188 pm_runtime_set_active(&bridge->dev); 3189 pm_runtime_no_callbacks(&bridge->dev); 3190 devm_pm_runtime_enable(&bridge->dev); 3191 3192 return 0; 3193 } 3194 EXPORT_SYMBOL_GPL(pci_host_probe); 3195 3196 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3197 { 3198 struct resource *res = &b->busn_res; 3199 struct resource *parent_res, *conflict; 3200 3201 res->start = bus; 3202 res->end = bus_max; 3203 res->flags = IORESOURCE_BUS; 3204 3205 if (!pci_is_root_bus(b)) 3206 parent_res = &b->parent->busn_res; 3207 else { 3208 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3209 res->flags |= IORESOURCE_PCI_FIXED; 3210 } 3211 3212 conflict = request_resource_conflict(parent_res, res); 3213 3214 if (conflict) 3215 dev_info(&b->dev, 3216 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3217 res, pci_is_root_bus(b) ? "domain " : "", 3218 parent_res, conflict->name, conflict); 3219 3220 return conflict == NULL; 3221 } 3222 3223 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3224 { 3225 struct resource *res = &b->busn_res; 3226 struct resource old_res = *res; 3227 resource_size_t size; 3228 int ret; 3229 3230 if (res->start > bus_max) 3231 return -EINVAL; 3232 3233 size = bus_max - res->start + 1; 3234 ret = adjust_resource(res, res->start, size); 3235 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3236 &old_res, ret ? "can not be" : "is", bus_max); 3237 3238 if (!ret && !res->parent) 3239 pci_bus_insert_busn_res(b, res->start, res->end); 3240 3241 return ret; 3242 } 3243 3244 void pci_bus_release_busn_res(struct pci_bus *b) 3245 { 3246 struct resource *res = &b->busn_res; 3247 int ret; 3248 3249 if (!res->flags || !res->parent) 3250 return; 3251 3252 ret = release_resource(res); 3253 dev_info(&b->dev, "busn_res: %pR %s released\n", 3254 res, ret ? "can not be" : "is"); 3255 } 3256 3257 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3258 { 3259 struct resource_entry *window; 3260 bool found = false; 3261 struct pci_bus *b; 3262 int max, bus, ret; 3263 3264 if (!bridge) 3265 return -EINVAL; 3266 3267 resource_list_for_each_entry(window, &bridge->windows) 3268 if (window->res->flags & IORESOURCE_BUS) { 3269 bridge->busnr = window->res->start; 3270 found = true; 3271 break; 3272 } 3273 3274 ret = pci_register_host_bridge(bridge); 3275 if (ret < 0) 3276 return ret; 3277 3278 b = bridge->bus; 3279 bus = bridge->busnr; 3280 3281 if (!found) { 3282 dev_info(&b->dev, 3283 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3284 bus); 3285 pci_bus_insert_busn_res(b, bus, 255); 3286 } 3287 3288 max = pci_scan_child_bus(b); 3289 3290 if (!found) 3291 pci_bus_update_busn_res_end(b, max); 3292 3293 return 0; 3294 } 3295 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3296 3297 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3298 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3299 { 3300 struct resource_entry *window; 3301 bool found = false; 3302 struct pci_bus *b; 3303 int max; 3304 3305 resource_list_for_each_entry(window, resources) 3306 if (window->res->flags & IORESOURCE_BUS) { 3307 found = true; 3308 break; 3309 } 3310 3311 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3312 if (!b) 3313 return NULL; 3314 3315 if (!found) { 3316 dev_info(&b->dev, 3317 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3318 bus); 3319 pci_bus_insert_busn_res(b, bus, 255); 3320 } 3321 3322 max = pci_scan_child_bus(b); 3323 3324 if (!found) 3325 pci_bus_update_busn_res_end(b, max); 3326 3327 return b; 3328 } 3329 EXPORT_SYMBOL(pci_scan_root_bus); 3330 3331 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3332 void *sysdata) 3333 { 3334 LIST_HEAD(resources); 3335 struct pci_bus *b; 3336 3337 pci_add_resource(&resources, &ioport_resource); 3338 pci_add_resource(&resources, &iomem_resource); 3339 pci_add_resource(&resources, &busn_resource); 3340 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3341 if (b) { 3342 pci_scan_child_bus(b); 3343 } else { 3344 pci_free_resource_list(&resources); 3345 } 3346 return b; 3347 } 3348 EXPORT_SYMBOL(pci_scan_bus); 3349 3350 /** 3351 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3352 * @bridge: PCI bridge for the bus to scan 3353 * 3354 * Scan a PCI bus and child buses for new devices, add them, 3355 * and enable them, resizing bridge mmio/io resource if necessary 3356 * and possible. The caller must ensure the child devices are already 3357 * removed for resizing to occur. 3358 * 3359 * Returns the max number of subordinate bus discovered. 3360 */ 3361 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3362 { 3363 unsigned int max; 3364 struct pci_bus *bus = bridge->subordinate; 3365 3366 max = pci_scan_child_bus(bus); 3367 3368 pci_assign_unassigned_bridge_resources(bridge); 3369 3370 pci_bus_add_devices(bus); 3371 3372 return max; 3373 } 3374 3375 /** 3376 * pci_rescan_bus - Scan a PCI bus for devices 3377 * @bus: PCI bus to scan 3378 * 3379 * Scan a PCI bus and child buses for new devices, add them, 3380 * and enable them. 3381 * 3382 * Returns the max number of subordinate bus discovered. 3383 */ 3384 unsigned int pci_rescan_bus(struct pci_bus *bus) 3385 { 3386 unsigned int max; 3387 3388 max = pci_scan_child_bus(bus); 3389 pci_assign_unassigned_bus_resources(bus); 3390 pci_bus_add_devices(bus); 3391 3392 return max; 3393 } 3394 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3395 3396 /* 3397 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3398 * routines should always be executed under this mutex. 3399 */ 3400 static DEFINE_MUTEX(pci_rescan_remove_lock); 3401 3402 void pci_lock_rescan_remove(void) 3403 { 3404 mutex_lock(&pci_rescan_remove_lock); 3405 } 3406 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3407 3408 void pci_unlock_rescan_remove(void) 3409 { 3410 mutex_unlock(&pci_rescan_remove_lock); 3411 } 3412 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3413 3414 static int __init pci_sort_bf_cmp(const struct device *d_a, 3415 const struct device *d_b) 3416 { 3417 const struct pci_dev *a = to_pci_dev(d_a); 3418 const struct pci_dev *b = to_pci_dev(d_b); 3419 3420 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3421 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3422 3423 if (a->bus->number < b->bus->number) return -1; 3424 else if (a->bus->number > b->bus->number) return 1; 3425 3426 if (a->devfn < b->devfn) return -1; 3427 else if (a->devfn > b->devfn) return 1; 3428 3429 return 0; 3430 } 3431 3432 void __init pci_sort_breadthfirst(void) 3433 { 3434 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3435 } 3436 3437 int pci_hp_add_bridge(struct pci_dev *dev) 3438 { 3439 struct pci_bus *parent = dev->bus; 3440 int busnr, start = parent->busn_res.start; 3441 unsigned int available_buses = 0; 3442 int end = parent->busn_res.end; 3443 3444 for (busnr = start; busnr <= end; busnr++) { 3445 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3446 break; 3447 } 3448 if (busnr-- > end) { 3449 pci_err(dev, "No bus number available for hot-added bridge\n"); 3450 return -1; 3451 } 3452 3453 /* Scan bridges that are already configured */ 3454 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3455 3456 /* 3457 * Distribute the available bus numbers between hotplug-capable 3458 * bridges to make extending the chain later possible. 3459 */ 3460 available_buses = end - busnr; 3461 3462 /* Scan bridges that need to be reconfigured */ 3463 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3464 3465 if (!dev->subordinate) 3466 return -1; 3467 3468 return 0; 3469 } 3470 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3471