1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI Express Downstream Port Containment services driver 4 * Author: Keith Busch <keith.busch@intel.com> 5 * 6 * Copyright (C) 2016 Intel Corp. 7 */ 8 9 #define dev_fmt(fmt) "DPC: " fmt 10 11 #include <linux/aer.h> 12 #include <linux/bitfield.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/init.h> 16 #include <linux/pci.h> 17 18 #include "portdrv.h" 19 #include "../pci.h" 20 21 #define PCI_EXP_DPC_CTL_EN_MASK (PCI_EXP_DPC_CTL_EN_FATAL | \ 22 PCI_EXP_DPC_CTL_EN_NONFATAL) 23 24 static const char * const rp_pio_error_string[] = { 25 "Configuration Request received UR Completion", /* Bit Position 0 */ 26 "Configuration Request received CA Completion", /* Bit Position 1 */ 27 "Configuration Request Completion Timeout", /* Bit Position 2 */ 28 NULL, 29 NULL, 30 NULL, 31 NULL, 32 NULL, 33 "I/O Request received UR Completion", /* Bit Position 8 */ 34 "I/O Request received CA Completion", /* Bit Position 9 */ 35 "I/O Request Completion Timeout", /* Bit Position 10 */ 36 NULL, 37 NULL, 38 NULL, 39 NULL, 40 NULL, 41 "Memory Request received UR Completion", /* Bit Position 16 */ 42 "Memory Request received CA Completion", /* Bit Position 17 */ 43 "Memory Request Completion Timeout", /* Bit Position 18 */ 44 }; 45 46 void pci_save_dpc_state(struct pci_dev *dev) 47 { 48 struct pci_cap_saved_state *save_state; 49 u16 *cap; 50 51 if (!pci_is_pcie(dev)) 52 return; 53 54 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC); 55 if (!save_state) 56 return; 57 58 cap = (u16 *)&save_state->cap.data[0]; 59 pci_read_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, cap); 60 } 61 62 void pci_restore_dpc_state(struct pci_dev *dev) 63 { 64 struct pci_cap_saved_state *save_state; 65 u16 *cap; 66 67 if (!pci_is_pcie(dev)) 68 return; 69 70 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC); 71 if (!save_state) 72 return; 73 74 cap = (u16 *)&save_state->cap.data[0]; 75 pci_write_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, *cap); 76 } 77 78 static DECLARE_WAIT_QUEUE_HEAD(dpc_completed_waitqueue); 79 80 #ifdef CONFIG_HOTPLUG_PCI_PCIE 81 static bool dpc_completed(struct pci_dev *pdev) 82 { 83 u16 status; 84 85 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status); 86 if ((!PCI_POSSIBLE_ERROR(status)) && (status & PCI_EXP_DPC_STATUS_TRIGGER)) 87 return false; 88 89 if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags)) 90 return false; 91 92 return true; 93 } 94 95 /** 96 * pci_dpc_recovered - whether DPC triggered and has recovered successfully 97 * @pdev: PCI device 98 * 99 * Return true if DPC was triggered for @pdev and has recovered successfully. 100 * Wait for recovery if it hasn't completed yet. Called from the PCIe hotplug 101 * driver to recognize and ignore Link Down/Up events caused by DPC. 102 */ 103 bool pci_dpc_recovered(struct pci_dev *pdev) 104 { 105 struct pci_host_bridge *host; 106 107 if (!pdev->dpc_cap) 108 return false; 109 110 /* 111 * Synchronization between hotplug and DPC is not supported 112 * if DPC is owned by firmware and EDR is not enabled. 113 */ 114 host = pci_find_host_bridge(pdev->bus); 115 if (!host->native_dpc && !IS_ENABLED(CONFIG_PCIE_EDR)) 116 return false; 117 118 /* 119 * Need a timeout in case DPC never completes due to failure of 120 * dpc_wait_rp_inactive(). The spec doesn't mandate a time limit, 121 * but reports indicate that DPC completes within 4 seconds. 122 */ 123 wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev), 124 msecs_to_jiffies(4000)); 125 126 return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); 127 } 128 #endif /* CONFIG_HOTPLUG_PCI_PCIE */ 129 130 static int dpc_wait_rp_inactive(struct pci_dev *pdev) 131 { 132 unsigned long timeout = jiffies + HZ; 133 u16 cap = pdev->dpc_cap, status; 134 135 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 136 while (status & PCI_EXP_DPC_RP_BUSY && 137 !time_after(jiffies, timeout)) { 138 msleep(10); 139 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 140 } 141 if (status & PCI_EXP_DPC_RP_BUSY) { 142 pci_warn(pdev, "root port still busy\n"); 143 return -EBUSY; 144 } 145 return 0; 146 } 147 148 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) 149 { 150 pci_ers_result_t ret; 151 u16 cap; 152 153 set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags); 154 155 /* 156 * DPC disables the Link automatically in hardware, so it has 157 * already been reset by the time we get here. 158 */ 159 cap = pdev->dpc_cap; 160 161 /* 162 * Wait until the Link is inactive, then clear DPC Trigger Status 163 * to allow the Port to leave DPC. 164 */ 165 if (!pcie_wait_for_link(pdev, false)) 166 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n"); 167 168 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) { 169 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); 170 ret = PCI_ERS_RESULT_DISCONNECT; 171 goto out; 172 } 173 174 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 175 PCI_EXP_DPC_STATUS_TRIGGER); 176 177 if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) { 178 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); 179 ret = PCI_ERS_RESULT_DISCONNECT; 180 } else { 181 set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); 182 ret = PCI_ERS_RESULT_RECOVERED; 183 } 184 out: 185 clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags); 186 wake_up_all(&dpc_completed_waitqueue); 187 return ret; 188 } 189 190 static void dpc_process_rp_pio_error(struct pci_dev *pdev) 191 { 192 u16 cap = pdev->dpc_cap, dpc_status, first_error; 193 u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix; 194 int i; 195 196 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status); 197 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask); 198 pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n", 199 status, mask); 200 201 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev); 202 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr); 203 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc); 204 pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n", 205 sev, syserr, exc); 206 207 /* Get First Error Pointer */ 208 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status); 209 first_error = FIELD_GET(PCI_EXP_DPC_RP_PIO_FEP, dpc_status); 210 211 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) { 212 if ((status & ~mask) & (1 << i)) 213 pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i], 214 first_error == i ? " (First)" : ""); 215 } 216 217 if (pdev->dpc_rp_log_size < 4) 218 goto clear_status; 219 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, 220 &dw0); 221 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4, 222 &dw1); 223 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8, 224 &dw2); 225 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12, 226 &dw3); 227 pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n", 228 dw0, dw1, dw2, dw3); 229 230 if (pdev->dpc_rp_log_size < 5) 231 goto clear_status; 232 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log); 233 pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log); 234 235 for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) { 236 pci_read_config_dword(pdev, 237 cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix); 238 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix); 239 } 240 clear_status: 241 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status); 242 } 243 244 static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev, 245 struct aer_err_info *info) 246 { 247 int pos = dev->aer_cap; 248 u32 status, mask, sev; 249 250 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status); 251 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask); 252 status &= ~mask; 253 if (!status) 254 return 0; 255 256 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev); 257 status &= sev; 258 if (status) 259 info->severity = AER_FATAL; 260 else 261 info->severity = AER_NONFATAL; 262 263 return 1; 264 } 265 266 void dpc_process_error(struct pci_dev *pdev) 267 { 268 u16 cap = pdev->dpc_cap, status, source, reason, ext_reason; 269 struct aer_err_info info; 270 271 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 272 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source); 273 274 pci_info(pdev, "containment event, status:%#06x source:%#06x\n", 275 status, source); 276 277 reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN; 278 ext_reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT; 279 pci_warn(pdev, "%s detected\n", 280 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR) ? 281 "unmasked uncorrectable error" : 282 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE) ? 283 "ERR_NONFATAL" : 284 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE) ? 285 "ERR_FATAL" : 286 (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO) ? 287 "RP PIO error" : 288 (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER) ? 289 "software trigger" : 290 "reserved error"); 291 292 /* show RP PIO error detail information */ 293 if (pdev->dpc_rp_extensions && 294 reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT && 295 ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO) 296 dpc_process_rp_pio_error(pdev); 297 else if (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR && 298 dpc_get_aer_uncorrect_severity(pdev, &info) && 299 aer_get_device_error_info(pdev, &info)) { 300 aer_print_error(pdev, &info); 301 pci_aer_clear_nonfatal_status(pdev); 302 pci_aer_clear_fatal_status(pdev); 303 } 304 } 305 306 static irqreturn_t dpc_handler(int irq, void *context) 307 { 308 struct pci_dev *pdev = context; 309 310 dpc_process_error(pdev); 311 312 /* We configure DPC so it only triggers on ERR_FATAL */ 313 pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link); 314 315 return IRQ_HANDLED; 316 } 317 318 static irqreturn_t dpc_irq(int irq, void *context) 319 { 320 struct pci_dev *pdev = context; 321 u16 cap = pdev->dpc_cap, status; 322 323 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 324 325 if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || PCI_POSSIBLE_ERROR(status)) 326 return IRQ_NONE; 327 328 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 329 PCI_EXP_DPC_STATUS_INTERRUPT); 330 if (status & PCI_EXP_DPC_STATUS_TRIGGER) 331 return IRQ_WAKE_THREAD; 332 return IRQ_HANDLED; 333 } 334 335 void pci_dpc_init(struct pci_dev *pdev) 336 { 337 u16 cap; 338 339 pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC); 340 if (!pdev->dpc_cap) 341 return; 342 343 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap); 344 if (!(cap & PCI_EXP_DPC_CAP_RP_EXT)) 345 return; 346 347 pdev->dpc_rp_extensions = true; 348 349 /* Quirks may set dpc_rp_log_size if device or firmware is buggy */ 350 if (!pdev->dpc_rp_log_size) { 351 pdev->dpc_rp_log_size = 352 FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, cap); 353 if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) { 354 pci_err(pdev, "RP PIO log size %u is invalid\n", 355 pdev->dpc_rp_log_size); 356 pdev->dpc_rp_log_size = 0; 357 } 358 } 359 } 360 361 #define FLAG(x, y) (((x) & (y)) ? '+' : '-') 362 static int dpc_probe(struct pcie_device *dev) 363 { 364 struct pci_dev *pdev = dev->port; 365 struct device *device = &dev->device; 366 int status; 367 u16 ctl, cap; 368 369 if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native) 370 return -ENOTSUPP; 371 372 status = devm_request_threaded_irq(device, dev->irq, dpc_irq, 373 dpc_handler, IRQF_SHARED, 374 "pcie-dpc", pdev); 375 if (status) { 376 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq, 377 status); 378 return status; 379 } 380 381 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap); 382 383 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); 384 ctl &= ~PCI_EXP_DPC_CTL_EN_MASK; 385 ctl |= PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; 386 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl); 387 388 pci_info(pdev, "enabled with IRQ %d\n", dev->irq); 389 pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", 390 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT), 391 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP), 392 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size, 393 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE)); 394 395 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16)); 396 return status; 397 } 398 399 static void dpc_remove(struct pcie_device *dev) 400 { 401 struct pci_dev *pdev = dev->port; 402 u16 ctl; 403 404 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); 405 ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN); 406 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl); 407 } 408 409 static struct pcie_port_service_driver dpcdriver = { 410 .name = "dpc", 411 .port_type = PCIE_ANY_PORT, 412 .service = PCIE_PORT_SERVICE_DPC, 413 .probe = dpc_probe, 414 .remove = dpc_remove, 415 }; 416 417 int __init pcie_dpc_init(void) 418 { 419 return pcie_port_service_register(&dpcdriver); 420 } 421