1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI Express Downstream Port Containment services driver 4 * Author: Keith Busch <keith.busch@intel.com> 5 * 6 * Copyright (C) 2016 Intel Corp. 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/init.h> 12 #include <linux/pci.h> 13 14 #include "portdrv.h" 15 #include "../pci.h" 16 #include "aer/aerdrv.h" 17 18 struct dpc_dev { 19 struct pcie_device *dev; 20 struct work_struct work; 21 u16 cap_pos; 22 bool rp_extensions; 23 u32 rp_pio_status; 24 u8 rp_log_size; 25 }; 26 27 static const char * const rp_pio_error_string[] = { 28 "Configuration Request received UR Completion", /* Bit Position 0 */ 29 "Configuration Request received CA Completion", /* Bit Position 1 */ 30 "Configuration Request Completion Timeout", /* Bit Position 2 */ 31 NULL, 32 NULL, 33 NULL, 34 NULL, 35 NULL, 36 "I/O Request received UR Completion", /* Bit Position 8 */ 37 "I/O Request received CA Completion", /* Bit Position 9 */ 38 "I/O Request Completion Timeout", /* Bit Position 10 */ 39 NULL, 40 NULL, 41 NULL, 42 NULL, 43 NULL, 44 "Memory Request received UR Completion", /* Bit Position 16 */ 45 "Memory Request received CA Completion", /* Bit Position 17 */ 46 "Memory Request Completion Timeout", /* Bit Position 18 */ 47 }; 48 49 static int dpc_wait_rp_inactive(struct dpc_dev *dpc) 50 { 51 unsigned long timeout = jiffies + HZ; 52 struct pci_dev *pdev = dpc->dev->port; 53 struct device *dev = &dpc->dev->device; 54 u16 cap = dpc->cap_pos, status; 55 56 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 57 while (status & PCI_EXP_DPC_RP_BUSY && 58 !time_after(jiffies, timeout)) { 59 msleep(10); 60 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 61 } 62 if (status & PCI_EXP_DPC_RP_BUSY) { 63 dev_warn(dev, "DPC root port still busy\n"); 64 return -EBUSY; 65 } 66 return 0; 67 } 68 69 static void dpc_wait_link_inactive(struct dpc_dev *dpc) 70 { 71 struct pci_dev *pdev = dpc->dev->port; 72 73 pcie_wait_for_link(pdev, false); 74 } 75 76 static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) 77 { 78 struct dpc_dev *dpc; 79 struct pcie_device *pciedev; 80 struct device *devdpc; 81 u16 cap, ctl; 82 83 /* 84 * DPC disables the Link automatically in hardware, so it has 85 * already been reset by the time we get here. 86 */ 87 devdpc = pcie_port_find_device(pdev, PCIE_PORT_SERVICE_DPC); 88 pciedev = to_pcie_device(devdpc); 89 dpc = get_service_data(pciedev); 90 cap = dpc->cap_pos; 91 92 /* 93 * Wait until the Link is inactive, then clear DPC Trigger Status 94 * to allow the Port to leave DPC. 95 */ 96 dpc_wait_link_inactive(dpc); 97 98 if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc)) 99 return PCI_ERS_RESULT_DISCONNECT; 100 if (dpc->rp_extensions && dpc->rp_pio_status) { 101 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, 102 dpc->rp_pio_status); 103 dpc->rp_pio_status = 0; 104 } 105 106 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 107 PCI_EXP_DPC_STATUS_TRIGGER); 108 109 pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl); 110 pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL, 111 ctl | PCI_EXP_DPC_CTL_INT_EN); 112 113 return PCI_ERS_RESULT_RECOVERED; 114 } 115 116 static void dpc_work(struct work_struct *work) 117 { 118 struct dpc_dev *dpc = container_of(work, struct dpc_dev, work); 119 struct pci_dev *pdev = dpc->dev->port; 120 121 /* We configure DPC so it only triggers on ERR_FATAL */ 122 pcie_do_fatal_recovery(pdev, PCIE_PORT_SERVICE_DPC); 123 } 124 125 static void dpc_process_rp_pio_error(struct dpc_dev *dpc) 126 { 127 struct device *dev = &dpc->dev->device; 128 struct pci_dev *pdev = dpc->dev->port; 129 u16 cap = dpc->cap_pos, dpc_status, first_error; 130 u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix; 131 int i; 132 133 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status); 134 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask); 135 dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n", 136 status, mask); 137 138 dpc->rp_pio_status = status; 139 140 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev); 141 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr); 142 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc); 143 dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n", 144 sev, syserr, exc); 145 146 /* Get First Error Pointer */ 147 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status); 148 first_error = (dpc_status & 0x1f00) >> 8; 149 150 status &= ~mask; 151 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) { 152 if (status & (1 << i)) 153 dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i], 154 first_error == i ? " (First)" : ""); 155 } 156 157 if (dpc->rp_log_size < 4) 158 return; 159 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, 160 &dw0); 161 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4, 162 &dw1); 163 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8, 164 &dw2); 165 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12, 166 &dw3); 167 dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n", 168 dw0, dw1, dw2, dw3); 169 170 if (dpc->rp_log_size < 5) 171 return; 172 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log); 173 dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log); 174 175 for (i = 0; i < dpc->rp_log_size - 5; i++) { 176 pci_read_config_dword(pdev, 177 cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix); 178 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix); 179 } 180 } 181 182 static irqreturn_t dpc_irq(int irq, void *context) 183 { 184 struct dpc_dev *dpc = (struct dpc_dev *)context; 185 struct pci_dev *pdev = dpc->dev->port; 186 struct device *dev = &dpc->dev->device; 187 u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason; 188 189 pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl); 190 191 if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0)) 192 return IRQ_NONE; 193 194 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 195 196 if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT)) 197 return IRQ_NONE; 198 199 if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) { 200 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 201 PCI_EXP_DPC_STATUS_INTERRUPT); 202 return IRQ_HANDLED; 203 } 204 205 pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL, 206 ctl & ~PCI_EXP_DPC_CTL_INT_EN); 207 208 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, 209 &source); 210 211 dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n", 212 status, source); 213 214 reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1; 215 ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5; 216 217 dev_warn(dev, "DPC %s detected, remove downstream devices\n", 218 (reason == 0) ? "unmasked uncorrectable error" : 219 (reason == 1) ? "ERR_NONFATAL" : 220 (reason == 2) ? "ERR_FATAL" : 221 (ext_reason == 0) ? "RP PIO error" : 222 (ext_reason == 1) ? "software trigger" : 223 "reserved error"); 224 /* show RP PIO error detail information */ 225 if (dpc->rp_extensions && reason == 3 && ext_reason == 0) 226 dpc_process_rp_pio_error(dpc); 227 228 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 229 PCI_EXP_DPC_STATUS_INTERRUPT); 230 231 schedule_work(&dpc->work); 232 233 return IRQ_HANDLED; 234 } 235 236 #define FLAG(x, y) (((x) & (y)) ? '+' : '-') 237 static int dpc_probe(struct pcie_device *dev) 238 { 239 struct dpc_dev *dpc; 240 struct pci_dev *pdev = dev->port; 241 struct device *device = &dev->device; 242 int status; 243 u16 ctl, cap; 244 245 if (pcie_aer_get_firmware_first(pdev)) 246 return -ENOTSUPP; 247 248 dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL); 249 if (!dpc) 250 return -ENOMEM; 251 252 dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC); 253 dpc->dev = dev; 254 INIT_WORK(&dpc->work, dpc_work); 255 set_service_data(dev, dpc); 256 257 status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED, 258 "pcie-dpc", dpc); 259 if (status) { 260 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq, 261 status); 262 return status; 263 } 264 265 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap); 266 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl); 267 268 dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT); 269 if (dpc->rp_extensions) { 270 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8; 271 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) { 272 dev_err(device, "RP PIO log size %u is invalid\n", 273 dpc->rp_log_size); 274 dpc->rp_log_size = 0; 275 } 276 } 277 278 ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; 279 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl); 280 281 dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", 282 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT), 283 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP), 284 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size, 285 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE)); 286 return status; 287 } 288 289 static void dpc_remove(struct pcie_device *dev) 290 { 291 struct dpc_dev *dpc = get_service_data(dev); 292 struct pci_dev *pdev = dev->port; 293 u16 ctl; 294 295 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl); 296 ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN); 297 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl); 298 } 299 300 static struct pcie_port_service_driver dpcdriver = { 301 .name = "dpc", 302 .port_type = PCIE_ANY_PORT, 303 .service = PCIE_PORT_SERVICE_DPC, 304 .probe = dpc_probe, 305 .remove = dpc_remove, 306 .reset_link = dpc_reset_link, 307 }; 308 309 static int __init dpc_service_init(void) 310 { 311 return pcie_port_service_register(&dpcdriver); 312 } 313 device_initcall(dpc_service_init); 314